1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright(c) 2020 Intel Corporation 4 // 5 // Author: Cezary Rojewski <cezary.rojewski@intel.com> 6 // 7 8 #include <linux/cleanup.h> 9 #include <linux/devcoredump.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/firmware.h> 12 #include <linux/pci.h> 13 #include <linux/pxa2xx_ssp.h> 14 #include "core.h" 15 #include "messages.h" 16 #include "registers.h" 17 18 static bool catpt_dma_filter(struct dma_chan *chan, void *param) 19 { 20 return param == chan->device->dev; 21 } 22 23 /* 24 * Either engine 0 or 1 can be used for image loading. 25 * Align with Windows driver equivalent and stick to engine 1. 26 */ 27 #define CATPT_DMA_DEVID 1 28 #define CATPT_DMA_DSP_ADDR_MASK GENMASK(31, 20) 29 30 struct dma_chan *catpt_dma_request_config_chan(struct catpt_dev *cdev) 31 { 32 struct dma_slave_config config; 33 struct dma_chan *chan; 34 dma_cap_mask_t mask; 35 int ret; 36 37 dma_cap_zero(mask); 38 dma_cap_set(DMA_MEMCPY, mask); 39 40 chan = dma_request_channel(mask, catpt_dma_filter, cdev->dev); 41 if (!chan) { 42 dev_err(cdev->dev, "request channel failed\n"); 43 return ERR_PTR(-ENODEV); 44 } 45 46 memset(&config, 0, sizeof(config)); 47 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 48 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 49 config.src_maxburst = 16; 50 config.dst_maxburst = 16; 51 52 ret = dmaengine_slave_config(chan, &config); 53 if (ret) { 54 dev_err(cdev->dev, "slave config failed: %d\n", ret); 55 dma_release_channel(chan); 56 return ERR_PTR(ret); 57 } 58 59 return chan; 60 } 61 62 static int catpt_dma_memcpy(struct catpt_dev *cdev, struct dma_chan *chan, 63 dma_addr_t dst_addr, dma_addr_t src_addr, 64 size_t size) 65 { 66 struct dma_async_tx_descriptor *desc; 67 enum dma_status status; 68 int ret; 69 70 desc = dmaengine_prep_dma_memcpy(chan, dst_addr, src_addr, size, 71 DMA_CTRL_ACK); 72 if (!desc) { 73 dev_err(cdev->dev, "prep dma memcpy failed\n"); 74 return -EIO; 75 } 76 77 /* enable demand mode for dma channel */ 78 catpt_updatel_shim(cdev, HMDC, 79 CATPT_HMDC_HDDA(CATPT_DMA_DEVID, chan->chan_id), 80 CATPT_HMDC_HDDA(CATPT_DMA_DEVID, chan->chan_id)); 81 82 ret = dma_submit_error(dmaengine_submit(desc)); 83 if (ret) { 84 dev_err(cdev->dev, "submit tx failed: %d\n", ret); 85 goto clear_hdda; 86 } 87 88 status = dma_wait_for_async_tx(desc); 89 ret = (status == DMA_COMPLETE) ? 0 : -EPROTO; 90 91 clear_hdda: 92 /* regardless of status, disable access to HOST memory in demand mode */ 93 catpt_updatel_shim(cdev, HMDC, 94 CATPT_HMDC_HDDA(CATPT_DMA_DEVID, chan->chan_id), 0); 95 96 return ret; 97 } 98 99 int catpt_dma_memcpy_todsp(struct catpt_dev *cdev, struct dma_chan *chan, 100 dma_addr_t dst_addr, dma_addr_t src_addr, 101 size_t size) 102 { 103 return catpt_dma_memcpy(cdev, chan, dst_addr | CATPT_DMA_DSP_ADDR_MASK, 104 src_addr, size); 105 } 106 107 int catpt_dma_memcpy_fromdsp(struct catpt_dev *cdev, struct dma_chan *chan, 108 dma_addr_t dst_addr, dma_addr_t src_addr, 109 size_t size) 110 { 111 return catpt_dma_memcpy(cdev, chan, dst_addr, 112 src_addr | CATPT_DMA_DSP_ADDR_MASK, size); 113 } 114 115 int catpt_dmac_probe(struct catpt_dev *cdev) 116 { 117 struct dw_dma_chip *dmac; 118 int ret; 119 120 dmac = devm_kzalloc(cdev->dev, sizeof(*dmac), GFP_KERNEL); 121 if (!dmac) 122 return -ENOMEM; 123 124 dmac->regs = catpt_dma_addr(cdev, CATPT_DMA_DEVID); 125 dmac->dev = cdev->dev; 126 dmac->irq = cdev->irq; 127 128 /* 129 * Caller is responsible for putting device in D0 to allow 130 * for I/O and memory access before probing DW. 131 */ 132 ret = dw_dma_probe(dmac); 133 if (ret) 134 return ret; 135 136 cdev->dmac = dmac; 137 return 0; 138 } 139 140 void catpt_dmac_remove(struct catpt_dev *cdev) 141 { 142 /* 143 * As do_dma_remove() juggles with pm_runtime_get_xxx() and 144 * pm_runtime_put_xxx() while both ADSP and DW 'devices' are part of 145 * the same module, caller makes sure pm_runtime_disable() is invoked 146 * before removing DW to prevent postmortem resume and suspend. 147 */ 148 dw_dma_remove(cdev->dmac); 149 } 150 151 static void catpt_dsp_set_srampge(struct catpt_dev *cdev, struct resource *sram, 152 unsigned long mask, unsigned long new) 153 { 154 unsigned long old; 155 u32 off = sram->start; 156 unsigned long b = __ffs(mask); 157 158 old = catpt_readl_pci(cdev, VDRTCTL0) & mask; 159 dev_dbg(cdev->dev, "SRAMPGE [0x%08lx] 0x%08lx -> 0x%08lx", 160 mask, old, new); 161 162 if (old == new) 163 return; 164 165 catpt_updatel_pci(cdev, VDRTCTL0, mask, new); 166 /* wait for SRAM power gating to propagate */ 167 udelay(60); 168 169 /* 170 * Dummy read as the very first access after block enable 171 * to prevent byte loss in future operations. 172 */ 173 for_each_clear_bit_from(b, &new, fls_long(mask)) { 174 u8 buf[4]; 175 176 /* newly enabled: new bit=0 while old bit=1 */ 177 if (test_bit(b, &old)) { 178 dev_dbg(cdev->dev, "sanitize block %ld: off 0x%08x\n", 179 b - __ffs(mask), off); 180 memcpy_fromio(buf, cdev->lpe_ba + off, sizeof(buf)); 181 } 182 off += CATPT_MEMBLOCK_SIZE; 183 } 184 } 185 186 void catpt_dsp_update_srampge(struct catpt_dev *cdev, struct resource *sram, 187 unsigned long mask) 188 { 189 struct resource *res; 190 unsigned long new = 0; 191 192 /* flag all busy blocks */ 193 for (res = sram->child; res; res = res->sibling) { 194 u32 h, l; 195 196 h = (res->end - sram->start) / CATPT_MEMBLOCK_SIZE; 197 l = (res->start - sram->start) / CATPT_MEMBLOCK_SIZE; 198 new |= GENMASK(h, l); 199 } 200 201 /* offset value given mask's start and invert it as ON=b0 */ 202 new = ~(new << __ffs(mask)) & mask; 203 204 /* disable core clock gating */ 205 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0); 206 207 catpt_dsp_set_srampge(cdev, sram, mask, new); 208 209 /* enable core clock gating */ 210 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 211 CATPT_VDRTCTL2_DCLCGE); 212 } 213 214 int catpt_dsp_stall(struct catpt_dev *cdev, bool stall) 215 { 216 u32 reg, val; 217 218 val = stall ? CATPT_CS_STALL : 0; 219 catpt_updatel_shim(cdev, CS1, CATPT_CS_STALL, val); 220 221 return catpt_readl_poll_shim(cdev, CS1, 222 reg, (reg & CATPT_CS_STALL) == val, 223 500, 10000); 224 } 225 226 static int catpt_dsp_reset(struct catpt_dev *cdev, bool reset) 227 { 228 u32 reg, val; 229 230 val = reset ? CATPT_CS_RST : 0; 231 catpt_updatel_shim(cdev, CS1, CATPT_CS_RST, val); 232 233 return catpt_readl_poll_shim(cdev, CS1, 234 reg, (reg & CATPT_CS_RST) == val, 235 500, 10000); 236 } 237 238 void lpt_dsp_pll_shutdown(struct catpt_dev *cdev, bool enable) 239 { 240 u32 val; 241 242 val = enable ? LPT_VDRTCTL0_APLLSE : 0; 243 catpt_updatel_pci(cdev, VDRTCTL0, LPT_VDRTCTL0_APLLSE, val); 244 } 245 246 void wpt_dsp_pll_shutdown(struct catpt_dev *cdev, bool enable) 247 { 248 u32 val; 249 250 val = enable ? WPT_VDRTCTL2_APLLSE : 0; 251 catpt_updatel_pci(cdev, VDRTCTL2, WPT_VDRTCTL2_APLLSE, val); 252 } 253 254 static int catpt_dsp_select_lpclock(struct catpt_dev *cdev, bool lp, bool waiti) 255 { 256 u32 mask, reg, val; 257 int ret; 258 259 guard(mutex)(&cdev->clk_mutex); 260 261 val = lp ? CATPT_CS_LPCS : 0; 262 reg = catpt_readl_shim(cdev, CS1) & CATPT_CS_LPCS; 263 dev_dbg(cdev->dev, "LPCS [0x%08lx] 0x%08x -> 0x%08x", 264 CATPT_CS_LPCS, reg, val); 265 266 if (reg == val) 267 return 0; 268 269 if (waiti) { 270 /* wait for DSP to signal WAIT state */ 271 ret = catpt_readl_poll_shim(cdev, ISD, 272 reg, (reg & CATPT_ISD_DCPWM), 273 500, 10000); 274 if (ret) { 275 dev_warn(cdev->dev, "await WAITI timeout\n"); 276 /* no signal - only high clock selection allowed */ 277 if (lp) 278 return 0; 279 } 280 } 281 282 ret = catpt_readl_poll_shim(cdev, CLKCTL, 283 reg, !(reg & CATPT_CLKCTL_CFCIP), 284 500, 10000); 285 if (ret) 286 dev_warn(cdev->dev, "clock change still in progress\n"); 287 288 /* default to DSP core & audio fabric high clock */ 289 val |= CATPT_CS_DCS_HIGH; 290 mask = CATPT_CS_LPCS | CATPT_CS_DCS; 291 catpt_updatel_shim(cdev, CS1, mask, val); 292 293 ret = catpt_readl_poll_shim(cdev, CLKCTL, 294 reg, !(reg & CATPT_CLKCTL_CFCIP), 295 500, 10000); 296 if (ret) 297 dev_warn(cdev->dev, "clock change still in progress\n"); 298 299 /* update PLL accordingly */ 300 cdev->spec->pll_shutdown(cdev, lp); 301 302 return 0; 303 } 304 305 int catpt_dsp_update_lpclock(struct catpt_dev *cdev) 306 { 307 struct catpt_stream_runtime *stream; 308 309 list_for_each_entry(stream, &cdev->stream_list, node) 310 if (stream->prepared) 311 return catpt_dsp_select_lpclock(cdev, false, true); 312 313 return catpt_dsp_select_lpclock(cdev, true, true); 314 } 315 316 /* bring registers to their defaults as HW won't reset itself */ 317 static void catpt_dsp_set_regs_defaults(struct catpt_dev *cdev) 318 { 319 int i; 320 321 catpt_writel_shim(cdev, CS1, CATPT_CS_DEFAULT); 322 catpt_writel_shim(cdev, ISC, CATPT_ISC_DEFAULT); 323 catpt_writel_shim(cdev, ISD, CATPT_ISD_DEFAULT); 324 catpt_writel_shim(cdev, IMC, CATPT_IMC_DEFAULT); 325 catpt_writel_shim(cdev, IMD, CATPT_IMD_DEFAULT); 326 catpt_writel_shim(cdev, IPCC, CATPT_IPCC_DEFAULT); 327 catpt_writel_shim(cdev, IPCD, CATPT_IPCD_DEFAULT); 328 catpt_writel_shim(cdev, CLKCTL, CATPT_CLKCTL_DEFAULT); 329 catpt_writel_shim(cdev, CS2, CATPT_CS2_DEFAULT); 330 catpt_writel_shim(cdev, LTRC, CATPT_LTRC_DEFAULT); 331 catpt_writel_shim(cdev, HMDC, CATPT_HMDC_DEFAULT); 332 333 for (i = 0; i < CATPT_SSP_COUNT; i++) { 334 catpt_writel_ssp(cdev, i, SSCR0, CATPT_SSC0_DEFAULT); 335 catpt_writel_ssp(cdev, i, SSCR1, CATPT_SSC1_DEFAULT); 336 catpt_writel_ssp(cdev, i, SSSR, CATPT_SSS_DEFAULT); 337 catpt_writel_ssp(cdev, i, SSITR, CATPT_SSIT_DEFAULT); 338 catpt_writel_ssp(cdev, i, SSDR, CATPT_SSD_DEFAULT); 339 catpt_writel_ssp(cdev, i, SSTO, CATPT_SSTO_DEFAULT); 340 catpt_writel_ssp(cdev, i, SSPSP, CATPT_SSPSP_DEFAULT); 341 catpt_writel_ssp(cdev, i, SSTSA, CATPT_SSTSA_DEFAULT); 342 catpt_writel_ssp(cdev, i, SSRSA, CATPT_SSRSA_DEFAULT); 343 catpt_writel_ssp(cdev, i, SSTSS, CATPT_SSTSS_DEFAULT); 344 catpt_writel_ssp(cdev, i, SSCR2, CATPT_SSCR2_DEFAULT); 345 catpt_writel_ssp(cdev, i, SSPSP2, CATPT_SSPSP2_DEFAULT); 346 } 347 } 348 349 int catpt_dsp_power_down(struct catpt_dev *cdev) 350 { 351 u32 mask, val; 352 353 /* disable core clock gating */ 354 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0); 355 356 catpt_dsp_reset(cdev, true); 357 /* set 24Mhz clock for both SSPs */ 358 catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1), 359 CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1)); 360 catpt_dsp_select_lpclock(cdev, true, false); 361 /* disable MCLK */ 362 catpt_updatel_shim(cdev, CLKCTL, CATPT_CLKCTL_SMOS, 0); 363 364 catpt_dsp_set_regs_defaults(cdev); 365 366 /* switch clock gating */ 367 mask = CATPT_VDRTCTL2_CGEALL & (~CATPT_VDRTCTL2_DCLCGE); 368 val = mask & (~CATPT_VDRTCTL2_DTCGE); 369 catpt_updatel_pci(cdev, VDRTCTL2, mask, val); 370 /* enable DTCGE separatelly */ 371 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DTCGE, 372 CATPT_VDRTCTL2_DTCGE); 373 374 /* SRAM power gating all */ 375 catpt_dsp_set_srampge(cdev, &cdev->dram, cdev->spec->dram_mask, 376 cdev->spec->dram_mask); 377 catpt_dsp_set_srampge(cdev, &cdev->iram, cdev->spec->iram_mask, 378 cdev->spec->iram_mask); 379 mask = cdev->spec->d3srampgd_bit | cdev->spec->d3pgd_bit; 380 catpt_updatel_pci(cdev, VDRTCTL0, mask, cdev->spec->d3pgd_bit); 381 382 catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, (__force u32)PCI_D3hot); 383 /* give hw time to drop off */ 384 udelay(50); 385 386 /* enable core clock gating */ 387 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 388 CATPT_VDRTCTL2_DCLCGE); 389 udelay(50); 390 391 return 0; 392 } 393 394 int catpt_dsp_power_up(struct catpt_dev *cdev) 395 { 396 u32 mask, val; 397 398 /* disable core clock gating */ 399 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0); 400 401 /* switch clock gating */ 402 mask = CATPT_VDRTCTL2_CGEALL & (~CATPT_VDRTCTL2_DCLCGE); 403 val = mask & (~CATPT_VDRTCTL2_DTCGE); 404 catpt_updatel_pci(cdev, VDRTCTL2, mask, val); 405 406 catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, (__force u32)PCI_D0); 407 408 /* SRAM power gating none */ 409 mask = cdev->spec->d3srampgd_bit | cdev->spec->d3pgd_bit; 410 catpt_updatel_pci(cdev, VDRTCTL0, mask, mask); 411 catpt_dsp_set_srampge(cdev, &cdev->dram, cdev->spec->dram_mask, 0); 412 catpt_dsp_set_srampge(cdev, &cdev->iram, cdev->spec->iram_mask, 0); 413 414 catpt_dsp_set_regs_defaults(cdev); 415 416 /* restore MCLK */ 417 catpt_updatel_shim(cdev, CLKCTL, CATPT_CLKCTL_SMOS, CATPT_CLKCTL_SMOS); 418 catpt_dsp_select_lpclock(cdev, false, false); 419 /* set 24Mhz clock for both SSPs */ 420 catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1), 421 CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1)); 422 catpt_dsp_reset(cdev, false); 423 424 /* enable core clock gating */ 425 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 426 CATPT_VDRTCTL2_DCLCGE); 427 428 /* generate int deassert msg to fix inversed int logic */ 429 catpt_updatel_shim(cdev, IMC, CATPT_IMC_IPCDB | CATPT_IMC_IPCCD, 0); 430 431 return 0; 432 } 433 434 #define CATPT_DUMP_MAGIC 0xcd42 435 #define CATPT_DUMP_SECTION_ID_FILE 0x00 436 #define CATPT_DUMP_SECTION_ID_IRAM 0x01 437 #define CATPT_DUMP_SECTION_ID_DRAM 0x02 438 #define CATPT_DUMP_SECTION_ID_REGS 0x03 439 #define CATPT_DUMP_HASH_SIZE 20 440 441 struct catpt_dump_section_hdr { 442 u16 magic; 443 u8 core_id; 444 u8 section_id; 445 u32 size; 446 }; 447 448 int catpt_coredump(struct catpt_dev *cdev) 449 { 450 struct catpt_dump_section_hdr *hdr; 451 size_t dump_size, regs_size; 452 u8 *dump, *pos; 453 const char *eof; 454 char *info; 455 int i; 456 457 regs_size = CATPT_SHIM_REGS_SIZE; 458 regs_size += CATPT_DMA_COUNT * CATPT_DMA_REGS_SIZE; 459 regs_size += CATPT_SSP_COUNT * CATPT_SSP_REGS_SIZE; 460 dump_size = resource_size(&cdev->dram); 461 dump_size += resource_size(&cdev->iram); 462 dump_size += regs_size; 463 /* account for header of each section and hash chunk */ 464 dump_size += 4 * sizeof(*hdr) + CATPT_DUMP_HASH_SIZE; 465 466 dump = vzalloc(dump_size); 467 if (!dump) 468 return -ENOMEM; 469 470 pos = dump; 471 472 hdr = (struct catpt_dump_section_hdr *)pos; 473 hdr->magic = CATPT_DUMP_MAGIC; 474 hdr->core_id = cdev->spec->core_id; 475 hdr->section_id = CATPT_DUMP_SECTION_ID_FILE; 476 hdr->size = dump_size - sizeof(*hdr); 477 pos += sizeof(*hdr); 478 479 info = cdev->ipc.config.fw_info; 480 eof = info + FW_INFO_SIZE_MAX; 481 /* navigate to fifth info segment (fw hash) */ 482 for (i = 0; i < 4 && info < eof; i++, info++) { 483 /* info segments are separated by space each */ 484 info = strnchr(info, eof - info, ' '); 485 if (!info) 486 break; 487 } 488 489 if (i == 4 && info) 490 memcpy(pos, info, min_t(u32, eof - info, CATPT_DUMP_HASH_SIZE)); 491 pos += CATPT_DUMP_HASH_SIZE; 492 493 hdr = (struct catpt_dump_section_hdr *)pos; 494 hdr->magic = CATPT_DUMP_MAGIC; 495 hdr->core_id = cdev->spec->core_id; 496 hdr->section_id = CATPT_DUMP_SECTION_ID_IRAM; 497 hdr->size = resource_size(&cdev->iram); 498 pos += sizeof(*hdr); 499 500 memcpy_fromio(pos, catpt_iram_addr(cdev), hdr->size); 501 pos += hdr->size; 502 503 hdr = (struct catpt_dump_section_hdr *)pos; 504 hdr->magic = CATPT_DUMP_MAGIC; 505 hdr->core_id = cdev->spec->core_id; 506 hdr->section_id = CATPT_DUMP_SECTION_ID_DRAM; 507 hdr->size = resource_size(&cdev->dram); 508 pos += sizeof(*hdr); 509 510 memcpy_fromio(pos, catpt_dram_addr(cdev), hdr->size); 511 pos += hdr->size; 512 513 hdr = (struct catpt_dump_section_hdr *)pos; 514 hdr->magic = CATPT_DUMP_MAGIC; 515 hdr->core_id = cdev->spec->core_id; 516 hdr->section_id = CATPT_DUMP_SECTION_ID_REGS; 517 hdr->size = regs_size; 518 pos += sizeof(*hdr); 519 520 memcpy_fromio(pos, catpt_shim_addr(cdev), CATPT_SHIM_REGS_SIZE); 521 pos += CATPT_SHIM_REGS_SIZE; 522 523 for (i = 0; i < CATPT_SSP_COUNT; i++) { 524 memcpy_fromio(pos, catpt_ssp_addr(cdev, i), 525 CATPT_SSP_REGS_SIZE); 526 pos += CATPT_SSP_REGS_SIZE; 527 } 528 for (i = 0; i < CATPT_DMA_COUNT; i++) { 529 memcpy_fromio(pos, catpt_dma_addr(cdev, i), 530 CATPT_DMA_REGS_SIZE); 531 pos += CATPT_DMA_REGS_SIZE; 532 } 533 534 dev_coredumpv(cdev->dev, dump, dump_size, GFP_KERNEL); 535 536 return 0; 537 } 538