1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022, Linaro Limited
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/mod_devicetable.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/regmap.h>
12
13 #include <dt-bindings/clock/qcom,sm6350-camcc.h>
14
15 #include "clk-alpha-pll.h"
16 #include "clk-branch.h"
17 #include "clk-rcg.h"
18 #include "common.h"
19 #include "gdsc.h"
20
21 enum {
22 DT_BI_TCXO,
23 };
24
25 enum {
26 P_BI_TCXO,
27 P_CAMCC_PLL0_OUT_EVEN,
28 P_CAMCC_PLL0_OUT_MAIN,
29 P_CAMCC_PLL1_OUT_EVEN,
30 P_CAMCC_PLL1_OUT_MAIN,
31 P_CAMCC_PLL2_OUT_EARLY,
32 P_CAMCC_PLL2_OUT_MAIN,
33 P_CAMCC_PLL3_OUT_MAIN,
34 };
35
36 static const struct pll_vco fabia_vco[] = {
37 { 249600000, 2000000000, 0 },
38 };
39
40 /* 600MHz configuration */
41 static const struct alpha_pll_config camcc_pll0_config = {
42 .l = 0x1f,
43 .alpha = 0x4000,
44 .config_ctl_val = 0x20485699,
45 .config_ctl_hi_val = 0x00002067,
46 .test_ctl_val = 0x40000000,
47 .test_ctl_hi_val = 0x00000002,
48 .user_ctl_val = 0x00000101,
49 .user_ctl_hi_val = 0x00004805,
50 };
51
52 static struct clk_alpha_pll camcc_pll0 = {
53 .offset = 0x0,
54 .vco_table = fabia_vco,
55 .num_vco = ARRAY_SIZE(fabia_vco),
56 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
57 .clkr = {
58 .hw.init = &(struct clk_init_data){
59 .name = "camcc_pll0",
60 .parent_data = &(const struct clk_parent_data){
61 .index = DT_BI_TCXO,
62 },
63 .num_parents = 1,
64 .ops = &clk_alpha_pll_fabia_ops,
65 },
66 },
67 };
68
69 static const struct clk_div_table post_div_table_camcc_pll0_out_even[] = {
70 { 0x1, 2 },
71 { }
72 };
73
74 static struct clk_alpha_pll_postdiv camcc_pll0_out_even = {
75 .offset = 0x0,
76 .post_div_shift = 8,
77 .post_div_table = post_div_table_camcc_pll0_out_even,
78 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll0_out_even),
79 .width = 4,
80 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
81 .clkr.hw.init = &(struct clk_init_data){
82 .name = "camcc_pll0_out_even",
83 .parent_hws = (const struct clk_hw*[]){
84 &camcc_pll0.clkr.hw,
85 },
86 .num_parents = 1,
87 .flags = CLK_SET_RATE_PARENT,
88 .ops = &clk_alpha_pll_postdiv_fabia_ops,
89 },
90 };
91
92 /* 808MHz configuration */
93 static const struct alpha_pll_config camcc_pll1_config = {
94 .l = 0x2a,
95 .alpha = 0x1555,
96 .config_ctl_val = 0x20485699,
97 .config_ctl_hi_val = 0x00002067,
98 .test_ctl_val = 0x40000000,
99 .test_ctl_hi_val = 0x00000000,
100 .user_ctl_val = 0x00000101,
101 .user_ctl_hi_val = 0x00004805,
102 };
103
104 static struct clk_alpha_pll camcc_pll1 = {
105 .offset = 0x1000,
106 .vco_table = fabia_vco,
107 .num_vco = ARRAY_SIZE(fabia_vco),
108 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
109 .clkr = {
110 .hw.init = &(struct clk_init_data){
111 .name = "camcc_pll1",
112 .parent_data = &(const struct clk_parent_data){
113 .index = DT_BI_TCXO,
114 },
115 .num_parents = 1,
116 .ops = &clk_alpha_pll_fabia_ops,
117 },
118 },
119 };
120
121 static const struct clk_div_table post_div_table_camcc_pll1_out_even[] = {
122 { 0x1, 2 },
123 { }
124 };
125
126 static struct clk_alpha_pll_postdiv camcc_pll1_out_even = {
127 .offset = 0x1000,
128 .post_div_shift = 8,
129 .post_div_table = post_div_table_camcc_pll1_out_even,
130 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll1_out_even),
131 .width = 4,
132 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
133 .clkr.hw.init = &(struct clk_init_data){
134 .name = "camcc_pll1_out_even",
135 .parent_hws = (const struct clk_hw*[]){
136 &camcc_pll1.clkr.hw,
137 },
138 .num_parents = 1,
139 .flags = CLK_SET_RATE_PARENT,
140 .ops = &clk_alpha_pll_postdiv_fabia_ops,
141 },
142 };
143
144 /* 1920MHz configuration */
145 static const struct alpha_pll_config camcc_pll2_config = {
146 .l = 0x64,
147 .alpha = 0x0,
148 .config_ctl_val = 0x20000800,
149 .config_ctl_hi_val = 0x400003d2,
150 .test_ctl_val = 0x04000400,
151 .test_ctl_hi_val = 0x00004000,
152 .user_ctl_val = 0x0000030b,
153 };
154
155 static struct clk_alpha_pll camcc_pll2 = {
156 .offset = 0x2000,
157 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA],
158 .clkr = {
159 .hw.init = &(struct clk_init_data){
160 .name = "camcc_pll2",
161 .parent_data = &(const struct clk_parent_data){
162 .index = DT_BI_TCXO,
163 },
164 .num_parents = 1,
165 .ops = &clk_alpha_pll_agera_ops,
166 },
167 },
168 };
169
170 static struct clk_fixed_factor camcc_pll2_out_early = {
171 .mult = 1,
172 .div = 2,
173 .hw.init = &(struct clk_init_data){
174 .name = "camcc_pll2_out_early",
175 .parent_hws = (const struct clk_hw*[]){
176 &camcc_pll2.clkr.hw,
177 },
178 .num_parents = 1,
179 .ops = &clk_fixed_factor_ops,
180 },
181 };
182
183 static const struct clk_div_table post_div_table_camcc_pll2_out_main[] = {
184 { 0x1, 2 },
185 { }
186 };
187
188 static struct clk_alpha_pll_postdiv camcc_pll2_out_main = {
189 .offset = 0x2000,
190 .post_div_shift = 8,
191 .post_div_table = post_div_table_camcc_pll2_out_main,
192 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll2_out_main),
193 .width = 2,
194 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA],
195 .clkr.hw.init = &(struct clk_init_data){
196 .name = "camcc_pll2_out_main",
197 .parent_hws = (const struct clk_hw*[]){
198 &camcc_pll2.clkr.hw,
199 },
200 .num_parents = 1,
201 .flags = CLK_SET_RATE_PARENT,
202 .ops = &clk_alpha_pll_postdiv_ops,
203 },
204 };
205
206 /* 384MHz configuration */
207 static const struct alpha_pll_config camcc_pll3_config = {
208 .l = 0x14,
209 .alpha = 0x0,
210 .config_ctl_val = 0x20485699,
211 .config_ctl_hi_val = 0x00002067,
212 .test_ctl_val = 0x40000000,
213 .test_ctl_hi_val = 0x00000002,
214 .user_ctl_val = 0x00000001,
215 .user_ctl_hi_val = 0x00014805,
216 };
217
218 static struct clk_alpha_pll camcc_pll3 = {
219 .offset = 0x3000,
220 .vco_table = fabia_vco,
221 .num_vco = ARRAY_SIZE(fabia_vco),
222 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
223 .clkr = {
224 .hw.init = &(struct clk_init_data){
225 .name = "camcc_pll3",
226 .parent_data = &(const struct clk_parent_data){
227 .index = DT_BI_TCXO,
228 },
229 .num_parents = 1,
230 .ops = &clk_alpha_pll_fabia_ops,
231 },
232 },
233 };
234
235 static const struct parent_map camcc_parent_map_0[] = {
236 { P_BI_TCXO, 0 },
237 { P_CAMCC_PLL0_OUT_EVEN, 6 },
238 };
239
240 static const struct clk_parent_data camcc_parent_data_0[] = {
241 { .fw_name = "bi_tcxo" },
242 { .hw = &camcc_pll0_out_even.clkr.hw },
243 };
244
245 static const struct parent_map camcc_parent_map_1[] = {
246 { P_BI_TCXO, 0 },
247 { P_CAMCC_PLL0_OUT_MAIN, 1 },
248 { P_CAMCC_PLL1_OUT_EVEN, 3 },
249 { P_CAMCC_PLL2_OUT_MAIN, 4 },
250 };
251
252 static const struct clk_parent_data camcc_parent_data_1[] = {
253 { .fw_name = "bi_tcxo" },
254 { .hw = &camcc_pll0.clkr.hw },
255 { .hw = &camcc_pll1_out_even.clkr.hw },
256 { .hw = &camcc_pll2_out_main.clkr.hw },
257 };
258
259 static const struct parent_map camcc_parent_map_2[] = {
260 { P_BI_TCXO, 0 },
261 { P_CAMCC_PLL0_OUT_MAIN, 1 },
262 { P_CAMCC_PLL3_OUT_MAIN, 5 },
263 };
264
265 static const struct clk_parent_data camcc_parent_data_2[] = {
266 { .fw_name = "bi_tcxo" },
267 { .hw = &camcc_pll0.clkr.hw },
268 { .hw = &camcc_pll3.clkr.hw },
269 };
270
271 static const struct parent_map camcc_parent_map_3[] = {
272 { P_BI_TCXO, 0 },
273 { P_CAMCC_PLL2_OUT_EARLY, 3 },
274 };
275
276 static const struct clk_parent_data camcc_parent_data_3[] = {
277 { .fw_name = "bi_tcxo" },
278 { .hw = &camcc_pll2_out_early.hw },
279 };
280
281 static const struct parent_map camcc_parent_map_4[] = {
282 { P_BI_TCXO, 0 },
283 { P_CAMCC_PLL0_OUT_MAIN, 1 },
284 { P_CAMCC_PLL1_OUT_EVEN, 3 },
285 };
286
287 static const struct clk_parent_data camcc_parent_data_4[] = {
288 { .fw_name = "bi_tcxo" },
289 { .hw = &camcc_pll0.clkr.hw },
290 { .hw = &camcc_pll1_out_even.clkr.hw },
291 };
292
293 static const struct parent_map camcc_parent_map_5[] = {
294 { P_BI_TCXO, 0 },
295 { P_CAMCC_PLL0_OUT_MAIN, 1 },
296 { P_CAMCC_PLL1_OUT_EVEN, 3 },
297 { P_CAMCC_PLL3_OUT_MAIN, 5 },
298 };
299
300 static const struct clk_parent_data camcc_parent_data_5[] = {
301 { .fw_name = "bi_tcxo" },
302 { .hw = &camcc_pll0.clkr.hw },
303 { .hw = &camcc_pll1_out_even.clkr.hw },
304 { .hw = &camcc_pll3.clkr.hw },
305 };
306
307 static const struct parent_map camcc_parent_map_6[] = {
308 { P_BI_TCXO, 0 },
309 { P_CAMCC_PLL0_OUT_MAIN, 1 },
310 { P_CAMCC_PLL2_OUT_MAIN, 4 },
311 };
312
313 static const struct clk_parent_data camcc_parent_data_6[] = {
314 { .fw_name = "bi_tcxo" },
315 { .hw = &camcc_pll0.clkr.hw },
316 { .hw = &camcc_pll2_out_main.clkr.hw },
317 };
318
319 static const struct parent_map camcc_parent_map_7[] = {
320 { P_BI_TCXO, 0 },
321 { P_CAMCC_PLL0_OUT_MAIN, 1 },
322 { P_CAMCC_PLL1_OUT_MAIN, 2 },
323 { P_CAMCC_PLL2_OUT_MAIN, 4 },
324 };
325
326 static const struct clk_parent_data camcc_parent_data_7[] = {
327 { .fw_name = "bi_tcxo" },
328 { .hw = &camcc_pll0.clkr.hw },
329 { .hw = &camcc_pll1.clkr.hw },
330 { .hw = &camcc_pll2_out_main.clkr.hw },
331 };
332
333 static const struct parent_map camcc_parent_map_8[] = {
334 { P_BI_TCXO, 0 },
335 { P_CAMCC_PLL0_OUT_MAIN, 1 },
336 { P_CAMCC_PLL1_OUT_MAIN, 2 },
337 };
338
339 static const struct clk_parent_data camcc_parent_data_8[] = {
340 { .fw_name = "bi_tcxo" },
341 { .hw = &camcc_pll0.clkr.hw },
342 { .hw = &camcc_pll1.clkr.hw },
343 };
344
345 static const struct parent_map camcc_parent_map_9[] = {
346 { P_BI_TCXO, 0 },
347 { P_CAMCC_PLL2_OUT_MAIN, 4 },
348 };
349
350 static const struct clk_parent_data camcc_parent_data_9[] = {
351 { .fw_name = "bi_tcxo" },
352 { .hw = &camcc_pll2_out_main.clkr.hw },
353 };
354
355 static const struct freq_tbl ftbl_camcc_bps_clk_src[] = {
356 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
357 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
358 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
359 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
360 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
361 { }
362 };
363
364 static struct clk_rcg2 camcc_bps_clk_src = {
365 .cmd_rcgr = 0x6010,
366 .mnd_width = 0,
367 .hid_width = 5,
368 .parent_map = camcc_parent_map_1,
369 .freq_tbl = ftbl_camcc_bps_clk_src,
370 .clkr.hw.init = &(struct clk_init_data){
371 .name = "camcc_bps_clk_src",
372 .parent_data = camcc_parent_data_1,
373 .num_parents = ARRAY_SIZE(camcc_parent_data_1),
374 .ops = &clk_rcg2_ops,
375 },
376 };
377
378 static const struct freq_tbl ftbl_camcc_cci_0_clk_src[] = {
379 F(37500000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0),
380 F(50000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
381 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0),
382 { }
383 };
384
385 static struct clk_rcg2 camcc_cci_0_clk_src = {
386 .cmd_rcgr = 0xf004,
387 .mnd_width = 8,
388 .hid_width = 5,
389 .parent_map = camcc_parent_map_0,
390 .freq_tbl = ftbl_camcc_cci_0_clk_src,
391 .clkr.hw.init = &(struct clk_init_data){
392 .name = "camcc_cci_0_clk_src",
393 .parent_data = camcc_parent_data_0,
394 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
395 .ops = &clk_rcg2_ops,
396 },
397 };
398
399 static struct clk_rcg2 camcc_cci_1_clk_src = {
400 .cmd_rcgr = 0x10004,
401 .mnd_width = 8,
402 .hid_width = 5,
403 .parent_map = camcc_parent_map_0,
404 .freq_tbl = ftbl_camcc_cci_0_clk_src,
405 .clkr.hw.init = &(struct clk_init_data){
406 .name = "camcc_cci_1_clk_src",
407 .parent_data = camcc_parent_data_0,
408 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
409 .ops = &clk_rcg2_ops,
410 },
411 };
412
413 static const struct freq_tbl ftbl_camcc_cphy_rx_clk_src[] = {
414 F(150000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0),
415 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
416 F(384000000, P_CAMCC_PLL3_OUT_MAIN, 1, 0, 0),
417 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 1.5, 0, 0),
418 { }
419 };
420
421 static struct clk_rcg2 camcc_cphy_rx_clk_src = {
422 .cmd_rcgr = 0x9064,
423 .mnd_width = 0,
424 .hid_width = 5,
425 .parent_map = camcc_parent_map_2,
426 .freq_tbl = ftbl_camcc_cphy_rx_clk_src,
427 .clkr.hw.init = &(struct clk_init_data){
428 .name = "camcc_cphy_rx_clk_src",
429 .parent_data = camcc_parent_data_2,
430 .num_parents = ARRAY_SIZE(camcc_parent_data_2),
431 .ops = &clk_rcg2_ops,
432 },
433 };
434
435 static const struct freq_tbl ftbl_camcc_csi0phytimer_clk_src[] = {
436 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 1, 0, 0),
437 { }
438 };
439
440 static struct clk_rcg2 camcc_csi0phytimer_clk_src = {
441 .cmd_rcgr = 0x5004,
442 .mnd_width = 0,
443 .hid_width = 5,
444 .parent_map = camcc_parent_map_0,
445 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
446 .clkr.hw.init = &(struct clk_init_data){
447 .name = "camcc_csi0phytimer_clk_src",
448 .parent_data = camcc_parent_data_0,
449 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
450 .ops = &clk_rcg2_ops,
451 },
452 };
453
454 static struct clk_rcg2 camcc_csi1phytimer_clk_src = {
455 .cmd_rcgr = 0x5028,
456 .mnd_width = 0,
457 .hid_width = 5,
458 .parent_map = camcc_parent_map_0,
459 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
460 .clkr.hw.init = &(struct clk_init_data){
461 .name = "camcc_csi1phytimer_clk_src",
462 .parent_data = camcc_parent_data_0,
463 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
464 .ops = &clk_rcg2_ops,
465 },
466 };
467
468 static struct clk_rcg2 camcc_csi2phytimer_clk_src = {
469 .cmd_rcgr = 0x504c,
470 .mnd_width = 0,
471 .hid_width = 5,
472 .parent_map = camcc_parent_map_0,
473 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
474 .clkr.hw.init = &(struct clk_init_data){
475 .name = "camcc_csi2phytimer_clk_src",
476 .parent_data = camcc_parent_data_0,
477 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
478 .ops = &clk_rcg2_ops,
479 },
480 };
481
482 static struct clk_rcg2 camcc_csi3phytimer_clk_src = {
483 .cmd_rcgr = 0x5070,
484 .mnd_width = 0,
485 .hid_width = 5,
486 .parent_map = camcc_parent_map_0,
487 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
488 .clkr.hw.init = &(struct clk_init_data){
489 .name = "camcc_csi3phytimer_clk_src",
490 .parent_data = camcc_parent_data_0,
491 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
492 .ops = &clk_rcg2_ops,
493 },
494 };
495
496 static const struct freq_tbl ftbl_camcc_fast_ahb_clk_src[] = {
497 F(100000000, P_CAMCC_PLL0_OUT_MAIN, 6, 0, 0),
498 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
499 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
500 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
501 { }
502 };
503
504 static struct clk_rcg2 camcc_fast_ahb_clk_src = {
505 .cmd_rcgr = 0x603c,
506 .mnd_width = 0,
507 .hid_width = 5,
508 .parent_map = camcc_parent_map_4,
509 .freq_tbl = ftbl_camcc_fast_ahb_clk_src,
510 .clkr.hw.init = &(struct clk_init_data){
511 .name = "camcc_fast_ahb_clk_src",
512 .parent_data = camcc_parent_data_4,
513 .num_parents = ARRAY_SIZE(camcc_parent_data_4),
514 .ops = &clk_rcg2_ops,
515 },
516 };
517
518 static const struct freq_tbl ftbl_camcc_icp_clk_src[] = {
519 F(240000000, P_CAMCC_PLL0_OUT_MAIN, 2.5, 0, 0),
520 F(384000000, P_CAMCC_PLL3_OUT_MAIN, 1, 0, 0),
521 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
522 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
523 { }
524 };
525
526 static struct clk_rcg2 camcc_icp_clk_src = {
527 .cmd_rcgr = 0xe014,
528 .mnd_width = 0,
529 .hid_width = 5,
530 .parent_map = camcc_parent_map_5,
531 .freq_tbl = ftbl_camcc_icp_clk_src,
532 .clkr.hw.init = &(struct clk_init_data){
533 .name = "camcc_icp_clk_src",
534 .parent_data = camcc_parent_data_5,
535 .num_parents = ARRAY_SIZE(camcc_parent_data_5),
536 .ops = &clk_rcg2_ops,
537 },
538 };
539
540 static const struct freq_tbl ftbl_camcc_ife_0_clk_src[] = {
541 F(240000000, P_CAMCC_PLL0_OUT_MAIN, 2.5, 0, 0),
542 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
543 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
544 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
545 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
546 { }
547 };
548
549 static struct clk_rcg2 camcc_ife_0_clk_src = {
550 .cmd_rcgr = 0x9010,
551 .mnd_width = 0,
552 .hid_width = 5,
553 .parent_map = camcc_parent_map_1,
554 .freq_tbl = ftbl_camcc_ife_0_clk_src,
555 .clkr.hw.init = &(struct clk_init_data){
556 .name = "camcc_ife_0_clk_src",
557 .parent_data = camcc_parent_data_1,
558 .num_parents = ARRAY_SIZE(camcc_parent_data_1),
559 .flags = CLK_SET_RATE_PARENT,
560 .ops = &clk_rcg2_ops,
561 },
562 };
563
564 static struct clk_rcg2 camcc_ife_0_csid_clk_src = {
565 .cmd_rcgr = 0x903c,
566 .mnd_width = 0,
567 .hid_width = 5,
568 .parent_map = camcc_parent_map_2,
569 .freq_tbl = ftbl_camcc_cphy_rx_clk_src,
570 .clkr.hw.init = &(struct clk_init_data){
571 .name = "camcc_ife_0_csid_clk_src",
572 .parent_data = camcc_parent_data_2,
573 .num_parents = ARRAY_SIZE(camcc_parent_data_2),
574 .ops = &clk_rcg2_ops,
575 },
576 };
577
578 static struct clk_rcg2 camcc_ife_1_clk_src = {
579 .cmd_rcgr = 0xa010,
580 .mnd_width = 0,
581 .hid_width = 5,
582 .parent_map = camcc_parent_map_1,
583 .freq_tbl = ftbl_camcc_ife_0_clk_src,
584 .clkr.hw.init = &(struct clk_init_data){
585 .name = "camcc_ife_1_clk_src",
586 .parent_data = camcc_parent_data_1,
587 .num_parents = ARRAY_SIZE(camcc_parent_data_1),
588 .flags = CLK_SET_RATE_PARENT,
589 .ops = &clk_rcg2_ops,
590 },
591 };
592
593 static struct clk_rcg2 camcc_ife_1_csid_clk_src = {
594 .cmd_rcgr = 0xa034,
595 .mnd_width = 0,
596 .hid_width = 5,
597 .parent_map = camcc_parent_map_2,
598 .freq_tbl = ftbl_camcc_cphy_rx_clk_src,
599 .clkr.hw.init = &(struct clk_init_data){
600 .name = "camcc_ife_1_csid_clk_src",
601 .parent_data = camcc_parent_data_2,
602 .num_parents = ARRAY_SIZE(camcc_parent_data_2),
603 .ops = &clk_rcg2_ops,
604 },
605 };
606
607 static struct clk_rcg2 camcc_ife_2_clk_src = {
608 .cmd_rcgr = 0xb00c,
609 .mnd_width = 0,
610 .hid_width = 5,
611 .parent_map = camcc_parent_map_1,
612 .freq_tbl = ftbl_camcc_ife_0_clk_src,
613 .clkr.hw.init = &(struct clk_init_data){
614 .name = "camcc_ife_2_clk_src",
615 .parent_data = camcc_parent_data_1,
616 .num_parents = ARRAY_SIZE(camcc_parent_data_1),
617 .ops = &clk_rcg2_ops,
618 },
619 };
620
621 static struct clk_rcg2 camcc_ife_2_csid_clk_src = {
622 .cmd_rcgr = 0xb030,
623 .mnd_width = 0,
624 .hid_width = 5,
625 .parent_map = camcc_parent_map_2,
626 .freq_tbl = ftbl_camcc_cphy_rx_clk_src,
627 .clkr.hw.init = &(struct clk_init_data){
628 .name = "camcc_ife_2_csid_clk_src",
629 .parent_data = camcc_parent_data_2,
630 .num_parents = ARRAY_SIZE(camcc_parent_data_2),
631 .ops = &clk_rcg2_ops,
632 },
633 };
634
635 static const struct freq_tbl ftbl_camcc_ife_lite_clk_src[] = {
636 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
637 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 1.5, 0, 0),
638 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
639 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
640 { }
641 };
642
643 static struct clk_rcg2 camcc_ife_lite_clk_src = {
644 .cmd_rcgr = 0xc004,
645 .mnd_width = 0,
646 .hid_width = 5,
647 .parent_map = camcc_parent_map_6,
648 .freq_tbl = ftbl_camcc_ife_lite_clk_src,
649 .clkr.hw.init = &(struct clk_init_data){
650 .name = "camcc_ife_lite_clk_src",
651 .parent_data = camcc_parent_data_6,
652 .num_parents = ARRAY_SIZE(camcc_parent_data_6),
653 .ops = &clk_rcg2_ops,
654 },
655 };
656
657 static struct clk_rcg2 camcc_ife_lite_csid_clk_src = {
658 .cmd_rcgr = 0xc024,
659 .mnd_width = 0,
660 .hid_width = 5,
661 .parent_map = camcc_parent_map_2,
662 .freq_tbl = ftbl_camcc_cphy_rx_clk_src,
663 .clkr.hw.init = &(struct clk_init_data){
664 .name = "camcc_ife_lite_csid_clk_src",
665 .parent_data = camcc_parent_data_2,
666 .num_parents = ARRAY_SIZE(camcc_parent_data_2),
667 .ops = &clk_rcg2_ops,
668 },
669 };
670
671 static const struct freq_tbl ftbl_camcc_ipe_0_clk_src[] = {
672 F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0),
673 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
674 F(404000000, P_CAMCC_PLL1_OUT_MAIN, 2, 0, 0),
675 F(538666667, P_CAMCC_PLL1_OUT_MAIN, 1.5, 0, 0),
676 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
677 { }
678 };
679
680 static struct clk_rcg2 camcc_ipe_0_clk_src = {
681 .cmd_rcgr = 0x7010,
682 .mnd_width = 0,
683 .hid_width = 5,
684 .parent_map = camcc_parent_map_7,
685 .freq_tbl = ftbl_camcc_ipe_0_clk_src,
686 .clkr.hw.init = &(struct clk_init_data){
687 .name = "camcc_ipe_0_clk_src",
688 .parent_data = camcc_parent_data_7,
689 .num_parents = ARRAY_SIZE(camcc_parent_data_7),
690 .flags = CLK_SET_RATE_PARENT,
691 .ops = &clk_rcg2_ops,
692 },
693 };
694
695 static const struct freq_tbl ftbl_camcc_jpeg_clk_src[] = {
696 F(66666667, P_CAMCC_PLL0_OUT_MAIN, 9, 0, 0),
697 F(133333333, P_CAMCC_PLL0_OUT_MAIN, 4.5, 0, 0),
698 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
699 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
700 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
701 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
702 { }
703 };
704
705 static struct clk_rcg2 camcc_jpeg_clk_src = {
706 .cmd_rcgr = 0xd004,
707 .mnd_width = 0,
708 .hid_width = 5,
709 .parent_map = camcc_parent_map_1,
710 .freq_tbl = ftbl_camcc_jpeg_clk_src,
711 .clkr.hw.init = &(struct clk_init_data){
712 .name = "camcc_jpeg_clk_src",
713 .parent_data = camcc_parent_data_1,
714 .num_parents = ARRAY_SIZE(camcc_parent_data_1),
715 .ops = &clk_rcg2_ops,
716 },
717 };
718
719 static const struct freq_tbl ftbl_camcc_lrme_clk_src[] = {
720 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
721 F(269333333, P_CAMCC_PLL1_OUT_MAIN, 3, 0, 0),
722 F(323200000, P_CAMCC_PLL1_OUT_MAIN, 2.5, 0, 0),
723 F(404000000, P_CAMCC_PLL1_OUT_MAIN, 2, 0, 0),
724 { }
725 };
726
727 static struct clk_rcg2 camcc_lrme_clk_src = {
728 .cmd_rcgr = 0x11004,
729 .mnd_width = 0,
730 .hid_width = 5,
731 .parent_map = camcc_parent_map_8,
732 .freq_tbl = ftbl_camcc_lrme_clk_src,
733 .clkr.hw.init = &(struct clk_init_data){
734 .name = "camcc_lrme_clk_src",
735 .parent_data = camcc_parent_data_8,
736 .num_parents = ARRAY_SIZE(camcc_parent_data_8),
737 .ops = &clk_rcg2_ops,
738 },
739 };
740
741 static const struct freq_tbl ftbl_camcc_mclk0_clk_src[] = {
742 F(19200000, P_CAMCC_PLL2_OUT_EARLY, 1, 1, 50),
743 F(24000000, P_CAMCC_PLL2_OUT_EARLY, 10, 1, 4),
744 F(64000000, P_CAMCC_PLL2_OUT_EARLY, 15, 0, 0),
745 { }
746 };
747
748 static struct clk_rcg2 camcc_mclk0_clk_src = {
749 .cmd_rcgr = 0x4004,
750 .mnd_width = 8,
751 .hid_width = 5,
752 .parent_map = camcc_parent_map_3,
753 .freq_tbl = ftbl_camcc_mclk0_clk_src,
754 .clkr.hw.init = &(struct clk_init_data){
755 .name = "camcc_mclk0_clk_src",
756 .parent_data = camcc_parent_data_3,
757 .num_parents = ARRAY_SIZE(camcc_parent_data_3),
758 .ops = &clk_rcg2_ops,
759 },
760 };
761
762 static struct clk_rcg2 camcc_mclk1_clk_src = {
763 .cmd_rcgr = 0x4024,
764 .mnd_width = 8,
765 .hid_width = 5,
766 .parent_map = camcc_parent_map_3,
767 .freq_tbl = ftbl_camcc_mclk0_clk_src,
768 .clkr.hw.init = &(struct clk_init_data){
769 .name = "camcc_mclk1_clk_src",
770 .parent_data = camcc_parent_data_3,
771 .num_parents = ARRAY_SIZE(camcc_parent_data_3),
772 .ops = &clk_rcg2_ops,
773 },
774 };
775
776 static struct clk_rcg2 camcc_mclk2_clk_src = {
777 .cmd_rcgr = 0x4044,
778 .mnd_width = 8,
779 .hid_width = 5,
780 .parent_map = camcc_parent_map_3,
781 .freq_tbl = ftbl_camcc_mclk0_clk_src,
782 .clkr.hw.init = &(struct clk_init_data){
783 .name = "camcc_mclk2_clk_src",
784 .parent_data = camcc_parent_data_3,
785 .num_parents = ARRAY_SIZE(camcc_parent_data_3),
786 .ops = &clk_rcg2_ops,
787 },
788 };
789
790 static struct clk_rcg2 camcc_mclk3_clk_src = {
791 .cmd_rcgr = 0x4064,
792 .mnd_width = 8,
793 .hid_width = 5,
794 .parent_map = camcc_parent_map_3,
795 .freq_tbl = ftbl_camcc_mclk0_clk_src,
796 .clkr.hw.init = &(struct clk_init_data){
797 .name = "camcc_mclk3_clk_src",
798 .parent_data = camcc_parent_data_3,
799 .num_parents = ARRAY_SIZE(camcc_parent_data_3),
800 .ops = &clk_rcg2_ops,
801 },
802 };
803
804 static struct clk_rcg2 camcc_mclk4_clk_src = {
805 .cmd_rcgr = 0x4084,
806 .mnd_width = 8,
807 .hid_width = 5,
808 .parent_map = camcc_parent_map_3,
809 .freq_tbl = ftbl_camcc_mclk0_clk_src,
810 .clkr.hw.init = &(struct clk_init_data){
811 .name = "camcc_mclk4_clk_src",
812 .parent_data = camcc_parent_data_3,
813 .num_parents = ARRAY_SIZE(camcc_parent_data_3),
814 .ops = &clk_rcg2_ops,
815 },
816 };
817
818 static const struct freq_tbl ftbl_camcc_slow_ahb_clk_src[] = {
819 F(80000000, P_CAMCC_PLL2_OUT_MAIN, 6, 0, 0),
820 { }
821 };
822
823 static struct clk_rcg2 camcc_slow_ahb_clk_src = {
824 .cmd_rcgr = 0x6058,
825 .mnd_width = 0,
826 .hid_width = 5,
827 .parent_map = camcc_parent_map_9,
828 .freq_tbl = ftbl_camcc_slow_ahb_clk_src,
829 .clkr.hw.init = &(struct clk_init_data){
830 .name = "camcc_slow_ahb_clk_src",
831 .parent_data = camcc_parent_data_9,
832 .num_parents = ARRAY_SIZE(camcc_parent_data_9),
833 .ops = &clk_rcg2_ops,
834 },
835 };
836
837 static struct clk_branch camcc_bps_ahb_clk = {
838 .halt_reg = 0x6070,
839 .halt_check = BRANCH_HALT,
840 .clkr = {
841 .enable_reg = 0x6070,
842 .enable_mask = BIT(0),
843 .hw.init = &(struct clk_init_data){
844 .name = "camcc_bps_ahb_clk",
845 .parent_hws = (const struct clk_hw*[]){
846 &camcc_slow_ahb_clk_src.clkr.hw
847 },
848 .num_parents = 1,
849 .flags = CLK_SET_RATE_PARENT,
850 .ops = &clk_branch2_ops,
851 },
852 },
853 };
854
855 static struct clk_branch camcc_bps_areg_clk = {
856 .halt_reg = 0x6054,
857 .halt_check = BRANCH_HALT,
858 .clkr = {
859 .enable_reg = 0x6054,
860 .enable_mask = BIT(0),
861 .hw.init = &(struct clk_init_data){
862 .name = "camcc_bps_areg_clk",
863 .parent_hws = (const struct clk_hw*[]){
864 &camcc_fast_ahb_clk_src.clkr.hw
865 },
866 .num_parents = 1,
867 .flags = CLK_SET_RATE_PARENT,
868 .ops = &clk_branch2_ops,
869 },
870 },
871 };
872
873 static struct clk_branch camcc_bps_axi_clk = {
874 .halt_reg = 0x6038,
875 .halt_check = BRANCH_HALT,
876 .clkr = {
877 .enable_reg = 0x6038,
878 .enable_mask = BIT(0),
879 .hw.init = &(struct clk_init_data){
880 .name = "camcc_bps_axi_clk",
881 .ops = &clk_branch2_ops,
882 },
883 },
884 };
885
886 static struct clk_branch camcc_bps_clk = {
887 .halt_reg = 0x6028,
888 .halt_check = BRANCH_HALT,
889 .clkr = {
890 .enable_reg = 0x6028,
891 .enable_mask = BIT(0),
892 .hw.init = &(struct clk_init_data){
893 .name = "camcc_bps_clk",
894 .parent_hws = (const struct clk_hw*[]){
895 &camcc_bps_clk_src.clkr.hw
896 },
897 .num_parents = 1,
898 .flags = CLK_SET_RATE_PARENT,
899 .ops = &clk_branch2_ops,
900 },
901 },
902 };
903
904 static struct clk_branch camcc_camnoc_axi_clk = {
905 .halt_reg = 0x13004,
906 .halt_check = BRANCH_HALT,
907 .clkr = {
908 .enable_reg = 0x13004,
909 .enable_mask = BIT(0),
910 .hw.init = &(struct clk_init_data){
911 .name = "camcc_camnoc_axi_clk",
912 .ops = &clk_branch2_ops,
913 },
914 },
915 };
916
917 static struct clk_branch camcc_cci_0_clk = {
918 .halt_reg = 0xf01c,
919 .halt_check = BRANCH_HALT,
920 .clkr = {
921 .enable_reg = 0xf01c,
922 .enable_mask = BIT(0),
923 .hw.init = &(struct clk_init_data){
924 .name = "camcc_cci_0_clk",
925 .parent_hws = (const struct clk_hw*[]){
926 &camcc_cci_0_clk_src.clkr.hw
927 },
928 .num_parents = 1,
929 .flags = CLK_SET_RATE_PARENT,
930 .ops = &clk_branch2_ops,
931 },
932 },
933 };
934
935 static struct clk_branch camcc_cci_1_clk = {
936 .halt_reg = 0x1001c,
937 .halt_check = BRANCH_HALT,
938 .clkr = {
939 .enable_reg = 0x1001c,
940 .enable_mask = BIT(0),
941 .hw.init = &(struct clk_init_data){
942 .name = "camcc_cci_1_clk",
943 .parent_hws = (const struct clk_hw*[]){
944 &camcc_cci_1_clk_src.clkr.hw
945 },
946 .num_parents = 1,
947 .flags = CLK_SET_RATE_PARENT,
948 .ops = &clk_branch2_ops,
949 },
950 },
951 };
952
953 static struct clk_branch camcc_core_ahb_clk = {
954 .halt_reg = 0x14010,
955 .halt_check = BRANCH_HALT_VOTED,
956 .clkr = {
957 .enable_reg = 0x14010,
958 .enable_mask = BIT(0),
959 .hw.init = &(struct clk_init_data){
960 .name = "camcc_core_ahb_clk",
961 .parent_hws = (const struct clk_hw*[]){
962 &camcc_slow_ahb_clk_src.clkr.hw
963 },
964 .num_parents = 1,
965 .flags = CLK_SET_RATE_PARENT,
966 .ops = &clk_branch2_ops,
967 },
968 },
969 };
970
971 static struct clk_branch camcc_cpas_ahb_clk = {
972 .halt_reg = 0x12004,
973 .halt_check = BRANCH_HALT,
974 .clkr = {
975 .enable_reg = 0x12004,
976 .enable_mask = BIT(0),
977 .hw.init = &(struct clk_init_data){
978 .name = "camcc_cpas_ahb_clk",
979 .parent_hws = (const struct clk_hw*[]){
980 &camcc_slow_ahb_clk_src.clkr.hw
981 },
982 .num_parents = 1,
983 .flags = CLK_SET_RATE_PARENT,
984 .ops = &clk_branch2_ops,
985 },
986 },
987 };
988
989 static struct clk_branch camcc_csi0phytimer_clk = {
990 .halt_reg = 0x501c,
991 .halt_check = BRANCH_HALT,
992 .clkr = {
993 .enable_reg = 0x501c,
994 .enable_mask = BIT(0),
995 .hw.init = &(struct clk_init_data){
996 .name = "camcc_csi0phytimer_clk",
997 .parent_hws = (const struct clk_hw*[]){
998 &camcc_csi0phytimer_clk_src.clkr.hw
999 },
1000 .num_parents = 1,
1001 .flags = CLK_SET_RATE_PARENT,
1002 .ops = &clk_branch2_ops,
1003 },
1004 },
1005 };
1006
1007 static struct clk_branch camcc_csi1phytimer_clk = {
1008 .halt_reg = 0x5040,
1009 .halt_check = BRANCH_HALT,
1010 .clkr = {
1011 .enable_reg = 0x5040,
1012 .enable_mask = BIT(0),
1013 .hw.init = &(struct clk_init_data){
1014 .name = "camcc_csi1phytimer_clk",
1015 .parent_hws = (const struct clk_hw*[]){
1016 &camcc_csi1phytimer_clk_src.clkr.hw
1017 },
1018 .num_parents = 1,
1019 .flags = CLK_SET_RATE_PARENT,
1020 .ops = &clk_branch2_ops,
1021 },
1022 },
1023 };
1024
1025 static struct clk_branch camcc_csi2phytimer_clk = {
1026 .halt_reg = 0x5064,
1027 .halt_check = BRANCH_HALT,
1028 .clkr = {
1029 .enable_reg = 0x5064,
1030 .enable_mask = BIT(0),
1031 .hw.init = &(struct clk_init_data){
1032 .name = "camcc_csi2phytimer_clk",
1033 .parent_hws = (const struct clk_hw*[]){
1034 &camcc_csi2phytimer_clk_src.clkr.hw
1035 },
1036 .num_parents = 1,
1037 .flags = CLK_SET_RATE_PARENT,
1038 .ops = &clk_branch2_ops,
1039 },
1040 },
1041 };
1042
1043 static struct clk_branch camcc_csi3phytimer_clk = {
1044 .halt_reg = 0x5088,
1045 .halt_check = BRANCH_HALT,
1046 .clkr = {
1047 .enable_reg = 0x5088,
1048 .enable_mask = BIT(0),
1049 .hw.init = &(struct clk_init_data){
1050 .name = "camcc_csi3phytimer_clk",
1051 .parent_hws = (const struct clk_hw*[]){
1052 &camcc_csi3phytimer_clk_src.clkr.hw
1053 },
1054 .num_parents = 1,
1055 .flags = CLK_SET_RATE_PARENT,
1056 .ops = &clk_branch2_ops,
1057 },
1058 },
1059 };
1060
1061 static struct clk_branch camcc_csiphy0_clk = {
1062 .halt_reg = 0x5020,
1063 .halt_check = BRANCH_HALT,
1064 .clkr = {
1065 .enable_reg = 0x5020,
1066 .enable_mask = BIT(0),
1067 .hw.init = &(struct clk_init_data){
1068 .name = "camcc_csiphy0_clk",
1069 .parent_hws = (const struct clk_hw*[]){
1070 &camcc_cphy_rx_clk_src.clkr.hw
1071 },
1072 .num_parents = 1,
1073 .flags = CLK_SET_RATE_PARENT,
1074 .ops = &clk_branch2_ops,
1075 },
1076 },
1077 };
1078
1079 static struct clk_branch camcc_csiphy1_clk = {
1080 .halt_reg = 0x5044,
1081 .halt_check = BRANCH_HALT,
1082 .clkr = {
1083 .enable_reg = 0x5044,
1084 .enable_mask = BIT(0),
1085 .hw.init = &(struct clk_init_data){
1086 .name = "camcc_csiphy1_clk",
1087 .parent_hws = (const struct clk_hw*[]){
1088 &camcc_cphy_rx_clk_src.clkr.hw
1089 },
1090 .num_parents = 1,
1091 .flags = CLK_SET_RATE_PARENT,
1092 .ops = &clk_branch2_ops,
1093 },
1094 },
1095 };
1096
1097 static struct clk_branch camcc_csiphy2_clk = {
1098 .halt_reg = 0x5068,
1099 .halt_check = BRANCH_HALT,
1100 .clkr = {
1101 .enable_reg = 0x5068,
1102 .enable_mask = BIT(0),
1103 .hw.init = &(struct clk_init_data){
1104 .name = "camcc_csiphy2_clk",
1105 .parent_hws = (const struct clk_hw*[]){
1106 &camcc_cphy_rx_clk_src.clkr.hw
1107 },
1108 .num_parents = 1,
1109 .flags = CLK_SET_RATE_PARENT,
1110 .ops = &clk_branch2_ops,
1111 },
1112 },
1113 };
1114
1115 static struct clk_branch camcc_csiphy3_clk = {
1116 .halt_reg = 0x508c,
1117 .halt_check = BRANCH_HALT,
1118 .clkr = {
1119 .enable_reg = 0x508c,
1120 .enable_mask = BIT(0),
1121 .hw.init = &(struct clk_init_data){
1122 .name = "camcc_csiphy3_clk",
1123 .parent_hws = (const struct clk_hw*[]){
1124 &camcc_cphy_rx_clk_src.clkr.hw
1125 },
1126 .num_parents = 1,
1127 .flags = CLK_SET_RATE_PARENT,
1128 .ops = &clk_branch2_ops,
1129 },
1130 },
1131 };
1132
1133 static struct clk_branch camcc_icp_clk = {
1134 .halt_reg = 0xe02c,
1135 .halt_check = BRANCH_HALT,
1136 .clkr = {
1137 .enable_reg = 0xe02c,
1138 .enable_mask = BIT(0),
1139 .hw.init = &(struct clk_init_data){
1140 .name = "camcc_icp_clk",
1141 .parent_hws = (const struct clk_hw*[]){
1142 &camcc_icp_clk_src.clkr.hw
1143 },
1144 .num_parents = 1,
1145 .flags = CLK_SET_RATE_PARENT,
1146 .ops = &clk_branch2_ops,
1147 },
1148 },
1149 };
1150
1151 static struct clk_branch camcc_icp_ts_clk = {
1152 .halt_reg = 0xe00c,
1153 .halt_check = BRANCH_HALT,
1154 .clkr = {
1155 .enable_reg = 0xe00c,
1156 .enable_mask = BIT(0),
1157 .hw.init = &(struct clk_init_data){
1158 .name = "camcc_icp_ts_clk",
1159 .ops = &clk_branch2_ops,
1160 },
1161 },
1162 };
1163
1164 static struct clk_branch camcc_ife_0_axi_clk = {
1165 .halt_reg = 0x9080,
1166 .halt_check = BRANCH_HALT,
1167 .clkr = {
1168 .enable_reg = 0x9080,
1169 .enable_mask = BIT(0),
1170 .hw.init = &(struct clk_init_data){
1171 .name = "camcc_ife_0_axi_clk",
1172 .ops = &clk_branch2_ops,
1173 },
1174 },
1175 };
1176
1177 static struct clk_branch camcc_ife_0_clk = {
1178 .halt_reg = 0x9028,
1179 .halt_check = BRANCH_HALT,
1180 .clkr = {
1181 .enable_reg = 0x9028,
1182 .enable_mask = BIT(0),
1183 .hw.init = &(struct clk_init_data){
1184 .name = "camcc_ife_0_clk",
1185 .parent_hws = (const struct clk_hw*[]){
1186 &camcc_ife_0_clk_src.clkr.hw
1187 },
1188 .num_parents = 1,
1189 .flags = CLK_SET_RATE_PARENT,
1190 .ops = &clk_branch2_ops,
1191 },
1192 },
1193 };
1194
1195 static struct clk_branch camcc_ife_0_cphy_rx_clk = {
1196 .halt_reg = 0x907c,
1197 .halt_check = BRANCH_HALT,
1198 .clkr = {
1199 .enable_reg = 0x907c,
1200 .enable_mask = BIT(0),
1201 .hw.init = &(struct clk_init_data){
1202 .name = "camcc_ife_0_cphy_rx_clk",
1203 .parent_hws = (const struct clk_hw*[]){
1204 &camcc_cphy_rx_clk_src.clkr.hw
1205 },
1206 .num_parents = 1,
1207 .flags = CLK_SET_RATE_PARENT,
1208 .ops = &clk_branch2_ops,
1209 },
1210 },
1211 };
1212
1213 static struct clk_branch camcc_ife_0_csid_clk = {
1214 .halt_reg = 0x9054,
1215 .halt_check = BRANCH_HALT,
1216 .clkr = {
1217 .enable_reg = 0x9054,
1218 .enable_mask = BIT(0),
1219 .hw.init = &(struct clk_init_data){
1220 .name = "camcc_ife_0_csid_clk",
1221 .parent_hws = (const struct clk_hw*[]){
1222 &camcc_ife_0_csid_clk_src.clkr.hw
1223 },
1224 .num_parents = 1,
1225 .flags = CLK_SET_RATE_PARENT,
1226 .ops = &clk_branch2_ops,
1227 },
1228 },
1229 };
1230
1231 static struct clk_branch camcc_ife_0_dsp_clk = {
1232 .halt_reg = 0x9038,
1233 .halt_check = BRANCH_HALT,
1234 .clkr = {
1235 .enable_reg = 0x9038,
1236 .enable_mask = BIT(0),
1237 .hw.init = &(struct clk_init_data){
1238 .name = "camcc_ife_0_dsp_clk",
1239 .parent_hws = (const struct clk_hw*[]){
1240 &camcc_ife_0_clk_src.clkr.hw
1241 },
1242 .num_parents = 1,
1243 .flags = CLK_SET_RATE_PARENT,
1244 .ops = &clk_branch2_ops,
1245 },
1246 },
1247 };
1248
1249 static struct clk_branch camcc_ife_1_axi_clk = {
1250 .halt_reg = 0xa058,
1251 .halt_check = BRANCH_HALT,
1252 .clkr = {
1253 .enable_reg = 0xa058,
1254 .enable_mask = BIT(0),
1255 .hw.init = &(struct clk_init_data){
1256 .name = "camcc_ife_1_axi_clk",
1257 .ops = &clk_branch2_ops,
1258 },
1259 },
1260 };
1261
1262 static struct clk_branch camcc_ife_1_clk = {
1263 .halt_reg = 0xa028,
1264 .halt_check = BRANCH_HALT,
1265 .clkr = {
1266 .enable_reg = 0xa028,
1267 .enable_mask = BIT(0),
1268 .hw.init = &(struct clk_init_data){
1269 .name = "camcc_ife_1_clk",
1270 .parent_hws = (const struct clk_hw*[]){
1271 &camcc_ife_1_clk_src.clkr.hw
1272 },
1273 .num_parents = 1,
1274 .flags = CLK_SET_RATE_PARENT,
1275 .ops = &clk_branch2_ops,
1276 },
1277 },
1278 };
1279
1280 static struct clk_branch camcc_ife_1_cphy_rx_clk = {
1281 .halt_reg = 0xa054,
1282 .halt_check = BRANCH_HALT,
1283 .clkr = {
1284 .enable_reg = 0xa054,
1285 .enable_mask = BIT(0),
1286 .hw.init = &(struct clk_init_data){
1287 .name = "camcc_ife_1_cphy_rx_clk",
1288 .parent_hws = (const struct clk_hw*[]){
1289 &camcc_cphy_rx_clk_src.clkr.hw
1290 },
1291 .num_parents = 1,
1292 .flags = CLK_SET_RATE_PARENT,
1293 .ops = &clk_branch2_ops,
1294 },
1295 },
1296 };
1297
1298 static struct clk_branch camcc_ife_1_csid_clk = {
1299 .halt_reg = 0xa04c,
1300 .halt_check = BRANCH_HALT,
1301 .clkr = {
1302 .enable_reg = 0xa04c,
1303 .enable_mask = BIT(0),
1304 .hw.init = &(struct clk_init_data){
1305 .name = "camcc_ife_1_csid_clk",
1306 .parent_hws = (const struct clk_hw*[]){
1307 &camcc_ife_1_csid_clk_src.clkr.hw
1308 },
1309 .num_parents = 1,
1310 .flags = CLK_SET_RATE_PARENT,
1311 .ops = &clk_branch2_ops,
1312 },
1313 },
1314 };
1315
1316 static struct clk_branch camcc_ife_1_dsp_clk = {
1317 .halt_reg = 0xa030,
1318 .halt_check = BRANCH_HALT,
1319 .clkr = {
1320 .enable_reg = 0xa030,
1321 .enable_mask = BIT(0),
1322 .hw.init = &(struct clk_init_data){
1323 .name = "camcc_ife_1_dsp_clk",
1324 .parent_hws = (const struct clk_hw*[]){
1325 &camcc_ife_1_clk_src.clkr.hw
1326 },
1327 .num_parents = 1,
1328 .flags = CLK_SET_RATE_PARENT,
1329 .ops = &clk_branch2_ops,
1330 },
1331 },
1332 };
1333
1334 static struct clk_branch camcc_ife_2_axi_clk = {
1335 .halt_reg = 0xb054,
1336 .halt_check = BRANCH_HALT,
1337 .clkr = {
1338 .enable_reg = 0xb054,
1339 .enable_mask = BIT(0),
1340 .hw.init = &(struct clk_init_data){
1341 .name = "camcc_ife_2_axi_clk",
1342 .ops = &clk_branch2_ops,
1343 },
1344 },
1345 };
1346
1347 static struct clk_branch camcc_ife_2_clk = {
1348 .halt_reg = 0xb024,
1349 .halt_check = BRANCH_HALT,
1350 .clkr = {
1351 .enable_reg = 0xb024,
1352 .enable_mask = BIT(0),
1353 .hw.init = &(struct clk_init_data){
1354 .name = "camcc_ife_2_clk",
1355 .parent_hws = (const struct clk_hw*[]){
1356 &camcc_ife_2_clk_src.clkr.hw
1357 },
1358 .num_parents = 1,
1359 .flags = CLK_SET_RATE_PARENT,
1360 .ops = &clk_branch2_ops,
1361 },
1362 },
1363 };
1364
1365 static struct clk_branch camcc_ife_2_cphy_rx_clk = {
1366 .halt_reg = 0xb050,
1367 .halt_check = BRANCH_HALT,
1368 .clkr = {
1369 .enable_reg = 0xb050,
1370 .enable_mask = BIT(0),
1371 .hw.init = &(struct clk_init_data){
1372 .name = "camcc_ife_2_cphy_rx_clk",
1373 .parent_hws = (const struct clk_hw*[]){
1374 &camcc_cphy_rx_clk_src.clkr.hw
1375 },
1376 .num_parents = 1,
1377 .flags = CLK_SET_RATE_PARENT,
1378 .ops = &clk_branch2_ops,
1379 },
1380 },
1381 };
1382
1383 static struct clk_branch camcc_ife_2_csid_clk = {
1384 .halt_reg = 0xb048,
1385 .halt_check = BRANCH_HALT,
1386 .clkr = {
1387 .enable_reg = 0xb048,
1388 .enable_mask = BIT(0),
1389 .hw.init = &(struct clk_init_data){
1390 .name = "camcc_ife_2_csid_clk",
1391 .parent_hws = (const struct clk_hw*[]){
1392 &camcc_ife_2_csid_clk_src.clkr.hw
1393 },
1394 .num_parents = 1,
1395 .flags = CLK_SET_RATE_PARENT,
1396 .ops = &clk_branch2_ops,
1397 },
1398 },
1399 };
1400
1401 static struct clk_branch camcc_ife_2_dsp_clk = {
1402 .halt_reg = 0xb02c,
1403 .halt_check = BRANCH_HALT,
1404 .clkr = {
1405 .enable_reg = 0xb02c,
1406 .enable_mask = BIT(0),
1407 .hw.init = &(struct clk_init_data){
1408 .name = "camcc_ife_2_dsp_clk",
1409 .parent_hws = (const struct clk_hw*[]){
1410 &camcc_ife_2_clk_src.clkr.hw
1411 },
1412 .num_parents = 1,
1413 .flags = CLK_SET_RATE_PARENT,
1414 .ops = &clk_branch2_ops,
1415 },
1416 },
1417 };
1418
1419 static struct clk_branch camcc_ife_lite_clk = {
1420 .halt_reg = 0xc01c,
1421 .halt_check = BRANCH_HALT,
1422 .clkr = {
1423 .enable_reg = 0xc01c,
1424 .enable_mask = BIT(0),
1425 .hw.init = &(struct clk_init_data){
1426 .name = "camcc_ife_lite_clk",
1427 .parent_hws = (const struct clk_hw*[]){
1428 &camcc_ife_lite_clk_src.clkr.hw
1429 },
1430 .num_parents = 1,
1431 .flags = CLK_SET_RATE_PARENT,
1432 .ops = &clk_branch2_ops,
1433 },
1434 },
1435 };
1436
1437 static struct clk_branch camcc_ife_lite_cphy_rx_clk = {
1438 .halt_reg = 0xc044,
1439 .halt_check = BRANCH_HALT,
1440 .clkr = {
1441 .enable_reg = 0xc044,
1442 .enable_mask = BIT(0),
1443 .hw.init = &(struct clk_init_data){
1444 .name = "camcc_ife_lite_cphy_rx_clk",
1445 .parent_hws = (const struct clk_hw*[]){
1446 &camcc_cphy_rx_clk_src.clkr.hw
1447 },
1448 .num_parents = 1,
1449 .flags = CLK_SET_RATE_PARENT,
1450 .ops = &clk_branch2_ops,
1451 },
1452 },
1453 };
1454
1455 static struct clk_branch camcc_ife_lite_csid_clk = {
1456 .halt_reg = 0xc03c,
1457 .halt_check = BRANCH_HALT,
1458 .clkr = {
1459 .enable_reg = 0xc03c,
1460 .enable_mask = BIT(0),
1461 .hw.init = &(struct clk_init_data){
1462 .name = "camcc_ife_lite_csid_clk",
1463 .parent_hws = (const struct clk_hw*[]){
1464 &camcc_ife_lite_csid_clk_src.clkr.hw
1465 },
1466 .num_parents = 1,
1467 .flags = CLK_SET_RATE_PARENT,
1468 .ops = &clk_branch2_ops,
1469 },
1470 },
1471 };
1472
1473 static struct clk_branch camcc_ipe_0_ahb_clk = {
1474 .halt_reg = 0x7040,
1475 .halt_check = BRANCH_HALT,
1476 .clkr = {
1477 .enable_reg = 0x7040,
1478 .enable_mask = BIT(0),
1479 .hw.init = &(struct clk_init_data){
1480 .name = "camcc_ipe_0_ahb_clk",
1481 .parent_hws = (const struct clk_hw*[]){
1482 &camcc_slow_ahb_clk_src.clkr.hw
1483 },
1484 .num_parents = 1,
1485 .flags = CLK_SET_RATE_PARENT,
1486 .ops = &clk_branch2_ops,
1487 },
1488 },
1489 };
1490
1491 static struct clk_branch camcc_ipe_0_areg_clk = {
1492 .halt_reg = 0x703c,
1493 .halt_check = BRANCH_HALT,
1494 .clkr = {
1495 .enable_reg = 0x703c,
1496 .enable_mask = BIT(0),
1497 .hw.init = &(struct clk_init_data){
1498 .name = "camcc_ipe_0_areg_clk",
1499 .parent_hws = (const struct clk_hw*[]){
1500 &camcc_fast_ahb_clk_src.clkr.hw
1501 },
1502 .num_parents = 1,
1503 .flags = CLK_SET_RATE_PARENT,
1504 .ops = &clk_branch2_ops,
1505 },
1506 },
1507 };
1508
1509 static struct clk_branch camcc_ipe_0_axi_clk = {
1510 .halt_reg = 0x7038,
1511 .halt_check = BRANCH_HALT,
1512 .clkr = {
1513 .enable_reg = 0x7038,
1514 .enable_mask = BIT(0),
1515 .hw.init = &(struct clk_init_data){
1516 .name = "camcc_ipe_0_axi_clk",
1517 .ops = &clk_branch2_ops,
1518 },
1519 },
1520 };
1521
1522 static struct clk_branch camcc_ipe_0_clk = {
1523 .halt_reg = 0x7028,
1524 .halt_check = BRANCH_HALT,
1525 .clkr = {
1526 .enable_reg = 0x7028,
1527 .enable_mask = BIT(0),
1528 .hw.init = &(struct clk_init_data){
1529 .name = "camcc_ipe_0_clk",
1530 .parent_hws = (const struct clk_hw*[]){
1531 &camcc_ipe_0_clk_src.clkr.hw
1532 },
1533 .num_parents = 1,
1534 .flags = CLK_SET_RATE_PARENT,
1535 .ops = &clk_branch2_ops,
1536 },
1537 },
1538 };
1539
1540 static struct clk_branch camcc_jpeg_clk = {
1541 .halt_reg = 0xd01c,
1542 .halt_check = BRANCH_HALT,
1543 .clkr = {
1544 .enable_reg = 0xd01c,
1545 .enable_mask = BIT(0),
1546 .hw.init = &(struct clk_init_data){
1547 .name = "camcc_jpeg_clk",
1548 .parent_hws = (const struct clk_hw*[]){
1549 &camcc_jpeg_clk_src.clkr.hw
1550 },
1551 .num_parents = 1,
1552 .flags = CLK_SET_RATE_PARENT,
1553 .ops = &clk_branch2_ops,
1554 },
1555 },
1556 };
1557
1558 static struct clk_branch camcc_lrme_clk = {
1559 .halt_reg = 0x1101c,
1560 .halt_check = BRANCH_HALT,
1561 .clkr = {
1562 .enable_reg = 0x1101c,
1563 .enable_mask = BIT(0),
1564 .hw.init = &(struct clk_init_data){
1565 .name = "camcc_lrme_clk",
1566 .parent_hws = (const struct clk_hw*[]){
1567 &camcc_lrme_clk_src.clkr.hw
1568 },
1569 .num_parents = 1,
1570 .flags = CLK_SET_RATE_PARENT,
1571 .ops = &clk_branch2_ops,
1572 },
1573 },
1574 };
1575
1576 static struct clk_branch camcc_mclk0_clk = {
1577 .halt_reg = 0x401c,
1578 .halt_check = BRANCH_HALT,
1579 .clkr = {
1580 .enable_reg = 0x401c,
1581 .enable_mask = BIT(0),
1582 .hw.init = &(struct clk_init_data){
1583 .name = "camcc_mclk0_clk",
1584 .parent_hws = (const struct clk_hw*[]){
1585 &camcc_mclk0_clk_src.clkr.hw
1586 },
1587 .num_parents = 1,
1588 .flags = CLK_SET_RATE_PARENT,
1589 .ops = &clk_branch2_ops,
1590 },
1591 },
1592 };
1593
1594 static struct clk_branch camcc_mclk1_clk = {
1595 .halt_reg = 0x403c,
1596 .halt_check = BRANCH_HALT,
1597 .clkr = {
1598 .enable_reg = 0x403c,
1599 .enable_mask = BIT(0),
1600 .hw.init = &(struct clk_init_data){
1601 .name = "camcc_mclk1_clk",
1602 .parent_hws = (const struct clk_hw*[]){
1603 &camcc_mclk1_clk_src.clkr.hw
1604 },
1605 .num_parents = 1,
1606 .flags = CLK_SET_RATE_PARENT,
1607 .ops = &clk_branch2_ops,
1608 },
1609 },
1610 };
1611
1612 static struct clk_branch camcc_mclk2_clk = {
1613 .halt_reg = 0x405c,
1614 .halt_check = BRANCH_HALT,
1615 .clkr = {
1616 .enable_reg = 0x405c,
1617 .enable_mask = BIT(0),
1618 .hw.init = &(struct clk_init_data){
1619 .name = "camcc_mclk2_clk",
1620 .parent_hws = (const struct clk_hw*[]){
1621 &camcc_mclk2_clk_src.clkr.hw
1622 },
1623 .num_parents = 1,
1624 .flags = CLK_SET_RATE_PARENT,
1625 .ops = &clk_branch2_ops,
1626 },
1627 },
1628 };
1629
1630 static struct clk_branch camcc_mclk3_clk = {
1631 .halt_reg = 0x407c,
1632 .halt_check = BRANCH_HALT,
1633 .clkr = {
1634 .enable_reg = 0x407c,
1635 .enable_mask = BIT(0),
1636 .hw.init = &(struct clk_init_data){
1637 .name = "camcc_mclk3_clk",
1638 .parent_hws = (const struct clk_hw*[]){
1639 &camcc_mclk3_clk_src.clkr.hw
1640 },
1641 .num_parents = 1,
1642 .flags = CLK_SET_RATE_PARENT,
1643 .ops = &clk_branch2_ops,
1644 },
1645 },
1646 };
1647
1648 static struct clk_branch camcc_mclk4_clk = {
1649 .halt_reg = 0x409c,
1650 .halt_check = BRANCH_HALT,
1651 .clkr = {
1652 .enable_reg = 0x409c,
1653 .enable_mask = BIT(0),
1654 .hw.init = &(struct clk_init_data){
1655 .name = "camcc_mclk4_clk",
1656 .parent_hws = (const struct clk_hw*[]){
1657 &camcc_mclk4_clk_src.clkr.hw
1658 },
1659 .num_parents = 1,
1660 .flags = CLK_SET_RATE_PARENT,
1661 .ops = &clk_branch2_ops,
1662 },
1663 },
1664 };
1665
1666 static struct clk_branch camcc_soc_ahb_clk = {
1667 .halt_reg = 0x1400c,
1668 .halt_check = BRANCH_HALT,
1669 .clkr = {
1670 .enable_reg = 0x1400c,
1671 .enable_mask = BIT(0),
1672 .hw.init = &(struct clk_init_data){
1673 .name = "camcc_soc_ahb_clk",
1674 .ops = &clk_branch2_ops,
1675 },
1676 },
1677 };
1678
1679 static struct clk_branch camcc_sys_tmr_clk = {
1680 .halt_reg = 0xe034,
1681 .halt_check = BRANCH_HALT,
1682 .clkr = {
1683 .enable_reg = 0xe034,
1684 .enable_mask = BIT(0),
1685 .hw.init = &(struct clk_init_data){
1686 .name = "camcc_sys_tmr_clk",
1687 .ops = &clk_branch2_ops,
1688 },
1689 },
1690 };
1691
1692 static struct gdsc titan_top_gdsc;
1693
1694 static struct gdsc bps_gdsc = {
1695 .gdscr = 0x6004,
1696 .en_rest_wait_val = 0x2,
1697 .en_few_wait_val = 0x2,
1698 .clk_dis_wait_val = 0xf,
1699 .pd = {
1700 .name = "bps_gdsc",
1701 },
1702 .pwrsts = PWRSTS_OFF_ON,
1703 .parent = &titan_top_gdsc.pd,
1704 .flags = VOTABLE,
1705 };
1706
1707 static struct gdsc ipe_0_gdsc = {
1708 .gdscr = 0x7004,
1709 .en_rest_wait_val = 0x2,
1710 .en_few_wait_val = 0x2,
1711 .clk_dis_wait_val = 0xf,
1712 .pd = {
1713 .name = "ipe_0_gdsc",
1714 },
1715 .pwrsts = PWRSTS_OFF_ON,
1716 .parent = &titan_top_gdsc.pd,
1717 .flags = VOTABLE,
1718 };
1719
1720 static struct gdsc ife_0_gdsc = {
1721 .gdscr = 0x9004,
1722 .en_rest_wait_val = 0x2,
1723 .en_few_wait_val = 0x2,
1724 .clk_dis_wait_val = 0xf,
1725 .pd = {
1726 .name = "ife_0_gdsc",
1727 },
1728 .pwrsts = PWRSTS_OFF_ON,
1729 .parent = &titan_top_gdsc.pd,
1730 };
1731
1732 static struct gdsc ife_1_gdsc = {
1733 .gdscr = 0xa004,
1734 .en_rest_wait_val = 0x2,
1735 .en_few_wait_val = 0x2,
1736 .clk_dis_wait_val = 0xf,
1737 .pd = {
1738 .name = "ife_1_gdsc",
1739 },
1740 .pwrsts = PWRSTS_OFF_ON,
1741 .parent = &titan_top_gdsc.pd,
1742 };
1743
1744 static struct gdsc ife_2_gdsc = {
1745 .gdscr = 0xb004,
1746 .en_rest_wait_val = 0x2,
1747 .en_few_wait_val = 0x2,
1748 .clk_dis_wait_val = 0xf,
1749 .pd = {
1750 .name = "ife_2_gdsc",
1751 },
1752 .pwrsts = PWRSTS_OFF_ON,
1753 .parent = &titan_top_gdsc.pd,
1754 };
1755
1756 static struct gdsc titan_top_gdsc = {
1757 .gdscr = 0x14004,
1758 .en_rest_wait_val = 0x2,
1759 .en_few_wait_val = 0x2,
1760 .clk_dis_wait_val = 0xf,
1761 .pd = {
1762 .name = "titan_top_gdsc",
1763 },
1764 .pwrsts = PWRSTS_OFF_ON,
1765 };
1766
1767 static struct clk_hw *camcc_sm6350_hws[] = {
1768 [CAMCC_PLL2_OUT_EARLY] = &camcc_pll2_out_early.hw,
1769 };
1770
1771 static struct clk_regmap *camcc_sm6350_clocks[] = {
1772 [CAMCC_BPS_AHB_CLK] = &camcc_bps_ahb_clk.clkr,
1773 [CAMCC_BPS_AREG_CLK] = &camcc_bps_areg_clk.clkr,
1774 [CAMCC_BPS_AXI_CLK] = &camcc_bps_axi_clk.clkr,
1775 [CAMCC_BPS_CLK] = &camcc_bps_clk.clkr,
1776 [CAMCC_BPS_CLK_SRC] = &camcc_bps_clk_src.clkr,
1777 [CAMCC_CAMNOC_AXI_CLK] = &camcc_camnoc_axi_clk.clkr,
1778 [CAMCC_CCI_0_CLK] = &camcc_cci_0_clk.clkr,
1779 [CAMCC_CCI_0_CLK_SRC] = &camcc_cci_0_clk_src.clkr,
1780 [CAMCC_CCI_1_CLK] = &camcc_cci_1_clk.clkr,
1781 [CAMCC_CCI_1_CLK_SRC] = &camcc_cci_1_clk_src.clkr,
1782 [CAMCC_CORE_AHB_CLK] = &camcc_core_ahb_clk.clkr,
1783 [CAMCC_CPAS_AHB_CLK] = &camcc_cpas_ahb_clk.clkr,
1784 [CAMCC_CPHY_RX_CLK_SRC] = &camcc_cphy_rx_clk_src.clkr,
1785 [CAMCC_CSI0PHYTIMER_CLK] = &camcc_csi0phytimer_clk.clkr,
1786 [CAMCC_CSI0PHYTIMER_CLK_SRC] = &camcc_csi0phytimer_clk_src.clkr,
1787 [CAMCC_CSI1PHYTIMER_CLK] = &camcc_csi1phytimer_clk.clkr,
1788 [CAMCC_CSI1PHYTIMER_CLK_SRC] = &camcc_csi1phytimer_clk_src.clkr,
1789 [CAMCC_CSI2PHYTIMER_CLK] = &camcc_csi2phytimer_clk.clkr,
1790 [CAMCC_CSI2PHYTIMER_CLK_SRC] = &camcc_csi2phytimer_clk_src.clkr,
1791 [CAMCC_CSI3PHYTIMER_CLK] = &camcc_csi3phytimer_clk.clkr,
1792 [CAMCC_CSI3PHYTIMER_CLK_SRC] = &camcc_csi3phytimer_clk_src.clkr,
1793 [CAMCC_CSIPHY0_CLK] = &camcc_csiphy0_clk.clkr,
1794 [CAMCC_CSIPHY1_CLK] = &camcc_csiphy1_clk.clkr,
1795 [CAMCC_CSIPHY2_CLK] = &camcc_csiphy2_clk.clkr,
1796 [CAMCC_CSIPHY3_CLK] = &camcc_csiphy3_clk.clkr,
1797 [CAMCC_FAST_AHB_CLK_SRC] = &camcc_fast_ahb_clk_src.clkr,
1798 [CAMCC_ICP_CLK] = &camcc_icp_clk.clkr,
1799 [CAMCC_ICP_CLK_SRC] = &camcc_icp_clk_src.clkr,
1800 [CAMCC_ICP_TS_CLK] = &camcc_icp_ts_clk.clkr,
1801 [CAMCC_IFE_0_AXI_CLK] = &camcc_ife_0_axi_clk.clkr,
1802 [CAMCC_IFE_0_CLK] = &camcc_ife_0_clk.clkr,
1803 [CAMCC_IFE_0_CLK_SRC] = &camcc_ife_0_clk_src.clkr,
1804 [CAMCC_IFE_0_CPHY_RX_CLK] = &camcc_ife_0_cphy_rx_clk.clkr,
1805 [CAMCC_IFE_0_CSID_CLK] = &camcc_ife_0_csid_clk.clkr,
1806 [CAMCC_IFE_0_CSID_CLK_SRC] = &camcc_ife_0_csid_clk_src.clkr,
1807 [CAMCC_IFE_0_DSP_CLK] = &camcc_ife_0_dsp_clk.clkr,
1808 [CAMCC_IFE_1_AXI_CLK] = &camcc_ife_1_axi_clk.clkr,
1809 [CAMCC_IFE_1_CLK] = &camcc_ife_1_clk.clkr,
1810 [CAMCC_IFE_1_CLK_SRC] = &camcc_ife_1_clk_src.clkr,
1811 [CAMCC_IFE_1_CPHY_RX_CLK] = &camcc_ife_1_cphy_rx_clk.clkr,
1812 [CAMCC_IFE_1_CSID_CLK] = &camcc_ife_1_csid_clk.clkr,
1813 [CAMCC_IFE_1_CSID_CLK_SRC] = &camcc_ife_1_csid_clk_src.clkr,
1814 [CAMCC_IFE_1_DSP_CLK] = &camcc_ife_1_dsp_clk.clkr,
1815 [CAMCC_IFE_2_AXI_CLK] = &camcc_ife_2_axi_clk.clkr,
1816 [CAMCC_IFE_2_CLK] = &camcc_ife_2_clk.clkr,
1817 [CAMCC_IFE_2_CLK_SRC] = &camcc_ife_2_clk_src.clkr,
1818 [CAMCC_IFE_2_CPHY_RX_CLK] = &camcc_ife_2_cphy_rx_clk.clkr,
1819 [CAMCC_IFE_2_CSID_CLK] = &camcc_ife_2_csid_clk.clkr,
1820 [CAMCC_IFE_2_CSID_CLK_SRC] = &camcc_ife_2_csid_clk_src.clkr,
1821 [CAMCC_IFE_2_DSP_CLK] = &camcc_ife_2_dsp_clk.clkr,
1822 [CAMCC_IFE_LITE_CLK] = &camcc_ife_lite_clk.clkr,
1823 [CAMCC_IFE_LITE_CLK_SRC] = &camcc_ife_lite_clk_src.clkr,
1824 [CAMCC_IFE_LITE_CPHY_RX_CLK] = &camcc_ife_lite_cphy_rx_clk.clkr,
1825 [CAMCC_IFE_LITE_CSID_CLK] = &camcc_ife_lite_csid_clk.clkr,
1826 [CAMCC_IFE_LITE_CSID_CLK_SRC] = &camcc_ife_lite_csid_clk_src.clkr,
1827 [CAMCC_IPE_0_AHB_CLK] = &camcc_ipe_0_ahb_clk.clkr,
1828 [CAMCC_IPE_0_AREG_CLK] = &camcc_ipe_0_areg_clk.clkr,
1829 [CAMCC_IPE_0_AXI_CLK] = &camcc_ipe_0_axi_clk.clkr,
1830 [CAMCC_IPE_0_CLK] = &camcc_ipe_0_clk.clkr,
1831 [CAMCC_IPE_0_CLK_SRC] = &camcc_ipe_0_clk_src.clkr,
1832 [CAMCC_JPEG_CLK] = &camcc_jpeg_clk.clkr,
1833 [CAMCC_JPEG_CLK_SRC] = &camcc_jpeg_clk_src.clkr,
1834 [CAMCC_LRME_CLK] = &camcc_lrme_clk.clkr,
1835 [CAMCC_LRME_CLK_SRC] = &camcc_lrme_clk_src.clkr,
1836 [CAMCC_MCLK0_CLK] = &camcc_mclk0_clk.clkr,
1837 [CAMCC_MCLK0_CLK_SRC] = &camcc_mclk0_clk_src.clkr,
1838 [CAMCC_MCLK1_CLK] = &camcc_mclk1_clk.clkr,
1839 [CAMCC_MCLK1_CLK_SRC] = &camcc_mclk1_clk_src.clkr,
1840 [CAMCC_MCLK2_CLK] = &camcc_mclk2_clk.clkr,
1841 [CAMCC_MCLK2_CLK_SRC] = &camcc_mclk2_clk_src.clkr,
1842 [CAMCC_MCLK3_CLK] = &camcc_mclk3_clk.clkr,
1843 [CAMCC_MCLK3_CLK_SRC] = &camcc_mclk3_clk_src.clkr,
1844 [CAMCC_MCLK4_CLK] = &camcc_mclk4_clk.clkr,
1845 [CAMCC_MCLK4_CLK_SRC] = &camcc_mclk4_clk_src.clkr,
1846 [CAMCC_PLL0] = &camcc_pll0.clkr,
1847 [CAMCC_PLL0_OUT_EVEN] = &camcc_pll0_out_even.clkr,
1848 [CAMCC_PLL1] = &camcc_pll1.clkr,
1849 [CAMCC_PLL1_OUT_EVEN] = &camcc_pll1_out_even.clkr,
1850 [CAMCC_PLL2] = &camcc_pll2.clkr,
1851 [CAMCC_PLL2_OUT_MAIN] = &camcc_pll2_out_main.clkr,
1852 [CAMCC_PLL3] = &camcc_pll3.clkr,
1853 [CAMCC_SLOW_AHB_CLK_SRC] = &camcc_slow_ahb_clk_src.clkr,
1854 [CAMCC_SOC_AHB_CLK] = &camcc_soc_ahb_clk.clkr,
1855 [CAMCC_SYS_TMR_CLK] = &camcc_sys_tmr_clk.clkr,
1856 };
1857
1858 static struct gdsc *camcc_sm6350_gdscs[] = {
1859 [BPS_GDSC] = &bps_gdsc,
1860 [IPE_0_GDSC] = &ipe_0_gdsc,
1861 [IFE_0_GDSC] = &ife_0_gdsc,
1862 [IFE_1_GDSC] = &ife_1_gdsc,
1863 [IFE_2_GDSC] = &ife_2_gdsc,
1864 [TITAN_TOP_GDSC] = &titan_top_gdsc,
1865 };
1866
1867 static const struct regmap_config camcc_sm6350_regmap_config = {
1868 .reg_bits = 32,
1869 .reg_stride = 4,
1870 .val_bits = 32,
1871 .max_register = 0x16000,
1872 .fast_io = true,
1873 };
1874
1875 static const struct qcom_cc_desc camcc_sm6350_desc = {
1876 .config = &camcc_sm6350_regmap_config,
1877 .clk_hws = camcc_sm6350_hws,
1878 .num_clk_hws = ARRAY_SIZE(camcc_sm6350_hws),
1879 .clks = camcc_sm6350_clocks,
1880 .num_clks = ARRAY_SIZE(camcc_sm6350_clocks),
1881 .gdscs = camcc_sm6350_gdscs,
1882 .num_gdscs = ARRAY_SIZE(camcc_sm6350_gdscs),
1883 };
1884
1885 static const struct of_device_id camcc_sm6350_match_table[] = {
1886 { .compatible = "qcom,sm6350-camcc" },
1887 { }
1888 };
1889 MODULE_DEVICE_TABLE(of, camcc_sm6350_match_table);
1890
camcc_sm6350_probe(struct platform_device * pdev)1891 static int camcc_sm6350_probe(struct platform_device *pdev)
1892 {
1893 struct regmap *regmap;
1894
1895 regmap = qcom_cc_map(pdev, &camcc_sm6350_desc);
1896 if (IS_ERR(regmap))
1897 return PTR_ERR(regmap);
1898
1899 clk_fabia_pll_configure(&camcc_pll0, regmap, &camcc_pll0_config);
1900 clk_fabia_pll_configure(&camcc_pll1, regmap, &camcc_pll1_config);
1901 clk_agera_pll_configure(&camcc_pll2, regmap, &camcc_pll2_config);
1902 clk_fabia_pll_configure(&camcc_pll3, regmap, &camcc_pll3_config);
1903
1904 return qcom_cc_really_probe(&pdev->dev, &camcc_sm6350_desc, regmap);
1905 }
1906
1907 static struct platform_driver camcc_sm6350_driver = {
1908 .probe = camcc_sm6350_probe,
1909 .driver = {
1910 .name = "sm6350-camcc",
1911 .of_match_table = camcc_sm6350_match_table,
1912 },
1913 };
1914
1915 module_platform_driver(camcc_sm6350_driver);
1916
1917 MODULE_DESCRIPTION("QTI CAMCC SM6350 Driver");
1918 MODULE_LICENSE("GPL");
1919