1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022, Linaro Limited
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/mod_devicetable.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/regmap.h>
12
13 #include <dt-bindings/clock/qcom,sm6350-camcc.h>
14
15 #include "clk-alpha-pll.h"
16 #include "clk-branch.h"
17 #include "clk-rcg.h"
18 #include "common.h"
19 #include "gdsc.h"
20
21 enum {
22 DT_BI_TCXO,
23 };
24
25 enum {
26 P_BI_TCXO,
27 P_CAMCC_PLL0_OUT_EVEN,
28 P_CAMCC_PLL0_OUT_MAIN,
29 P_CAMCC_PLL1_OUT_EVEN,
30 P_CAMCC_PLL1_OUT_MAIN,
31 P_CAMCC_PLL2_OUT_EARLY,
32 P_CAMCC_PLL2_OUT_MAIN,
33 P_CAMCC_PLL3_OUT_MAIN,
34 };
35
36 static const struct pll_vco fabia_vco[] = {
37 { 249600000, 2000000000, 0 },
38 };
39
40 /* 600MHz configuration */
41 static const struct alpha_pll_config camcc_pll0_config = {
42 .l = 0x1f,
43 .alpha = 0x4000,
44 .config_ctl_val = 0x20485699,
45 .config_ctl_hi_val = 0x00002067,
46 .test_ctl_val = 0x40000000,
47 .test_ctl_hi_val = 0x00000002,
48 .user_ctl_val = 0x00000101,
49 .user_ctl_hi_val = 0x00004805,
50 };
51
52 static struct clk_alpha_pll camcc_pll0 = {
53 .offset = 0x0,
54 .vco_table = fabia_vco,
55 .num_vco = ARRAY_SIZE(fabia_vco),
56 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
57 .clkr = {
58 .hw.init = &(struct clk_init_data){
59 .name = "camcc_pll0",
60 .parent_data = &(const struct clk_parent_data){
61 .index = DT_BI_TCXO,
62 },
63 .num_parents = 1,
64 .ops = &clk_alpha_pll_fabia_ops,
65 },
66 },
67 };
68
69 static const struct clk_div_table post_div_table_camcc_pll0_out_even[] = {
70 { 0x1, 2 },
71 { }
72 };
73
74 static struct clk_alpha_pll_postdiv camcc_pll0_out_even = {
75 .offset = 0x0,
76 .post_div_shift = 8,
77 .post_div_table = post_div_table_camcc_pll0_out_even,
78 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll0_out_even),
79 .width = 4,
80 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
81 .clkr.hw.init = &(struct clk_init_data){
82 .name = "camcc_pll0_out_even",
83 .parent_hws = (const struct clk_hw*[]){
84 &camcc_pll0.clkr.hw,
85 },
86 .num_parents = 1,
87 .flags = CLK_SET_RATE_PARENT,
88 .ops = &clk_alpha_pll_postdiv_fabia_ops,
89 },
90 };
91
92 /* 808MHz configuration */
93 static const struct alpha_pll_config camcc_pll1_config = {
94 .l = 0x2a,
95 .alpha = 0x1555,
96 .config_ctl_val = 0x20485699,
97 .config_ctl_hi_val = 0x00002067,
98 .test_ctl_val = 0x40000000,
99 .test_ctl_hi_val = 0x00000000,
100 .user_ctl_val = 0x00000101,
101 .user_ctl_hi_val = 0x00004805,
102 };
103
104 static struct clk_alpha_pll camcc_pll1 = {
105 .offset = 0x1000,
106 .vco_table = fabia_vco,
107 .num_vco = ARRAY_SIZE(fabia_vco),
108 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
109 .clkr = {
110 .hw.init = &(struct clk_init_data){
111 .name = "camcc_pll1",
112 .parent_data = &(const struct clk_parent_data){
113 .index = DT_BI_TCXO,
114 },
115 .num_parents = 1,
116 .ops = &clk_alpha_pll_fabia_ops,
117 },
118 },
119 };
120
121 static const struct clk_div_table post_div_table_camcc_pll1_out_even[] = {
122 { 0x1, 2 },
123 { }
124 };
125
126 static struct clk_alpha_pll_postdiv camcc_pll1_out_even = {
127 .offset = 0x1000,
128 .post_div_shift = 8,
129 .post_div_table = post_div_table_camcc_pll1_out_even,
130 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll1_out_even),
131 .width = 4,
132 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
133 .clkr.hw.init = &(struct clk_init_data){
134 .name = "camcc_pll1_out_even",
135 .parent_hws = (const struct clk_hw*[]){
136 &camcc_pll1.clkr.hw,
137 },
138 .num_parents = 1,
139 .flags = CLK_SET_RATE_PARENT,
140 .ops = &clk_alpha_pll_postdiv_fabia_ops,
141 },
142 };
143
144 /* 1920MHz configuration */
145 static const struct alpha_pll_config camcc_pll2_config = {
146 .l = 0x64,
147 .alpha = 0x0,
148 .post_div_val = 0x3 << 8,
149 .post_div_mask = 0x3 << 8,
150 .aux_output_mask = BIT(1),
151 .main_output_mask = BIT(0),
152 .early_output_mask = BIT(3),
153 .config_ctl_val = 0x20000800,
154 .config_ctl_hi_val = 0x400003d2,
155 .test_ctl_val = 0x04000400,
156 .test_ctl_hi_val = 0x00004000,
157 };
158
159 static struct clk_alpha_pll camcc_pll2 = {
160 .offset = 0x2000,
161 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA],
162 .clkr = {
163 .hw.init = &(struct clk_init_data){
164 .name = "camcc_pll2",
165 .parent_data = &(const struct clk_parent_data){
166 .index = DT_BI_TCXO,
167 },
168 .num_parents = 1,
169 .ops = &clk_alpha_pll_agera_ops,
170 },
171 },
172 };
173
174 static struct clk_fixed_factor camcc_pll2_out_early = {
175 .mult = 1,
176 .div = 2,
177 .hw.init = &(struct clk_init_data){
178 .name = "camcc_pll2_out_early",
179 .parent_hws = (const struct clk_hw*[]){
180 &camcc_pll2.clkr.hw,
181 },
182 .num_parents = 1,
183 .ops = &clk_fixed_factor_ops,
184 },
185 };
186
187 static const struct clk_div_table post_div_table_camcc_pll2_out_main[] = {
188 { 0x1, 2 },
189 { }
190 };
191
192 static struct clk_alpha_pll_postdiv camcc_pll2_out_main = {
193 .offset = 0x2000,
194 .post_div_shift = 8,
195 .post_div_table = post_div_table_camcc_pll2_out_main,
196 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll2_out_main),
197 .width = 2,
198 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA],
199 .clkr.hw.init = &(struct clk_init_data){
200 .name = "camcc_pll2_out_main",
201 .parent_hws = (const struct clk_hw*[]){
202 &camcc_pll2.clkr.hw,
203 },
204 .num_parents = 1,
205 .flags = CLK_SET_RATE_PARENT,
206 .ops = &clk_alpha_pll_postdiv_ops,
207 },
208 };
209
210 /* 384MHz configuration */
211 static const struct alpha_pll_config camcc_pll3_config = {
212 .l = 0x14,
213 .alpha = 0x0,
214 .config_ctl_val = 0x20485699,
215 .config_ctl_hi_val = 0x00002067,
216 .test_ctl_val = 0x40000000,
217 .test_ctl_hi_val = 0x00000002,
218 .user_ctl_val = 0x00000001,
219 .user_ctl_hi_val = 0x00014805,
220 };
221
222 static struct clk_alpha_pll camcc_pll3 = {
223 .offset = 0x3000,
224 .vco_table = fabia_vco,
225 .num_vco = ARRAY_SIZE(fabia_vco),
226 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
227 .clkr = {
228 .hw.init = &(struct clk_init_data){
229 .name = "camcc_pll3",
230 .parent_data = &(const struct clk_parent_data){
231 .index = DT_BI_TCXO,
232 },
233 .num_parents = 1,
234 .ops = &clk_alpha_pll_fabia_ops,
235 },
236 },
237 };
238
239 static const struct parent_map camcc_parent_map_0[] = {
240 { P_BI_TCXO, 0 },
241 { P_CAMCC_PLL0_OUT_EVEN, 6 },
242 };
243
244 static const struct clk_parent_data camcc_parent_data_0[] = {
245 { .fw_name = "bi_tcxo" },
246 { .hw = &camcc_pll0_out_even.clkr.hw },
247 };
248
249 static const struct parent_map camcc_parent_map_1[] = {
250 { P_BI_TCXO, 0 },
251 { P_CAMCC_PLL0_OUT_MAIN, 1 },
252 { P_CAMCC_PLL1_OUT_EVEN, 3 },
253 { P_CAMCC_PLL2_OUT_MAIN, 4 },
254 };
255
256 static const struct clk_parent_data camcc_parent_data_1[] = {
257 { .fw_name = "bi_tcxo" },
258 { .hw = &camcc_pll0.clkr.hw },
259 { .hw = &camcc_pll1_out_even.clkr.hw },
260 { .hw = &camcc_pll2_out_main.clkr.hw },
261 };
262
263 static const struct parent_map camcc_parent_map_2[] = {
264 { P_BI_TCXO, 0 },
265 { P_CAMCC_PLL0_OUT_MAIN, 1 },
266 { P_CAMCC_PLL3_OUT_MAIN, 5 },
267 };
268
269 static const struct clk_parent_data camcc_parent_data_2[] = {
270 { .fw_name = "bi_tcxo" },
271 { .hw = &camcc_pll0.clkr.hw },
272 { .hw = &camcc_pll3.clkr.hw },
273 };
274
275 static const struct parent_map camcc_parent_map_3[] = {
276 { P_BI_TCXO, 0 },
277 { P_CAMCC_PLL2_OUT_EARLY, 3 },
278 };
279
280 static const struct clk_parent_data camcc_parent_data_3[] = {
281 { .fw_name = "bi_tcxo" },
282 { .hw = &camcc_pll2_out_early.hw },
283 };
284
285 static const struct parent_map camcc_parent_map_4[] = {
286 { P_BI_TCXO, 0 },
287 { P_CAMCC_PLL0_OUT_MAIN, 1 },
288 { P_CAMCC_PLL1_OUT_EVEN, 3 },
289 };
290
291 static const struct clk_parent_data camcc_parent_data_4[] = {
292 { .fw_name = "bi_tcxo" },
293 { .hw = &camcc_pll0.clkr.hw },
294 { .hw = &camcc_pll1_out_even.clkr.hw },
295 };
296
297 static const struct parent_map camcc_parent_map_5[] = {
298 { P_BI_TCXO, 0 },
299 { P_CAMCC_PLL0_OUT_MAIN, 1 },
300 { P_CAMCC_PLL1_OUT_EVEN, 3 },
301 { P_CAMCC_PLL3_OUT_MAIN, 5 },
302 };
303
304 static const struct clk_parent_data camcc_parent_data_5[] = {
305 { .fw_name = "bi_tcxo" },
306 { .hw = &camcc_pll0.clkr.hw },
307 { .hw = &camcc_pll1_out_even.clkr.hw },
308 { .hw = &camcc_pll3.clkr.hw },
309 };
310
311 static const struct parent_map camcc_parent_map_6[] = {
312 { P_BI_TCXO, 0 },
313 { P_CAMCC_PLL0_OUT_MAIN, 1 },
314 { P_CAMCC_PLL2_OUT_MAIN, 4 },
315 };
316
317 static const struct clk_parent_data camcc_parent_data_6[] = {
318 { .fw_name = "bi_tcxo" },
319 { .hw = &camcc_pll0.clkr.hw },
320 { .hw = &camcc_pll2_out_main.clkr.hw },
321 };
322
323 static const struct parent_map camcc_parent_map_7[] = {
324 { P_BI_TCXO, 0 },
325 { P_CAMCC_PLL0_OUT_MAIN, 1 },
326 { P_CAMCC_PLL1_OUT_MAIN, 2 },
327 { P_CAMCC_PLL2_OUT_MAIN, 4 },
328 };
329
330 static const struct clk_parent_data camcc_parent_data_7[] = {
331 { .fw_name = "bi_tcxo" },
332 { .hw = &camcc_pll0.clkr.hw },
333 { .hw = &camcc_pll1.clkr.hw },
334 { .hw = &camcc_pll2_out_main.clkr.hw },
335 };
336
337 static const struct parent_map camcc_parent_map_8[] = {
338 { P_BI_TCXO, 0 },
339 { P_CAMCC_PLL0_OUT_MAIN, 1 },
340 { P_CAMCC_PLL1_OUT_MAIN, 2 },
341 };
342
343 static const struct clk_parent_data camcc_parent_data_8[] = {
344 { .fw_name = "bi_tcxo" },
345 { .hw = &camcc_pll0.clkr.hw },
346 { .hw = &camcc_pll1.clkr.hw },
347 };
348
349 static const struct parent_map camcc_parent_map_9[] = {
350 { P_BI_TCXO, 0 },
351 { P_CAMCC_PLL2_OUT_MAIN, 4 },
352 };
353
354 static const struct clk_parent_data camcc_parent_data_9[] = {
355 { .fw_name = "bi_tcxo" },
356 { .hw = &camcc_pll2_out_main.clkr.hw },
357 };
358
359 static const struct freq_tbl ftbl_camcc_bps_clk_src[] = {
360 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
361 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
362 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
363 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
364 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
365 { }
366 };
367
368 static struct clk_rcg2 camcc_bps_clk_src = {
369 .cmd_rcgr = 0x6010,
370 .mnd_width = 0,
371 .hid_width = 5,
372 .parent_map = camcc_parent_map_1,
373 .freq_tbl = ftbl_camcc_bps_clk_src,
374 .clkr.hw.init = &(struct clk_init_data){
375 .name = "camcc_bps_clk_src",
376 .parent_data = camcc_parent_data_1,
377 .num_parents = ARRAY_SIZE(camcc_parent_data_1),
378 .ops = &clk_rcg2_ops,
379 },
380 };
381
382 static const struct freq_tbl ftbl_camcc_cci_0_clk_src[] = {
383 F(37500000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0),
384 F(50000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
385 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0),
386 { }
387 };
388
389 static struct clk_rcg2 camcc_cci_0_clk_src = {
390 .cmd_rcgr = 0xf004,
391 .mnd_width = 8,
392 .hid_width = 5,
393 .parent_map = camcc_parent_map_0,
394 .freq_tbl = ftbl_camcc_cci_0_clk_src,
395 .clkr.hw.init = &(struct clk_init_data){
396 .name = "camcc_cci_0_clk_src",
397 .parent_data = camcc_parent_data_0,
398 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
399 .ops = &clk_rcg2_ops,
400 },
401 };
402
403 static struct clk_rcg2 camcc_cci_1_clk_src = {
404 .cmd_rcgr = 0x10004,
405 .mnd_width = 8,
406 .hid_width = 5,
407 .parent_map = camcc_parent_map_0,
408 .freq_tbl = ftbl_camcc_cci_0_clk_src,
409 .clkr.hw.init = &(struct clk_init_data){
410 .name = "camcc_cci_1_clk_src",
411 .parent_data = camcc_parent_data_0,
412 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
413 .ops = &clk_rcg2_ops,
414 },
415 };
416
417 static const struct freq_tbl ftbl_camcc_cphy_rx_clk_src[] = {
418 F(150000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0),
419 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
420 F(384000000, P_CAMCC_PLL3_OUT_MAIN, 1, 0, 0),
421 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 1.5, 0, 0),
422 { }
423 };
424
425 static struct clk_rcg2 camcc_cphy_rx_clk_src = {
426 .cmd_rcgr = 0x9064,
427 .mnd_width = 0,
428 .hid_width = 5,
429 .parent_map = camcc_parent_map_2,
430 .freq_tbl = ftbl_camcc_cphy_rx_clk_src,
431 .clkr.hw.init = &(struct clk_init_data){
432 .name = "camcc_cphy_rx_clk_src",
433 .parent_data = camcc_parent_data_2,
434 .num_parents = ARRAY_SIZE(camcc_parent_data_2),
435 .ops = &clk_rcg2_ops,
436 },
437 };
438
439 static const struct freq_tbl ftbl_camcc_csi0phytimer_clk_src[] = {
440 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 1, 0, 0),
441 { }
442 };
443
444 static struct clk_rcg2 camcc_csi0phytimer_clk_src = {
445 .cmd_rcgr = 0x5004,
446 .mnd_width = 0,
447 .hid_width = 5,
448 .parent_map = camcc_parent_map_0,
449 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
450 .clkr.hw.init = &(struct clk_init_data){
451 .name = "camcc_csi0phytimer_clk_src",
452 .parent_data = camcc_parent_data_0,
453 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
454 .ops = &clk_rcg2_ops,
455 },
456 };
457
458 static struct clk_rcg2 camcc_csi1phytimer_clk_src = {
459 .cmd_rcgr = 0x5028,
460 .mnd_width = 0,
461 .hid_width = 5,
462 .parent_map = camcc_parent_map_0,
463 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
464 .clkr.hw.init = &(struct clk_init_data){
465 .name = "camcc_csi1phytimer_clk_src",
466 .parent_data = camcc_parent_data_0,
467 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
468 .ops = &clk_rcg2_ops,
469 },
470 };
471
472 static struct clk_rcg2 camcc_csi2phytimer_clk_src = {
473 .cmd_rcgr = 0x504c,
474 .mnd_width = 0,
475 .hid_width = 5,
476 .parent_map = camcc_parent_map_0,
477 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
478 .clkr.hw.init = &(struct clk_init_data){
479 .name = "camcc_csi2phytimer_clk_src",
480 .parent_data = camcc_parent_data_0,
481 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
482 .ops = &clk_rcg2_ops,
483 },
484 };
485
486 static struct clk_rcg2 camcc_csi3phytimer_clk_src = {
487 .cmd_rcgr = 0x5070,
488 .mnd_width = 0,
489 .hid_width = 5,
490 .parent_map = camcc_parent_map_0,
491 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
492 .clkr.hw.init = &(struct clk_init_data){
493 .name = "camcc_csi3phytimer_clk_src",
494 .parent_data = camcc_parent_data_0,
495 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
496 .ops = &clk_rcg2_ops,
497 },
498 };
499
500 static const struct freq_tbl ftbl_camcc_fast_ahb_clk_src[] = {
501 F(100000000, P_CAMCC_PLL0_OUT_MAIN, 6, 0, 0),
502 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
503 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
504 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
505 { }
506 };
507
508 static struct clk_rcg2 camcc_fast_ahb_clk_src = {
509 .cmd_rcgr = 0x603c,
510 .mnd_width = 0,
511 .hid_width = 5,
512 .parent_map = camcc_parent_map_4,
513 .freq_tbl = ftbl_camcc_fast_ahb_clk_src,
514 .clkr.hw.init = &(struct clk_init_data){
515 .name = "camcc_fast_ahb_clk_src",
516 .parent_data = camcc_parent_data_4,
517 .num_parents = ARRAY_SIZE(camcc_parent_data_4),
518 .ops = &clk_rcg2_ops,
519 },
520 };
521
522 static const struct freq_tbl ftbl_camcc_icp_clk_src[] = {
523 F(240000000, P_CAMCC_PLL0_OUT_MAIN, 2.5, 0, 0),
524 F(384000000, P_CAMCC_PLL3_OUT_MAIN, 1, 0, 0),
525 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
526 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
527 { }
528 };
529
530 static struct clk_rcg2 camcc_icp_clk_src = {
531 .cmd_rcgr = 0xe014,
532 .mnd_width = 0,
533 .hid_width = 5,
534 .parent_map = camcc_parent_map_5,
535 .freq_tbl = ftbl_camcc_icp_clk_src,
536 .clkr.hw.init = &(struct clk_init_data){
537 .name = "camcc_icp_clk_src",
538 .parent_data = camcc_parent_data_5,
539 .num_parents = ARRAY_SIZE(camcc_parent_data_5),
540 .ops = &clk_rcg2_ops,
541 },
542 };
543
544 static const struct freq_tbl ftbl_camcc_ife_0_clk_src[] = {
545 F(240000000, P_CAMCC_PLL0_OUT_MAIN, 2.5, 0, 0),
546 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
547 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
548 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
549 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
550 { }
551 };
552
553 static struct clk_rcg2 camcc_ife_0_clk_src = {
554 .cmd_rcgr = 0x9010,
555 .mnd_width = 0,
556 .hid_width = 5,
557 .parent_map = camcc_parent_map_1,
558 .freq_tbl = ftbl_camcc_ife_0_clk_src,
559 .clkr.hw.init = &(struct clk_init_data){
560 .name = "camcc_ife_0_clk_src",
561 .parent_data = camcc_parent_data_1,
562 .num_parents = ARRAY_SIZE(camcc_parent_data_1),
563 .flags = CLK_SET_RATE_PARENT,
564 .ops = &clk_rcg2_ops,
565 },
566 };
567
568 static struct clk_rcg2 camcc_ife_0_csid_clk_src = {
569 .cmd_rcgr = 0x903c,
570 .mnd_width = 0,
571 .hid_width = 5,
572 .parent_map = camcc_parent_map_2,
573 .freq_tbl = ftbl_camcc_cphy_rx_clk_src,
574 .clkr.hw.init = &(struct clk_init_data){
575 .name = "camcc_ife_0_csid_clk_src",
576 .parent_data = camcc_parent_data_2,
577 .num_parents = ARRAY_SIZE(camcc_parent_data_2),
578 .ops = &clk_rcg2_ops,
579 },
580 };
581
582 static struct clk_rcg2 camcc_ife_1_clk_src = {
583 .cmd_rcgr = 0xa010,
584 .mnd_width = 0,
585 .hid_width = 5,
586 .parent_map = camcc_parent_map_1,
587 .freq_tbl = ftbl_camcc_ife_0_clk_src,
588 .clkr.hw.init = &(struct clk_init_data){
589 .name = "camcc_ife_1_clk_src",
590 .parent_data = camcc_parent_data_1,
591 .num_parents = ARRAY_SIZE(camcc_parent_data_1),
592 .flags = CLK_SET_RATE_PARENT,
593 .ops = &clk_rcg2_ops,
594 },
595 };
596
597 static struct clk_rcg2 camcc_ife_1_csid_clk_src = {
598 .cmd_rcgr = 0xa034,
599 .mnd_width = 0,
600 .hid_width = 5,
601 .parent_map = camcc_parent_map_2,
602 .freq_tbl = ftbl_camcc_cphy_rx_clk_src,
603 .clkr.hw.init = &(struct clk_init_data){
604 .name = "camcc_ife_1_csid_clk_src",
605 .parent_data = camcc_parent_data_2,
606 .num_parents = ARRAY_SIZE(camcc_parent_data_2),
607 .ops = &clk_rcg2_ops,
608 },
609 };
610
611 static struct clk_rcg2 camcc_ife_2_clk_src = {
612 .cmd_rcgr = 0xb00c,
613 .mnd_width = 0,
614 .hid_width = 5,
615 .parent_map = camcc_parent_map_1,
616 .freq_tbl = ftbl_camcc_ife_0_clk_src,
617 .clkr.hw.init = &(struct clk_init_data){
618 .name = "camcc_ife_2_clk_src",
619 .parent_data = camcc_parent_data_1,
620 .num_parents = ARRAY_SIZE(camcc_parent_data_1),
621 .ops = &clk_rcg2_ops,
622 },
623 };
624
625 static struct clk_rcg2 camcc_ife_2_csid_clk_src = {
626 .cmd_rcgr = 0xb030,
627 .mnd_width = 0,
628 .hid_width = 5,
629 .parent_map = camcc_parent_map_2,
630 .freq_tbl = ftbl_camcc_cphy_rx_clk_src,
631 .clkr.hw.init = &(struct clk_init_data){
632 .name = "camcc_ife_2_csid_clk_src",
633 .parent_data = camcc_parent_data_2,
634 .num_parents = ARRAY_SIZE(camcc_parent_data_2),
635 .ops = &clk_rcg2_ops,
636 },
637 };
638
639 static const struct freq_tbl ftbl_camcc_ife_lite_clk_src[] = {
640 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
641 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 1.5, 0, 0),
642 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
643 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
644 { }
645 };
646
647 static struct clk_rcg2 camcc_ife_lite_clk_src = {
648 .cmd_rcgr = 0xc004,
649 .mnd_width = 0,
650 .hid_width = 5,
651 .parent_map = camcc_parent_map_6,
652 .freq_tbl = ftbl_camcc_ife_lite_clk_src,
653 .clkr.hw.init = &(struct clk_init_data){
654 .name = "camcc_ife_lite_clk_src",
655 .parent_data = camcc_parent_data_6,
656 .num_parents = ARRAY_SIZE(camcc_parent_data_6),
657 .ops = &clk_rcg2_ops,
658 },
659 };
660
661 static struct clk_rcg2 camcc_ife_lite_csid_clk_src = {
662 .cmd_rcgr = 0xc024,
663 .mnd_width = 0,
664 .hid_width = 5,
665 .parent_map = camcc_parent_map_2,
666 .freq_tbl = ftbl_camcc_cphy_rx_clk_src,
667 .clkr.hw.init = &(struct clk_init_data){
668 .name = "camcc_ife_lite_csid_clk_src",
669 .parent_data = camcc_parent_data_2,
670 .num_parents = ARRAY_SIZE(camcc_parent_data_2),
671 .ops = &clk_rcg2_ops,
672 },
673 };
674
675 static const struct freq_tbl ftbl_camcc_ipe_0_clk_src[] = {
676 F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0),
677 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
678 F(404000000, P_CAMCC_PLL1_OUT_MAIN, 2, 0, 0),
679 F(538666667, P_CAMCC_PLL1_OUT_MAIN, 1.5, 0, 0),
680 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
681 { }
682 };
683
684 static struct clk_rcg2 camcc_ipe_0_clk_src = {
685 .cmd_rcgr = 0x7010,
686 .mnd_width = 0,
687 .hid_width = 5,
688 .parent_map = camcc_parent_map_7,
689 .freq_tbl = ftbl_camcc_ipe_0_clk_src,
690 .clkr.hw.init = &(struct clk_init_data){
691 .name = "camcc_ipe_0_clk_src",
692 .parent_data = camcc_parent_data_7,
693 .num_parents = ARRAY_SIZE(camcc_parent_data_7),
694 .flags = CLK_SET_RATE_PARENT,
695 .ops = &clk_rcg2_ops,
696 },
697 };
698
699 static const struct freq_tbl ftbl_camcc_jpeg_clk_src[] = {
700 F(66666667, P_CAMCC_PLL0_OUT_MAIN, 9, 0, 0),
701 F(133333333, P_CAMCC_PLL0_OUT_MAIN, 4.5, 0, 0),
702 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
703 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
704 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
705 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
706 { }
707 };
708
709 static struct clk_rcg2 camcc_jpeg_clk_src = {
710 .cmd_rcgr = 0xd004,
711 .mnd_width = 0,
712 .hid_width = 5,
713 .parent_map = camcc_parent_map_1,
714 .freq_tbl = ftbl_camcc_jpeg_clk_src,
715 .clkr.hw.init = &(struct clk_init_data){
716 .name = "camcc_jpeg_clk_src",
717 .parent_data = camcc_parent_data_1,
718 .num_parents = ARRAY_SIZE(camcc_parent_data_1),
719 .ops = &clk_rcg2_ops,
720 },
721 };
722
723 static const struct freq_tbl ftbl_camcc_lrme_clk_src[] = {
724 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
725 F(269333333, P_CAMCC_PLL1_OUT_MAIN, 3, 0, 0),
726 F(323200000, P_CAMCC_PLL1_OUT_MAIN, 2.5, 0, 0),
727 F(404000000, P_CAMCC_PLL1_OUT_MAIN, 2, 0, 0),
728 { }
729 };
730
731 static struct clk_rcg2 camcc_lrme_clk_src = {
732 .cmd_rcgr = 0x11004,
733 .mnd_width = 0,
734 .hid_width = 5,
735 .parent_map = camcc_parent_map_8,
736 .freq_tbl = ftbl_camcc_lrme_clk_src,
737 .clkr.hw.init = &(struct clk_init_data){
738 .name = "camcc_lrme_clk_src",
739 .parent_data = camcc_parent_data_8,
740 .num_parents = ARRAY_SIZE(camcc_parent_data_8),
741 .ops = &clk_rcg2_ops,
742 },
743 };
744
745 static const struct freq_tbl ftbl_camcc_mclk0_clk_src[] = {
746 F(19200000, P_CAMCC_PLL2_OUT_EARLY, 1, 1, 50),
747 F(24000000, P_CAMCC_PLL2_OUT_EARLY, 10, 1, 4),
748 F(64000000, P_CAMCC_PLL2_OUT_EARLY, 15, 0, 0),
749 { }
750 };
751
752 static struct clk_rcg2 camcc_mclk0_clk_src = {
753 .cmd_rcgr = 0x4004,
754 .mnd_width = 8,
755 .hid_width = 5,
756 .parent_map = camcc_parent_map_3,
757 .freq_tbl = ftbl_camcc_mclk0_clk_src,
758 .clkr.hw.init = &(struct clk_init_data){
759 .name = "camcc_mclk0_clk_src",
760 .parent_data = camcc_parent_data_3,
761 .num_parents = ARRAY_SIZE(camcc_parent_data_3),
762 .ops = &clk_rcg2_ops,
763 },
764 };
765
766 static struct clk_rcg2 camcc_mclk1_clk_src = {
767 .cmd_rcgr = 0x4024,
768 .mnd_width = 8,
769 .hid_width = 5,
770 .parent_map = camcc_parent_map_3,
771 .freq_tbl = ftbl_camcc_mclk0_clk_src,
772 .clkr.hw.init = &(struct clk_init_data){
773 .name = "camcc_mclk1_clk_src",
774 .parent_data = camcc_parent_data_3,
775 .num_parents = ARRAY_SIZE(camcc_parent_data_3),
776 .ops = &clk_rcg2_ops,
777 },
778 };
779
780 static struct clk_rcg2 camcc_mclk2_clk_src = {
781 .cmd_rcgr = 0x4044,
782 .mnd_width = 8,
783 .hid_width = 5,
784 .parent_map = camcc_parent_map_3,
785 .freq_tbl = ftbl_camcc_mclk0_clk_src,
786 .clkr.hw.init = &(struct clk_init_data){
787 .name = "camcc_mclk2_clk_src",
788 .parent_data = camcc_parent_data_3,
789 .num_parents = ARRAY_SIZE(camcc_parent_data_3),
790 .ops = &clk_rcg2_ops,
791 },
792 };
793
794 static struct clk_rcg2 camcc_mclk3_clk_src = {
795 .cmd_rcgr = 0x4064,
796 .mnd_width = 8,
797 .hid_width = 5,
798 .parent_map = camcc_parent_map_3,
799 .freq_tbl = ftbl_camcc_mclk0_clk_src,
800 .clkr.hw.init = &(struct clk_init_data){
801 .name = "camcc_mclk3_clk_src",
802 .parent_data = camcc_parent_data_3,
803 .num_parents = ARRAY_SIZE(camcc_parent_data_3),
804 .ops = &clk_rcg2_ops,
805 },
806 };
807
808 static struct clk_rcg2 camcc_mclk4_clk_src = {
809 .cmd_rcgr = 0x4084,
810 .mnd_width = 8,
811 .hid_width = 5,
812 .parent_map = camcc_parent_map_3,
813 .freq_tbl = ftbl_camcc_mclk0_clk_src,
814 .clkr.hw.init = &(struct clk_init_data){
815 .name = "camcc_mclk4_clk_src",
816 .parent_data = camcc_parent_data_3,
817 .num_parents = ARRAY_SIZE(camcc_parent_data_3),
818 .ops = &clk_rcg2_ops,
819 },
820 };
821
822 static const struct freq_tbl ftbl_camcc_slow_ahb_clk_src[] = {
823 F(80000000, P_CAMCC_PLL2_OUT_MAIN, 6, 0, 0),
824 { }
825 };
826
827 static struct clk_rcg2 camcc_slow_ahb_clk_src = {
828 .cmd_rcgr = 0x6058,
829 .mnd_width = 0,
830 .hid_width = 5,
831 .parent_map = camcc_parent_map_9,
832 .freq_tbl = ftbl_camcc_slow_ahb_clk_src,
833 .clkr.hw.init = &(struct clk_init_data){
834 .name = "camcc_slow_ahb_clk_src",
835 .parent_data = camcc_parent_data_9,
836 .num_parents = ARRAY_SIZE(camcc_parent_data_9),
837 .ops = &clk_rcg2_ops,
838 },
839 };
840
841 static struct clk_branch camcc_bps_ahb_clk = {
842 .halt_reg = 0x6070,
843 .halt_check = BRANCH_HALT,
844 .clkr = {
845 .enable_reg = 0x6070,
846 .enable_mask = BIT(0),
847 .hw.init = &(struct clk_init_data){
848 .name = "camcc_bps_ahb_clk",
849 .parent_hws = (const struct clk_hw*[]){
850 &camcc_slow_ahb_clk_src.clkr.hw
851 },
852 .num_parents = 1,
853 .flags = CLK_SET_RATE_PARENT,
854 .ops = &clk_branch2_ops,
855 },
856 },
857 };
858
859 static struct clk_branch camcc_bps_areg_clk = {
860 .halt_reg = 0x6054,
861 .halt_check = BRANCH_HALT,
862 .clkr = {
863 .enable_reg = 0x6054,
864 .enable_mask = BIT(0),
865 .hw.init = &(struct clk_init_data){
866 .name = "camcc_bps_areg_clk",
867 .parent_hws = (const struct clk_hw*[]){
868 &camcc_fast_ahb_clk_src.clkr.hw
869 },
870 .num_parents = 1,
871 .flags = CLK_SET_RATE_PARENT,
872 .ops = &clk_branch2_ops,
873 },
874 },
875 };
876
877 static struct clk_branch camcc_bps_axi_clk = {
878 .halt_reg = 0x6038,
879 .halt_check = BRANCH_HALT,
880 .clkr = {
881 .enable_reg = 0x6038,
882 .enable_mask = BIT(0),
883 .hw.init = &(struct clk_init_data){
884 .name = "camcc_bps_axi_clk",
885 .ops = &clk_branch2_ops,
886 },
887 },
888 };
889
890 static struct clk_branch camcc_bps_clk = {
891 .halt_reg = 0x6028,
892 .halt_check = BRANCH_HALT,
893 .clkr = {
894 .enable_reg = 0x6028,
895 .enable_mask = BIT(0),
896 .hw.init = &(struct clk_init_data){
897 .name = "camcc_bps_clk",
898 .parent_hws = (const struct clk_hw*[]){
899 &camcc_bps_clk_src.clkr.hw
900 },
901 .num_parents = 1,
902 .flags = CLK_SET_RATE_PARENT,
903 .ops = &clk_branch2_ops,
904 },
905 },
906 };
907
908 static struct clk_branch camcc_camnoc_axi_clk = {
909 .halt_reg = 0x13004,
910 .halt_check = BRANCH_HALT,
911 .clkr = {
912 .enable_reg = 0x13004,
913 .enable_mask = BIT(0),
914 .hw.init = &(struct clk_init_data){
915 .name = "camcc_camnoc_axi_clk",
916 .ops = &clk_branch2_ops,
917 },
918 },
919 };
920
921 static struct clk_branch camcc_cci_0_clk = {
922 .halt_reg = 0xf01c,
923 .halt_check = BRANCH_HALT,
924 .clkr = {
925 .enable_reg = 0xf01c,
926 .enable_mask = BIT(0),
927 .hw.init = &(struct clk_init_data){
928 .name = "camcc_cci_0_clk",
929 .parent_hws = (const struct clk_hw*[]){
930 &camcc_cci_0_clk_src.clkr.hw
931 },
932 .num_parents = 1,
933 .flags = CLK_SET_RATE_PARENT,
934 .ops = &clk_branch2_ops,
935 },
936 },
937 };
938
939 static struct clk_branch camcc_cci_1_clk = {
940 .halt_reg = 0x1001c,
941 .halt_check = BRANCH_HALT,
942 .clkr = {
943 .enable_reg = 0x1001c,
944 .enable_mask = BIT(0),
945 .hw.init = &(struct clk_init_data){
946 .name = "camcc_cci_1_clk",
947 .parent_hws = (const struct clk_hw*[]){
948 &camcc_cci_1_clk_src.clkr.hw
949 },
950 .num_parents = 1,
951 .flags = CLK_SET_RATE_PARENT,
952 .ops = &clk_branch2_ops,
953 },
954 },
955 };
956
957 static struct clk_branch camcc_core_ahb_clk = {
958 .halt_reg = 0x14010,
959 .halt_check = BRANCH_HALT_VOTED,
960 .clkr = {
961 .enable_reg = 0x14010,
962 .enable_mask = BIT(0),
963 .hw.init = &(struct clk_init_data){
964 .name = "camcc_core_ahb_clk",
965 .parent_hws = (const struct clk_hw*[]){
966 &camcc_slow_ahb_clk_src.clkr.hw
967 },
968 .num_parents = 1,
969 .flags = CLK_SET_RATE_PARENT,
970 .ops = &clk_branch2_ops,
971 },
972 },
973 };
974
975 static struct clk_branch camcc_cpas_ahb_clk = {
976 .halt_reg = 0x12004,
977 .halt_check = BRANCH_HALT,
978 .clkr = {
979 .enable_reg = 0x12004,
980 .enable_mask = BIT(0),
981 .hw.init = &(struct clk_init_data){
982 .name = "camcc_cpas_ahb_clk",
983 .parent_hws = (const struct clk_hw*[]){
984 &camcc_slow_ahb_clk_src.clkr.hw
985 },
986 .num_parents = 1,
987 .flags = CLK_SET_RATE_PARENT,
988 .ops = &clk_branch2_ops,
989 },
990 },
991 };
992
993 static struct clk_branch camcc_csi0phytimer_clk = {
994 .halt_reg = 0x501c,
995 .halt_check = BRANCH_HALT,
996 .clkr = {
997 .enable_reg = 0x501c,
998 .enable_mask = BIT(0),
999 .hw.init = &(struct clk_init_data){
1000 .name = "camcc_csi0phytimer_clk",
1001 .parent_hws = (const struct clk_hw*[]){
1002 &camcc_csi0phytimer_clk_src.clkr.hw
1003 },
1004 .num_parents = 1,
1005 .flags = CLK_SET_RATE_PARENT,
1006 .ops = &clk_branch2_ops,
1007 },
1008 },
1009 };
1010
1011 static struct clk_branch camcc_csi1phytimer_clk = {
1012 .halt_reg = 0x5040,
1013 .halt_check = BRANCH_HALT,
1014 .clkr = {
1015 .enable_reg = 0x5040,
1016 .enable_mask = BIT(0),
1017 .hw.init = &(struct clk_init_data){
1018 .name = "camcc_csi1phytimer_clk",
1019 .parent_hws = (const struct clk_hw*[]){
1020 &camcc_csi1phytimer_clk_src.clkr.hw
1021 },
1022 .num_parents = 1,
1023 .flags = CLK_SET_RATE_PARENT,
1024 .ops = &clk_branch2_ops,
1025 },
1026 },
1027 };
1028
1029 static struct clk_branch camcc_csi2phytimer_clk = {
1030 .halt_reg = 0x5064,
1031 .halt_check = BRANCH_HALT,
1032 .clkr = {
1033 .enable_reg = 0x5064,
1034 .enable_mask = BIT(0),
1035 .hw.init = &(struct clk_init_data){
1036 .name = "camcc_csi2phytimer_clk",
1037 .parent_hws = (const struct clk_hw*[]){
1038 &camcc_csi2phytimer_clk_src.clkr.hw
1039 },
1040 .num_parents = 1,
1041 .flags = CLK_SET_RATE_PARENT,
1042 .ops = &clk_branch2_ops,
1043 },
1044 },
1045 };
1046
1047 static struct clk_branch camcc_csi3phytimer_clk = {
1048 .halt_reg = 0x5088,
1049 .halt_check = BRANCH_HALT,
1050 .clkr = {
1051 .enable_reg = 0x5088,
1052 .enable_mask = BIT(0),
1053 .hw.init = &(struct clk_init_data){
1054 .name = "camcc_csi3phytimer_clk",
1055 .parent_hws = (const struct clk_hw*[]){
1056 &camcc_csi3phytimer_clk_src.clkr.hw
1057 },
1058 .num_parents = 1,
1059 .flags = CLK_SET_RATE_PARENT,
1060 .ops = &clk_branch2_ops,
1061 },
1062 },
1063 };
1064
1065 static struct clk_branch camcc_csiphy0_clk = {
1066 .halt_reg = 0x5020,
1067 .halt_check = BRANCH_HALT,
1068 .clkr = {
1069 .enable_reg = 0x5020,
1070 .enable_mask = BIT(0),
1071 .hw.init = &(struct clk_init_data){
1072 .name = "camcc_csiphy0_clk",
1073 .parent_hws = (const struct clk_hw*[]){
1074 &camcc_cphy_rx_clk_src.clkr.hw
1075 },
1076 .num_parents = 1,
1077 .flags = CLK_SET_RATE_PARENT,
1078 .ops = &clk_branch2_ops,
1079 },
1080 },
1081 };
1082
1083 static struct clk_branch camcc_csiphy1_clk = {
1084 .halt_reg = 0x5044,
1085 .halt_check = BRANCH_HALT,
1086 .clkr = {
1087 .enable_reg = 0x5044,
1088 .enable_mask = BIT(0),
1089 .hw.init = &(struct clk_init_data){
1090 .name = "camcc_csiphy1_clk",
1091 .parent_hws = (const struct clk_hw*[]){
1092 &camcc_cphy_rx_clk_src.clkr.hw
1093 },
1094 .num_parents = 1,
1095 .flags = CLK_SET_RATE_PARENT,
1096 .ops = &clk_branch2_ops,
1097 },
1098 },
1099 };
1100
1101 static struct clk_branch camcc_csiphy2_clk = {
1102 .halt_reg = 0x5068,
1103 .halt_check = BRANCH_HALT,
1104 .clkr = {
1105 .enable_reg = 0x5068,
1106 .enable_mask = BIT(0),
1107 .hw.init = &(struct clk_init_data){
1108 .name = "camcc_csiphy2_clk",
1109 .parent_hws = (const struct clk_hw*[]){
1110 &camcc_cphy_rx_clk_src.clkr.hw
1111 },
1112 .num_parents = 1,
1113 .flags = CLK_SET_RATE_PARENT,
1114 .ops = &clk_branch2_ops,
1115 },
1116 },
1117 };
1118
1119 static struct clk_branch camcc_csiphy3_clk = {
1120 .halt_reg = 0x508c,
1121 .halt_check = BRANCH_HALT,
1122 .clkr = {
1123 .enable_reg = 0x508c,
1124 .enable_mask = BIT(0),
1125 .hw.init = &(struct clk_init_data){
1126 .name = "camcc_csiphy3_clk",
1127 .parent_hws = (const struct clk_hw*[]){
1128 &camcc_cphy_rx_clk_src.clkr.hw
1129 },
1130 .num_parents = 1,
1131 .flags = CLK_SET_RATE_PARENT,
1132 .ops = &clk_branch2_ops,
1133 },
1134 },
1135 };
1136
1137 static struct clk_branch camcc_icp_clk = {
1138 .halt_reg = 0xe02c,
1139 .halt_check = BRANCH_HALT,
1140 .clkr = {
1141 .enable_reg = 0xe02c,
1142 .enable_mask = BIT(0),
1143 .hw.init = &(struct clk_init_data){
1144 .name = "camcc_icp_clk",
1145 .parent_hws = (const struct clk_hw*[]){
1146 &camcc_icp_clk_src.clkr.hw
1147 },
1148 .num_parents = 1,
1149 .flags = CLK_SET_RATE_PARENT,
1150 .ops = &clk_branch2_ops,
1151 },
1152 },
1153 };
1154
1155 static struct clk_branch camcc_icp_ts_clk = {
1156 .halt_reg = 0xe00c,
1157 .halt_check = BRANCH_HALT,
1158 .clkr = {
1159 .enable_reg = 0xe00c,
1160 .enable_mask = BIT(0),
1161 .hw.init = &(struct clk_init_data){
1162 .name = "camcc_icp_ts_clk",
1163 .ops = &clk_branch2_ops,
1164 },
1165 },
1166 };
1167
1168 static struct clk_branch camcc_ife_0_axi_clk = {
1169 .halt_reg = 0x9080,
1170 .halt_check = BRANCH_HALT,
1171 .clkr = {
1172 .enable_reg = 0x9080,
1173 .enable_mask = BIT(0),
1174 .hw.init = &(struct clk_init_data){
1175 .name = "camcc_ife_0_axi_clk",
1176 .ops = &clk_branch2_ops,
1177 },
1178 },
1179 };
1180
1181 static struct clk_branch camcc_ife_0_clk = {
1182 .halt_reg = 0x9028,
1183 .halt_check = BRANCH_HALT,
1184 .clkr = {
1185 .enable_reg = 0x9028,
1186 .enable_mask = BIT(0),
1187 .hw.init = &(struct clk_init_data){
1188 .name = "camcc_ife_0_clk",
1189 .parent_hws = (const struct clk_hw*[]){
1190 &camcc_ife_0_clk_src.clkr.hw
1191 },
1192 .num_parents = 1,
1193 .flags = CLK_SET_RATE_PARENT,
1194 .ops = &clk_branch2_ops,
1195 },
1196 },
1197 };
1198
1199 static struct clk_branch camcc_ife_0_cphy_rx_clk = {
1200 .halt_reg = 0x907c,
1201 .halt_check = BRANCH_HALT,
1202 .clkr = {
1203 .enable_reg = 0x907c,
1204 .enable_mask = BIT(0),
1205 .hw.init = &(struct clk_init_data){
1206 .name = "camcc_ife_0_cphy_rx_clk",
1207 .parent_hws = (const struct clk_hw*[]){
1208 &camcc_cphy_rx_clk_src.clkr.hw
1209 },
1210 .num_parents = 1,
1211 .flags = CLK_SET_RATE_PARENT,
1212 .ops = &clk_branch2_ops,
1213 },
1214 },
1215 };
1216
1217 static struct clk_branch camcc_ife_0_csid_clk = {
1218 .halt_reg = 0x9054,
1219 .halt_check = BRANCH_HALT,
1220 .clkr = {
1221 .enable_reg = 0x9054,
1222 .enable_mask = BIT(0),
1223 .hw.init = &(struct clk_init_data){
1224 .name = "camcc_ife_0_csid_clk",
1225 .parent_hws = (const struct clk_hw*[]){
1226 &camcc_ife_0_csid_clk_src.clkr.hw
1227 },
1228 .num_parents = 1,
1229 .flags = CLK_SET_RATE_PARENT,
1230 .ops = &clk_branch2_ops,
1231 },
1232 },
1233 };
1234
1235 static struct clk_branch camcc_ife_0_dsp_clk = {
1236 .halt_reg = 0x9038,
1237 .halt_check = BRANCH_HALT,
1238 .clkr = {
1239 .enable_reg = 0x9038,
1240 .enable_mask = BIT(0),
1241 .hw.init = &(struct clk_init_data){
1242 .name = "camcc_ife_0_dsp_clk",
1243 .parent_hws = (const struct clk_hw*[]){
1244 &camcc_ife_0_clk_src.clkr.hw
1245 },
1246 .num_parents = 1,
1247 .flags = CLK_SET_RATE_PARENT,
1248 .ops = &clk_branch2_ops,
1249 },
1250 },
1251 };
1252
1253 static struct clk_branch camcc_ife_1_axi_clk = {
1254 .halt_reg = 0xa058,
1255 .halt_check = BRANCH_HALT,
1256 .clkr = {
1257 .enable_reg = 0xa058,
1258 .enable_mask = BIT(0),
1259 .hw.init = &(struct clk_init_data){
1260 .name = "camcc_ife_1_axi_clk",
1261 .ops = &clk_branch2_ops,
1262 },
1263 },
1264 };
1265
1266 static struct clk_branch camcc_ife_1_clk = {
1267 .halt_reg = 0xa028,
1268 .halt_check = BRANCH_HALT,
1269 .clkr = {
1270 .enable_reg = 0xa028,
1271 .enable_mask = BIT(0),
1272 .hw.init = &(struct clk_init_data){
1273 .name = "camcc_ife_1_clk",
1274 .parent_hws = (const struct clk_hw*[]){
1275 &camcc_ife_1_clk_src.clkr.hw
1276 },
1277 .num_parents = 1,
1278 .flags = CLK_SET_RATE_PARENT,
1279 .ops = &clk_branch2_ops,
1280 },
1281 },
1282 };
1283
1284 static struct clk_branch camcc_ife_1_cphy_rx_clk = {
1285 .halt_reg = 0xa054,
1286 .halt_check = BRANCH_HALT,
1287 .clkr = {
1288 .enable_reg = 0xa054,
1289 .enable_mask = BIT(0),
1290 .hw.init = &(struct clk_init_data){
1291 .name = "camcc_ife_1_cphy_rx_clk",
1292 .parent_hws = (const struct clk_hw*[]){
1293 &camcc_cphy_rx_clk_src.clkr.hw
1294 },
1295 .num_parents = 1,
1296 .flags = CLK_SET_RATE_PARENT,
1297 .ops = &clk_branch2_ops,
1298 },
1299 },
1300 };
1301
1302 static struct clk_branch camcc_ife_1_csid_clk = {
1303 .halt_reg = 0xa04c,
1304 .halt_check = BRANCH_HALT,
1305 .clkr = {
1306 .enable_reg = 0xa04c,
1307 .enable_mask = BIT(0),
1308 .hw.init = &(struct clk_init_data){
1309 .name = "camcc_ife_1_csid_clk",
1310 .parent_hws = (const struct clk_hw*[]){
1311 &camcc_ife_1_csid_clk_src.clkr.hw
1312 },
1313 .num_parents = 1,
1314 .flags = CLK_SET_RATE_PARENT,
1315 .ops = &clk_branch2_ops,
1316 },
1317 },
1318 };
1319
1320 static struct clk_branch camcc_ife_1_dsp_clk = {
1321 .halt_reg = 0xa030,
1322 .halt_check = BRANCH_HALT,
1323 .clkr = {
1324 .enable_reg = 0xa030,
1325 .enable_mask = BIT(0),
1326 .hw.init = &(struct clk_init_data){
1327 .name = "camcc_ife_1_dsp_clk",
1328 .parent_hws = (const struct clk_hw*[]){
1329 &camcc_ife_1_clk_src.clkr.hw
1330 },
1331 .num_parents = 1,
1332 .flags = CLK_SET_RATE_PARENT,
1333 .ops = &clk_branch2_ops,
1334 },
1335 },
1336 };
1337
1338 static struct clk_branch camcc_ife_2_axi_clk = {
1339 .halt_reg = 0xb054,
1340 .halt_check = BRANCH_HALT,
1341 .clkr = {
1342 .enable_reg = 0xb054,
1343 .enable_mask = BIT(0),
1344 .hw.init = &(struct clk_init_data){
1345 .name = "camcc_ife_2_axi_clk",
1346 .ops = &clk_branch2_ops,
1347 },
1348 },
1349 };
1350
1351 static struct clk_branch camcc_ife_2_clk = {
1352 .halt_reg = 0xb024,
1353 .halt_check = BRANCH_HALT,
1354 .clkr = {
1355 .enable_reg = 0xb024,
1356 .enable_mask = BIT(0),
1357 .hw.init = &(struct clk_init_data){
1358 .name = "camcc_ife_2_clk",
1359 .parent_hws = (const struct clk_hw*[]){
1360 &camcc_ife_2_clk_src.clkr.hw
1361 },
1362 .num_parents = 1,
1363 .flags = CLK_SET_RATE_PARENT,
1364 .ops = &clk_branch2_ops,
1365 },
1366 },
1367 };
1368
1369 static struct clk_branch camcc_ife_2_cphy_rx_clk = {
1370 .halt_reg = 0xb050,
1371 .halt_check = BRANCH_HALT,
1372 .clkr = {
1373 .enable_reg = 0xb050,
1374 .enable_mask = BIT(0),
1375 .hw.init = &(struct clk_init_data){
1376 .name = "camcc_ife_2_cphy_rx_clk",
1377 .parent_hws = (const struct clk_hw*[]){
1378 &camcc_cphy_rx_clk_src.clkr.hw
1379 },
1380 .num_parents = 1,
1381 .flags = CLK_SET_RATE_PARENT,
1382 .ops = &clk_branch2_ops,
1383 },
1384 },
1385 };
1386
1387 static struct clk_branch camcc_ife_2_csid_clk = {
1388 .halt_reg = 0xb048,
1389 .halt_check = BRANCH_HALT,
1390 .clkr = {
1391 .enable_reg = 0xb048,
1392 .enable_mask = BIT(0),
1393 .hw.init = &(struct clk_init_data){
1394 .name = "camcc_ife_2_csid_clk",
1395 .parent_hws = (const struct clk_hw*[]){
1396 &camcc_ife_2_csid_clk_src.clkr.hw
1397 },
1398 .num_parents = 1,
1399 .flags = CLK_SET_RATE_PARENT,
1400 .ops = &clk_branch2_ops,
1401 },
1402 },
1403 };
1404
1405 static struct clk_branch camcc_ife_2_dsp_clk = {
1406 .halt_reg = 0xb02c,
1407 .halt_check = BRANCH_HALT,
1408 .clkr = {
1409 .enable_reg = 0xb02c,
1410 .enable_mask = BIT(0),
1411 .hw.init = &(struct clk_init_data){
1412 .name = "camcc_ife_2_dsp_clk",
1413 .parent_hws = (const struct clk_hw*[]){
1414 &camcc_ife_2_clk_src.clkr.hw
1415 },
1416 .num_parents = 1,
1417 .flags = CLK_SET_RATE_PARENT,
1418 .ops = &clk_branch2_ops,
1419 },
1420 },
1421 };
1422
1423 static struct clk_branch camcc_ife_lite_clk = {
1424 .halt_reg = 0xc01c,
1425 .halt_check = BRANCH_HALT,
1426 .clkr = {
1427 .enable_reg = 0xc01c,
1428 .enable_mask = BIT(0),
1429 .hw.init = &(struct clk_init_data){
1430 .name = "camcc_ife_lite_clk",
1431 .parent_hws = (const struct clk_hw*[]){
1432 &camcc_ife_lite_clk_src.clkr.hw
1433 },
1434 .num_parents = 1,
1435 .flags = CLK_SET_RATE_PARENT,
1436 .ops = &clk_branch2_ops,
1437 },
1438 },
1439 };
1440
1441 static struct clk_branch camcc_ife_lite_cphy_rx_clk = {
1442 .halt_reg = 0xc044,
1443 .halt_check = BRANCH_HALT,
1444 .clkr = {
1445 .enable_reg = 0xc044,
1446 .enable_mask = BIT(0),
1447 .hw.init = &(struct clk_init_data){
1448 .name = "camcc_ife_lite_cphy_rx_clk",
1449 .parent_hws = (const struct clk_hw*[]){
1450 &camcc_cphy_rx_clk_src.clkr.hw
1451 },
1452 .num_parents = 1,
1453 .flags = CLK_SET_RATE_PARENT,
1454 .ops = &clk_branch2_ops,
1455 },
1456 },
1457 };
1458
1459 static struct clk_branch camcc_ife_lite_csid_clk = {
1460 .halt_reg = 0xc03c,
1461 .halt_check = BRANCH_HALT,
1462 .clkr = {
1463 .enable_reg = 0xc03c,
1464 .enable_mask = BIT(0),
1465 .hw.init = &(struct clk_init_data){
1466 .name = "camcc_ife_lite_csid_clk",
1467 .parent_hws = (const struct clk_hw*[]){
1468 &camcc_ife_lite_csid_clk_src.clkr.hw
1469 },
1470 .num_parents = 1,
1471 .flags = CLK_SET_RATE_PARENT,
1472 .ops = &clk_branch2_ops,
1473 },
1474 },
1475 };
1476
1477 static struct clk_branch camcc_ipe_0_ahb_clk = {
1478 .halt_reg = 0x7040,
1479 .halt_check = BRANCH_HALT,
1480 .clkr = {
1481 .enable_reg = 0x7040,
1482 .enable_mask = BIT(0),
1483 .hw.init = &(struct clk_init_data){
1484 .name = "camcc_ipe_0_ahb_clk",
1485 .parent_hws = (const struct clk_hw*[]){
1486 &camcc_slow_ahb_clk_src.clkr.hw
1487 },
1488 .num_parents = 1,
1489 .flags = CLK_SET_RATE_PARENT,
1490 .ops = &clk_branch2_ops,
1491 },
1492 },
1493 };
1494
1495 static struct clk_branch camcc_ipe_0_areg_clk = {
1496 .halt_reg = 0x703c,
1497 .halt_check = BRANCH_HALT,
1498 .clkr = {
1499 .enable_reg = 0x703c,
1500 .enable_mask = BIT(0),
1501 .hw.init = &(struct clk_init_data){
1502 .name = "camcc_ipe_0_areg_clk",
1503 .parent_hws = (const struct clk_hw*[]){
1504 &camcc_fast_ahb_clk_src.clkr.hw
1505 },
1506 .num_parents = 1,
1507 .flags = CLK_SET_RATE_PARENT,
1508 .ops = &clk_branch2_ops,
1509 },
1510 },
1511 };
1512
1513 static struct clk_branch camcc_ipe_0_axi_clk = {
1514 .halt_reg = 0x7038,
1515 .halt_check = BRANCH_HALT,
1516 .clkr = {
1517 .enable_reg = 0x7038,
1518 .enable_mask = BIT(0),
1519 .hw.init = &(struct clk_init_data){
1520 .name = "camcc_ipe_0_axi_clk",
1521 .ops = &clk_branch2_ops,
1522 },
1523 },
1524 };
1525
1526 static struct clk_branch camcc_ipe_0_clk = {
1527 .halt_reg = 0x7028,
1528 .halt_check = BRANCH_HALT,
1529 .clkr = {
1530 .enable_reg = 0x7028,
1531 .enable_mask = BIT(0),
1532 .hw.init = &(struct clk_init_data){
1533 .name = "camcc_ipe_0_clk",
1534 .parent_hws = (const struct clk_hw*[]){
1535 &camcc_ipe_0_clk_src.clkr.hw
1536 },
1537 .num_parents = 1,
1538 .flags = CLK_SET_RATE_PARENT,
1539 .ops = &clk_branch2_ops,
1540 },
1541 },
1542 };
1543
1544 static struct clk_branch camcc_jpeg_clk = {
1545 .halt_reg = 0xd01c,
1546 .halt_check = BRANCH_HALT,
1547 .clkr = {
1548 .enable_reg = 0xd01c,
1549 .enable_mask = BIT(0),
1550 .hw.init = &(struct clk_init_data){
1551 .name = "camcc_jpeg_clk",
1552 .parent_hws = (const struct clk_hw*[]){
1553 &camcc_jpeg_clk_src.clkr.hw
1554 },
1555 .num_parents = 1,
1556 .flags = CLK_SET_RATE_PARENT,
1557 .ops = &clk_branch2_ops,
1558 },
1559 },
1560 };
1561
1562 static struct clk_branch camcc_lrme_clk = {
1563 .halt_reg = 0x1101c,
1564 .halt_check = BRANCH_HALT,
1565 .clkr = {
1566 .enable_reg = 0x1101c,
1567 .enable_mask = BIT(0),
1568 .hw.init = &(struct clk_init_data){
1569 .name = "camcc_lrme_clk",
1570 .parent_hws = (const struct clk_hw*[]){
1571 &camcc_lrme_clk_src.clkr.hw
1572 },
1573 .num_parents = 1,
1574 .flags = CLK_SET_RATE_PARENT,
1575 .ops = &clk_branch2_ops,
1576 },
1577 },
1578 };
1579
1580 static struct clk_branch camcc_mclk0_clk = {
1581 .halt_reg = 0x401c,
1582 .halt_check = BRANCH_HALT,
1583 .clkr = {
1584 .enable_reg = 0x401c,
1585 .enable_mask = BIT(0),
1586 .hw.init = &(struct clk_init_data){
1587 .name = "camcc_mclk0_clk",
1588 .parent_hws = (const struct clk_hw*[]){
1589 &camcc_mclk0_clk_src.clkr.hw
1590 },
1591 .num_parents = 1,
1592 .flags = CLK_SET_RATE_PARENT,
1593 .ops = &clk_branch2_ops,
1594 },
1595 },
1596 };
1597
1598 static struct clk_branch camcc_mclk1_clk = {
1599 .halt_reg = 0x403c,
1600 .halt_check = BRANCH_HALT,
1601 .clkr = {
1602 .enable_reg = 0x403c,
1603 .enable_mask = BIT(0),
1604 .hw.init = &(struct clk_init_data){
1605 .name = "camcc_mclk1_clk",
1606 .parent_hws = (const struct clk_hw*[]){
1607 &camcc_mclk1_clk_src.clkr.hw
1608 },
1609 .num_parents = 1,
1610 .flags = CLK_SET_RATE_PARENT,
1611 .ops = &clk_branch2_ops,
1612 },
1613 },
1614 };
1615
1616 static struct clk_branch camcc_mclk2_clk = {
1617 .halt_reg = 0x405c,
1618 .halt_check = BRANCH_HALT,
1619 .clkr = {
1620 .enable_reg = 0x405c,
1621 .enable_mask = BIT(0),
1622 .hw.init = &(struct clk_init_data){
1623 .name = "camcc_mclk2_clk",
1624 .parent_hws = (const struct clk_hw*[]){
1625 &camcc_mclk2_clk_src.clkr.hw
1626 },
1627 .num_parents = 1,
1628 .flags = CLK_SET_RATE_PARENT,
1629 .ops = &clk_branch2_ops,
1630 },
1631 },
1632 };
1633
1634 static struct clk_branch camcc_mclk3_clk = {
1635 .halt_reg = 0x407c,
1636 .halt_check = BRANCH_HALT,
1637 .clkr = {
1638 .enable_reg = 0x407c,
1639 .enable_mask = BIT(0),
1640 .hw.init = &(struct clk_init_data){
1641 .name = "camcc_mclk3_clk",
1642 .parent_hws = (const struct clk_hw*[]){
1643 &camcc_mclk3_clk_src.clkr.hw
1644 },
1645 .num_parents = 1,
1646 .flags = CLK_SET_RATE_PARENT,
1647 .ops = &clk_branch2_ops,
1648 },
1649 },
1650 };
1651
1652 static struct clk_branch camcc_mclk4_clk = {
1653 .halt_reg = 0x409c,
1654 .halt_check = BRANCH_HALT,
1655 .clkr = {
1656 .enable_reg = 0x409c,
1657 .enable_mask = BIT(0),
1658 .hw.init = &(struct clk_init_data){
1659 .name = "camcc_mclk4_clk",
1660 .parent_hws = (const struct clk_hw*[]){
1661 &camcc_mclk4_clk_src.clkr.hw
1662 },
1663 .num_parents = 1,
1664 .flags = CLK_SET_RATE_PARENT,
1665 .ops = &clk_branch2_ops,
1666 },
1667 },
1668 };
1669
1670 static struct clk_branch camcc_soc_ahb_clk = {
1671 .halt_reg = 0x1400c,
1672 .halt_check = BRANCH_HALT,
1673 .clkr = {
1674 .enable_reg = 0x1400c,
1675 .enable_mask = BIT(0),
1676 .hw.init = &(struct clk_init_data){
1677 .name = "camcc_soc_ahb_clk",
1678 .ops = &clk_branch2_ops,
1679 },
1680 },
1681 };
1682
1683 static struct clk_branch camcc_sys_tmr_clk = {
1684 .halt_reg = 0xe034,
1685 .halt_check = BRANCH_HALT,
1686 .clkr = {
1687 .enable_reg = 0xe034,
1688 .enable_mask = BIT(0),
1689 .hw.init = &(struct clk_init_data){
1690 .name = "camcc_sys_tmr_clk",
1691 .ops = &clk_branch2_ops,
1692 },
1693 },
1694 };
1695
1696 static struct gdsc bps_gdsc = {
1697 .gdscr = 0x6004,
1698 .en_rest_wait_val = 0x2,
1699 .en_few_wait_val = 0x2,
1700 .clk_dis_wait_val = 0xf,
1701 .pd = {
1702 .name = "bps_gdsc",
1703 },
1704 .pwrsts = PWRSTS_OFF_ON,
1705 .flags = VOTABLE,
1706 };
1707
1708 static struct gdsc ipe_0_gdsc = {
1709 .gdscr = 0x7004,
1710 .en_rest_wait_val = 0x2,
1711 .en_few_wait_val = 0x2,
1712 .clk_dis_wait_val = 0xf,
1713 .pd = {
1714 .name = "ipe_0_gdsc",
1715 },
1716 .pwrsts = PWRSTS_OFF_ON,
1717 .flags = VOTABLE,
1718 };
1719
1720 static struct gdsc ife_0_gdsc = {
1721 .gdscr = 0x9004,
1722 .en_rest_wait_val = 0x2,
1723 .en_few_wait_val = 0x2,
1724 .clk_dis_wait_val = 0xf,
1725 .pd = {
1726 .name = "ife_0_gdsc",
1727 },
1728 .pwrsts = PWRSTS_OFF_ON,
1729 };
1730
1731 static struct gdsc ife_1_gdsc = {
1732 .gdscr = 0xa004,
1733 .en_rest_wait_val = 0x2,
1734 .en_few_wait_val = 0x2,
1735 .clk_dis_wait_val = 0xf,
1736 .pd = {
1737 .name = "ife_1_gdsc",
1738 },
1739 .pwrsts = PWRSTS_OFF_ON,
1740 };
1741
1742 static struct gdsc ife_2_gdsc = {
1743 .gdscr = 0xb004,
1744 .en_rest_wait_val = 0x2,
1745 .en_few_wait_val = 0x2,
1746 .clk_dis_wait_val = 0xf,
1747 .pd = {
1748 .name = "ife_2_gdsc",
1749 },
1750 .pwrsts = PWRSTS_OFF_ON,
1751 };
1752
1753 static struct gdsc titan_top_gdsc = {
1754 .gdscr = 0x14004,
1755 .en_rest_wait_val = 0x2,
1756 .en_few_wait_val = 0x2,
1757 .clk_dis_wait_val = 0xf,
1758 .pd = {
1759 .name = "titan_top_gdsc",
1760 },
1761 .pwrsts = PWRSTS_OFF_ON,
1762 };
1763
1764 static struct clk_hw *camcc_sm6350_hws[] = {
1765 [CAMCC_PLL2_OUT_EARLY] = &camcc_pll2_out_early.hw,
1766 };
1767
1768 static struct clk_regmap *camcc_sm6350_clocks[] = {
1769 [CAMCC_BPS_AHB_CLK] = &camcc_bps_ahb_clk.clkr,
1770 [CAMCC_BPS_AREG_CLK] = &camcc_bps_areg_clk.clkr,
1771 [CAMCC_BPS_AXI_CLK] = &camcc_bps_axi_clk.clkr,
1772 [CAMCC_BPS_CLK] = &camcc_bps_clk.clkr,
1773 [CAMCC_BPS_CLK_SRC] = &camcc_bps_clk_src.clkr,
1774 [CAMCC_CAMNOC_AXI_CLK] = &camcc_camnoc_axi_clk.clkr,
1775 [CAMCC_CCI_0_CLK] = &camcc_cci_0_clk.clkr,
1776 [CAMCC_CCI_0_CLK_SRC] = &camcc_cci_0_clk_src.clkr,
1777 [CAMCC_CCI_1_CLK] = &camcc_cci_1_clk.clkr,
1778 [CAMCC_CCI_1_CLK_SRC] = &camcc_cci_1_clk_src.clkr,
1779 [CAMCC_CORE_AHB_CLK] = &camcc_core_ahb_clk.clkr,
1780 [CAMCC_CPAS_AHB_CLK] = &camcc_cpas_ahb_clk.clkr,
1781 [CAMCC_CPHY_RX_CLK_SRC] = &camcc_cphy_rx_clk_src.clkr,
1782 [CAMCC_CSI0PHYTIMER_CLK] = &camcc_csi0phytimer_clk.clkr,
1783 [CAMCC_CSI0PHYTIMER_CLK_SRC] = &camcc_csi0phytimer_clk_src.clkr,
1784 [CAMCC_CSI1PHYTIMER_CLK] = &camcc_csi1phytimer_clk.clkr,
1785 [CAMCC_CSI1PHYTIMER_CLK_SRC] = &camcc_csi1phytimer_clk_src.clkr,
1786 [CAMCC_CSI2PHYTIMER_CLK] = &camcc_csi2phytimer_clk.clkr,
1787 [CAMCC_CSI2PHYTIMER_CLK_SRC] = &camcc_csi2phytimer_clk_src.clkr,
1788 [CAMCC_CSI3PHYTIMER_CLK] = &camcc_csi3phytimer_clk.clkr,
1789 [CAMCC_CSI3PHYTIMER_CLK_SRC] = &camcc_csi3phytimer_clk_src.clkr,
1790 [CAMCC_CSIPHY0_CLK] = &camcc_csiphy0_clk.clkr,
1791 [CAMCC_CSIPHY1_CLK] = &camcc_csiphy1_clk.clkr,
1792 [CAMCC_CSIPHY2_CLK] = &camcc_csiphy2_clk.clkr,
1793 [CAMCC_CSIPHY3_CLK] = &camcc_csiphy3_clk.clkr,
1794 [CAMCC_FAST_AHB_CLK_SRC] = &camcc_fast_ahb_clk_src.clkr,
1795 [CAMCC_ICP_CLK] = &camcc_icp_clk.clkr,
1796 [CAMCC_ICP_CLK_SRC] = &camcc_icp_clk_src.clkr,
1797 [CAMCC_ICP_TS_CLK] = &camcc_icp_ts_clk.clkr,
1798 [CAMCC_IFE_0_AXI_CLK] = &camcc_ife_0_axi_clk.clkr,
1799 [CAMCC_IFE_0_CLK] = &camcc_ife_0_clk.clkr,
1800 [CAMCC_IFE_0_CLK_SRC] = &camcc_ife_0_clk_src.clkr,
1801 [CAMCC_IFE_0_CPHY_RX_CLK] = &camcc_ife_0_cphy_rx_clk.clkr,
1802 [CAMCC_IFE_0_CSID_CLK] = &camcc_ife_0_csid_clk.clkr,
1803 [CAMCC_IFE_0_CSID_CLK_SRC] = &camcc_ife_0_csid_clk_src.clkr,
1804 [CAMCC_IFE_0_DSP_CLK] = &camcc_ife_0_dsp_clk.clkr,
1805 [CAMCC_IFE_1_AXI_CLK] = &camcc_ife_1_axi_clk.clkr,
1806 [CAMCC_IFE_1_CLK] = &camcc_ife_1_clk.clkr,
1807 [CAMCC_IFE_1_CLK_SRC] = &camcc_ife_1_clk_src.clkr,
1808 [CAMCC_IFE_1_CPHY_RX_CLK] = &camcc_ife_1_cphy_rx_clk.clkr,
1809 [CAMCC_IFE_1_CSID_CLK] = &camcc_ife_1_csid_clk.clkr,
1810 [CAMCC_IFE_1_CSID_CLK_SRC] = &camcc_ife_1_csid_clk_src.clkr,
1811 [CAMCC_IFE_1_DSP_CLK] = &camcc_ife_1_dsp_clk.clkr,
1812 [CAMCC_IFE_2_AXI_CLK] = &camcc_ife_2_axi_clk.clkr,
1813 [CAMCC_IFE_2_CLK] = &camcc_ife_2_clk.clkr,
1814 [CAMCC_IFE_2_CLK_SRC] = &camcc_ife_2_clk_src.clkr,
1815 [CAMCC_IFE_2_CPHY_RX_CLK] = &camcc_ife_2_cphy_rx_clk.clkr,
1816 [CAMCC_IFE_2_CSID_CLK] = &camcc_ife_2_csid_clk.clkr,
1817 [CAMCC_IFE_2_CSID_CLK_SRC] = &camcc_ife_2_csid_clk_src.clkr,
1818 [CAMCC_IFE_2_DSP_CLK] = &camcc_ife_2_dsp_clk.clkr,
1819 [CAMCC_IFE_LITE_CLK] = &camcc_ife_lite_clk.clkr,
1820 [CAMCC_IFE_LITE_CLK_SRC] = &camcc_ife_lite_clk_src.clkr,
1821 [CAMCC_IFE_LITE_CPHY_RX_CLK] = &camcc_ife_lite_cphy_rx_clk.clkr,
1822 [CAMCC_IFE_LITE_CSID_CLK] = &camcc_ife_lite_csid_clk.clkr,
1823 [CAMCC_IFE_LITE_CSID_CLK_SRC] = &camcc_ife_lite_csid_clk_src.clkr,
1824 [CAMCC_IPE_0_AHB_CLK] = &camcc_ipe_0_ahb_clk.clkr,
1825 [CAMCC_IPE_0_AREG_CLK] = &camcc_ipe_0_areg_clk.clkr,
1826 [CAMCC_IPE_0_AXI_CLK] = &camcc_ipe_0_axi_clk.clkr,
1827 [CAMCC_IPE_0_CLK] = &camcc_ipe_0_clk.clkr,
1828 [CAMCC_IPE_0_CLK_SRC] = &camcc_ipe_0_clk_src.clkr,
1829 [CAMCC_JPEG_CLK] = &camcc_jpeg_clk.clkr,
1830 [CAMCC_JPEG_CLK_SRC] = &camcc_jpeg_clk_src.clkr,
1831 [CAMCC_LRME_CLK] = &camcc_lrme_clk.clkr,
1832 [CAMCC_LRME_CLK_SRC] = &camcc_lrme_clk_src.clkr,
1833 [CAMCC_MCLK0_CLK] = &camcc_mclk0_clk.clkr,
1834 [CAMCC_MCLK0_CLK_SRC] = &camcc_mclk0_clk_src.clkr,
1835 [CAMCC_MCLK1_CLK] = &camcc_mclk1_clk.clkr,
1836 [CAMCC_MCLK1_CLK_SRC] = &camcc_mclk1_clk_src.clkr,
1837 [CAMCC_MCLK2_CLK] = &camcc_mclk2_clk.clkr,
1838 [CAMCC_MCLK2_CLK_SRC] = &camcc_mclk2_clk_src.clkr,
1839 [CAMCC_MCLK3_CLK] = &camcc_mclk3_clk.clkr,
1840 [CAMCC_MCLK3_CLK_SRC] = &camcc_mclk3_clk_src.clkr,
1841 [CAMCC_MCLK4_CLK] = &camcc_mclk4_clk.clkr,
1842 [CAMCC_MCLK4_CLK_SRC] = &camcc_mclk4_clk_src.clkr,
1843 [CAMCC_PLL0] = &camcc_pll0.clkr,
1844 [CAMCC_PLL0_OUT_EVEN] = &camcc_pll0_out_even.clkr,
1845 [CAMCC_PLL1] = &camcc_pll1.clkr,
1846 [CAMCC_PLL1_OUT_EVEN] = &camcc_pll1_out_even.clkr,
1847 [CAMCC_PLL2] = &camcc_pll2.clkr,
1848 [CAMCC_PLL2_OUT_MAIN] = &camcc_pll2_out_main.clkr,
1849 [CAMCC_PLL3] = &camcc_pll3.clkr,
1850 [CAMCC_SLOW_AHB_CLK_SRC] = &camcc_slow_ahb_clk_src.clkr,
1851 [CAMCC_SOC_AHB_CLK] = &camcc_soc_ahb_clk.clkr,
1852 [CAMCC_SYS_TMR_CLK] = &camcc_sys_tmr_clk.clkr,
1853 };
1854
1855 static struct gdsc *camcc_sm6350_gdscs[] = {
1856 [BPS_GDSC] = &bps_gdsc,
1857 [IPE_0_GDSC] = &ipe_0_gdsc,
1858 [IFE_0_GDSC] = &ife_0_gdsc,
1859 [IFE_1_GDSC] = &ife_1_gdsc,
1860 [IFE_2_GDSC] = &ife_2_gdsc,
1861 [TITAN_TOP_GDSC] = &titan_top_gdsc,
1862 };
1863
1864 static const struct regmap_config camcc_sm6350_regmap_config = {
1865 .reg_bits = 32,
1866 .reg_stride = 4,
1867 .val_bits = 32,
1868 .max_register = 0x16000,
1869 .fast_io = true,
1870 };
1871
1872 static const struct qcom_cc_desc camcc_sm6350_desc = {
1873 .config = &camcc_sm6350_regmap_config,
1874 .clk_hws = camcc_sm6350_hws,
1875 .num_clk_hws = ARRAY_SIZE(camcc_sm6350_hws),
1876 .clks = camcc_sm6350_clocks,
1877 .num_clks = ARRAY_SIZE(camcc_sm6350_clocks),
1878 .gdscs = camcc_sm6350_gdscs,
1879 .num_gdscs = ARRAY_SIZE(camcc_sm6350_gdscs),
1880 };
1881
1882 static const struct of_device_id camcc_sm6350_match_table[] = {
1883 { .compatible = "qcom,sm6350-camcc" },
1884 { }
1885 };
1886 MODULE_DEVICE_TABLE(of, camcc_sm6350_match_table);
1887
camcc_sm6350_probe(struct platform_device * pdev)1888 static int camcc_sm6350_probe(struct platform_device *pdev)
1889 {
1890 struct regmap *regmap;
1891
1892 regmap = qcom_cc_map(pdev, &camcc_sm6350_desc);
1893 if (IS_ERR(regmap))
1894 return PTR_ERR(regmap);
1895
1896 clk_fabia_pll_configure(&camcc_pll0, regmap, &camcc_pll0_config);
1897 clk_fabia_pll_configure(&camcc_pll1, regmap, &camcc_pll1_config);
1898 clk_agera_pll_configure(&camcc_pll2, regmap, &camcc_pll2_config);
1899 clk_fabia_pll_configure(&camcc_pll3, regmap, &camcc_pll3_config);
1900
1901 return qcom_cc_really_probe(&pdev->dev, &camcc_sm6350_desc, regmap);
1902 }
1903
1904 static struct platform_driver camcc_sm6350_driver = {
1905 .probe = camcc_sm6350_probe,
1906 .driver = {
1907 .name = "sm6350-camcc",
1908 .of_match_table = camcc_sm6350_match_table,
1909 },
1910 };
1911
1912 module_platform_driver(camcc_sm6350_driver);
1913
1914 MODULE_DESCRIPTION("QTI CAMCC SM6350 Driver");
1915 MODULE_LICENSE("GPL");
1916