xref: /linux/arch/arm/boot/dts/ti/omap/omap34xx-omap36xx-clocks.dtsi (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Device Tree Source for OMAP34XX/OMAP36XX clock data
4 *
5 * Copyright (C) 2013 Texas Instruments, Inc.
6 */
7&cm_clocks {
8	security_l4_ick2: security_l4_ick2 {
9		#clock-cells = <0>;
10		compatible = "fixed-factor-clock";
11		clocks = <&l4_ick>;
12		clock-mult = <1>;
13		clock-div = <1>;
14	};
15
16	clock@a14 {
17		compatible = "ti,clksel";
18		reg = <0xa14>;
19		#clock-cells = <2>;
20		#address-cells = <1>;
21		#size-cells = <0>;
22
23		aes1_ick: clock-aes1-ick@3 {
24			reg = <3>;
25			#clock-cells = <0>;
26			compatible = "ti,omap3-interface-clock";
27			clock-output-names = "aes1_ick";
28			clocks = <&security_l4_ick2>;
29		};
30
31		rng_ick: clock-rng-ick@2 {
32			reg = <2>;
33			#clock-cells = <0>;
34			compatible = "ti,omap3-interface-clock";
35			clock-output-names = "rng_ick";
36			clocks = <&security_l4_ick2>;
37		};
38
39		sha11_ick: clock-sha11-ick@1 {
40			reg = <1>;
41			#clock-cells = <0>;
42			compatible = "ti,omap3-interface-clock";
43			clock-output-names = "sha11_ick";
44			clocks = <&security_l4_ick2>;
45		};
46
47		des1_ick: clock-des1-ick@0 {
48			reg = <0>;
49			#clock-cells = <0>;
50			compatible = "ti,omap3-interface-clock";
51			clock-output-names = "des1_ick";
52			clocks = <&security_l4_ick2>;
53		};
54
55		pka_ick: clock-pka-ick@4 {
56			reg = <4>;
57			#clock-cells = <0>;
58			compatible = "ti,omap3-interface-clock";
59			clock-output-names = "pka_ick";
60			clocks = <&security_l3_ick>;
61		};
62	};
63
64	/* CM_FCLKEN_CAM */
65	clock@f00 {
66		compatible = "ti,clksel";
67		reg = <0xf00>;
68		#clock-cells = <2>;
69		#address-cells = <1>;
70		#size-cells = <0>;
71
72		cam_mclk: clock-cam-mclk@0 {
73			reg = <0>;
74			#clock-cells = <0>;
75			compatible = "ti,gate-clock";
76			clock-output-names = "cam_mclk";
77			clocks = <&dpll4_m5x2_ck>;
78			ti,set-rate-parent;
79		};
80
81		csi2_96m_fck: clock-csi2-96m-fck@1 {
82			reg = <1>;
83			#clock-cells = <0>;
84			compatible = "ti,gate-clock";
85			clock-output-names = "csi2_96m_fck";
86			clocks = <&core_96m_fck>;
87		};
88	};
89
90	cam_ick: cam_ick@f10 {
91		#clock-cells = <0>;
92		compatible = "ti,omap3-no-wait-interface-clock";
93		clocks = <&l4_ick>;
94		reg = <0x0f10>;
95		ti,bit-shift = <0>;
96	};
97
98	security_l3_ick: security_l3_ick {
99		#clock-cells = <0>;
100		compatible = "fixed-factor-clock";
101		clocks = <&l3_ick>;
102		clock-mult = <1>;
103		clock-div = <1>;
104	};
105
106	clock@a10 {
107		compatible = "ti,clksel";
108		reg = <0xa10>;
109		#clock-cells = <2>;
110		#address-cells = <1>;
111		#size-cells = <0>;
112
113		icr_ick: clock-icr-ick@29 {
114			reg = <29>;
115			#clock-cells = <0>;
116			compatible = "ti,omap3-interface-clock";
117			clock-output-names = "icr_ick";
118			clocks = <&core_l4_ick>;
119		};
120
121		des2_ick: clock-des2-ick@26 {
122			reg = <26>;
123			#clock-cells = <0>;
124			compatible = "ti,omap3-interface-clock";
125			clock-output-names = "des2_ick";
126			clocks = <&core_l4_ick>;
127		};
128
129		mspro_ick: clock-mspro-ick@23 {
130			reg = <23>;
131			#clock-cells = <0>;
132			compatible = "ti,omap3-interface-clock";
133			clock-output-names = "mspro_ick";
134			clocks = <&core_l4_ick>;
135		};
136
137		mailboxes_ick: clock-mailboxes-ick@7 {
138			reg = <7>;
139			#clock-cells = <0>;
140			compatible = "ti,omap3-interface-clock";
141			clock-output-names = "mailboxes_ick";
142			clocks = <&core_l4_ick>;
143		};
144
145		sad2d_ick: clock-sad2d-ick@3 {
146			reg = <3>;
147			#clock-cells = <0>;
148			compatible = "ti,omap3-interface-clock";
149			clock-output-names = "sad2d_ick";
150			clocks = <&l3_ick>;
151		};
152	};
153
154	ssi_l4_ick: ssi_l4_ick {
155		#clock-cells = <0>;
156		compatible = "fixed-factor-clock";
157		clocks = <&l4_ick>;
158		clock-mult = <1>;
159		clock-div = <1>;
160	};
161
162	clock@c00 {
163		compatible = "ti,clksel";
164		reg = <0xc00>;
165		#clock-cells = <2>;
166		#address-cells = <1>;
167		#size-cells = <0>;
168
169		sr1_fck: clock-sr1-fck@6 {
170			reg = <6>;
171			#clock-cells = <0>;
172			compatible = "ti,wait-gate-clock";
173			clock-output-names = "sr1_fck";
174			clocks = <&sys_ck>;
175		};
176
177		sr2_fck: clock-sr2-fck@7 {
178			reg = <7>;
179			#clock-cells = <0>;
180			compatible = "ti,wait-gate-clock";
181			clock-output-names = "sr2_fck";
182			clocks = <&sys_ck>;
183		};
184	};
185
186	sr_l4_ick: sr_l4_ick {
187		#clock-cells = <0>;
188		compatible = "fixed-factor-clock";
189		clocks = <&l4_ick>;
190		clock-mult = <1>;
191		clock-div = <1>;
192	};
193
194	dpll2_fck: dpll2_fck@40 {
195		#clock-cells = <0>;
196		compatible = "ti,divider-clock";
197		clocks = <&core_ck>;
198		ti,bit-shift = <19>;
199		ti,max-div = <7>;
200		reg = <0x0040>;
201		ti,index-starts-at-one;
202	};
203
204	dpll2_ck: dpll2_ck@4 {
205		#clock-cells = <0>;
206		compatible = "ti,omap3-dpll-clock";
207		clocks = <&sys_ck>, <&dpll2_fck>;
208		reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
209		ti,low-power-stop;
210		ti,lock;
211		ti,low-power-bypass;
212	};
213
214	dpll2_m2_ck: dpll2_m2_ck@44 {
215		#clock-cells = <0>;
216		compatible = "ti,divider-clock";
217		clocks = <&dpll2_ck>;
218		ti,max-div = <31>;
219		reg = <0x0044>;
220		ti,index-starts-at-one;
221	};
222
223	iva2_ck: iva2_ck@0 {
224		#clock-cells = <0>;
225		compatible = "ti,wait-gate-clock";
226		clocks = <&dpll2_m2_ck>;
227		reg = <0x0000>;
228		ti,bit-shift = <0>;
229	};
230
231	clock@a00 {
232		compatible = "ti,clksel";
233		reg = <0xa00>;
234		#clock-cells = <2>;
235		#address-cells = <1>;
236		#size-cells = <0>;
237
238		modem_fck: clock-modem-fck@31 {
239			reg = <31>;
240			#clock-cells = <0>;
241			compatible = "ti,omap3-interface-clock";
242			clock-output-names = "modem_fck";
243			clocks = <&sys_ck>;
244		};
245
246		mspro_fck: clock-mspro-fck@23 {
247			reg = <23>;
248			#clock-cells = <0>;
249			compatible = "ti,wait-gate-clock";
250			clock-output-names = "mspro_fck";
251			clocks = <&core_96m_fck>;
252		};
253	};
254
255	/* CM_ICLKEN3_CORE */
256	clock@a18 {
257		compatible = "ti,clksel";
258		reg = <0xa18>;
259		#clock-cells = <2>;
260		#address-cells = <1>;
261		#ssize-cells = <0>;
262
263		mad2d_ick: clock-mad2d-ick@3 {
264			reg = <3>;
265			#clock-cells = <0>;
266			compatible = "ti,omap3-interface-clock";
267			clock-output-names = "mad2d_ick";
268			clocks = <&l3_ick>;
269		};
270	};
271
272};
273
274&cm_clockdomains {
275	cam_clkdm: cam_clkdm {
276		compatible = "ti,clockdomain";
277		clocks = <&cam_ick>, <&csi2_96m_fck>;
278	};
279
280	iva2_clkdm: iva2_clkdm {
281		compatible = "ti,clockdomain";
282		clocks = <&iva2_ck>;
283	};
284
285	dpll2_clkdm: dpll2_clkdm {
286		compatible = "ti,clockdomain";
287		clocks = <&dpll2_ck>;
288	};
289
290	wkup_clkdm: wkup_clkdm {
291		compatible = "ti,clockdomain";
292		clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
293			 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
294			 <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
295	};
296
297	d2d_clkdm: d2d_clkdm {
298		compatible = "ti,clockdomain";
299		clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
300	};
301
302	core_l4_clkdm: core_l4_clkdm {
303		compatible = "ti,clockdomain";
304		clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
305			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
306			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
307			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
308			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
309			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
310			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
311			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
312			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
313			 <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
314			 <&rng_ick>, <&mspro_fck>;
315	};
316};
317