1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 * 5 * Code used in the main and auxiliary Qualcomm PMIC voltage ADCs 6 * of type ADC5 Gen3. 7 */ 8 9 #ifndef QCOM_ADC5_GEN3_COMMON_H 10 #define QCOM_ADC5_GEN3_COMMON_H 11 12 #include <linux/auxiliary_bus.h> 13 #include <linux/bitfield.h> 14 #include <linux/bits.h> 15 #include <linux/device.h> 16 #include <linux/iio/adc/qcom-vadc-common.h> 17 #include <linux/regmap.h> 18 #include <linux/types.h> 19 20 #define ADC5_GEN3_HS 0x45 21 #define ADC5_GEN3_HS_BUSY BIT(7) 22 #define ADC5_GEN3_HS_READY BIT(0) 23 24 #define ADC5_GEN3_STATUS1 0x46 25 #define ADC5_GEN3_STATUS1_CONV_FAULT BIT(7) 26 #define ADC5_GEN3_STATUS1_THR_CROSS BIT(6) 27 #define ADC5_GEN3_STATUS1_EOC BIT(0) 28 29 #define ADC5_GEN3_TM_EN_STS 0x47 30 #define ADC5_GEN3_TM_HIGH_STS 0x48 31 #define ADC5_GEN3_TM_LOW_STS 0x49 32 33 #define ADC5_GEN3_EOC_STS 0x4a 34 #define ADC5_GEN3_EOC_CHAN_0 BIT(0) 35 36 #define ADC5_GEN3_EOC_CLR 0x4b 37 #define ADC5_GEN3_TM_HIGH_STS_CLR 0x4c 38 #define ADC5_GEN3_TM_LOW_STS_CLR 0x4d 39 #define ADC5_GEN3_CONV_ERR_CLR 0x4e 40 #define ADC5_GEN3_CONV_ERR_CLR_REQ BIT(0) 41 42 #define ADC5_GEN3_SID 0x4f 43 #define ADC5_GEN3_SID_MASK GENMASK(3, 0) 44 45 #define ADC5_GEN3_PERPH_CH 0x50 46 #define ADC5_GEN3_CHAN_CONV_REQ BIT(7) 47 48 #define ADC5_GEN3_TIMER_SEL 0x51 49 #define ADC5_GEN3_TIME_IMMEDIATE 0x1 50 51 #define ADC5_GEN3_DIG_PARAM 0x52 52 #define ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK GENMASK(5, 4) 53 #define ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK GENMASK(3, 2) 54 55 #define ADC5_GEN3_FAST_AVG 0x53 56 #define ADC5_GEN3_FAST_AVG_CTL_EN BIT(7) 57 #define ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK GENMASK(2, 0) 58 59 #define ADC5_GEN3_ADC_CH_SEL_CTL 0x54 60 #define ADC5_GEN3_DELAY_CTL 0x55 61 #define ADC5_GEN3_HW_SETTLE_DELAY_MASK GENMASK(3, 0) 62 63 #define ADC5_GEN3_CH_EN 0x56 64 #define ADC5_GEN3_HIGH_THR_INT_EN BIT(1) 65 #define ADC5_GEN3_LOW_THR_INT_EN BIT(0) 66 67 #define ADC5_GEN3_LOW_THR0 0x57 68 #define ADC5_GEN3_LOW_THR1 0x58 69 #define ADC5_GEN3_HIGH_THR0 0x59 70 #define ADC5_GEN3_HIGH_THR1 0x5a 71 72 #define ADC5_GEN3_CH_DATA0(channel) (0x5c + (channel) * 2) 73 #define ADC5_GEN3_CH_DATA1(channel) (0x5d + (channel) * 2) 74 75 #define ADC5_GEN3_CONV_REQ 0xe5 76 #define ADC5_GEN3_CONV_REQ_REQ BIT(0) 77 78 #define ADC5_GEN3_VIRTUAL_SID_MASK GENMASK(15, 8) 79 #define ADC5_GEN3_CHANNEL_MASK GENMASK(7, 0) 80 #define ADC5_GEN3_V_CHAN(x) \ 81 (FIELD_PREP(ADC5_GEN3_VIRTUAL_SID_MASK, (x).sid) | (x).channel) 82 83 /* ADC channels for PMIC5 Gen3 */ 84 #define ADC5_GEN3_REF_GND 0x00 85 #define ADC5_GEN3_1P25VREF 0x01 86 #define ADC5_GEN3_DIE_TEMP 0x03 87 #define ADC5_GEN3_USB_SNS_V_16 0x11 88 #define ADC5_GEN3_VIN_DIV16_MUX 0x12 89 #define ADC5_GEN3_VPH_PWR 0x8e 90 #define ADC5_GEN3_VBAT_SNS_QBG 0x8f 91 /* 100k pull-up channels */ 92 #define ADC5_GEN3_AMUX1_THM_100K_PU 0x44 93 #define ADC5_GEN3_AMUX2_THM_100K_PU 0x45 94 #define ADC5_GEN3_AMUX3_THM_100K_PU 0x46 95 #define ADC5_GEN3_AMUX4_THM_100K_PU 0x47 96 #define ADC5_GEN3_AMUX5_THM_100K_PU 0x48 97 #define ADC5_GEN3_AMUX6_THM_100K_PU 0x49 98 #define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a 99 #define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b 100 #define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c 101 #define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d 102 103 #define ADC5_MAX_CHANNEL 0xc0 104 105 enum adc5_cal_method { 106 ADC5_NO_CAL = 0, 107 ADC5_RATIOMETRIC_CAL, 108 ADC5_ABSOLUTE_CAL, 109 }; 110 111 enum adc5_time_select { 112 MEAS_INT_DISABLE = 0, 113 MEAS_INT_IMMEDIATE, 114 MEAS_INT_50MS, 115 MEAS_INT_100MS, 116 MEAS_INT_1S, 117 MEAS_INT_NONE, 118 }; 119 120 /** 121 * struct adc5_sdam_data - data per SDAM allocated for adc usage 122 * @base_addr: base address for the ADC SDAM peripheral. 123 * @irq_name: ADC IRQ name. 124 * @irq: ADC IRQ number. 125 */ 126 struct adc5_sdam_data { 127 u16 base_addr; 128 const char *irq_name; 129 int irq; 130 }; 131 132 /** 133 * struct adc5_device_data - Top-level ADC device data 134 * @regmap: ADC peripheral register map field. 135 * @base: array of SDAM data. 136 * @num_sdams: number of ADC SDAM peripherals. 137 */ 138 struct adc5_device_data { 139 struct regmap *regmap; 140 struct adc5_sdam_data *base; 141 int num_sdams; 142 }; 143 144 /** 145 * struct adc5_channel_common_prop - ADC channel properties (common to ADC and TM). 146 * @channel: channel number, refer to the channel list. 147 * @cal_method: calibration method. 148 * @decimation: sampling rate supported for the channel. 149 * @sid: ID of PMIC owning the channel. 150 * @label: Channel name used in device tree. 151 * @prescale: channel scaling performed on the input signal. 152 * @hw_settle_time_us: the time between AMUX being configured and the 153 * start of conversion in uS. 154 * @avg_samples: ability to provide single result from the ADC 155 * that is an average of multiple measurements. 156 * @scale_fn_type: Represents the scaling function to convert voltage 157 * physical units desired by the client for the channel. 158 */ 159 struct adc5_channel_common_prop { 160 unsigned int channel; 161 enum adc5_cal_method cal_method; 162 unsigned int decimation; 163 unsigned int sid; 164 const char *label; 165 unsigned int prescale; 166 unsigned int hw_settle_time_us; 167 unsigned int avg_samples; 168 enum vadc_scale_fn_type scale_fn_type; 169 }; 170 171 /** 172 * struct tm5_aux_dev_wrapper - wrapper structure around TM auxiliary device 173 * @aux_dev: TM auxiliary device structure. 174 * @dev_data: Top-level ADC device data. 175 * @tm_props: Array of common ADC channel properties for TM channels. 176 * @n_tm_channels: number of TM channels. 177 */ 178 struct tm5_aux_dev_wrapper { 179 struct auxiliary_device aux_dev; 180 struct adc5_device_data *dev_data; 181 struct adc5_channel_common_prop *tm_props; 182 unsigned int n_tm_channels; 183 }; 184 185 int adc5_gen3_read(struct adc5_device_data *adc, unsigned int sdam_index, 186 u16 offset, u8 *data, int len); 187 188 int adc5_gen3_write(struct adc5_device_data *adc, unsigned int sdam_index, 189 u16 offset, u8 *data, int len); 190 191 int adc5_gen3_poll_wait_hs(struct adc5_device_data *adc, 192 unsigned int sdam_index); 193 194 void adc5_gen3_update_dig_param(struct adc5_channel_common_prop *prop, 195 u8 *data); 196 197 int adc5_gen3_status_clear(struct adc5_device_data *adc, 198 int sdam_index, u16 offset, u8 *val, int len); 199 200 void adc5_gen3_mutex_lock(struct device *dev); 201 void adc5_gen3_mutex_unlock(struct device *dev); 202 int adc5_gen3_get_scaled_reading(struct device *dev, 203 struct adc5_channel_common_prop *common_props, 204 int *val); 205 int adc5_gen3_therm_code_to_temp(struct device *dev, 206 struct adc5_channel_common_prop *common_props, 207 u16 code, int *val); 208 void adc5_gen3_register_tm_event_notifier(struct device *dev, 209 void (*handler)(struct auxiliary_device *)); 210 211 #endif /* QCOM_ADC5_GEN3_COMMON_H */ 212