1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Common definitions for Cirrus Logic CS35L56 smart amp 4 * 5 * Copyright (C) 2023 Cirrus Logic, Inc. and 6 * Cirrus Logic International Semiconductor Ltd. 7 */ 8 9 #ifndef __CS35L56_H 10 #define __CS35L56_H 11 12 #include <linux/firmware/cirrus/cs_dsp.h> 13 #include <linux/regulator/consumer.h> 14 #include <linux/regmap.h> 15 #include <linux/spi/spi.h> 16 #include <sound/cs-amp-lib.h> 17 18 #define CS35L56_DEVID 0x0000000 19 #define CS35L56_REVID 0x0000004 20 #define CS35L56_RELID 0x000000C 21 #define CS35L56_OTPID 0x0000010 22 #define CS35L56_SFT_RESET 0x0000020 23 #define CS35L56_GLOBAL_ENABLES 0x0002014 24 #define CS35L56_BLOCK_ENABLES 0x0002018 25 #define CS35L56_BLOCK_ENABLES2 0x000201C 26 #define CS35L56_REFCLK_INPUT 0x0002C04 27 #define CS35L56_GLOBAL_SAMPLE_RATE 0x0002C0C 28 #define CS35L56_OTP_MEM_53 0x00300D4 29 #define CS35L56_OTP_MEM_54 0x00300D8 30 #define CS35L56_OTP_MEM_55 0x00300DC 31 #define CS35L56_ASP1_ENABLES1 0x0004800 32 #define CS35L56_ASP1_CONTROL1 0x0004804 33 #define CS35L56_ASP1_CONTROL2 0x0004808 34 #define CS35L56_ASP1_CONTROL3 0x000480C 35 #define CS35L56_ASP1_FRAME_CONTROL1 0x0004810 36 #define CS35L56_ASP1_FRAME_CONTROL5 0x0004820 37 #define CS35L56_ASP1_DATA_CONTROL1 0x0004830 38 #define CS35L56_ASP1_DATA_CONTROL5 0x0004840 39 #define CS35L56_DACPCM1_INPUT 0x0004C00 40 #define CS35L56_DACPCM2_INPUT 0x0004C08 41 #define CS35L56_ASP1TX1_INPUT 0x0004C20 42 #define CS35L56_ASP1TX2_INPUT 0x0004C24 43 #define CS35L56_ASP1TX3_INPUT 0x0004C28 44 #define CS35L56_ASP1TX4_INPUT 0x0004C2C 45 #define CS35L56_DSP1RX1_INPUT 0x0004C40 46 #define CS35L56_DSP1RX2_INPUT 0x0004C44 47 #define CS35L56_SWIRE_DP3_CH1_INPUT 0x0004C70 48 #define CS35L56_SWIRE_DP3_CH2_INPUT 0x0004C74 49 #define CS35L56_SWIRE_DP3_CH3_INPUT 0x0004C78 50 #define CS35L56_SWIRE_DP3_CH4_INPUT 0x0004C7C 51 #define CS35L56_IRQ1_CFG 0x000E000 52 #define CS35L56_IRQ1_STATUS 0x000E004 53 #define CS35L56_IRQ1_EINT_1 0x000E010 54 #define CS35L56_IRQ1_EINT_2 0x000E014 55 #define CS35L56_IRQ1_EINT_4 0x000E01C 56 #define CS35L56_IRQ1_EINT_8 0x000E02C 57 #define CS35L56_IRQ1_EINT_18 0x000E054 58 #define CS35L56_IRQ1_EINT_20 0x000E05C 59 #define CS35L56_IRQ1_MASK_1 0x000E090 60 #define CS35L56_IRQ1_MASK_2 0x000E094 61 #define CS35L56_IRQ1_MASK_4 0x000E09C 62 #define CS35L56_IRQ1_MASK_8 0x000E0AC 63 #define CS35L56_IRQ1_MASK_18 0x000E0D4 64 #define CS35L56_IRQ1_MASK_20 0x000E0DC 65 #define CS35L56_DSP_MBOX_1_RAW 0x0011000 66 #define CS35L56_DSP_VIRTUAL1_MBOX_1 0x0011020 67 #define CS35L56_DSP_VIRTUAL1_MBOX_2 0x0011024 68 #define CS35L56_DSP_VIRTUAL1_MBOX_3 0x0011028 69 #define CS35L56_DSP_VIRTUAL1_MBOX_4 0x001102C 70 #define CS35L56_DSP_VIRTUAL1_MBOX_5 0x0011030 71 #define CS35L56_DSP_VIRTUAL1_MBOX_6 0x0011034 72 #define CS35L56_DSP_VIRTUAL1_MBOX_7 0x0011038 73 #define CS35L56_DSP_VIRTUAL1_MBOX_8 0x001103C 74 #define CS35L56_DIE_STS1 0x0017040 75 #define CS35L56_DIE_STS2 0x0017044 76 #define CS35L56_DSP_RESTRICT_STS1 0x00190F0 77 #define CS35L56_DSP1_XMEM_PACKED_0 0x2000000 78 #define CS35L56_DSP1_XMEM_PACKED_6143 0x2005FFC 79 #define CS35L56_DSP1_XMEM_UNPACKED32_0 0x2400000 80 #define CS35L56_DSP1_XMEM_UNPACKED32_4095 0x2403FFC 81 #define CS35L56_DSP1_SYS_INFO_ID 0x25E0000 82 #define CS35L56_DSP1_SYS_INFO_END 0x25E004C 83 #define CS35L56_DSP1_AHBM_WINDOW_DEBUG_0 0x25E2040 84 #define CS35L56_DSP1_AHBM_WINDOW_DEBUG_1 0x25E2044 85 #define CS35L56_DSP1_XMEM_UNPACKED24_0 0x2800000 86 #define CS35L56_DSP1_FW_VER 0x2800010 87 #define CS35L56_DSP1_HALO_STATE 0x28021E0 88 #define CS35L56_B2_DSP1_HALO_STATE 0x2803D20 89 #define CS35L56_DSP1_PM_CUR_STATE 0x2804308 90 #define CS35L56_B2_DSP1_PM_CUR_STATE 0x2804678 91 #define CS35L56_DSP1_XMEM_UNPACKED24_8191 0x2807FFC 92 #define CS35L56_DSP1_CORE_BASE 0x2B80000 93 #define CS35L56_DSP1_SCRATCH1 0x2B805C0 94 #define CS35L56_DSP1_SCRATCH2 0x2B805C8 95 #define CS35L56_DSP1_SCRATCH3 0x2B805D0 96 #define CS35L56_DSP1_SCRATCH4 0x2B805D8 97 #define CS35L56_DSP1_YMEM_PACKED_0 0x2C00000 98 #define CS35L56_DSP1_YMEM_PACKED_4604 0x2C047F0 99 #define CS35L56_DSP1_YMEM_UNPACKED32_0 0x3000000 100 #define CS35L56_DSP1_YMEM_UNPACKED32_3070 0x3002FF8 101 #define CS35L56_DSP1_YMEM_UNPACKED24_0 0x3400000 102 #define CS35L56_MAIN_RENDER_USER_MUTE 0x3400024 103 #define CS35L56_MAIN_RENDER_USER_VOLUME 0x340002C 104 #define CS35L56_MAIN_POSTURE_NUMBER 0x3400094 105 #define CS35L56_PROTECTION_STATUS 0x34000D8 106 #define CS35L56_TRANSDUCER_ACTUAL_PS 0x3400150 107 #define CS35L56_DSP1_YMEM_UNPACKED24_6141 0x3405FF4 108 #define CS35L56_DSP1_PMEM_0 0x3800000 109 #define CS35L56_DSP1_PMEM_5114 0x3804FE8 110 111 #define CS35L63_DSP1_FW_VER CS35L56_DSP1_FW_VER 112 #define CS35L63_DSP1_HALO_STATE 0x2803C04 113 #define CS35L63_DSP1_PM_CUR_STATE 0x2804518 114 #define CS35L63_PROTECTION_STATUS 0x340009C 115 #define CS35L63_TRANSDUCER_ACTUAL_PS 0x34000F4 116 #define CS35L63_MAIN_RENDER_USER_MUTE 0x3400020 117 #define CS35L63_MAIN_RENDER_USER_VOLUME 0x3400028 118 #define CS35L63_MAIN_POSTURE_NUMBER 0x3400068 119 120 /* DEVID */ 121 #define CS35L56_DEVID_MASK 0x00FFFFFF 122 123 /* REVID */ 124 #define CS35L56_AREVID_MASK 0x000000F0 125 #define CS35L56_MTLREVID_MASK 0x0000000F 126 #define CS35L56_REVID_B0 0x000000B0 127 128 /* ASP_ENABLES1 */ 129 #define CS35L56_ASP_RX2_EN_SHIFT 17 130 #define CS35L56_ASP_RX1_EN_SHIFT 16 131 #define CS35L56_ASP_TX4_EN_SHIFT 3 132 #define CS35L56_ASP_TX3_EN_SHIFT 2 133 #define CS35L56_ASP_TX2_EN_SHIFT 1 134 #define CS35L56_ASP_TX1_EN_SHIFT 0 135 136 /* ASP_CONTROL1 */ 137 #define CS35L56_ASP_BCLK_FREQ_MASK 0x0000003F 138 #define CS35L56_ASP_BCLK_FREQ_SHIFT 0 139 140 /* ASP_CONTROL2 */ 141 #define CS35L56_ASP_RX_WIDTH_MASK 0xFF000000 142 #define CS35L56_ASP_RX_WIDTH_SHIFT 24 143 #define CS35L56_ASP_TX_WIDTH_MASK 0x00FF0000 144 #define CS35L56_ASP_TX_WIDTH_SHIFT 16 145 #define CS35L56_ASP_FMT_MASK 0x00000700 146 #define CS35L56_ASP_FMT_SHIFT 8 147 #define CS35L56_ASP_BCLK_INV_MASK 0x00000040 148 #define CS35L56_ASP_FSYNC_INV_MASK 0x00000004 149 150 /* ASP_CONTROL3 */ 151 #define CS35L56_ASP1_DOUT_HIZ_CTRL_MASK 0x00000003 152 153 /* ASP_DATA_CONTROL1 */ 154 #define CS35L56_ASP_TX_WL_MASK 0x0000003F 155 156 /* ASP_DATA_CONTROL5 */ 157 #define CS35L56_ASP_RX_WL_MASK 0x0000003F 158 159 /* ASPTXn_INPUT */ 160 #define CS35L56_ASP_TXn_SRC_MASK 0x0000007F 161 162 /* SWIRETX[1..7]_SRC SDWTXn INPUT */ 163 #define CS35L56_SWIRETXn_SRC_MASK 0x0000007F 164 165 /* IRQ1_STATUS */ 166 #define CS35L56_IRQ1_STS_MASK 0x00000001 167 168 /* IRQ1_EINT_1 */ 169 #define CS35L56_AMP_SHORT_ERR_EINT1_MASK 0x80000000 170 171 /* IRQ1_EINT_2 */ 172 #define CS35L56_DSP_VIRTUAL2_MBOX_WR_EINT1_MASK 0x00200000 173 174 /* IRQ1_EINT_4 */ 175 #define CS35L56_OTP_BOOT_DONE_MASK 0x00000002 176 177 /* IRQ1_EINT_8 */ 178 #define CS35L56_TEMP_ERR_EINT1_MASK 0x80000000 179 180 /* Mixer input sources */ 181 #define CS35L56_INPUT_SRC_NONE 0x00 182 #define CS35L56_INPUT_SRC_ASP1RX1 0x08 183 #define CS35L56_INPUT_SRC_ASP1RX2 0x09 184 #define CS35L56_INPUT_SRC_VMON 0x18 185 #define CS35L56_INPUT_SRC_IMON 0x19 186 #define CS35L56_INPUT_SRC_ERR_VOL 0x20 187 #define CS35L56_INPUT_SRC_CLASSH 0x21 188 #define CS35L56_INPUT_SRC_VDDBMON 0x28 189 #define CS35L56_INPUT_SRC_VBSTMON 0x29 190 #define CS35L56_INPUT_SRC_DSP1TX1 0x32 191 #define CS35L56_INPUT_SRC_DSP1TX2 0x33 192 #define CS35L56_INPUT_SRC_DSP1TX3 0x34 193 #define CS35L56_INPUT_SRC_DSP1TX4 0x35 194 #define CS35L56_INPUT_SRC_DSP1TX5 0x36 195 #define CS35L56_INPUT_SRC_DSP1TX6 0x37 196 #define CS35L56_INPUT_SRC_DSP1TX7 0x38 197 #define CS35L56_INPUT_SRC_DSP1TX8 0x39 198 #define CS35L56_INPUT_SRC_TEMPMON 0x3A 199 #define CS35L56_INPUT_SRC_INTERPOLATOR 0x40 200 #define CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1 0x44 201 #define CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2 0x45 202 #define CS35L56_INPUT_MASK 0x7F 203 204 #define CS35L56_NUM_INPUT_SRC 21 205 206 /* ASP formats */ 207 #define CS35L56_ASP_FMT_DSP_A 0 208 #define CS35L56_ASP_FMT_I2S 2 209 210 /* ASP HiZ modes */ 211 #define CS35L56_ASP_UNUSED_HIZ_OFF_HIZ 3 212 213 /* MAIN_RENDER_ACTUAL_PS */ 214 #define CS35L56_PS0 0 215 #define CS35L56_PS3 3 216 217 /* CS35L56_DSP_RESTRICT_STS1 */ 218 #define CS35L56_RESTRICTED_MASK 0x7 219 220 /* CS35L56_MAIN_RENDER_USER_MUTE */ 221 #define CS35L56_MAIN_RENDER_USER_MUTE_MASK 1 222 223 /* CS35L56_MAIN_RENDER_USER_VOLUME */ 224 #define CS35L56_MAIN_RENDER_USER_VOLUME_MIN -400 225 #define CS35L56_MAIN_RENDER_USER_VOLUME_MAX 48 226 #define CS35L56_MAIN_RENDER_USER_VOLUME_MASK 0x0000FFC0 227 #define CS35L56_MAIN_RENDER_USER_VOLUME_SHIFT 6 228 #define CS35L56_MAIN_RENDER_USER_VOLUME_SIGNBIT 9 229 230 /* CS35L56_MAIN_POSTURE_NUMBER */ 231 #define CS35L56_MAIN_POSTURE_MIN 0 232 #define CS35L56_MAIN_POSTURE_MAX 255 233 #define CS35L56_MAIN_POSTURE_MASK CS35L56_MAIN_POSTURE_MAX 234 235 /* CS35L56_PROTECTION_STATUS */ 236 #define CS35L56_FIRMWARE_MISSING BIT(0) 237 238 /* Software Values */ 239 #define CS35L56_HALO_STATE_SHUTDOWN 1 240 #define CS35L56_HALO_STATE_BOOT_DONE 2 241 242 #define CS35L56_MBOX_CMD_PING 0x0A000000 243 #define CS35L56_MBOX_CMD_AUDIO_PLAY 0x0B000001 244 #define CS35L56_MBOX_CMD_AUDIO_PAUSE 0x0B000002 245 #define CS35L56_MBOX_CMD_AUDIO_REINIT 0x0B000003 246 #define CS35L56_MBOX_CMD_HIBERNATE_NOW 0x02000001 247 #define CS35L56_MBOX_CMD_WAKEUP 0x02000002 248 #define CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE 0x02000003 249 #define CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE 0x02000004 250 #define CS35L56_MBOX_CMD_SHUTDOWN 0x02000005 251 #define CS35L56_MBOX_CMD_SYSTEM_RESET 0x02000007 252 253 #define CS35L56_MBOX_TIMEOUT_US 5000 254 #define CS35L56_MBOX_POLL_US 250 255 256 #define CS35L56_PS0_POLL_US 500 257 #define CS35L56_PS0_TIMEOUT_US 50000 258 #define CS35L56_PS3_POLL_US 500 259 #define CS35L56_PS3_TIMEOUT_US 300000 260 261 #define CS35L56_CONTROL_PORT_READY_US 2200 262 #define CS35L56_HALO_STATE_POLL_US 1000 263 #define CS35L56_HALO_STATE_TIMEOUT_US 250000 264 #define CS35L56_RESET_PULSE_MIN_US 1100 265 #define CS35L56_WAKE_HOLD_TIME_US 1000 266 267 #define CS35L56_SDW1_PLAYBACK_PORT 1 268 #define CS35L56_SDW1_CAPTURE_PORT 3 269 270 #define CS35L56_NUM_BULK_SUPPLIES 3 271 #define CS35L56_NUM_DSP_REGIONS 5 272 273 /* Additional margin for SYSTEM_RESET to control port ready on SPI */ 274 #define CS35L56_SPI_RESET_TO_PORT_READY_US (CS35L56_CONTROL_PORT_READY_US + 2500) 275 276 struct cs35l56_spi_payload { 277 __be32 addr; 278 __be16 pad; 279 __be32 value; 280 } __packed; 281 static_assert(sizeof(struct cs35l56_spi_payload) == 10); 282 283 struct cs35l56_fw_reg { 284 unsigned int fw_ver; 285 unsigned int halo_state; 286 unsigned int pm_cur_stat; 287 unsigned int prot_sts; 288 unsigned int transducer_actual_ps; 289 unsigned int user_mute; 290 unsigned int user_volume; 291 unsigned int posture_number; 292 }; 293 294 struct cs35l56_base { 295 struct device *dev; 296 struct regmap *regmap; 297 int irq; 298 struct mutex irq_lock; 299 u8 type; 300 u8 rev; 301 bool init_done; 302 bool fw_patched; 303 bool secured; 304 bool can_hibernate; 305 bool cal_data_valid; 306 s8 cal_index; 307 struct cirrus_amp_cal_data cal_data; 308 struct gpio_desc *reset_gpio; 309 struct cs35l56_spi_payload *spi_payload_buf; 310 const struct cs35l56_fw_reg *fw_reg; 311 const struct cirrus_amp_cal_controls *calibration_controls; 312 }; 313 314 static inline bool cs35l56_is_otp_register(unsigned int reg) 315 { 316 return (reg >> 16) == 3; 317 } 318 319 static inline int cs35l56_init_config_for_spi(struct cs35l56_base *cs35l56, 320 struct spi_device *spi) 321 { 322 cs35l56->spi_payload_buf = devm_kzalloc(&spi->dev, 323 sizeof(*cs35l56->spi_payload_buf), 324 GFP_KERNEL | GFP_DMA); 325 if (!cs35l56->spi_payload_buf) 326 return -ENOMEM; 327 328 return 0; 329 } 330 331 static inline bool cs35l56_is_spi(struct cs35l56_base *cs35l56) 332 { 333 return IS_ENABLED(CONFIG_SPI_MASTER) && !!cs35l56->spi_payload_buf; 334 } 335 336 extern const struct regmap_config cs35l56_regmap_i2c; 337 extern const struct regmap_config cs35l56_regmap_spi; 338 extern const struct regmap_config cs35l56_regmap_sdw; 339 extern const struct regmap_config cs35l63_regmap_i2c; 340 extern const struct regmap_config cs35l63_regmap_sdw; 341 342 extern const struct cirrus_amp_cal_controls cs35l56_calibration_controls; 343 344 extern const char * const cs35l56_tx_input_texts[CS35L56_NUM_INPUT_SRC]; 345 extern const unsigned int cs35l56_tx_input_values[CS35L56_NUM_INPUT_SRC]; 346 347 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base); 348 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command); 349 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base); 350 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base); 351 void cs35l56_wait_control_port_ready(void); 352 void cs35l56_wait_min_reset_pulse(void); 353 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire); 354 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq); 355 irqreturn_t cs35l56_irq(int irq, void *data); 356 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base); 357 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base); 358 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire); 359 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp); 360 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base); 361 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base, 362 bool *fw_missing, unsigned int *fw_version); 363 void cs35l56_log_tuning(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp); 364 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base); 365 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base); 366 int cs35l56_get_bclk_freq_id(unsigned int freq); 367 void cs35l56_fill_supply_names(struct regulator_bulk_data *data); 368 369 #endif /* ifndef __CS35L56_H */ 370