xref: /linux/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2021-2022 Intel Corporation
4  */
5 
6 #ifndef _INTEL_GUC_CAPTURE_FWIF_H
7 #define _INTEL_GUC_CAPTURE_FWIF_H
8 
9 #include <linux/types.h>
10 #include "intel_guc_fwif.h"
11 
12 struct intel_guc;
13 struct file;
14 
15 /*
16  * struct __guc_capture_bufstate
17  *
18  * Book-keeping structure used to track read and write pointers
19  * as we extract error capture data from the GuC-log-buffer's
20  * error-capture region as a stream of dwords.
21  */
22 struct __guc_capture_bufstate {
23 	u32 size;
24 	void *data;
25 	u32 rd;
26 	u32 wr;
27 };
28 
29 /*
30  * struct __guc_capture_parsed_output - extracted error capture node
31  *
32  * A single unit of extracted error-capture output data grouped together
33  * at an engine-instance level. We keep these nodes in a linked list.
34  * See cachelist and outlist below.
35  */
36 struct __guc_capture_parsed_output {
37 	/*
38 	 * A single set of 3 capture lists: a global-list
39 	 * an engine-class-list and an engine-instance list.
40 	 * outlist in __guc_capture_parsed_output will keep
41 	 * a linked list of these nodes that will eventually
42 	 * be detached from outlist and attached into to
43 	 * i915_gpu_codedump in response to a context reset
44 	 */
45 	struct list_head link;
46 	bool is_partial;
47 	u32 eng_class;
48 	u32 eng_inst;
49 	u32 guc_id;
50 	u32 lrca;
51 	struct gcap_reg_list_info {
52 		u32 vfid;
53 		u32 num_regs;
54 		struct guc_mmio_reg *regs;
55 	} reginfo[GUC_CAPTURE_LIST_TYPE_MAX];
56 #define GCAP_PARSED_REGLIST_INDEX_GLOBAL   BIT(GUC_CAPTURE_LIST_TYPE_GLOBAL)
57 #define GCAP_PARSED_REGLIST_INDEX_ENGCLASS BIT(GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS)
58 #define GCAP_PARSED_REGLIST_INDEX_ENGINST  BIT(GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE)
59 };
60 
61 /*
62  * struct guc_debug_capture_list_header / struct guc_debug_capture_list
63  *
64  * As part of ADS registration, these header structures (followed by
65  * an array of 'struct guc_mmio_reg' entries) are used to register with
66  * GuC microkernel the list of registers we want it to dump out prior
67  * to a engine reset.
68  */
69 struct guc_debug_capture_list_header {
70 	u32 info;
71 #define GUC_CAPTURELISTHDR_NUMDESCR GENMASK(15, 0)
72 } __packed;
73 
74 struct guc_debug_capture_list {
75 	struct guc_debug_capture_list_header header;
76 	struct guc_mmio_reg regs[];
77 } __packed;
78 
79 /*
80  * struct __guc_mmio_reg_descr / struct __guc_mmio_reg_descr_group
81  *
82  * intel_guc_capture module uses these structures to maintain static
83  * tables (per unique platform) that consists of lists of registers
84  * (offsets, names, flags,...) that are used at the ADS regisration
85  * time as well as during runtime processing and reporting of error-
86  * capture states generated by GuC just prior to engine reset events.
87  */
88 struct __guc_mmio_reg_descr {
89 	i915_reg_t reg;
90 	u32 flags;
91 	u32 mask;
92 	const char *regname;
93 };
94 
95 struct __guc_mmio_reg_descr_group {
96 	const struct __guc_mmio_reg_descr *list;
97 	u32 num_regs;
98 	u32 owner; /* see enum guc_capture_owner */
99 	u32 type; /* see enum guc_capture_type */
100 	u32 engine; /* as per MAX_ENGINE_CLASS */
101 	struct __guc_mmio_reg_descr *extlist; /* only used for steered registers */
102 };
103 
104 /*
105  * struct guc_state_capture_header_t / struct guc_state_capture_t /
106  * guc_state_capture_group_header_t / guc_state_capture_group_t
107  *
108  * Prior to resetting engines that have hung or faulted, GuC microkernel
109  * reports the engine error-state (register values that was read) by
110  * logging them into the shared GuC log buffer using these hierarchy
111  * of structures.
112  */
113 struct guc_state_capture_header_t {
114 	u32 owner;
115 #define CAP_HDR_CAPTURE_VFID GENMASK(7, 0)
116 	u32 info;
117 #define CAP_HDR_CAPTURE_TYPE GENMASK(3, 0) /* see enum guc_capture_type */
118 #define CAP_HDR_ENGINE_CLASS GENMASK(7, 4) /* see GUC_MAX_ENGINE_CLASSES */
119 #define CAP_HDR_ENGINE_INSTANCE GENMASK(11, 8)
120 	u32 lrca; /* if type-instance, LRCA (address) that hung, else set to ~0 */
121 	u32 guc_id; /* if type-instance, context index of hung context, else set to ~0 */
122 	u32 num_mmios;
123 #define CAP_HDR_NUM_MMIOS GENMASK(9, 0)
124 } __packed;
125 
126 struct guc_state_capture_t {
127 	struct guc_state_capture_header_t header;
128 	struct guc_mmio_reg mmio_entries[];
129 } __packed;
130 
131 enum guc_capture_group_types {
132 	GUC_STATE_CAPTURE_GROUP_TYPE_FULL,
133 	GUC_STATE_CAPTURE_GROUP_TYPE_PARTIAL,
134 	GUC_STATE_CAPTURE_GROUP_TYPE_MAX,
135 };
136 
137 struct guc_state_capture_group_header_t {
138 	u32 owner;
139 #define CAP_GRP_HDR_CAPTURE_VFID GENMASK(7, 0)
140 	u32 info;
141 #define CAP_GRP_HDR_NUM_CAPTURES GENMASK(7, 0)
142 #define CAP_GRP_HDR_CAPTURE_TYPE GENMASK(15, 8) /* guc_capture_group_types */
143 } __packed;
144 
145 /* this is the top level structure where an error-capture dump starts */
146 struct guc_state_capture_group_t {
147 	struct guc_state_capture_group_header_t grp_header;
148 	struct guc_state_capture_t capture_entries[];
149 } __packed;
150 
151 /*
152  * struct __guc_capture_ads_cache
153  *
154  * A structure to cache register lists that were populated and registered
155  * with GuC at startup during ADS registration. This allows much quicker
156  * GuC resets without re-parsing all the tables for the given gt.
157  */
158 struct __guc_capture_ads_cache {
159 	bool is_valid;
160 	void *ptr;
161 	size_t size;
162 	int status;
163 };
164 
165 /**
166  * struct intel_guc_state_capture
167  *
168  * Internal context of the intel_guc_capture module.
169  */
170 struct intel_guc_state_capture {
171 	/**
172 	 * @reglists: static table of register lists used for error-capture state.
173 	 */
174 	const struct __guc_mmio_reg_descr_group *reglists;
175 
176 	/**
177 	 * @extlists: allocated table of steered register lists used for error-capture state.
178 	 *
179 	 * NOTE: steered registers have multiple instances depending on the HW configuration
180 	 * (slices or dual-sub-slices) and thus depends on HW fuses discovered at startup
181 	 */
182 	struct __guc_mmio_reg_descr_group *extlists;
183 
184 	/**
185 	 * @ads_cache: cached register lists that is ADS format ready
186 	 */
187 	struct __guc_capture_ads_cache ads_cache[GUC_CAPTURE_LIST_INDEX_MAX]
188 						[GUC_CAPTURE_LIST_TYPE_MAX]
189 						[GUC_MAX_ENGINE_CLASSES];
190 
191 	/**
192 	 * @ads_null_cache: ADS null cache.
193 	 */
194 	void *ads_null_cache;
195 
196 	/**
197 	 * @cachelist: Pool of pre-allocated nodes for error capture output
198 	 *
199 	 * We need this pool of pre-allocated nodes because we cannot
200 	 * dynamically allocate new nodes when receiving the G2H notification
201 	 * because the event handlers for all G2H event-processing is called
202 	 * by the ct processing worker queue and when that queue is being
203 	 * processed, there is no absoluate guarantee that we are not in the
204 	 * midst of a GT reset operation (which doesn't allow allocations).
205 	 */
206 	struct list_head cachelist;
207 #define PREALLOC_NODES_MAX_COUNT (3 * GUC_MAX_ENGINE_CLASSES * GUC_MAX_INSTANCES_PER_CLASS)
208 #define PREALLOC_NODES_DEFAULT_NUMREGS 64
209 
210 	/**
211 	 * @max_mmio_per_node: Max MMIO per node.
212 	 */
213 	int max_mmio_per_node;
214 
215 	/**
216 	 * @outlist: Pool of pre-allocated nodes for error capture output
217 	 *
218 	 * A linked list of parsed GuC error-capture output data before
219 	 * reporting with formatting via i915_gpu_coredump. Each node in this linked list shall
220 	 * contain a single engine-capture including global, engine-class and
221 	 * engine-instance register dumps as per guc_capture_parsed_output_node
222 	 */
223 	struct list_head outlist;
224 };
225 
226 #endif /* _INTEL_GUC_CAPTURE_FWIF_H */
227