1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __AMDGPU_DM_H__ 28 #define __AMDGPU_DM_H__ 29 30 #include <drm/display/drm_dp_mst_helper.h> 31 #include <drm/drm_atomic.h> 32 #include <drm/drm_connector.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_plane.h> 35 #include "link_service_types.h" 36 #include <drm/drm_writeback.h> 37 38 /* 39 * This file contains the definition for amdgpu_display_manager 40 * and its API for amdgpu driver's use. 41 * This component provides all the display related functionality 42 * and this is the only component that calls DAL API. 43 * The API contained here intended for amdgpu driver use. 44 * The API that is called directly from KMS framework is located 45 * in amdgpu_dm_kms.h file 46 */ 47 48 #define AMDGPU_DM_MAX_CRTC 6 49 50 #define AMDGPU_DM_MAX_NUM_EDP 2 51 52 #define AMDGPU_DMUB_NOTIFICATION_MAX 8 53 54 enum amd_vsdb_panel_type { 55 AMD_VSDB_PANEL_TYPE_DEFAULT = 0, 56 AMD_VSDB_PANEL_TYPE_MINILED, 57 AMD_VSDB_PANEL_TYPE_OLED, 58 AMD_VSDB_PANEL_TYPE_RESERVED, 59 }; 60 61 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) 62 63 /* 64 * Maximum HDMI HPD debounce delay in milliseconds 65 */ 66 #define AMDGPU_DM_MAX_HDMI_HPD_DEBOUNCE_MS 5000 67 /* 68 #include "include/amdgpu_dal_power_if.h" 69 #include "amdgpu_dm_irq.h" 70 */ 71 72 #include "irq_types.h" 73 #include "signal_types.h" 74 #include "amdgpu_dm_crc.h" 75 #include "mod_info_packet.h" 76 struct aux_payload; 77 struct set_config_cmd_payload; 78 enum aux_return_code_type; 79 enum set_config_status; 80 81 /* Forward declarations */ 82 struct amdgpu_device; 83 struct amdgpu_crtc; 84 struct drm_device; 85 struct dc; 86 struct amdgpu_bo; 87 struct dmub_srv; 88 struct dc_plane_state; 89 struct dc_stream_state; 90 struct dc_stream_update; 91 struct dc_surface_update; 92 struct dmub_notification; 93 struct dmub_cmd_fused_request; 94 95 struct common_irq_params { 96 struct amdgpu_device *adev; 97 enum dc_irq_source irq_src; 98 atomic64_t previous_timestamp; 99 }; 100 101 /** 102 * struct dm_compressor_info - Buffer info used by frame buffer compression 103 * @cpu_addr: MMIO cpu addr 104 * @bo_ptr: Pointer to the buffer object 105 * @gpu_addr: MMIO gpu addr 106 */ 107 struct dm_compressor_info { 108 void *cpu_addr; 109 struct amdgpu_bo *bo_ptr; 110 uint64_t gpu_addr; 111 }; 112 113 /** 114 * struct dm_boot_time_crc_info - Buffer info used by boot time CRC 115 * @cpu_addr: MMIO cpu addr 116 * @bo_ptr: Pointer to the buffer object 117 * @gpu_addr: MMIO gpu addr 118 * @size: Size of the buffer 119 */ 120 struct dm_boot_time_crc_info { 121 void *cpu_addr; 122 struct amdgpu_bo *bo_ptr; 123 uint64_t gpu_addr; 124 uint32_t size; 125 }; 126 127 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); 128 129 /** 130 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ 131 * 132 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq 133 * @dmub_notify: notification for callback function 134 * @adev: amdgpu_device pointer 135 */ 136 struct dmub_hpd_work { 137 struct work_struct handle_hpd_work; 138 struct dmub_notification *dmub_notify; 139 struct amdgpu_device *adev; 140 }; 141 142 /** 143 * struct vblank_control_work - Work data for vblank control 144 * @work: Kernel work data for the work event 145 * @dm: amdgpu display manager device 146 * @acrtc: amdgpu CRTC instance for which the event has occurred 147 * @stream: DC stream for which the event has occurred 148 * @enable: true if enabling vblank 149 */ 150 struct vblank_control_work { 151 struct work_struct work; 152 struct amdgpu_display_manager *dm; 153 struct amdgpu_crtc *acrtc; 154 struct dc_stream_state *stream; 155 bool enable; 156 }; 157 158 /** 159 * struct idle_workqueue - Work data for periodic action in idle 160 * @work: Kernel work data for the work event 161 * @dm: amdgpu display manager device 162 * @enable: true if idle worker is enabled 163 * @running: true if idle worker is running 164 */ 165 struct idle_workqueue { 166 struct work_struct work; 167 struct amdgpu_display_manager *dm; 168 bool enable; 169 bool running; 170 }; 171 172 /** 173 * struct vupdate_offload_work - Work data for offloading task from vupdate handler 174 * @work: Kernel work data for the work event 175 * @adev: amdgpu_device back pointer 176 * @stream: DC stream associated with the crtc 177 * @adjust: DC CRTC timing adjust to be applied to the crtc 178 */ 179 struct vupdate_offload_work { 180 struct work_struct work; 181 struct amdgpu_device *adev; 182 struct dc_stream_state *stream; 183 struct dc_crtc_timing_adjust *adjust; 184 }; 185 186 #define MAX_LUMINANCE_DATA_POINTS 99 187 188 /** 189 * struct amdgpu_dm_luminance_data - Custom luminance data 190 * @luminance: Luminance in percent 191 * @input_signal: Input signal in range 0-255 192 */ 193 struct amdgpu_dm_luminance_data { 194 u8 luminance; 195 u8 input_signal; 196 } __packed; 197 198 /** 199 * struct amdgpu_dm_backlight_caps - Information about backlight 200 * 201 * Describe the backlight support for ACPI or eDP AUX. 202 */ 203 struct amdgpu_dm_backlight_caps { 204 /** 205 * @ext_caps: Keep the data struct with all the information about the 206 * display support for HDR. 207 */ 208 union dpcd_sink_ext_caps *ext_caps; 209 /** 210 * @aux_min_input_signal: Min brightness value supported by the display 211 */ 212 u32 aux_min_input_signal; 213 /** 214 * @aux_max_input_signal: Max brightness value supported by the display 215 * in nits. 216 */ 217 u32 aux_max_input_signal; 218 /** 219 * @min_input_signal: minimum possible input in range 0-255. 220 */ 221 int min_input_signal; 222 /** 223 * @max_input_signal: maximum possible input in range 0-255. 224 */ 225 int max_input_signal; 226 /** 227 * @caps_valid: true if these values are from the ACPI interface. 228 */ 229 bool caps_valid; 230 /** 231 * @aux_support: Describes if the display supports AUX backlight. 232 */ 233 bool aux_support; 234 /** 235 * @brightness_mask: After deriving brightness, OR it with this mask. 236 * Workaround for panels with issues with certain brightness values. 237 */ 238 u32 brightness_mask; 239 /** 240 * @ac_level: the default brightness if booted on AC 241 */ 242 u8 ac_level; 243 /** 244 * @dc_level: the default brightness if booted on DC 245 */ 246 u8 dc_level; 247 /** 248 * @data_points: the number of custom luminance data points 249 */ 250 u8 data_points; 251 /** 252 * @luminance_data: custom luminance data 253 */ 254 struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; 255 }; 256 257 /** 258 * struct dal_allocation - Tracks mapped FB memory for SMU communication 259 * @list: list of dal allocations 260 * @bo: GPU buffer object 261 * @cpu_ptr: CPU virtual address of the GPU buffer object 262 * @gpu_addr: GPU virtual address of the GPU buffer object 263 */ 264 struct dal_allocation { 265 struct list_head list; 266 struct amdgpu_bo *bo; 267 void *cpu_ptr; 268 u64 gpu_addr; 269 }; 270 271 /** 272 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq 273 * offload work 274 */ 275 struct hpd_rx_irq_offload_work_queue { 276 /** 277 * @wq: workqueue structure to queue offload work. 278 */ 279 struct workqueue_struct *wq; 280 /** 281 * @offload_lock: To protect fields of offload work queue. 282 */ 283 spinlock_t offload_lock; 284 /** 285 * @is_handling_link_loss: Used to prevent inserting link loss event when 286 * we're handling link loss 287 */ 288 bool is_handling_link_loss; 289 /** 290 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message 291 * ready event when we're already handling mst message ready event 292 */ 293 bool is_handling_mst_msg_rdy_event; 294 /** 295 * @aconnector: The aconnector that this work queue is attached to 296 */ 297 struct amdgpu_dm_connector *aconnector; 298 }; 299 300 /** 301 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure 302 */ 303 struct hpd_rx_irq_offload_work { 304 /** 305 * @work: offload work 306 */ 307 struct work_struct work; 308 /** 309 * @data: reference irq data which is used while handling offload work 310 */ 311 union hpd_irq_data data; 312 /** 313 * @offload_wq: offload work queue that this work is queued to 314 */ 315 struct hpd_rx_irq_offload_work_queue *offload_wq; 316 /** 317 * @adev: amdgpu_device pointer 318 */ 319 struct amdgpu_device *adev; 320 }; 321 322 /** 323 * struct amdgpu_display_manager - Central amdgpu display manager device 324 * 325 * @dc: Display Core control structure 326 * @adev: AMDGPU base driver structure 327 * @ddev: DRM base driver structure 328 * @display_indexes_num: Max number of display streams supported 329 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 330 * @irq_wq: Dedicated high-priority unbound workqueue for deferred IRQ work 331 * @vmin_vmax_wq: Dedicated unbound workqueue for deferred vmin/vmax updates 332 * @backlight_dev: Backlight control device 333 * @backlight_link: Link on which to control backlight 334 * @backlight_caps: Capabilities of the backlight device 335 * @freesync_module: Module handling freesync calculations 336 * @power_module: Module handling power calculations 337 * @hdcp_workqueue: AMDGPU content protection queue 338 * @fw_dmcu: Reference to DMCU firmware 339 * @dmcu_fw_version: Version of the DMCU firmware 340 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 341 * @cached_state: Caches device atomic state for suspend/resume 342 * @cached_dc_state: Cached state of content streams 343 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 344 * @force_timing_sync: set via debugfs. When set, indicates that all connected 345 * displays will be forced to synchronize. 346 * @dmcub_trace_event_en: enable dmcub trace events 347 * @dmub_outbox_params: DMUB Outbox parameters 348 * @num_of_edps: number of backlight eDPs 349 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the 350 * driver when true 351 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB 352 * transfers are done 353 * @delayed_hpd_wq: work queue used to delay DMUB HPD work 354 */ 355 struct amdgpu_display_manager { 356 357 struct dc *dc; 358 359 /** 360 * @dmub_srv: 361 * 362 * DMUB service, used for controlling the DMUB on hardware 363 * that supports it. The pointer to the dmub_srv will be 364 * NULL on hardware that does not support it. 365 */ 366 struct dmub_srv *dmub_srv; 367 368 /** 369 * @dmub_notify: 370 * 371 * Notification from DMUB. 372 */ 373 374 struct dmub_notification *dmub_notify; 375 376 /** 377 * @dmub_callback: 378 * 379 * Callback functions to handle notification from DMUB. 380 */ 381 382 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; 383 384 /** 385 * @dmub_thread_offload: 386 * 387 * Flag to indicate if callback is offload. 388 */ 389 390 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; 391 392 /** 393 * @dmub_fb_info: 394 * 395 * Framebuffer regions for the DMUB. 396 */ 397 struct dmub_srv_fb_info *dmub_fb_info; 398 399 /** 400 * @dmub_fw: 401 * 402 * DMUB firmware, required on hardware that has DMUB support. 403 */ 404 const struct firmware *dmub_fw; 405 406 /** 407 * @dmub_bo: 408 * 409 * Buffer object for the DMUB. 410 */ 411 struct amdgpu_bo *dmub_bo; 412 413 /** 414 * @dmub_bo_gpu_addr: 415 * 416 * GPU virtual address for the DMUB buffer object. 417 */ 418 u64 dmub_bo_gpu_addr; 419 420 /** 421 * @dmub_bo_cpu_addr: 422 * 423 * CPU address for the DMUB buffer object. 424 */ 425 void *dmub_bo_cpu_addr; 426 427 /** 428 * @dmcub_fw_version: 429 * 430 * DMCUB firmware version. 431 */ 432 uint32_t dmcub_fw_version; 433 434 /** 435 * @fw_inst_size: 436 * 437 * Size of the firmware instruction buffer. 438 */ 439 uint32_t fw_inst_size; 440 441 /** 442 * @cgs_device: 443 * 444 * The Common Graphics Services device. It provides an interface for 445 * accessing registers. 446 */ 447 struct cgs_device *cgs_device; 448 449 struct amdgpu_device *adev; 450 struct drm_device *ddev; 451 u16 display_indexes_num; 452 453 /** 454 * @atomic_obj: 455 * 456 * In combination with &dm_atomic_state it helps manage 457 * global atomic state that doesn't map cleanly into existing 458 * drm resources, like &dc_context. 459 */ 460 struct drm_private_obj atomic_obj; 461 462 /** 463 * @dc_lock: 464 * 465 * Guards access to DC functions that can issue register write 466 * sequences. 467 */ 468 struct mutex dc_lock; 469 470 /** 471 * @dmub_lock: 472 * 473 * Guards access to DMUB command submission. 474 */ 475 spinlock_t dmub_lock; 476 477 /** 478 * @audio_lock: 479 * 480 * Guards access to audio instance changes. 481 */ 482 struct mutex audio_lock; 483 484 /** 485 * @audio_component: 486 * 487 * Used to notify ELD changes to sound driver. 488 */ 489 struct drm_audio_component *audio_component; 490 491 /** 492 * @audio_registered: 493 * 494 * True if the audio component has been registered 495 * successfully, false otherwise. 496 */ 497 bool audio_registered; 498 499 /** 500 * @irq_handler_list_low_tab: 501 * 502 * Low priority IRQ handler table. 503 * 504 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 505 * source. Low priority IRQ handlers are deferred to a workqueue to be 506 * processed. Hence, they can sleep. 507 * 508 * Note that handlers are called in the same order as they were 509 * registered (FIFO). 510 */ 511 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 512 513 /** 514 * @irq_handler_list_high_tab: 515 * 516 * High priority IRQ handler table. 517 * 518 * It is a n*m table, same as &irq_handler_list_low_tab. However, 519 * handlers in this table are not deferred and are called immediately. 520 */ 521 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 522 523 /** 524 * @pflip_params: 525 * 526 * Page flip IRQ parameters, passed to registered handlers when 527 * triggered. 528 */ 529 struct common_irq_params 530 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 531 532 /** 533 * @vblank_params: 534 * 535 * Vertical blanking IRQ parameters, passed to registered handlers when 536 * triggered. 537 */ 538 struct common_irq_params 539 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 540 541 /** 542 * @vline0_params: 543 * 544 * OTG vertical interrupt0 IRQ parameters, passed to registered 545 * handlers when triggered. 546 */ 547 struct common_irq_params 548 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 549 550 /** 551 * @vupdate_params: 552 * 553 * Vertical update IRQ parameters, passed to registered handlers when 554 * triggered. 555 */ 556 struct common_irq_params 557 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 558 559 /** 560 * @irq_reg_lock: 561 * 562 * Serializes the read-modify-writes of the HW interrupt control 563 * registers. Several interrupt sources share one register - e.g. the 564 * enable and clear bits of both VSTARTUP (vblank) and VUPDATE_NO_LOCK 565 * live in OTG_GLOBAL_SYNC_STATUS. Therefore, enabling one source must 566 * not race with acking another. Held only across amdgpu_dm_irq_set() 567 * and amdgpu_dm_irq_ack(). 568 */ 569 spinlock_t irq_reg_lock; 570 571 /** 572 * @dmub_trace_params: 573 * 574 * DMUB trace event IRQ parameters, passed to registered handlers when 575 * triggered. 576 */ 577 struct common_irq_params 578 dmub_trace_params[1]; 579 580 struct common_irq_params 581 dmub_outbox_params[1]; 582 583 spinlock_t irq_handler_list_table_lock; 584 struct workqueue_struct *irq_wq; 585 struct workqueue_struct *vmin_vmax_wq; 586 587 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 588 589 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 590 591 uint8_t num_of_edps; 592 593 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 594 595 struct mod_freesync *freesync_module; 596 /** 597 * @power_module: 598 * 599 * Power management module. 600 */ 601 struct mod_power *power_module; 602 struct hdcp_workqueue *hdcp_workqueue; 603 604 /** 605 * @vblank_control_workqueue: 606 * 607 * Deferred work for vblank control events. 608 */ 609 struct workqueue_struct *vblank_control_workqueue; 610 611 /** 612 * @idle_workqueue: 613 * 614 * Periodic work for idle events. 615 */ 616 struct idle_workqueue *idle_workqueue; 617 618 struct drm_atomic_commit *cached_state; 619 struct dc_state *cached_dc_state; 620 621 struct dm_compressor_info compressor; 622 623 const struct firmware *fw_dmcu; 624 uint32_t dmcu_fw_version; 625 /** 626 * @soc_bounding_box: 627 * 628 * gpu_info FW provided soc bounding box struct or 0 if not 629 * available in FW 630 */ 631 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 632 633 /** 634 * @active_vblank_irq_count: 635 * 636 * number of currently active vblank irqs 637 */ 638 uint32_t active_vblank_irq_count; 639 640 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 641 /** 642 * @secure_display_ctx: 643 * 644 * Store secure display relevant info. e.g. the ROI information 645 * , the work_struct to command dmub, etc. 646 */ 647 struct secure_display_context secure_display_ctx; 648 #endif 649 /** 650 * @hpd_rx_offload_wq: 651 * 652 * Work queue to offload works of hpd_rx_irq 653 */ 654 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; 655 /** 656 * @mst_encoders: 657 * 658 * fake encoders used for DP MST. 659 */ 660 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 661 bool force_timing_sync; 662 bool disable_hpd_irq; 663 bool dmcub_trace_event_en; 664 /** 665 * @da_list: 666 * 667 * DAL fb memory allocation list, for communication with SMU. 668 */ 669 struct list_head da_list; 670 struct completion dmub_aux_transfer_done; 671 struct workqueue_struct *delayed_hpd_wq; 672 673 /** 674 * @brightness: 675 * 676 * cached backlight values. 677 */ 678 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 679 /** 680 * @actual_brightness: 681 * 682 * last successfully applied backlight values. 683 */ 684 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; 685 686 /** 687 * @aux_hpd_discon_quirk: 688 * 689 * quirk for hpd discon while aux is on-going. 690 * occurred on certain intel platform 691 */ 692 bool aux_hpd_discon_quirk; 693 694 /** 695 * @edp0_on_dp1_quirk: 696 * 697 * quirk for platforms that put edp0 on DP1. 698 */ 699 bool edp0_on_dp1_quirk; 700 701 /** 702 * @dpia_aux_lock: 703 * 704 * Guards access to DPIA AUX 705 */ 706 struct mutex dpia_aux_lock; 707 708 /** 709 * @bb_from_dmub: 710 * 711 * Bounding box data read from dmub during early initialization for DCN4+ 712 * Data is stored as a byte array that should be casted to the appropriate bb struct 713 */ 714 void *bb_from_dmub; 715 716 /** 717 * @i2c_devres_group: 718 * 719 * Devres group for DM i2c adapter lifetime management. 720 */ 721 void *i2c_devres_group; 722 723 /** 724 * @oem_i2c: 725 * 726 * OEM i2c bus 727 */ 728 struct amdgpu_i2c_adapter *oem_i2c; 729 730 /** 731 * @fused_io: 732 * 733 * dmub fused io interface 734 */ 735 struct fused_io_sync { 736 struct completion replied; 737 char reply_data[0x40]; // Cannot include dmub_cmd here 738 } fused_io[8]; 739 /** 740 * @hdmi_frl_status_polling_wq: 741 * 742 * Workqueue for HDMI FRL status polling. 743 */ 744 struct workqueue_struct *hdmi_frl_status_polling_wq; 745 /** 746 * @hdmi_frl_status_polling_work: 747 * 748 * Delayed work for 200ms HDMI FRL status polling. 749 */ 750 struct delayed_work hdmi_frl_status_polling_work; 751 /** 752 * @hdmi_frl_status_polling_delay_ms: 753 * 754 * Delay, in milliseconds, between HDMI FRL status polls. 755 */ 756 unsigned int hdmi_frl_status_polling_delay_ms; 757 758 /** 759 * @boot_time_crc_info: 760 * 761 * Buffer info for the boot time crc. 762 */ 763 struct dm_boot_time_crc_info boot_time_crc_info; 764 }; 765 766 enum dsc_clock_force_state { 767 DSC_CLK_FORCE_DEFAULT = 0, 768 DSC_CLK_FORCE_ENABLE, 769 DSC_CLK_FORCE_DISABLE, 770 }; 771 772 struct dsc_preferred_settings { 773 enum dsc_clock_force_state dsc_force_enable; 774 uint32_t dsc_num_slices_v; 775 uint32_t dsc_num_slices_h; 776 uint32_t dsc_bits_per_pixel; 777 bool dsc_force_disable_passthrough; 778 }; 779 780 enum mst_progress_status { 781 MST_STATUS_DEFAULT = 0, 782 MST_PROBE = BIT(0), 783 MST_REMOTE_EDID = BIT(1), 784 MST_ALLOCATE_NEW_PAYLOAD = BIT(2), 785 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), 786 }; 787 788 /** 789 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info 790 * 791 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this 792 * struct is useful to keep track of the display-specific information about 793 * FreeSync. 794 */ 795 struct amdgpu_hdmi_vsdb_info { 796 /** 797 * @amd_vsdb_version: Vendor Specific Data Block Version, should be 798 * used to determine which Vendor Specific InfoFrame (VSIF) to send. 799 */ 800 unsigned int amd_vsdb_version; 801 802 /** 803 * @freesync_supported: FreeSync Supported. 804 */ 805 bool freesync_supported; 806 807 /** 808 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. 809 */ 810 unsigned int min_refresh_rate_hz; 811 812 /** 813 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz 814 */ 815 unsigned int max_refresh_rate_hz; 816 817 /** 818 * @freesync_mccs_vcp_code: MCCS VCP code for freesync state 819 */ 820 unsigned int freesync_mccs_vcp_code; 821 822 /** 823 * @replay_mode: Replay supported 824 */ 825 bool replay_mode; 826 }; 827 828 struct amdgpu_dm_connector { 829 830 struct drm_connector base; 831 uint32_t connector_id; 832 int bl_idx; 833 834 struct cec_notifier *notifier; 835 836 /* we need to mind the EDID between detect 837 and get modes due to analog/digital/tvencoder */ 838 const struct drm_edid *drm_edid; 839 840 /* shared with amdgpu */ 841 struct amdgpu_hpd hpd; 842 843 /* number of modes generated from EDID at 'dc_sink' */ 844 int num_modes; 845 846 /* The 'old' sink - before an HPD. 847 * The 'current' sink is in dc_link->sink. */ 848 struct dc_sink *dc_sink; 849 struct dc_link *dc_link; 850 851 /** 852 * @dc_em_sink: Reference to the emulated (virtual) sink. 853 */ 854 struct dc_sink *dc_em_sink; 855 856 /* DM only */ 857 struct drm_dp_mst_topology_mgr mst_mgr; 858 struct amdgpu_dm_dp_aux dm_dp_aux; 859 struct drm_dp_mst_port *mst_output_port; 860 struct amdgpu_dm_connector *mst_root; 861 struct drm_dp_aux *dsc_aux; 862 uint32_t mst_local_bw; 863 uint16_t vc_full_pbn; 864 struct mutex handle_mst_msg_ready; 865 866 /* branch device specific data */ 867 uint32_t branch_ieee_oui; 868 869 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 870 struct amdgpu_i2c_adapter *i2c; 871 872 /* Monitor range limits */ 873 /** 874 * @min_vfreq: Minimal frequency supported by the display in Hz. This 875 * value is set to zero when there is no FreeSync support. 876 */ 877 int min_vfreq; 878 879 /** 880 * @max_vfreq: Maximum frequency supported by the display in Hz. This 881 * value is set to zero when there is no FreeSync support. 882 */ 883 int max_vfreq ; 884 885 /* Audio instance - protected by audio_lock. */ 886 int audio_inst; 887 888 struct mutex hpd_lock; 889 890 bool fake_enable; 891 uint8_t force_yuv_pixel_format; 892 struct dsc_preferred_settings dsc_settings; 893 struct psr_caps psr_caps; 894 union dp_downstream_port_present mst_downstream_port_present; 895 /* Cached display modes */ 896 struct drm_display_mode freesync_vid_base; 897 898 int sr_skip_count; 899 bool disallow_edp_enter_psr; 900 bool disallow_edp_enter_replay; 901 902 union dwnstream_portxcaps mst_downstream_port_caps; 903 904 /* Record progress status of mst*/ 905 uint8_t mst_status; 906 907 /* Automated testing */ 908 bool timing_changed; 909 struct dc_crtc_timing *timing_requested; 910 911 /* Adaptive Sync */ 912 bool pack_sdp_v1_3; 913 enum adaptive_sync_type as_type; 914 struct amdgpu_hdmi_vsdb_info vsdb_info; 915 916 /* HDMI HPD debounce support */ 917 unsigned int hdmi_hpd_debounce_delay_ms; 918 struct delayed_work hdmi_hpd_debounce_work; 919 struct dc_sink *hdmi_prev_sink; 920 921 /* HDMI compliance automation */ 922 bool hdmi_comp_auto; 923 }; 924 925 static inline void amdgpu_dm_set_mst_status(uint8_t *status, 926 uint8_t flags, bool set) 927 { 928 if (set) 929 *status |= flags; 930 else 931 *status &= ~flags; 932 } 933 934 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 935 936 struct amdgpu_dm_wb_connector { 937 struct drm_writeback_connector base; 938 struct dc_link *link; 939 }; 940 941 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base) 942 943 extern const struct amdgpu_ip_block_version dm_ip_block; 944 945 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD. 946 * 947 * It includes standardized transfer functions and pure power functions. The 948 * transfer function coefficients are available at modules/color/color_gamma.c 949 */ 950 enum amdgpu_transfer_function { 951 AMDGPU_TRANSFER_FUNCTION_DEFAULT, 952 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF, 953 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF, 954 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF, 955 AMDGPU_TRANSFER_FUNCTION_IDENTITY, 956 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF, 957 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF, 958 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF, 959 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF, 960 AMDGPU_TRANSFER_FUNCTION_BT709_OETF, 961 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF, 962 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF, 963 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF, 964 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF, 965 AMDGPU_TRANSFER_FUNCTION_COUNT 966 }; 967 968 struct dc_flip_addrs; 969 struct dc_scaling_info; 970 struct dc_plane_info; 971 972 struct dm_plane_state { 973 struct drm_plane_state base; 974 struct dc_plane_state *dc_state; 975 976 /* Plane color mgmt */ 977 /** 978 * @degamma_lut: 979 * 980 * 1D LUT for mapping framebuffer/plane pixel data before sampling or 981 * blending operations. It's usually applied to linearize input space. 982 * The blob (if not NULL) is an array of &struct drm_color_lut. 983 */ 984 struct drm_property_blob *degamma_lut; 985 /** 986 * @degamma_tf: 987 * 988 * Predefined transfer function to tell DC driver the input space to 989 * linearize. 990 */ 991 enum amdgpu_transfer_function degamma_tf; 992 /** 993 * @hdr_mult: 994 * 995 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed 996 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on 997 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously. 998 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you 999 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is 1000 * S31.32 sign-magnitude. 1001 * 1002 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ 1003 * TF is needed for any subsequent linear-to-non-linear transforms. 1004 */ 1005 __u64 hdr_mult; 1006 /** 1007 * @ctm: 1008 * 1009 * Color transformation matrix. The blob (if not NULL) is a &struct 1010 * drm_color_ctm_3x4. 1011 */ 1012 struct drm_property_blob *ctm; 1013 /** 1014 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an 1015 * array of &struct drm_color_lut. 1016 */ 1017 struct drm_property_blob *shaper_lut; 1018 /** 1019 * @shaper_tf: 1020 * 1021 * Predefined transfer function to delinearize color space. 1022 */ 1023 enum amdgpu_transfer_function shaper_tf; 1024 /** 1025 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of 1026 * &struct drm_color_lut. 1027 */ 1028 struct drm_property_blob *lut3d; 1029 /** 1030 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an 1031 * array of &struct drm_color_lut. 1032 */ 1033 struct drm_property_blob *blend_lut; 1034 /** 1035 * @blend_tf: 1036 * 1037 * Pre-defined transfer function for converting plane pixel data before 1038 * applying blend LUT. 1039 */ 1040 enum amdgpu_transfer_function blend_tf; 1041 1042 /* Cached per-plane surface descriptors kept in the DRM plane state. 1043 * The DRM atomic old/new state swap lets us compare the previous 1044 * commit's values (old) against the newly computed ones to detect a 1045 * real plane change (vs an address-only flip) so DC only gets a 1046 * scaling_info/plane_info surface update when it actually changed. 1047 */ 1048 struct dc_flip_addrs *flip_addr; 1049 struct dc_scaling_info *scaling_info; 1050 struct dc_plane_info *plane_info; 1051 }; 1052 1053 enum amdgpu_dm_cursor_mode { 1054 DM_CURSOR_NATIVE_MODE = 0, 1055 DM_CURSOR_OVERLAY_MODE, 1056 }; 1057 1058 struct dm_crtc_state { 1059 struct drm_crtc_state base; 1060 struct dc_stream_state *stream; 1061 1062 bool cm_has_degamma; 1063 bool cm_is_degamma_srgb; 1064 1065 bool mpo_requested; 1066 1067 int update_type; 1068 int active_planes; 1069 1070 int crc_skip_count; 1071 1072 bool freesync_vrr_info_changed; 1073 1074 bool mode_changed_independent_from_dsc; 1075 bool dsc_force_changed; 1076 bool vrr_supported; 1077 struct mod_freesync_config freesync_config; 1078 struct dc_info_packet vrr_infopacket; 1079 struct dc_info_packet vtem_infopacket; 1080 1081 int abm_level; 1082 1083 /** 1084 * @regamma_tf: 1085 * 1086 * Pre-defined transfer function for converting internal FB -> wire 1087 * encoding. 1088 */ 1089 enum amdgpu_transfer_function regamma_tf; 1090 1091 enum amdgpu_dm_cursor_mode cursor_mode; 1092 }; 1093 1094 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 1095 1096 struct dm_atomic_state { 1097 struct drm_private_state base; 1098 1099 struct dc_state *context; 1100 }; 1101 1102 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 1103 1104 struct dm_connector_state { 1105 struct drm_connector_state base; 1106 1107 enum amdgpu_rmx_type scaling; 1108 uint8_t underscan_vborder; 1109 uint8_t underscan_hborder; 1110 bool underscan_enable; 1111 bool freesync_capable; 1112 bool update_hdcp; 1113 bool abm_sysfs_forbidden; 1114 uint8_t abm_level; 1115 int vcpi_slots; 1116 uint64_t pbn; 1117 }; 1118 1119 #define to_dm_connector_state(x)\ 1120 container_of((x), struct dm_connector_state, base) 1121 1122 #include "amdgpu_dm_connector.h" 1123 1124 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 1125 1126 /* 3D LUT max size is 17x17x17 (4913 entries) */ 1127 #define MAX_COLOR_3DLUT_SIZE 17 1128 #define MAX_COLOR_3DLUT_BITDEPTH 12 1129 int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, 1130 struct drm_plane_state *plane_state); 1131 /* 1D LUT size */ 1132 #define MAX_COLOR_LUT_ENTRIES 4096 1133 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 1134 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 1135 1136 void amdgpu_dm_init_color_mod(void); 1137 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev); 1138 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 1139 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 1140 int amdgpu_dm_check_crtc_color_mgmt(struct dm_crtc_state *crtc, 1141 bool check_only); 1142 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 1143 struct drm_plane_state *plane_state, 1144 struct dc_plane_state *dc_plane_state); 1145 1146 void populate_hdmi_info_from_connector(bool enable_frl, struct drm_hdmi_info *info, 1147 struct dc_edid_caps *edid_caps); 1148 1149 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, 1150 struct aux_payload *payload, enum aux_return_code_type *operation_result); 1151 1152 bool amdgpu_dm_execute_fused_io( 1153 struct amdgpu_device *dev, 1154 struct dc_link *link, 1155 union dmub_rb_cmd *commands, 1156 uint8_t count, 1157 uint32_t timeout_us 1158 ); 1159 1160 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, 1161 struct set_config_cmd_payload *payload, enum set_config_status *operation_result); 1162 1163 int dm_atomic_get_state(struct drm_atomic_commit *state, 1164 struct dm_atomic_state **dm_state); 1165 1166 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); 1167 1168 void *dm_allocate_gpu_mem(struct amdgpu_device *adev, 1169 enum dc_gpu_mem_alloc_type type, 1170 size_t size, 1171 long long *addr); 1172 void dm_free_gpu_mem(struct amdgpu_device *adev, 1173 enum dc_gpu_mem_alloc_type type, 1174 void *addr); 1175 1176 bool amdgpu_dm_is_headless(struct amdgpu_device *adev); 1177 1178 bool amdgpu_dm_crtc_complete_writeback(struct amdgpu_crtc *acrtc); 1179 1180 void retrieve_dmi_info(struct amdgpu_display_manager *dm); 1181 struct pci_dev; 1182 bool dm_should_disable_stutter(struct pci_dev *pdev); 1183 1184 void amdgpu_dm_emulated_link_detect(struct dc_link *link); 1185 void amdgpu_dm_apply_delay_after_dpcd_poweroff(struct amdgpu_device *adev, 1186 struct dc_sink *sink); 1187 1188 struct __drm_planes_state *amdgpu_dm_get_next_zpos(struct drm_atomic_commit *state, 1189 struct __drm_planes_state *prev); 1190 1191 /* 1192 * Use the uniqueness of the plane's (zpos, drm obj ID) combination to iterate 1193 * by descending zpos, as read from the new plane state. This is the same 1194 * ordering as defined by drm_atomic_normalize_zpos(). 1195 */ 1196 #define for_each_oldnew_plane_in_descending_zpos(__state, plane, old_plane_state, new_plane_state) \ 1197 for (struct __drm_planes_state *__i = amdgpu_dm_get_next_zpos((__state), NULL); \ 1198 __i != NULL; __i = amdgpu_dm_get_next_zpos((__state), __i)) \ 1199 for_each_if(((plane) = __i->ptr, \ 1200 (void)(plane) /* Only to avoid unused-but-set-variable warning */, \ 1201 (old_plane_state) = __i->old_state, \ 1202 (new_plane_state) = __i->new_state, 1)) 1203 1204 #if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST) 1205 struct amdgpu_ip_block; 1206 int dm_wait_for_idle(struct amdgpu_ip_block *ip_block); 1207 int dm_soft_reset(struct amdgpu_ip_block *ip_block); 1208 int dm_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1209 enum amd_clockgating_state state); 1210 int dm_set_powergating_state(struct amdgpu_ip_block *ip_block, 1211 enum amd_powergating_state state); 1212 void dm_bandwidth_update(struct amdgpu_device *adev); 1213 u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc); 1214 int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 1215 u32 *vbl, u32 *position); 1216 struct dm_atomic_state *dm_atomic_get_new_state(struct drm_atomic_commit *state); 1217 struct drm_private_state *dm_atomic_duplicate_state(struct drm_private_obj *obj); 1218 void dm_atomic_destroy_state(struct drm_private_obj *obj, 1219 struct drm_private_state *state); 1220 struct dc_flip_addrs; 1221 void fill_dc_dirty_rects(struct drm_plane *plane, 1222 struct drm_plane_state *old_plane_state, 1223 struct drm_plane_state *new_plane_state, 1224 struct drm_crtc_state *crtc_state, 1225 struct dc_flip_addrs *flip_addrs, 1226 bool is_psr_su, 1227 bool *dirty_regions_changed); 1228 void dm_update_pflip_irq_state(struct amdgpu_device *adev, 1229 struct amdgpu_crtc *acrtc); 1230 void amdgpu_dm_commit_cursors(struct drm_atomic_commit *state); 1231 void amdgpu_dm_update_cursor(struct drm_plane *plane, 1232 struct drm_plane_state *old_plane_state, 1233 struct dc_stream_update *update); 1234 void dm_arm_vblank_event(struct amdgpu_crtc *acrtc, 1235 struct dm_crtc_state *acrtc_state, 1236 bool pflip_update, bool cursor_update); 1237 void dm_arm_vblank_event_pre_programming(struct amdgpu_crtc *acrtc, 1238 struct dm_crtc_state *acrtc_state, 1239 bool pflip_update, bool cursor_update); 1240 bool should_reset_plane(struct drm_atomic_commit *state, 1241 struct drm_plane *plane, 1242 struct drm_plane_state *old_plane_state, 1243 struct drm_plane_state *new_plane_state); 1244 int add_affected_mst_dsc_crtcs(struct drm_atomic_commit *state, 1245 struct drm_crtc *crtc); 1246 bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev, 1247 struct drm_atomic_commit *state, 1248 struct drm_crtc_state *crtc_state); 1249 void amdgpu_dm_dump_links_and_sinks(struct amdgpu_device *adev); 1250 void amdgpu_dm_update_hdcp(struct drm_atomic_commit *state); 1251 int amdgpu_dm_atomic_setup_commit(struct drm_atomic_commit *state); 1252 int do_aquire_global_lock(struct drm_device *dev, 1253 struct drm_atomic_commit *state); 1254 int dm_update_crtc_state(struct amdgpu_display_manager *dm, 1255 struct drm_atomic_commit *state, 1256 struct drm_crtc *crtc, 1257 struct drm_crtc_state *old_crtc_state, 1258 struct drm_crtc_state *new_crtc_state, 1259 bool enable, 1260 bool *lock_and_validation_needed); 1261 int dm_update_plane_state(struct dc *dc, 1262 struct drm_atomic_commit *state, 1263 struct drm_plane *plane, 1264 struct drm_plane_state *old_plane_state, 1265 struct drm_plane_state *new_plane_state, 1266 bool enable, 1267 bool *lock_and_validation_needed, 1268 bool *is_top_most_overlay); 1269 int amdgpu_dm_atomic_check(struct drm_device *dev, 1270 struct drm_atomic_commit *state); 1271 void amdgpu_dm_mod_power_update_streams(struct drm_atomic_commit *state, 1272 struct amdgpu_display_manager *dm); 1273 void amdgpu_dm_mod_power_setup_streams(struct drm_atomic_commit *state, 1274 struct amdgpu_display_manager *dm); 1275 int amdgpu_dm_early_fini(struct amdgpu_ip_block *ip_block); 1276 int dm_sw_fini(struct amdgpu_ip_block *ip_block); 1277 int dm_oem_i2c_hw_init(struct amdgpu_device *adev); 1278 void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr); 1279 void s3_handle_mst(struct drm_device *dev, bool suspend); 1280 void dm_gpureset_commit_state(struct dc_state *dc_state, struct amdgpu_display_manager *dm); 1281 int dm_plane_layer_index_cmp(const void *a, const void *b); 1282 bool update_planes_and_stream_adapter(struct dc *dc, 1283 int planes_count, 1284 struct dc_stream_state *stream, 1285 struct dc_stream_update *stream_update, 1286 struct dc_surface_update *array_of_surface_update); 1287 int fill_plane_color_attributes(struct drm_atomic_commit *state, 1288 const struct drm_plane_state *plane_state, 1289 const enum surface_pixel_format format, 1290 enum dc_color_space *color_space); 1291 bool modereset_required(struct drm_crtc_state *crtc_state); 1292 bool is_scaling_state_different(const struct dm_connector_state *dm_state, 1293 const struct dm_connector_state *old_dm_state); 1294 void set_multisync_trigger_params(struct dc_stream_state *stream); 1295 void set_master_stream(struct dc_stream_state *stream_set[], int stream_count); 1296 void dm_enable_per_frame_crtc_master_sync(struct dc_state *context); 1297 struct hdcp_workqueue; 1298 bool is_content_protection_different(struct drm_crtc_state *new_crtc_state, 1299 struct drm_crtc_state *old_crtc_state, 1300 struct drm_connector_state *new_conn_state, 1301 struct drm_connector_state *old_conn_state, 1302 const struct drm_connector *connector, 1303 struct hdcp_workqueue *hdcp_w); 1304 1305 struct amdgpu_dm_services_kunit_ops { 1306 int (*bo_create_kernel)(struct amdgpu_device *adev, unsigned long size, 1307 int align, u32 domain, struct amdgpu_bo **bo_ptr, 1308 u64 *gpu_addr, void **cpu_addr); 1309 void (*bo_free_kernel)(struct amdgpu_bo **bo, u64 *gpu_addr, 1310 void **cpu_addr); 1311 }; 1312 1313 void amdgpu_dm_services_kunit_set_ops(const struct amdgpu_dm_services_kunit_ops *ops); 1314 1315 struct amdgpu_dm_kunit_ops { 1316 uint64_t (*gmc_pd_addr)(struct amdgpu_bo *bo); 1317 void (*post_update_surfaces_to_stream)(struct dc *dc); 1318 bool (*update_planes_and_stream)(struct dc *dc, 1319 struct dc_surface_update *surface_updates, 1320 int surface_count, 1321 struct dc_stream_state *dc_stream, 1322 struct dc_stream_update *stream_update); 1323 struct drm_atomic_commit *(*atomic_helper_suspend)(struct drm_device *dev); 1324 }; 1325 1326 void amdgpu_dm_kunit_set_ops(const struct amdgpu_dm_kunit_ops *ops); 1327 1328 struct dc_phy_addr_space_config; 1329 struct dc_plane_address; 1330 struct dc_plane_cap; 1331 struct dc_plane_info; 1332 struct dsc_mst_fairness_vars; 1333 1334 void mmhub_read_system_context(struct amdgpu_device *adev, 1335 struct dc_phy_addr_space_config *pa_config); 1336 int amdgpu_dm_init_power_module(struct amdgpu_display_manager *dm); 1337 void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, struct dc_state *state, bool enable); 1338 enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc); 1339 int dm_cache_state(struct amdgpu_device *adev); 1340 void dm_destroy_cached_state(struct amdgpu_device *adev); 1341 void dm_clear_writeback(struct amdgpu_display_manager *dm, 1342 struct amdgpu_crtc *acrtc, 1343 struct dm_crtc_state *crtc_state); 1344 void dm_set_writeback(struct amdgpu_display_manager *dm, 1345 struct dm_crtc_state *crtc_state, 1346 struct drm_connector *connector, 1347 struct drm_connector_state *new_con_state); 1348 int dm_early_init(struct amdgpu_ip_block *ip_block); 1349 int fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 1350 struct drm_atomic_commit *state, 1351 const struct drm_plane_state *plane_state, 1352 struct dc_plane_info *plane_info, 1353 struct dc_plane_address *address, 1354 bool tmz_surface); 1355 int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_commit *state, struct dc_state *dc_state, 1356 struct dsc_mst_fairness_vars *vars); 1357 void manage_dm_interrupts(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc, 1358 struct dm_crtc_state *acrtc_state); 1359 void amdgpu_dm_enable_self_refresh(struct amdgpu_display_manager *dm, 1360 struct amdgpu_crtc *acrtc_attach, 1361 const struct dm_crtc_state *acrtc_state, const u64 current_ts); 1362 int load_dmcu_fw(struct amdgpu_device *adev); 1363 int dm_sw_init(struct amdgpu_ip_block *ip_block); 1364 int dm_late_init(struct amdgpu_ip_block *ip_block); 1365 int amdgpu_dm_mode_config_init(struct amdgpu_device *adev); 1366 int initialize_plane(struct amdgpu_display_manager *dm, struct amdgpu_mode_info *mode_info, 1367 int plane_id, enum drm_plane_type plane_type, 1368 const struct dc_plane_cap *plane_cap); 1369 int fill_dc_plane_attributes(struct amdgpu_device *adev, struct dc_plane_state *dc_plane_state, 1370 struct drm_plane_state *plane_state, 1371 struct drm_crtc_state *crtc_state); 1372 #endif 1373 1374 #endif /* __AMDGPU_DM_H__ */ 1375