1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dc_types.h" 28 #include "dm_services.h" 29 #include "dc.h" 30 31 #include "dcn32/dcn32_init.h" 32 33 #include "resource.h" 34 #include "include/irq_service_interface.h" 35 #include "dcn32_resource.h" 36 37 #include "dcn20/dcn20_resource.h" 38 #include "dcn30/dcn30_resource.h" 39 40 #include "dcn10/dcn10_ipp.h" 41 #include "dcn30/dcn30_hubbub.h" 42 #include "dcn31/dcn31_hubbub.h" 43 #include "dcn32/dcn32_hubbub.h" 44 #include "dcn32/dcn32_mpc.h" 45 #include "dcn32/dcn32_hubp.h" 46 #include "irq/dcn32/irq_service_dcn32.h" 47 #include "dcn32/dcn32_dpp.h" 48 #include "dcn32/dcn32_optc.h" 49 #include "dcn20/dcn20_hwseq.h" 50 #include "dcn30/dcn30_hwseq.h" 51 #include "dce110/dce110_hwseq.h" 52 #include "dcn30/dcn30_opp.h" 53 #include "dcn20/dcn20_dsc.h" 54 #include "dcn30/dcn30_vpg.h" 55 #include "dcn30/dcn30_afmt.h" 56 #include "dcn30/dcn30_dio_stream_encoder.h" 57 #include "dcn32/dcn32_dio_stream_encoder.h" 58 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 59 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 60 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 61 #include "dcn31/dcn31_apg.h" 62 #include "dcn31/dcn31_dio_link_encoder.h" 63 #include "dcn32/dcn32_dio_link_encoder.h" 64 #include "dce/dce_clock_source.h" 65 #include "dce/dce_audio.h" 66 #include "dce/dce_hwseq.h" 67 #include "clk_mgr.h" 68 #include "dio/virtual/virtual_stream_encoder.h" 69 #include "dio/dcn10/dcn10_dio.h" 70 #include "dml/display_mode_vba.h" 71 #include "dcn32/dcn32_dccg.h" 72 #include "dcn10/dcn10_resource.h" 73 #include "link_service.h" 74 #include "dcn31/dcn31_panel_cntl.h" 75 76 #include "dcn30/dcn30_dwb.h" 77 #include "dcn32/dcn32_mmhubbub.h" 78 79 #include "dcn/dcn_3_2_0_offset.h" 80 #include "dcn/dcn_3_2_0_sh_mask.h" 81 #include "nbio/nbio_4_3_0_offset.h" 82 83 #include "reg_helper.h" 84 #include "dce/dmub_abm.h" 85 #include "dce/dmub_psr.h" 86 #include "dce/dce_aux.h" 87 #include "dce/dce_i2c.h" 88 89 #include "dml/dcn30/display_mode_vba_30.h" 90 #include "vm_helper.h" 91 #include "dcn20/dcn20_vmid.h" 92 #include "dml/dcn32/dcn32_fpu.h" 93 94 #include "dc_state_priv.h" 95 96 #include "dml2_0/dml2_wrapper.h" 97 98 #define DC_LOGGER_INIT(logger) 99 100 enum dcn32_clk_src_array_id { 101 DCN32_CLK_SRC_PLL0, 102 DCN32_CLK_SRC_PLL1, 103 DCN32_CLK_SRC_PLL2, 104 DCN32_CLK_SRC_PLL3, 105 DCN32_CLK_SRC_PLL4, 106 DCN32_CLK_SRC_TOTAL 107 }; 108 109 /* begin ********************* 110 * macros to expend register list macro defined in HW object header file 111 */ 112 113 /* DCN */ 114 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 115 116 #define BASE(seg) BASE_INNER(seg) 117 118 #define SR(reg_name)\ 119 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 120 reg ## reg_name 121 #define SR_ARR(reg_name, id) \ 122 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 123 124 #define SR_ARR_INIT(reg_name, id, value) \ 125 REG_STRUCT[id].reg_name = value 126 127 #define SRI(reg_name, block, id)\ 128 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 129 reg ## block ## id ## _ ## reg_name 130 131 #define SRI_ARR(reg_name, block, id)\ 132 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 133 reg ## block ## id ## _ ## reg_name 134 135 #define SR_ARR_I2C(reg_name, id) \ 136 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 137 138 #define SRI_ARR_I2C(reg_name, block, id)\ 139 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 140 reg ## block ## id ## _ ## reg_name 141 142 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 143 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 144 reg ## block ## id ## _ ## reg_name 145 146 #define SRI2(reg_name, block, id)\ 147 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 148 reg ## reg_name 149 #define SRI2_ARR(reg_name, block, id)\ 150 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 151 reg ## reg_name 152 153 #define SRIR(var_name, reg_name, block, id)\ 154 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 155 reg ## block ## id ## _ ## reg_name 156 157 #define SRII(reg_name, block, id)\ 158 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 159 reg ## block ## id ## _ ## reg_name 160 161 #define SRII_ARR_2(reg_name, block, id, inst)\ 162 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 163 reg ## block ## id ## _ ## reg_name 164 165 #define SRII_MPC_RMU(reg_name, block, id)\ 166 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 167 reg ## block ## id ## _ ## reg_name 168 169 #define SRII_DWB(reg_name, temp_name, block, id)\ 170 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 171 reg ## block ## id ## _ ## temp_name 172 173 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 174 .field_name = reg_name ## __ ## field_name ## post_fix 175 176 #define DCCG_SRII(reg_name, block, id)\ 177 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 178 reg ## block ## id ## _ ## reg_name 179 180 #define VUPDATE_SRII(reg_name, block, id)\ 181 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 182 reg ## reg_name ## _ ## block ## id 183 184 /* NBIO */ 185 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 186 187 #define NBIO_BASE(seg) \ 188 NBIO_BASE_INNER(seg) 189 190 #define NBIO_SR(reg_name)\ 191 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 192 regBIF_BX0_ ## reg_name 193 #define NBIO_SR_ARR(reg_name, id)\ 194 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 195 regBIF_BX0_ ## reg_name 196 197 #undef CTX 198 #define CTX ctx 199 #define REG(reg_name) \ 200 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 201 202 static struct bios_registers bios_regs; 203 204 #define bios_regs_init() \ 205 ( \ 206 NBIO_SR(BIOS_SCRATCH_3),\ 207 NBIO_SR(BIOS_SCRATCH_6)\ 208 ) 209 210 #define clk_src_regs_init(index, pllid)\ 211 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 212 213 static struct dce110_clk_src_regs clk_src_regs[5]; 214 215 static const struct dce110_clk_src_shift cs_shift = { 216 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 217 }; 218 219 static const struct dce110_clk_src_mask cs_mask = { 220 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 221 }; 222 223 #define abm_regs_init(id)\ 224 ABM_DCN32_REG_LIST_RI(id) 225 226 static struct dce_abm_registers abm_regs[4]; 227 228 static const struct dce_abm_shift abm_shift = { 229 ABM_MASK_SH_LIST_DCN32(__SHIFT) 230 }; 231 232 static const struct dce_abm_mask abm_mask = { 233 ABM_MASK_SH_LIST_DCN32(_MASK) 234 }; 235 236 #define audio_regs_init(id)\ 237 AUD_COMMON_REG_LIST_RI(id) 238 239 static struct dce_audio_registers audio_regs[5]; 240 241 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 242 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 243 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 244 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 245 246 static const struct dce_audio_shift audio_shift = { 247 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 248 }; 249 250 static const struct dce_audio_mask audio_mask = { 251 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 252 }; 253 254 #define vpg_regs_init(id)\ 255 VPG_DCN3_REG_LIST_RI(id) 256 257 static struct dcn30_vpg_registers vpg_regs[10]; 258 259 static const struct dcn30_vpg_shift vpg_shift = { 260 DCN3_VPG_MASK_SH_LIST(__SHIFT) 261 }; 262 263 static const struct dcn30_vpg_mask vpg_mask = { 264 DCN3_VPG_MASK_SH_LIST(_MASK) 265 }; 266 267 #define afmt_regs_init(id)\ 268 AFMT_DCN3_REG_LIST_RI(id) 269 270 static struct dcn30_afmt_registers afmt_regs[6]; 271 272 static const struct dcn30_afmt_shift afmt_shift = { 273 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 274 }; 275 276 static const struct dcn30_afmt_mask afmt_mask = { 277 DCN3_AFMT_MASK_SH_LIST(_MASK) 278 }; 279 280 #define apg_regs_init(id)\ 281 APG_DCN31_REG_LIST_RI(id) 282 283 static struct dcn31_apg_registers apg_regs[4]; 284 285 static const struct dcn31_apg_shift apg_shift = { 286 DCN31_APG_MASK_SH_LIST(__SHIFT) 287 }; 288 289 static const struct dcn31_apg_mask apg_mask = { 290 DCN31_APG_MASK_SH_LIST(_MASK) 291 }; 292 293 #define stream_enc_regs_init(id)\ 294 SE_DCN32_REG_LIST_RI(id) 295 296 static struct dcn10_stream_enc_registers stream_enc_regs[5]; 297 298 static const struct dcn10_stream_encoder_shift se_shift = { 299 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 300 }; 301 302 static const struct dcn10_stream_encoder_mask se_mask = { 303 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 304 }; 305 306 307 #define aux_regs_init(id)\ 308 DCN2_AUX_REG_LIST_RI(id) 309 310 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 311 312 #define hpd_regs_init(id)\ 313 HPD_REG_LIST_RI(id) 314 315 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 316 317 #define link_regs_init(id, phyid)\ 318 ( \ 319 LE_DCN31_REG_LIST_RI(id), \ 320 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\ 321 ) 322 /*DPCS_DCN31_REG_LIST(id),*/ \ 323 324 static struct dcn10_link_enc_registers link_enc_regs[5]; 325 326 static const struct dcn10_link_enc_shift le_shift = { 327 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 328 //DPCS_DCN31_MASK_SH_LIST(__SHIFT) 329 }; 330 331 static const struct dcn10_link_enc_mask le_mask = { 332 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 333 //DPCS_DCN31_MASK_SH_LIST(_MASK) 334 }; 335 336 #define hpo_dp_stream_encoder_reg_init(id)\ 337 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 338 339 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 340 341 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 342 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 343 }; 344 345 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 346 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 347 }; 348 349 350 #define hpo_dp_link_encoder_reg_init(id)\ 351 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 352 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 353 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 354 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 355 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 356 357 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 358 359 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 360 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 361 }; 362 363 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 364 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 365 }; 366 367 #define dpp_regs_init(id)\ 368 DPP_REG_LIST_DCN30_COMMON_RI(id) 369 370 static struct dcn3_dpp_registers dpp_regs[4]; 371 372 static const struct dcn3_dpp_shift tf_shift = { 373 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 374 }; 375 376 static const struct dcn3_dpp_mask tf_mask = { 377 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 378 }; 379 380 381 #define opp_regs_init(id)\ 382 OPP_REG_LIST_DCN30_RI(id) 383 384 static struct dcn20_opp_registers opp_regs[4]; 385 386 static const struct dcn20_opp_shift opp_shift = { 387 OPP_MASK_SH_LIST_DCN20(__SHIFT) 388 }; 389 390 static const struct dcn20_opp_mask opp_mask = { 391 OPP_MASK_SH_LIST_DCN20(_MASK) 392 }; 393 394 #define aux_engine_regs_init(id)\ 395 ( \ 396 AUX_COMMON_REG_LIST0_RI(id), \ 397 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 398 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 399 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ 400 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\ 401 ) 402 403 static struct dce110_aux_registers aux_engine_regs[5]; 404 405 static const struct dce110_aux_registers_shift aux_shift = { 406 DCN_AUX_MASK_SH_LIST(__SHIFT) 407 }; 408 409 static const struct dce110_aux_registers_mask aux_mask = { 410 DCN_AUX_MASK_SH_LIST(_MASK) 411 }; 412 413 #define dwbc_regs_dcn3_init(id)\ 414 DWBC_COMMON_REG_LIST_DCN30_RI(id) 415 416 static struct dcn30_dwbc_registers dwbc30_regs[1]; 417 418 static const struct dcn30_dwbc_shift dwbc30_shift = { 419 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 420 }; 421 422 static const struct dcn30_dwbc_mask dwbc30_mask = { 423 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 424 }; 425 426 #define mcif_wb_regs_dcn3_init(id)\ 427 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id) 428 429 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1]; 430 431 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 432 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 433 }; 434 435 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 436 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 437 }; 438 439 #define dsc_regsDCN20_init(id)\ 440 DSC_REG_LIST_DCN20_RI(id) 441 442 static struct dcn20_dsc_registers dsc_regs[4]; 443 444 static const struct dcn20_dsc_shift dsc_shift = { 445 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 446 }; 447 448 static const struct dcn20_dsc_mask dsc_mask = { 449 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 450 }; 451 452 static struct dcn30_mpc_registers mpc_regs; 453 454 #define dcn_mpc_regs_init() \ 455 MPC_REG_LIST_DCN3_2_RI(0),\ 456 MPC_REG_LIST_DCN3_2_RI(1),\ 457 MPC_REG_LIST_DCN3_2_RI(2),\ 458 MPC_REG_LIST_DCN3_2_RI(3),\ 459 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 460 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 461 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 462 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\ 463 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0) 464 465 static const struct dcn30_mpc_shift mpc_shift = { 466 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 467 }; 468 469 static const struct dcn30_mpc_mask mpc_mask = { 470 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 471 }; 472 473 #define optc_regs_init(id)\ 474 OPTC_COMMON_REG_LIST_DCN3_2_RI(id) 475 476 static struct dcn_optc_registers optc_regs[4]; 477 478 static const struct dcn_optc_shift optc_shift = { 479 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 480 }; 481 482 static const struct dcn_optc_mask optc_mask = { 483 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 484 }; 485 486 #define hubp_regs_init(id)\ 487 HUBP_REG_LIST_DCN32_RI(id) 488 489 static struct dcn_hubp2_registers hubp_regs[4]; 490 491 492 static const struct dcn_hubp2_shift hubp_shift = { 493 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 494 }; 495 496 static const struct dcn_hubp2_mask hubp_mask = { 497 HUBP_MASK_SH_LIST_DCN32(_MASK) 498 }; 499 500 static struct dcn_hubbub_registers hubbub_reg; 501 #define hubbub_reg_init()\ 502 HUBBUB_REG_LIST_DCN32_RI(0) 503 504 static const struct dcn_hubbub_shift hubbub_shift = { 505 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 506 }; 507 508 static const struct dcn_hubbub_mask hubbub_mask = { 509 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 510 }; 511 512 static struct dccg_registers dccg_regs; 513 514 #define dccg_regs_init()\ 515 DCCG_REG_LIST_DCN32_RI() 516 517 static const struct dccg_shift dccg_shift = { 518 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 519 }; 520 521 static const struct dccg_mask dccg_mask = { 522 DCCG_MASK_SH_LIST_DCN32(_MASK) 523 }; 524 525 526 #define SRII2(reg_name_pre, reg_name_post, id)\ 527 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 528 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 529 reg ## reg_name_pre ## id ## _ ## reg_name_post 530 531 532 #define HWSEQ_DCN32_REG_LIST()\ 533 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 534 SR(DIO_MEM_PWR_CTRL), \ 535 SR(ODM_MEM_PWR_CTRL3), \ 536 SR(MMHUBBUB_MEM_PWR_CNTL), \ 537 SR(DCCG_GATE_DISABLE_CNTL), \ 538 SR(DCCG_GATE_DISABLE_CNTL2), \ 539 SR(DCFCLK_CNTL),\ 540 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 541 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 542 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 543 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 544 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 545 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 546 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 547 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 548 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 549 SR(MICROSECOND_TIME_BASE_DIV), \ 550 SR(MILLISECOND_TIME_BASE_DIV), \ 551 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 552 SR(RBBMIF_TIMEOUT_DIS), \ 553 SR(RBBMIF_TIMEOUT_DIS_2), \ 554 SR(DCHUBBUB_CRC_CTRL), \ 555 SR(DPP_TOP0_DPP_CRC_CTRL), \ 556 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 557 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 558 SR(MPC_CRC_CTRL), \ 559 SR(MPC_CRC_RESULT_GB), \ 560 SR(MPC_CRC_RESULT_C), \ 561 SR(MPC_CRC_RESULT_AR), \ 562 SR(DOMAIN0_PG_CONFIG), \ 563 SR(DOMAIN1_PG_CONFIG), \ 564 SR(DOMAIN2_PG_CONFIG), \ 565 SR(DOMAIN3_PG_CONFIG), \ 566 SR(DOMAIN16_PG_CONFIG), \ 567 SR(DOMAIN17_PG_CONFIG), \ 568 SR(DOMAIN18_PG_CONFIG), \ 569 SR(DOMAIN19_PG_CONFIG), \ 570 SR(DOMAIN0_PG_STATUS), \ 571 SR(DOMAIN1_PG_STATUS), \ 572 SR(DOMAIN2_PG_STATUS), \ 573 SR(DOMAIN3_PG_STATUS), \ 574 SR(DOMAIN16_PG_STATUS), \ 575 SR(DOMAIN17_PG_STATUS), \ 576 SR(DOMAIN18_PG_STATUS), \ 577 SR(DOMAIN19_PG_STATUS), \ 578 SR(D1VGA_CONTROL), \ 579 SR(D2VGA_CONTROL), \ 580 SR(D3VGA_CONTROL), \ 581 SR(D4VGA_CONTROL), \ 582 SR(D5VGA_CONTROL), \ 583 SR(D6VGA_CONTROL), \ 584 SR(DC_IP_REQUEST_CNTL), \ 585 SR(AZALIA_AUDIO_DTO), \ 586 SR(AZALIA_CONTROLLER_CLOCK_GATING) 587 588 static struct dce_hwseq_registers hwseq_reg; 589 590 #define hwseq_reg_init()\ 591 HWSEQ_DCN32_REG_LIST() 592 593 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 594 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 595 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 596 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 597 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 598 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 599 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 600 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 601 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 602 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 603 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 604 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 605 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 606 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 607 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 608 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 609 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 610 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 611 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 612 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 613 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 614 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 615 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 616 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 617 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 618 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 619 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 620 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 621 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 622 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 623 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 624 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 625 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 626 627 static const struct dce_hwseq_shift hwseq_shift = { 628 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 629 }; 630 631 static const struct dce_hwseq_mask hwseq_mask = { 632 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 633 }; 634 #define vmid_regs_init(id)\ 635 DCN20_VMID_REG_LIST_RI(id) 636 637 static struct dcn_vmid_registers vmid_regs[16]; 638 639 static const struct dcn20_vmid_shift vmid_shifts = { 640 DCN20_VMID_MASK_SH_LIST(__SHIFT) 641 }; 642 643 static const struct dcn20_vmid_mask vmid_masks = { 644 DCN20_VMID_MASK_SH_LIST(_MASK) 645 }; 646 647 static struct dcn_dio_registers dio_regs; 648 649 #define DIO_MASK_SH_LIST(mask_sh)\ 650 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 651 652 static const struct dcn_dio_shift dio_shift = { 653 DIO_MASK_SH_LIST(__SHIFT) 654 }; 655 656 static const struct dcn_dio_mask dio_mask = { 657 DIO_MASK_SH_LIST(_MASK) 658 }; 659 660 static const struct resource_caps res_cap_dcn32 = { 661 .num_timing_generator = 4, 662 .num_opp = 4, 663 .num_video_plane = 4, 664 .num_audio = 5, 665 .num_stream_encoder = 5, 666 .num_hpo_dp_stream_encoder = 4, 667 .num_hpo_dp_link_encoder = 2, 668 .num_pll = 5, 669 .num_dwb = 1, 670 .num_ddc = 5, 671 .num_vmid = 16, 672 .num_mpc_3dlut = 4, 673 .num_dsc = 4, 674 }; 675 676 static const struct dc_plane_cap plane_cap = { 677 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 678 .per_pixel_alpha = true, 679 680 .pixel_format_support = { 681 .argb8888 = true, 682 .nv12 = true, 683 .fp16 = true, 684 .p010 = true, 685 .ayuv = false, 686 }, 687 688 .max_upscale_factor = { 689 .argb8888 = 16000, 690 .nv12 = 16000, 691 .fp16 = 16000 692 }, 693 694 // 6:1 downscaling ratio: 1000/6 = 166.666 695 .max_downscale_factor = { 696 .argb8888 = 167, 697 .nv12 = 167, 698 .fp16 = 167 699 }, 700 64, 701 64 702 }; 703 704 static const struct dc_debug_options debug_defaults_drv = { 705 .disable_dmcu = true, 706 .force_abm_enable = false, 707 .clock_trace = true, 708 .disable_pplib_clock_request = false, 709 .pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore 710 .force_single_disp_pipe_split = false, 711 .disable_dcc = DCC_ENABLE, 712 .vsr_support = true, 713 .performance_trace = false, 714 .max_downscale_src_width = 7680,/*upto 8K*/ 715 .disable_pplib_wm_range = false, 716 .scl_reset_length10 = true, 717 .sanity_checks = false, 718 .underflow_assert_delay_us = 0xFFFFFFFF, 719 .dwb_fi_phase = -1, // -1 = disable, 720 .dmub_command_table = true, 721 .enable_mem_low_power = { 722 .bits = { 723 .vga = false, 724 .i2c = false, 725 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 726 .dscl = false, 727 .cm = false, 728 .mpc = false, 729 .optc = true, 730 } 731 }, 732 .use_max_lb = true, 733 .force_disable_subvp = false, 734 .exit_idle_opt_for_cursor_updates = true, 735 .using_dml2 = false, 736 .using_dml21 = false, // TODO : Temporary for N-1 validation. Remove after N-1 is done. 737 .enable_single_display_2to1_odm_policy = true, 738 739 /* Must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/ 740 .enable_double_buffered_dsc_pg_support = true, 741 .enable_dp_dig_pixel_rate_div_policy = 1, 742 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback" 743 .alloc_extra_way_for_cursor = true, 744 .min_prefetch_in_strobe_ns = 60000, // 60us 745 .disable_unbounded_requesting = false, 746 .override_dispclk_programming = true, 747 .disable_fpo_optimizations = false, 748 .fpo_vactive_margin_us = 2000, // 2000us 749 .disable_fpo_vactive = false, 750 .disable_boot_optimizations = false, 751 .disable_subvp_high_refresh = false, 752 .disable_dp_plus_plus_wa = true, 753 .fpo_vactive_min_active_margin_us = 200, 754 .fpo_vactive_max_blank_us = 1000, 755 .disable_stutter_for_wm_program = true 756 }; 757 758 static const struct dc_check_config config_defaults = { 759 .enable_legacy_fast_update = false, 760 }; 761 762 static struct dce_aux *dcn32_aux_engine_create( 763 struct dc_context *ctx, 764 uint32_t inst) 765 { 766 struct aux_engine_dce110 *aux_engine = 767 kzalloc_obj(struct aux_engine_dce110); 768 769 if (!aux_engine) 770 return NULL; 771 772 #undef REG_STRUCT 773 #define REG_STRUCT aux_engine_regs 774 aux_engine_regs_init(0), 775 aux_engine_regs_init(1), 776 aux_engine_regs_init(2), 777 aux_engine_regs_init(3), 778 aux_engine_regs_init(4); 779 780 dce110_aux_engine_construct(aux_engine, ctx, inst, 781 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 782 &aux_engine_regs[inst], 783 &aux_mask, 784 &aux_shift, 785 ctx->dc->caps.extended_aux_timeout_support); 786 787 return &aux_engine->base; 788 } 789 #define i2c_inst_regs_init(id)\ 790 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 791 792 static struct dce_i2c_registers i2c_hw_regs[5]; 793 794 static const struct dce_i2c_shift i2c_shifts = { 795 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 796 }; 797 798 static const struct dce_i2c_mask i2c_masks = { 799 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 800 }; 801 802 static struct dce_i2c_hw *dcn32_i2c_hw_create( 803 struct dc_context *ctx, 804 uint32_t inst) 805 { 806 struct dce_i2c_hw *dce_i2c_hw = 807 kzalloc_obj(struct dce_i2c_hw); 808 809 if (!dce_i2c_hw) 810 return NULL; 811 812 #undef REG_STRUCT 813 #define REG_STRUCT i2c_hw_regs 814 i2c_inst_regs_init(1), 815 i2c_inst_regs_init(2), 816 i2c_inst_regs_init(3), 817 i2c_inst_regs_init(4), 818 i2c_inst_regs_init(5); 819 820 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 821 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 822 823 return dce_i2c_hw; 824 } 825 826 static struct clock_source *dcn32_clock_source_create( 827 struct dc_context *ctx, 828 struct dc_bios *bios, 829 enum clock_source_id id, 830 const struct dce110_clk_src_regs *regs, 831 bool dp_clk_src) 832 { 833 struct dce110_clk_src *clk_src = 834 kzalloc_obj(struct dce110_clk_src); 835 836 if (!clk_src) 837 return NULL; 838 839 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 840 regs, &cs_shift, &cs_mask)) { 841 clk_src->base.dp_clk_src = dp_clk_src; 842 return &clk_src->base; 843 } 844 845 kfree(clk_src); 846 BREAK_TO_DEBUGGER(); 847 return NULL; 848 } 849 850 static struct dio *dcn32_dio_create(struct dc_context *ctx) 851 { 852 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 853 854 if (!dio10) 855 return NULL; 856 857 #undef REG_STRUCT 858 #define REG_STRUCT dio_regs 859 DIO_REG_LIST_DCN10(); 860 861 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 862 863 return &dio10->base; 864 } 865 866 static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx) 867 { 868 int i; 869 870 struct dcn20_hubbub *hubbub2 = kzalloc_obj(struct dcn20_hubbub); 871 872 if (!hubbub2) 873 return NULL; 874 875 #undef REG_STRUCT 876 #define REG_STRUCT hubbub_reg 877 hubbub_reg_init(); 878 879 #undef REG_STRUCT 880 #define REG_STRUCT vmid_regs 881 vmid_regs_init(0), 882 vmid_regs_init(1), 883 vmid_regs_init(2), 884 vmid_regs_init(3), 885 vmid_regs_init(4), 886 vmid_regs_init(5), 887 vmid_regs_init(6), 888 vmid_regs_init(7), 889 vmid_regs_init(8), 890 vmid_regs_init(9), 891 vmid_regs_init(10), 892 vmid_regs_init(11), 893 vmid_regs_init(12), 894 vmid_regs_init(13), 895 vmid_regs_init(14), 896 vmid_regs_init(15); 897 898 hubbub32_construct(hubbub2, ctx, 899 &hubbub_reg, 900 &hubbub_shift, 901 &hubbub_mask, 902 ctx->dc->dml.ip.det_buffer_size_kbytes, 903 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 904 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 905 906 907 for (i = 0; i < res_cap_dcn32.num_vmid; i++) { 908 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 909 910 vmid->ctx = ctx; 911 912 vmid->regs = &vmid_regs[i]; 913 vmid->shifts = &vmid_shifts; 914 vmid->masks = &vmid_masks; 915 } 916 917 return &hubbub2->base; 918 } 919 920 static struct hubp *dcn32_hubp_create( 921 struct dc_context *ctx, 922 uint32_t inst) 923 { 924 struct dcn20_hubp *hubp2 = 925 kzalloc_obj(struct dcn20_hubp); 926 927 if (!hubp2) 928 return NULL; 929 930 #undef REG_STRUCT 931 #define REG_STRUCT hubp_regs 932 hubp_regs_init(0), 933 hubp_regs_init(1), 934 hubp_regs_init(2), 935 hubp_regs_init(3); 936 937 if (hubp32_construct(hubp2, ctx, inst, 938 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 939 return &hubp2->base; 940 941 BREAK_TO_DEBUGGER(); 942 kfree(hubp2); 943 return NULL; 944 } 945 946 static void dcn32_dpp_destroy(struct dpp **dpp) 947 { 948 kfree(TO_DCN30_DPP(*dpp)); 949 *dpp = NULL; 950 } 951 952 static struct dpp *dcn32_dpp_create( 953 struct dc_context *ctx, 954 uint32_t inst) 955 { 956 struct dcn3_dpp *dpp3 = 957 kzalloc_obj(struct dcn3_dpp); 958 959 if (!dpp3) 960 return NULL; 961 962 #undef REG_STRUCT 963 #define REG_STRUCT dpp_regs 964 dpp_regs_init(0), 965 dpp_regs_init(1), 966 dpp_regs_init(2), 967 dpp_regs_init(3); 968 969 if (dpp32_construct(dpp3, ctx, inst, 970 &dpp_regs[inst], &tf_shift, &tf_mask)) 971 return &dpp3->base; 972 973 BREAK_TO_DEBUGGER(); 974 kfree(dpp3); 975 return NULL; 976 } 977 978 static struct mpc *dcn32_mpc_create( 979 struct dc_context *ctx, 980 int num_mpcc, 981 int num_rmu) 982 { 983 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc); 984 985 if (!mpc30) 986 return NULL; 987 988 #undef REG_STRUCT 989 #define REG_STRUCT mpc_regs 990 dcn_mpc_regs_init(); 991 992 dcn32_mpc_construct(mpc30, ctx, 993 &mpc_regs, 994 &mpc_shift, 995 &mpc_mask, 996 num_mpcc, 997 num_rmu); 998 999 return &mpc30->base; 1000 } 1001 1002 static struct output_pixel_processor *dcn32_opp_create( 1003 struct dc_context *ctx, uint32_t inst) 1004 { 1005 struct dcn20_opp *opp2 = 1006 kzalloc_obj(struct dcn20_opp); 1007 1008 if (!opp2) { 1009 BREAK_TO_DEBUGGER(); 1010 return NULL; 1011 } 1012 1013 #undef REG_STRUCT 1014 #define REG_STRUCT opp_regs 1015 opp_regs_init(0), 1016 opp_regs_init(1), 1017 opp_regs_init(2), 1018 opp_regs_init(3); 1019 1020 dcn20_opp_construct(opp2, ctx, inst, 1021 &opp_regs[inst], &opp_shift, &opp_mask); 1022 return &opp2->base; 1023 } 1024 1025 1026 static struct timing_generator *dcn32_timing_generator_create( 1027 struct dc_context *ctx, 1028 uint32_t instance) 1029 { 1030 struct optc *tgn10 = 1031 kzalloc_obj(struct optc); 1032 1033 if (!tgn10) 1034 return NULL; 1035 1036 #undef REG_STRUCT 1037 #define REG_STRUCT optc_regs 1038 optc_regs_init(0), 1039 optc_regs_init(1), 1040 optc_regs_init(2), 1041 optc_regs_init(3); 1042 1043 tgn10->base.inst = instance; 1044 tgn10->base.ctx = ctx; 1045 1046 tgn10->tg_regs = &optc_regs[instance]; 1047 tgn10->tg_shift = &optc_shift; 1048 tgn10->tg_mask = &optc_mask; 1049 1050 dcn32_timing_generator_init(tgn10); 1051 1052 return &tgn10->base; 1053 } 1054 1055 static const struct encoder_feature_support link_enc_feature = { 1056 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1057 .max_hdmi_pixel_clock = 600000, 1058 .hdmi_ycbcr420_supported = true, 1059 .dp_ycbcr420_supported = true, 1060 .fec_supported = true, 1061 .flags.bits.IS_HBR2_CAPABLE = true, 1062 .flags.bits.IS_HBR3_CAPABLE = true, 1063 .flags.bits.IS_TPS3_CAPABLE = true, 1064 .flags.bits.IS_TPS4_CAPABLE = true 1065 }; 1066 1067 static struct link_encoder *dcn32_link_encoder_create( 1068 struct dc_context *ctx, 1069 const struct encoder_init_data *enc_init_data) 1070 { 1071 struct dcn20_link_encoder *enc20 = 1072 kzalloc_obj(struct dcn20_link_encoder); 1073 1074 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 1075 return NULL; 1076 1077 #undef REG_STRUCT 1078 #define REG_STRUCT link_enc_aux_regs 1079 aux_regs_init(0), 1080 aux_regs_init(1), 1081 aux_regs_init(2), 1082 aux_regs_init(3), 1083 aux_regs_init(4); 1084 1085 #undef REG_STRUCT 1086 #define REG_STRUCT link_enc_hpd_regs 1087 hpd_regs_init(0), 1088 hpd_regs_init(1), 1089 hpd_regs_init(2), 1090 hpd_regs_init(3), 1091 hpd_regs_init(4); 1092 1093 #undef REG_STRUCT 1094 #define REG_STRUCT link_enc_regs 1095 link_regs_init(0, A), 1096 link_regs_init(1, B), 1097 link_regs_init(2, C), 1098 link_regs_init(3, D), 1099 link_regs_init(4, E); 1100 1101 dcn32_link_encoder_construct(enc20, 1102 enc_init_data, 1103 &link_enc_feature, 1104 &link_enc_regs[enc_init_data->transmitter], 1105 &link_enc_aux_regs[enc_init_data->channel - 1], 1106 &link_enc_hpd_regs[enc_init_data->hpd_source], 1107 &le_shift, 1108 &le_mask); 1109 1110 return &enc20->enc10.base; 1111 } 1112 1113 struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1114 { 1115 struct dcn31_panel_cntl *panel_cntl = 1116 kzalloc_obj(struct dcn31_panel_cntl); 1117 1118 if (!panel_cntl) 1119 return NULL; 1120 1121 dcn31_panel_cntl_construct(panel_cntl, init_data); 1122 1123 return &panel_cntl->base; 1124 } 1125 1126 static void read_dce_straps( 1127 struct dc_context *ctx, 1128 struct resource_straps *straps) 1129 { 1130 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, 1131 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1132 1133 } 1134 1135 static struct audio *dcn32_create_audio( 1136 struct dc_context *ctx, unsigned int inst) 1137 { 1138 1139 #undef REG_STRUCT 1140 #define REG_STRUCT audio_regs 1141 audio_regs_init(0), 1142 audio_regs_init(1), 1143 audio_regs_init(2), 1144 audio_regs_init(3), 1145 audio_regs_init(4); 1146 1147 return dce_audio_create(ctx, inst, 1148 &audio_regs[inst], &audio_shift, &audio_mask); 1149 } 1150 1151 static struct vpg *dcn32_vpg_create( 1152 struct dc_context *ctx, 1153 uint32_t inst) 1154 { 1155 struct dcn30_vpg *vpg3 = kzalloc_obj(struct dcn30_vpg); 1156 1157 if (!vpg3) 1158 return NULL; 1159 1160 #undef REG_STRUCT 1161 #define REG_STRUCT vpg_regs 1162 vpg_regs_init(0), 1163 vpg_regs_init(1), 1164 vpg_regs_init(2), 1165 vpg_regs_init(3), 1166 vpg_regs_init(4), 1167 vpg_regs_init(5), 1168 vpg_regs_init(6), 1169 vpg_regs_init(7), 1170 vpg_regs_init(8), 1171 vpg_regs_init(9); 1172 1173 vpg3_construct(vpg3, ctx, inst, 1174 &vpg_regs[inst], 1175 &vpg_shift, 1176 &vpg_mask); 1177 1178 return &vpg3->base; 1179 } 1180 1181 static struct afmt *dcn32_afmt_create( 1182 struct dc_context *ctx, 1183 uint32_t inst) 1184 { 1185 struct dcn30_afmt *afmt3 = kzalloc_obj(struct dcn30_afmt); 1186 1187 if (!afmt3) 1188 return NULL; 1189 1190 #undef REG_STRUCT 1191 #define REG_STRUCT afmt_regs 1192 afmt_regs_init(0), 1193 afmt_regs_init(1), 1194 afmt_regs_init(2), 1195 afmt_regs_init(3), 1196 afmt_regs_init(4), 1197 afmt_regs_init(5); 1198 1199 afmt3_construct(afmt3, ctx, inst, 1200 &afmt_regs[inst], 1201 &afmt_shift, 1202 &afmt_mask); 1203 1204 return &afmt3->base; 1205 } 1206 1207 static struct apg *dcn31_apg_create( 1208 struct dc_context *ctx, 1209 uint32_t inst) 1210 { 1211 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg); 1212 1213 if (!apg31) 1214 return NULL; 1215 1216 #undef REG_STRUCT 1217 #define REG_STRUCT apg_regs 1218 apg_regs_init(0), 1219 apg_regs_init(1), 1220 apg_regs_init(2), 1221 apg_regs_init(3); 1222 1223 apg31_construct(apg31, ctx, inst, 1224 &apg_regs[inst], 1225 &apg_shift, 1226 &apg_mask); 1227 1228 return &apg31->base; 1229 } 1230 1231 static struct stream_encoder *dcn32_stream_encoder_create( 1232 enum engine_id eng_id, 1233 struct dc_context *ctx) 1234 { 1235 struct dcn10_stream_encoder *enc1; 1236 struct vpg *vpg; 1237 struct afmt *afmt; 1238 int vpg_inst; 1239 int afmt_inst; 1240 1241 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1242 if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs)) 1243 return NULL; 1244 1245 vpg_inst = eng_id; 1246 afmt_inst = eng_id; 1247 1248 enc1 = kzalloc_obj(struct dcn10_stream_encoder); 1249 vpg = dcn32_vpg_create(ctx, vpg_inst); 1250 afmt = dcn32_afmt_create(ctx, afmt_inst); 1251 1252 if (!enc1 || !vpg || !afmt) { 1253 kfree(enc1); 1254 kfree(vpg); 1255 kfree(afmt); 1256 return NULL; 1257 } 1258 1259 #undef REG_STRUCT 1260 #define REG_STRUCT stream_enc_regs 1261 stream_enc_regs_init(0), 1262 stream_enc_regs_init(1), 1263 stream_enc_regs_init(2), 1264 stream_enc_regs_init(3), 1265 stream_enc_regs_init(4); 1266 1267 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1268 eng_id, vpg, afmt, 1269 &stream_enc_regs[eng_id], 1270 &se_shift, &se_mask); 1271 1272 return &enc1->base; 1273 } 1274 1275 static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create( 1276 enum engine_id eng_id, 1277 struct dc_context *ctx) 1278 { 1279 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1280 struct vpg *vpg; 1281 struct apg *apg; 1282 uint32_t hpo_dp_inst; 1283 uint32_t vpg_inst; 1284 uint32_t apg_inst; 1285 1286 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1287 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1288 1289 /* Mapping of VPG register blocks to HPO DP block instance: 1290 * VPG[6] -> HPO_DP[0] 1291 * VPG[7] -> HPO_DP[1] 1292 * VPG[8] -> HPO_DP[2] 1293 * VPG[9] -> HPO_DP[3] 1294 */ 1295 vpg_inst = hpo_dp_inst + 6; 1296 1297 /* Mapping of APG register blocks to HPO DP block instance: 1298 * APG[0] -> HPO_DP[0] 1299 * APG[1] -> HPO_DP[1] 1300 * APG[2] -> HPO_DP[2] 1301 * APG[3] -> HPO_DP[3] 1302 */ 1303 apg_inst = hpo_dp_inst; 1304 1305 /* allocate HPO stream encoder and create VPG sub-block */ 1306 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder); 1307 vpg = dcn32_vpg_create(ctx, vpg_inst); 1308 apg = dcn31_apg_create(ctx, apg_inst); 1309 1310 if (!hpo_dp_enc31 || !vpg || !apg) { 1311 kfree(hpo_dp_enc31); 1312 kfree(vpg); 1313 kfree(apg); 1314 return NULL; 1315 } 1316 1317 #undef REG_STRUCT 1318 #define REG_STRUCT hpo_dp_stream_enc_regs 1319 hpo_dp_stream_encoder_reg_init(0), 1320 hpo_dp_stream_encoder_reg_init(1), 1321 hpo_dp_stream_encoder_reg_init(2), 1322 hpo_dp_stream_encoder_reg_init(3); 1323 1324 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1325 hpo_dp_inst, eng_id, vpg, apg, 1326 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1327 &hpo_dp_se_shift, &hpo_dp_se_mask); 1328 1329 return &hpo_dp_enc31->base; 1330 } 1331 1332 static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create( 1333 uint8_t inst, 1334 struct dc_context *ctx) 1335 { 1336 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1337 1338 /* allocate HPO link encoder */ 1339 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder); 1340 if (!hpo_dp_enc31) 1341 return NULL; /* out of memory */ 1342 1343 #undef REG_STRUCT 1344 #define REG_STRUCT hpo_dp_link_enc_regs 1345 hpo_dp_link_encoder_reg_init(0), 1346 hpo_dp_link_encoder_reg_init(1); 1347 1348 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1349 &hpo_dp_link_enc_regs[inst], 1350 &hpo_dp_le_shift, &hpo_dp_le_mask); 1351 1352 return &hpo_dp_enc31->base; 1353 } 1354 1355 static struct dce_hwseq *dcn32_hwseq_create( 1356 struct dc_context *ctx) 1357 { 1358 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq); 1359 1360 #undef REG_STRUCT 1361 #define REG_STRUCT hwseq_reg 1362 hwseq_reg_init(); 1363 1364 if (hws) { 1365 hws->ctx = ctx; 1366 hws->regs = &hwseq_reg; 1367 hws->shifts = &hwseq_shift; 1368 hws->masks = &hwseq_mask; 1369 } 1370 return hws; 1371 } 1372 static const struct resource_create_funcs res_create_funcs = { 1373 .read_dce_straps = read_dce_straps, 1374 .create_audio = dcn32_create_audio, 1375 .create_stream_encoder = dcn32_stream_encoder_create, 1376 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, 1377 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, 1378 .create_hwseq = dcn32_hwseq_create, 1379 }; 1380 1381 static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) 1382 { 1383 unsigned int i; 1384 1385 for (i = 0; i < pool->base.stream_enc_count; i++) { 1386 if (pool->base.stream_enc[i] != NULL) { 1387 if (pool->base.stream_enc[i]->vpg != NULL) { 1388 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1389 pool->base.stream_enc[i]->vpg = NULL; 1390 } 1391 if (pool->base.stream_enc[i]->afmt != NULL) { 1392 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1393 pool->base.stream_enc[i]->afmt = NULL; 1394 } 1395 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1396 pool->base.stream_enc[i] = NULL; 1397 } 1398 } 1399 1400 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1401 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1402 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1403 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1404 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1405 } 1406 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1407 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1408 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1409 } 1410 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1411 pool->base.hpo_dp_stream_enc[i] = NULL; 1412 } 1413 } 1414 1415 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1416 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1417 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1418 pool->base.hpo_dp_link_enc[i] = NULL; 1419 } 1420 } 1421 1422 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1423 if (pool->base.dscs[i] != NULL) 1424 dcn20_dsc_destroy(&pool->base.dscs[i]); 1425 } 1426 1427 if (pool->base.mpc != NULL) { 1428 kfree(TO_DCN20_MPC(pool->base.mpc)); 1429 pool->base.mpc = NULL; 1430 } 1431 if (pool->base.hubbub != NULL) { 1432 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1433 pool->base.hubbub = NULL; 1434 } 1435 for (i = 0; i < pool->base.pipe_count; i++) { 1436 if (pool->base.dpps[i] != NULL) 1437 dcn32_dpp_destroy(&pool->base.dpps[i]); 1438 1439 if (pool->base.ipps[i] != NULL) 1440 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1441 1442 if (pool->base.hubps[i] != NULL) { 1443 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1444 pool->base.hubps[i] = NULL; 1445 } 1446 1447 if (pool->base.irqs != NULL) { 1448 dal_irq_service_destroy(&pool->base.irqs); 1449 } 1450 } 1451 1452 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1453 if (pool->base.engines[i] != NULL) 1454 dce110_engine_destroy(&pool->base.engines[i]); 1455 if (pool->base.hw_i2cs[i] != NULL) { 1456 kfree(pool->base.hw_i2cs[i]); 1457 pool->base.hw_i2cs[i] = NULL; 1458 } 1459 if (pool->base.sw_i2cs[i] != NULL) { 1460 kfree(pool->base.sw_i2cs[i]); 1461 pool->base.sw_i2cs[i] = NULL; 1462 } 1463 } 1464 1465 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1466 if (pool->base.opps[i] != NULL) 1467 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1468 } 1469 1470 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1471 if (pool->base.timing_generators[i] != NULL) { 1472 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1473 pool->base.timing_generators[i] = NULL; 1474 } 1475 } 1476 1477 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1478 if (pool->base.dwbc[i] != NULL) { 1479 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1480 pool->base.dwbc[i] = NULL; 1481 } 1482 if (pool->base.mcif_wb[i] != NULL) { 1483 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1484 pool->base.mcif_wb[i] = NULL; 1485 } 1486 } 1487 1488 for (i = 0; i < pool->base.audio_count; i++) { 1489 if (pool->base.audios[i]) 1490 dce_aud_destroy(&pool->base.audios[i]); 1491 } 1492 1493 for (i = 0; i < pool->base.clk_src_count; i++) { 1494 if (pool->base.clock_sources[i] != NULL) { 1495 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1496 pool->base.clock_sources[i] = NULL; 1497 } 1498 } 1499 1500 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1501 if (pool->base.mpc_lut[i] != NULL) { 1502 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1503 pool->base.mpc_lut[i] = NULL; 1504 } 1505 if (pool->base.mpc_shaper[i] != NULL) { 1506 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1507 pool->base.mpc_shaper[i] = NULL; 1508 } 1509 } 1510 1511 if (pool->base.dp_clock_source != NULL) { 1512 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1513 pool->base.dp_clock_source = NULL; 1514 } 1515 1516 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1517 if (pool->base.multiple_abms[i] != NULL) 1518 dce_abm_destroy(&pool->base.multiple_abms[i]); 1519 } 1520 1521 if (pool->base.psr != NULL) 1522 dmub_psr_destroy(&pool->base.psr); 1523 1524 if (pool->base.dccg != NULL) 1525 dcn_dccg_destroy(&pool->base.dccg); 1526 1527 if (pool->base.dio != NULL) { 1528 kfree(TO_DCN10_DIO(pool->base.dio)); 1529 pool->base.dio = NULL; 1530 } 1531 1532 if (pool->base.oem_device != NULL) { 1533 struct dc *dc = pool->base.oem_device->ctx->dc; 1534 1535 dc->link_srv->destroy_ddc_service(&pool->base.oem_device); 1536 } 1537 } 1538 1539 1540 static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1541 { 1542 int i; 1543 uint32_t dwb_count = pool->res_cap->num_dwb; 1544 1545 for (i = 0; i < dwb_count; i++) { 1546 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc); 1547 1548 if (!dwbc30) { 1549 dm_error("DC: failed to create dwbc30!\n"); 1550 return false; 1551 } 1552 1553 #undef REG_STRUCT 1554 #define REG_STRUCT dwbc30_regs 1555 dwbc_regs_dcn3_init(0); 1556 1557 dcn30_dwbc_construct(dwbc30, ctx, 1558 &dwbc30_regs[i], 1559 &dwbc30_shift, 1560 &dwbc30_mask, 1561 i); 1562 1563 pool->dwbc[i] = &dwbc30->base; 1564 } 1565 return true; 1566 } 1567 1568 static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1569 { 1570 int i; 1571 uint32_t dwb_count = pool->res_cap->num_dwb; 1572 1573 for (i = 0; i < dwb_count; i++) { 1574 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub); 1575 1576 if (!mcif_wb30) { 1577 dm_error("DC: failed to create mcif_wb30!\n"); 1578 return false; 1579 } 1580 1581 #undef REG_STRUCT 1582 #define REG_STRUCT mcif_wb30_regs 1583 mcif_wb_regs_dcn3_init(0); 1584 1585 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1586 &mcif_wb30_regs[i], 1587 &mcif_wb30_shift, 1588 &mcif_wb30_mask, 1589 i); 1590 1591 pool->mcif_wb[i] = &mcif_wb30->base; 1592 } 1593 return true; 1594 } 1595 1596 static struct display_stream_compressor *dcn32_dsc_create( 1597 struct dc_context *ctx, uint32_t inst) 1598 { 1599 struct dcn20_dsc *dsc = 1600 kzalloc_obj(struct dcn20_dsc); 1601 1602 if (!dsc) { 1603 BREAK_TO_DEBUGGER(); 1604 return NULL; 1605 } 1606 1607 #undef REG_STRUCT 1608 #define REG_STRUCT dsc_regs 1609 dsc_regsDCN20_init(0), 1610 dsc_regsDCN20_init(1), 1611 dsc_regsDCN20_init(2), 1612 dsc_regsDCN20_init(3); 1613 1614 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1615 1616 dsc->max_image_width = 6016; 1617 1618 return &dsc->base; 1619 } 1620 1621 static void dcn32_destroy_resource_pool(struct resource_pool **pool) 1622 { 1623 struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool); 1624 1625 dcn32_resource_destruct(dcn32_pool); 1626 kfree(dcn32_pool); 1627 *pool = NULL; 1628 } 1629 1630 bool dcn32_acquire_post_bldn_3dlut( 1631 struct resource_context *res_ctx, 1632 const struct resource_pool *pool, 1633 int mpcc_id, 1634 struct dc_3dlut **lut, 1635 struct dc_transfer_func **shaper) 1636 { 1637 bool ret = false; 1638 1639 ASSERT(*lut == NULL && *shaper == NULL); 1640 *lut = NULL; 1641 *shaper = NULL; 1642 1643 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { 1644 *lut = pool->mpc_lut[mpcc_id]; 1645 *shaper = pool->mpc_shaper[mpcc_id]; 1646 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; 1647 ret = true; 1648 } 1649 return ret; 1650 } 1651 1652 bool dcn32_release_post_bldn_3dlut( 1653 struct resource_context *res_ctx, 1654 const struct resource_pool *pool, 1655 struct dc_3dlut **lut, 1656 struct dc_transfer_func **shaper) 1657 { 1658 int i; 1659 bool ret = false; 1660 1661 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1662 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) { 1663 res_ctx->is_mpc_3dlut_acquired[i] = false; 1664 pool->mpc_lut[i]->state.raw = 0; 1665 *lut = NULL; 1666 *shaper = NULL; 1667 ret = true; 1668 break; 1669 } 1670 } 1671 return ret; 1672 } 1673 1674 static void dcn32_enable_phantom_plane(struct dc *dc, 1675 struct dc_state *context, 1676 struct dc_stream_state *phantom_stream, 1677 unsigned int dc_pipe_idx) 1678 { 1679 struct dc_plane_state *phantom_plane = NULL; 1680 struct dc_plane_state *prev_phantom_plane = NULL; 1681 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1682 1683 while (curr_pipe) { 1684 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state) 1685 phantom_plane = prev_phantom_plane; 1686 else 1687 phantom_plane = dc_state_create_phantom_plane(dc, context, curr_pipe->plane_state); 1688 1689 if (!phantom_plane) 1690 continue; 1691 1692 memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address)); 1693 memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality, 1694 sizeof(phantom_plane->scaling_quality)); 1695 memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect)); 1696 memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect)); 1697 memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect)); 1698 memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size, 1699 sizeof(phantom_plane->plane_size)); 1700 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info, 1701 sizeof(phantom_plane->tiling_info)); 1702 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc)); 1703 phantom_plane->format = curr_pipe->plane_state->format; 1704 phantom_plane->rotation = curr_pipe->plane_state->rotation; 1705 phantom_plane->visible = curr_pipe->plane_state->visible; 1706 1707 /* Shadow pipe has small viewport. */ 1708 phantom_plane->clip_rect.y = 0; 1709 phantom_plane->clip_rect.height = phantom_stream->src.height; 1710 1711 dc_state_add_phantom_plane(dc, phantom_stream, phantom_plane, context); 1712 1713 curr_pipe = curr_pipe->bottom_pipe; 1714 prev_phantom_plane = phantom_plane; 1715 } 1716 } 1717 1718 static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc, 1719 struct dc_state *context, 1720 display_e2e_pipe_params_st *pipes, 1721 unsigned int pipe_cnt, 1722 unsigned int dc_pipe_idx) 1723 { 1724 struct dc_stream_state *phantom_stream = NULL; 1725 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1726 1727 phantom_stream = dc_state_create_phantom_stream(dc, context, ref_pipe->stream); 1728 if (!phantom_stream) 1729 return phantom_stream; 1730 1731 /* stream has limited viewport and small timing */ 1732 memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing)); 1733 memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src)); 1734 memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst)); 1735 DC_FP_START(); 1736 dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx); 1737 DC_FP_END(); 1738 1739 dc_state_add_phantom_stream(dc, context, phantom_stream, ref_pipe->stream); 1740 return phantom_stream; 1741 } 1742 1743 /* TODO: Input to this function should indicate which pipe indexes (or streams) 1744 * require a phantom pipe / stream 1745 */ 1746 void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context, 1747 display_e2e_pipe_params_st *pipes, 1748 unsigned int pipe_cnt, 1749 unsigned int index) 1750 { 1751 struct dc_stream_state *phantom_stream = NULL; 1752 unsigned int i; 1753 1754 // The index of the DC pipe passed into this function is guarenteed to 1755 // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't 1756 // already have phantom pipe assigned, etc.) by previous checks. 1757 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index); 1758 if (!phantom_stream) 1759 return; 1760 1761 dcn32_enable_phantom_plane(dc, context, phantom_stream, index); 1762 1763 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1764 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1765 1766 // Build scaling params for phantom pipes which were newly added. 1767 // We determine which phantom pipes were added by comparing with 1768 // the phantom stream. 1769 if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream && 1770 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) { 1771 pipe->stream->use_dynamic_meta = false; 1772 pipe->plane_state->flip_immediate = false; 1773 if (!resource_build_scaling_params(pipe)) { 1774 // Log / remove phantom pipes since failed to build scaling params 1775 } 1776 } 1777 } 1778 } 1779 1780 static bool dml1_validate(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode) 1781 { 1782 bool out = false; 1783 1784 BW_VAL_TRACE_SETUP(); 1785 1786 int vlevel = 0; 1787 int pipe_cnt = 0; 1788 display_e2e_pipe_params_st *pipes = kzalloc_objs(display_e2e_pipe_params_st, 1789 dc->res_pool->pipe_count); 1790 1791 /* To handle Freesync properly, setting FreeSync DML parameters 1792 * to its default state for the first stage of validation 1793 */ 1794 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; 1795 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 1796 1797 DC_LOGGER_INIT(dc->ctx->logger); 1798 1799 BW_VAL_TRACE_COUNT(); 1800 1801 if (!pipes) 1802 goto validate_fail; 1803 1804 DC_FP_START(); 1805 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode); 1806 DC_FP_END(); 1807 1808 if (pipe_cnt == 0) 1809 goto validate_out; 1810 1811 if (!out) 1812 goto validate_fail; 1813 1814 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1815 1816 if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) { 1817 BW_VAL_TRACE_SKIP(fast); 1818 goto validate_out; 1819 } 1820 1821 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1822 1823 DC_FP_START(); 1824 dcn32_override_min_req_memclk(dc, context); 1825 DC_FP_END(); 1826 1827 dcn32_override_min_req_dcfclk(dc, context); 1828 1829 BW_VAL_TRACE_END_WATERMARKS(); 1830 1831 goto validate_out; 1832 1833 validate_fail: 1834 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1835 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1836 1837 BW_VAL_TRACE_SKIP(fail); 1838 out = false; 1839 1840 validate_out: 1841 kfree(pipes); 1842 1843 BW_VAL_TRACE_FINISH(); 1844 1845 return out; 1846 } 1847 1848 enum dc_status dcn32_validate_bandwidth(struct dc *dc, 1849 struct dc_state *context, 1850 enum dc_validate_mode validate_mode) 1851 { 1852 unsigned int i; 1853 enum dc_status status; 1854 const struct dc_stream_state *stream; 1855 1856 /* reset cursor limitations on subvp */ 1857 for (i = 0; i < context->stream_count; i++) { 1858 stream = context->streams[i]; 1859 1860 if (dc_state_can_clear_stream_cursor_subvp_limit(stream, context)) { 1861 dc_state_set_stream_cursor_subvp_limit(stream, context, false); 1862 } 1863 } 1864 1865 if (dc->debug.using_dml2) 1866 status = dml2_validate(dc, context, 1867 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, 1868 validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; 1869 else 1870 status = dml1_validate(dc, context, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; 1871 1872 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_OK && dc_state_is_subvp_in_use(context)) { 1873 /* check new stream configuration still supports cursor if subvp used */ 1874 for (i = 0; i < context->stream_count; i++) { 1875 stream = context->streams[i]; 1876 1877 if (dc_state_get_stream_subvp_type(context, stream) != SUBVP_PHANTOM && 1878 stream->cursor_position.enable && 1879 !dc_stream_check_cursor_attributes(stream, context, &stream->cursor_attributes)) { 1880 /* hw cursor cannot be supported with subvp active, so disable subvp for now */ 1881 dc_state_set_stream_cursor_subvp_limit(stream, context, true); 1882 status = DC_FAIL_HW_CURSOR_SUPPORT; 1883 } 1884 } 1885 } 1886 1887 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_FAIL_HW_CURSOR_SUPPORT) { 1888 /* attempt to validate again with subvp disabled due to cursor */ 1889 if (dc->debug.using_dml2) 1890 status = dml2_validate(dc, context, 1891 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, 1892 validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; 1893 else 1894 status = dml1_validate(dc, context, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; 1895 } 1896 1897 return status; 1898 } 1899 1900 int dcn32_populate_dml_pipes_from_context( 1901 struct dc *dc, struct dc_state *context, 1902 display_e2e_pipe_params_st *pipes, 1903 enum dc_validate_mode validate_mode) 1904 { 1905 int i, pipe_cnt; 1906 struct resource_context *res_ctx = &context->res_ctx; 1907 struct pipe_ctx *pipe = NULL; 1908 bool subvp_in_use = false; 1909 struct dc_crtc_timing *timing; 1910 int subvp_main_pipe_index = -1; 1911 enum mall_stream_type mall_type; 1912 bool single_display_subvp = false; 1913 struct dc_stream_state *stream = NULL; 1914 int num_subvp_main = 0; 1915 int num_subvp_phantom = 0; 1916 int num_subvp_none = 0; 1917 int odm_slice_count; 1918 1919 dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode); 1920 1921 /* For single display subvp, look for subvp main so if we have phantom 1922 * pipe, we can set odm policy to match main pipe 1923 */ 1924 for (i = 0; i < context->stream_count; i++) { 1925 stream = context->streams[i]; 1926 mall_type = dc_state_get_stream_subvp_type(context, stream); 1927 if (mall_type == SUBVP_MAIN) 1928 num_subvp_main++; 1929 else if (mall_type == SUBVP_PHANTOM) 1930 num_subvp_phantom++; 1931 else 1932 num_subvp_none++; 1933 } 1934 if (num_subvp_main == 1 && num_subvp_phantom == 1 && num_subvp_none == 0) 1935 single_display_subvp = true; 1936 1937 if (single_display_subvp) { 1938 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1939 pipe = &res_ctx->pipe_ctx[i]; 1940 if (!res_ctx->pipe_ctx[i].stream) 1941 continue; 1942 1943 mall_type = dc_state_get_pipe_subvp_type(context, pipe); 1944 if (mall_type == SUBVP_MAIN) { 1945 if (resource_is_pipe_type(pipe, OTG_MASTER)) 1946 subvp_main_pipe_index = i; 1947 } 1948 pipe_cnt++; 1949 } 1950 } 1951 1952 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1953 1954 if (!res_ctx->pipe_ctx[i].stream) 1955 continue; 1956 pipe = &res_ctx->pipe_ctx[i]; 1957 timing = &pipe->stream->timing; 1958 1959 pipes[pipe_cnt].pipe.src.gpuvm = true; 1960 DC_FP_START(); 1961 dcn32_zero_pipe_dcc_fraction(pipes, pipe_cnt); 1962 DC_FP_END(); 1963 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1964 if (dc->config.enable_windowed_mpo_odm && 1965 dc->debug.enable_single_display_2to1_odm_policy) { 1966 /* For single display subvp, if pipe is phantom pipe, 1967 * then copy odm policy from subvp main pipe 1968 */ 1969 mall_type = dc_state_get_pipe_subvp_type(context, pipe); 1970 if (single_display_subvp && (mall_type == SUBVP_PHANTOM)) { 1971 if (subvp_main_pipe_index < 0) { 1972 odm_slice_count = -1; 1973 ASSERT(0); 1974 } else { 1975 odm_slice_count = resource_get_odm_slice_count(&res_ctx->pipe_ctx[subvp_main_pipe_index]); 1976 } 1977 } else { 1978 odm_slice_count = resource_get_odm_slice_count(pipe); 1979 } 1980 switch (odm_slice_count) { 1981 case 2: 1982 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1; 1983 break; 1984 case 4: 1985 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_4to1; 1986 break; 1987 default: 1988 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal; 1989 } 1990 } else { 1991 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal; 1992 } 1993 1994 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet 1995 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1996 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19; 1997 1998 /* Only populate DML input with subvp info for full updates. 1999 * This is just a workaround -- needs a proper fix. 2000 */ 2001 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) { 2002 switch (dc_state_get_pipe_subvp_type(context, pipe)) { 2003 case SUBVP_MAIN: 2004 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport; 2005 subvp_in_use = true; 2006 break; 2007 case SUBVP_PHANTOM: 2008 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe; 2009 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 2010 // Disallow unbounded req for SubVP according to DCHUB programming guide 2011 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 2012 break; 2013 case SUBVP_NONE: 2014 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable; 2015 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 2016 break; 2017 default: 2018 break; 2019 } 2020 } 2021 2022 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 2023 if (pipes[pipe_cnt].dout.dsc_enable) { 2024 switch (timing->display_color_depth) { 2025 case COLOR_DEPTH_888: 2026 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 2027 break; 2028 case COLOR_DEPTH_101010: 2029 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 2030 break; 2031 case COLOR_DEPTH_121212: 2032 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 2033 break; 2034 default: 2035 ASSERT(0); 2036 break; 2037 } 2038 } 2039 2040 2041 pipe_cnt++; 2042 } 2043 2044 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all 2045 * the DET available for each pipe). Use the DET override input to maintain our driver 2046 * policy. 2047 */ 2048 dcn32_set_det_allocations(dc, context, pipes); 2049 2050 // In general cases we want to keep the dram clock change requirement 2051 // (prefer configs that support MCLK switch). Only override to false 2052 // for SubVP 2053 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || subvp_in_use) 2054 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false; 2055 else 2056 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 2057 2058 return pipe_cnt; 2059 } 2060 2061 unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned int total_size_in_mall_bytes) 2062 { 2063 uint32_t cache_lines_used, lines_per_way, total_cache_lines, num_ways; 2064 2065 if (total_size_in_mall_bytes == 0) { 2066 return 0; 2067 } 2068 2069 if (dc->caps.max_cab_allocation_bytes == 0) { 2070 return 0xffffffff; 2071 } 2072 2073 /* add 2 lines for worst case alignment */ 2074 cache_lines_used = total_size_in_mall_bytes / dc->caps.cache_line_size + 2; 2075 2076 total_cache_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size; 2077 lines_per_way = total_cache_lines / dc->caps.cache_num_ways; 2078 num_ways = cache_lines_used / lines_per_way; 2079 if (cache_lines_used % lines_per_way > 0) 2080 num_ways++; 2081 2082 return num_ways; 2083 } 2084 2085 static struct dc_cap_funcs cap_funcs = { 2086 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap, 2087 .get_subvp_en = dcn32_subvp_in_use, 2088 }; 2089 2090 void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context, 2091 display_e2e_pipe_params_st *pipes, 2092 int pipe_cnt, 2093 int vlevel) 2094 { 2095 DC_FP_START(); 2096 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel); 2097 DC_FP_END(); 2098 } 2099 2100 static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 2101 { 2102 DC_FP_START(); 2103 2104 dcn32_update_bw_bounding_box_fpu(dc, bw_params); 2105 2106 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2) 2107 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); 2108 2109 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source) 2110 dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source); 2111 2112 DC_FP_END(); 2113 } 2114 2115 unsigned int dcn32_get_max_hw_cursor_size(const struct dc *dc, 2116 struct dc_state *state, 2117 const struct dc_stream_state *stream) 2118 { 2119 bool limit_cur_to_buf; 2120 2121 limit_cur_to_buf = dc_state_get_stream_subvp_cursor_limit(stream, state) && 2122 !stream->hw_cursor_req; 2123 2124 return limit_cur_to_buf ? dc->caps.max_buffered_cursor_size : dc->caps.max_cursor_size; 2125 } 2126 2127 static struct resource_funcs dcn32_res_pool_funcs = { 2128 .destroy = dcn32_destroy_resource_pool, 2129 .link_enc_create = dcn32_link_encoder_create, 2130 .link_enc_create_minimal = NULL, 2131 .panel_cntl_create = dcn32_panel_cntl_create, 2132 .validate_bandwidth = dcn32_validate_bandwidth, 2133 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 2134 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 2135 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe, 2136 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head, 2137 .release_pipe = dcn20_release_pipe, 2138 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 2139 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 2140 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 2141 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 2142 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 2143 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 2144 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 2145 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 2146 .update_bw_bounding_box = dcn32_update_bw_bounding_box, 2147 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 2148 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 2149 .add_phantom_pipes = dcn32_add_phantom_pipes, 2150 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, 2151 .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, 2152 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, 2153 .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size, 2154 }; 2155 2156 static uint32_t read_pipe_fuses(struct dc_context *ctx) 2157 { 2158 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 2159 /* DCN32 support max 4 pipes */ 2160 value = value & 0xf; 2161 return value; 2162 } 2163 2164 2165 static bool dcn32_resource_construct( 2166 uint8_t num_virtual_links, 2167 struct dc *dc, 2168 struct dcn32_resource_pool *pool) 2169 { 2170 int i, j; 2171 struct dc_context *ctx = dc->ctx; 2172 struct irq_service_init_data init_data; 2173 struct ddc_service_init_data ddc_init_data = {0}; 2174 uint32_t pipe_fuses = 0; 2175 uint32_t num_pipes = 4; 2176 2177 #undef REG_STRUCT 2178 #define REG_STRUCT bios_regs 2179 bios_regs_init(); 2180 2181 #undef REG_STRUCT 2182 #define REG_STRUCT clk_src_regs 2183 clk_src_regs_init(0, A), 2184 clk_src_regs_init(1, B), 2185 clk_src_regs_init(2, C), 2186 clk_src_regs_init(3, D), 2187 clk_src_regs_init(4, E); 2188 2189 #undef REG_STRUCT 2190 #define REG_STRUCT abm_regs 2191 abm_regs_init(0), 2192 abm_regs_init(1), 2193 abm_regs_init(2), 2194 abm_regs_init(3); 2195 2196 #undef REG_STRUCT 2197 #define REG_STRUCT dccg_regs 2198 dccg_regs_init(); 2199 2200 ctx->dc_bios->regs = &bios_regs; 2201 2202 pool->base.res_cap = &res_cap_dcn32; 2203 /* max number of pipes for ASIC before checking for pipe fuses */ 2204 num_pipes = pool->base.res_cap->num_timing_generator; 2205 pipe_fuses = read_pipe_fuses(ctx); 2206 2207 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 2208 if (pipe_fuses & 1 << i) 2209 num_pipes--; 2210 2211 if (pipe_fuses & 1) 2212 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 2213 2214 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 2215 ASSERT(0); //Entire DCN is harvested! 2216 2217 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 2218 * value will be changed, update max_num_dpp and max_num_otg for dml. 2219 */ 2220 dcn3_2_ip.max_num_dpp = num_pipes; 2221 dcn3_2_ip.max_num_otg = num_pipes; 2222 2223 pool->base.funcs = &dcn32_res_pool_funcs; 2224 2225 /************************************************* 2226 * Resource + asic cap harcoding * 2227 *************************************************/ 2228 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2229 pool->base.timing_generator_count = num_pipes; 2230 pool->base.pipe_count = num_pipes; 2231 pool->base.mpcc_count = num_pipes; 2232 dc->caps.max_downscale_ratio = 600; 2233 dc->caps.i2c_speed_in_khz = 100; 2234 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 2235 /* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/ 2236 dc->caps.max_cursor_size = 64; 2237 /* floor(sqrt(buf_size_bytes / bpp ) * bpp, fixed_req_size) / bpp = max_width */ 2238 dc->caps.max_buffered_cursor_size = 64; // floor(sqrt(16 * 1024 / 4) * 4, 256) / 4 = 64 2239 dc->caps.min_horizontal_blanking_period = 80; 2240 dc->caps.dmdata_alloc_size = 2048; 2241 dc->caps.mall_size_per_mem_channel = 4; 2242 /* total size = mall per channel * num channels * 1024 * 1024 */ 2243 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; 2244 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 2245 2246 dc->caps.cache_line_size = 64; 2247 dc->caps.cache_num_ways = 16; 2248 2249 /* Calculate the available MALL space */ 2250 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall( 2251 dc, dc->ctx->dc_bios->vram_info.num_chans) * 2252 dc->caps.mall_size_per_mem_channel * 1024 * 1024; 2253 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; 2254 2255 dc->caps.subvp_fw_processing_delay_us = 15; 2256 dc->caps.subvp_drr_max_vblank_margin_us = 40; 2257 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 2258 dc->caps.subvp_swath_height_margin_lines = 16; 2259 dc->caps.subvp_pstate_allow_width_us = 20; 2260 dc->caps.subvp_vertical_int_margin_us = 30; 2261 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin 2262 2263 dc->caps.max_slave_planes = 2; 2264 dc->caps.max_slave_yuv_planes = 2; 2265 dc->caps.max_slave_rgb_planes = 2; 2266 dc->caps.post_blend_color_processing = true; 2267 dc->caps.force_dp_tps4_for_cp2520 = true; 2268 if (dc->config.forceHBR2CP2520) 2269 dc->caps.force_dp_tps4_for_cp2520 = false; 2270 dc->caps.dp_hpo = true; 2271 dc->caps.dp_hdmi21_pcon_support = true; 2272 dc->caps.edp_dsc_support = true; 2273 dc->caps.extended_aux_timeout_support = true; 2274 dc->caps.dmcub_support = true; 2275 dc->caps.seamless_odm = true; 2276 dc->caps.max_v_total = (1 << 15) - 1; 2277 dc->caps.vtotal_limited_by_fp2 = true; 2278 2279 /* Color pipeline capabilities */ 2280 dc->caps.color.dpp.dcn_arch = 1; 2281 dc->caps.color.dpp.input_lut_shared = 0; 2282 dc->caps.color.dpp.icsc = 1; 2283 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2284 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2285 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2286 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2287 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2288 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2289 dc->caps.color.dpp.post_csc = 1; 2290 dc->caps.color.dpp.gamma_corr = 1; 2291 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2292 2293 dc->caps.color.dpp.hw_3d_lut = 0; 2294 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1 2295 // no OGAM ROM on DCN2 and later ASICs 2296 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2297 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2298 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2299 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2300 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2301 dc->caps.color.dpp.ocsc = 0; 2302 2303 dc->caps.color.mpc.gamut_remap = 1; 2304 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 2305 dc->caps.color.mpc.ogam_ram = 1; 2306 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2307 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2308 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2309 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2310 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2311 dc->caps.color.mpc.ocsc = 1; 2312 dc->caps.color.mpc.preblend = true; 2313 2314 /* Use pipe context based otg sync logic */ 2315 dc->config.use_pipe_ctx_sync_logic = true; 2316 2317 dc->config.dc_mode_clk_limit_support = true; 2318 dc->config.enable_windowed_mpo_odm = true; 2319 dc->config.disable_hbr_audio_dp2 = true; 2320 /* read VBIOS LTTPR caps */ 2321 { 2322 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2323 enum bp_result bp_query_result; 2324 uint8_t is_vbios_lttpr_enable = 0; 2325 2326 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2327 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2328 } 2329 2330 /* interop bit is implicit */ 2331 { 2332 dc->caps.vbios_lttpr_aware = true; 2333 } 2334 } 2335 dc->check_config = config_defaults; 2336 2337 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2338 dc->debug = debug_defaults_drv; 2339 2340 // Init the vm_helper 2341 if (dc->vm_helper) 2342 vm_helper_init(dc->vm_helper, 16); 2343 2344 /************************************************* 2345 * Create resources * 2346 *************************************************/ 2347 2348 /* Clock Sources for Pixel Clock*/ 2349 pool->base.clock_sources[DCN32_CLK_SRC_PLL0] = 2350 dcn32_clock_source_create(ctx, ctx->dc_bios, 2351 CLOCK_SOURCE_COMBO_PHY_PLL0, 2352 &clk_src_regs[0], false); 2353 pool->base.clock_sources[DCN32_CLK_SRC_PLL1] = 2354 dcn32_clock_source_create(ctx, ctx->dc_bios, 2355 CLOCK_SOURCE_COMBO_PHY_PLL1, 2356 &clk_src_regs[1], false); 2357 pool->base.clock_sources[DCN32_CLK_SRC_PLL2] = 2358 dcn32_clock_source_create(ctx, ctx->dc_bios, 2359 CLOCK_SOURCE_COMBO_PHY_PLL2, 2360 &clk_src_regs[2], false); 2361 pool->base.clock_sources[DCN32_CLK_SRC_PLL3] = 2362 dcn32_clock_source_create(ctx, ctx->dc_bios, 2363 CLOCK_SOURCE_COMBO_PHY_PLL3, 2364 &clk_src_regs[3], false); 2365 pool->base.clock_sources[DCN32_CLK_SRC_PLL4] = 2366 dcn32_clock_source_create(ctx, ctx->dc_bios, 2367 CLOCK_SOURCE_COMBO_PHY_PLL4, 2368 &clk_src_regs[4], false); 2369 2370 pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL; 2371 2372 /* todo: not reuse phy_pll registers */ 2373 pool->base.dp_clock_source = 2374 dcn32_clock_source_create(ctx, ctx->dc_bios, 2375 CLOCK_SOURCE_ID_DP_DTO, 2376 &clk_src_regs[0], true); 2377 2378 for (i = 0; i < pool->base.clk_src_count; i++) { 2379 if (pool->base.clock_sources[i] == NULL) { 2380 dm_error("DC: failed to create clock sources!\n"); 2381 BREAK_TO_DEBUGGER(); 2382 goto create_fail; 2383 } 2384 } 2385 2386 /* DCCG */ 2387 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2388 if (pool->base.dccg == NULL) { 2389 dm_error("DC: failed to create dccg!\n"); 2390 BREAK_TO_DEBUGGER(); 2391 goto create_fail; 2392 } 2393 2394 /* DML */ 2395 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); 2396 2397 /* IRQ Service */ 2398 init_data.ctx = dc->ctx; 2399 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 2400 if (!pool->base.irqs) 2401 goto create_fail; 2402 2403 /* HUBBUB */ 2404 pool->base.hubbub = dcn32_hubbub_create(ctx); 2405 if (pool->base.hubbub == NULL) { 2406 BREAK_TO_DEBUGGER(); 2407 dm_error("DC: failed to create hubbub!\n"); 2408 goto create_fail; 2409 } 2410 2411 /* DIO */ 2412 pool->base.dio = dcn32_dio_create(ctx); 2413 if (pool->base.dio == NULL) { 2414 BREAK_TO_DEBUGGER(); 2415 dm_error("DC: failed to create dio!\n"); 2416 goto create_fail; 2417 } 2418 2419 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 2420 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2421 2422 /* if pipe is disabled, skip instance of HW pipe, 2423 * i.e, skip ASIC register instance 2424 */ 2425 if (pipe_fuses & 1 << i) 2426 continue; 2427 2428 /* HUBPs */ 2429 pool->base.hubps[j] = dcn32_hubp_create(ctx, i); 2430 if (pool->base.hubps[j] == NULL) { 2431 BREAK_TO_DEBUGGER(); 2432 dm_error( 2433 "DC: failed to create hubps!\n"); 2434 goto create_fail; 2435 } 2436 2437 /* DPPs */ 2438 pool->base.dpps[j] = dcn32_dpp_create(ctx, i); 2439 if (pool->base.dpps[j] == NULL) { 2440 BREAK_TO_DEBUGGER(); 2441 dm_error( 2442 "DC: failed to create dpps!\n"); 2443 goto create_fail; 2444 } 2445 2446 /* OPPs */ 2447 pool->base.opps[j] = dcn32_opp_create(ctx, i); 2448 if (pool->base.opps[j] == NULL) { 2449 BREAK_TO_DEBUGGER(); 2450 dm_error( 2451 "DC: failed to create output pixel processor!\n"); 2452 goto create_fail; 2453 } 2454 2455 /* TGs */ 2456 pool->base.timing_generators[j] = dcn32_timing_generator_create( 2457 ctx, i); 2458 if (pool->base.timing_generators[j] == NULL) { 2459 BREAK_TO_DEBUGGER(); 2460 dm_error("DC: failed to create tg!\n"); 2461 goto create_fail; 2462 } 2463 2464 /* ABMs */ 2465 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 2466 &abm_regs[i], 2467 &abm_shift, 2468 &abm_mask); 2469 if (pool->base.multiple_abms[j] == NULL) { 2470 dm_error("DC: failed to create abm for pipe %d!\n", i); 2471 BREAK_TO_DEBUGGER(); 2472 goto create_fail; 2473 } 2474 2475 /* index for resource pool arrays for next valid pipe */ 2476 j++; 2477 } 2478 2479 /* PSR */ 2480 pool->base.psr = dmub_psr_create(ctx); 2481 if (pool->base.psr == NULL) { 2482 dm_error("DC: failed to create psr obj!\n"); 2483 BREAK_TO_DEBUGGER(); 2484 goto create_fail; 2485 } 2486 2487 /* MPCCs */ 2488 pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 2489 if (pool->base.mpc == NULL) { 2490 BREAK_TO_DEBUGGER(); 2491 dm_error("DC: failed to create mpc!\n"); 2492 goto create_fail; 2493 } 2494 2495 /* DSCs */ 2496 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2497 pool->base.dscs[i] = dcn32_dsc_create(ctx, i); 2498 if (pool->base.dscs[i] == NULL) { 2499 BREAK_TO_DEBUGGER(); 2500 dm_error("DC: failed to create display stream compressor %d!\n", i); 2501 goto create_fail; 2502 } 2503 } 2504 2505 /* DWB */ 2506 if (!dcn32_dwbc_create(ctx, &pool->base)) { 2507 BREAK_TO_DEBUGGER(); 2508 dm_error("DC: failed to create dwbc!\n"); 2509 goto create_fail; 2510 } 2511 2512 /* MMHUBBUB */ 2513 if (!dcn32_mmhubbub_create(ctx, &pool->base)) { 2514 BREAK_TO_DEBUGGER(); 2515 dm_error("DC: failed to create mcif_wb!\n"); 2516 goto create_fail; 2517 } 2518 2519 /* AUX and I2C */ 2520 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2521 pool->base.engines[i] = dcn32_aux_engine_create(ctx, i); 2522 if (pool->base.engines[i] == NULL) { 2523 BREAK_TO_DEBUGGER(); 2524 dm_error( 2525 "DC:failed to create aux engine!!\n"); 2526 goto create_fail; 2527 } 2528 pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i); 2529 if (pool->base.hw_i2cs[i] == NULL) { 2530 BREAK_TO_DEBUGGER(); 2531 dm_error( 2532 "DC:failed to create hw i2c!!\n"); 2533 goto create_fail; 2534 } 2535 pool->base.sw_i2cs[i] = NULL; 2536 } 2537 2538 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2539 if (!resource_construct(num_virtual_links, dc, &pool->base, 2540 &res_create_funcs)) 2541 goto create_fail; 2542 2543 /* HW Sequencer init functions and Plane caps */ 2544 dcn32_hw_sequencer_init_functions(dc); 2545 2546 dc->caps.max_planes = pool->base.pipe_count; 2547 2548 for (i = 0; i < dc->caps.max_planes; ++i) 2549 dc->caps.planes[i] = plane_cap; 2550 2551 dc->caps.max_odm_combine_factor = 4; 2552 2553 dc->cap_funcs = cap_funcs; 2554 2555 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 2556 ddc_init_data.ctx = dc->ctx; 2557 ddc_init_data.link = NULL; 2558 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2559 ddc_init_data.id.enum_id = 0; 2560 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2561 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data); 2562 } else { 2563 pool->base.oem_device = NULL; 2564 } 2565 2566 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; 2567 dc->dml2_options.use_native_soc_bb_construction = true; 2568 dc->dml2_options.minimize_dispclk_using_odm = true; 2569 2570 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); 2571 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch; 2572 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc; 2573 dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes; 2574 2575 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us; 2576 dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us; 2577 dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; 2578 dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines; 2579 2580 dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp; 2581 dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch; 2582 2583 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size; 2584 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways; 2585 dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes; 2586 dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE; 2587 dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE; 2588 dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES; 2589 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH; 2590 2591 dc->dml2_options.max_segments_per_hubp = 18; 2592 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE; 2593 dc->dml2_options.map_dc_pipes_with_callbacks = true; 2594 2595 if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc == 0)) 2596 dc->config.sdpif_request_limit_words_per_umc = 16; 2597 2598 /* init DC limited DML2 options */ 2599 memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options)); 2600 dc->dml2_dc_power_options.use_clock_dc_limits = true; 2601 2602 return true; 2603 2604 create_fail: 2605 2606 dcn32_resource_destruct(pool); 2607 2608 return false; 2609 } 2610 2611 struct resource_pool *dcn32_create_resource_pool( 2612 const struct dc_init_data *init_data, 2613 struct dc *dc) 2614 { 2615 struct dcn32_resource_pool *pool = 2616 kzalloc_obj(struct dcn32_resource_pool); 2617 2618 if (!pool) 2619 return NULL; 2620 2621 if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool)) 2622 return &pool->base; 2623 2624 BREAK_TO_DEBUGGER(); 2625 kfree(pool); 2626 return NULL; 2627 } 2628 2629 /* 2630 * Find the most optimal free pipe from res_ctx, which could be used as a 2631 * secondary dpp pipe for input opp head pipe. 2632 * 2633 * a free pipe - a pipe in input res_ctx not yet used for any streams or 2634 * planes. 2635 * secondary dpp pipe - a pipe gets inserted to a head OPP pipe's MPC blending 2636 * tree. This is typical used for rendering MPO planes or additional offset 2637 * areas in MPCC combine. 2638 * 2639 * Hardware Transition Minimization Algorithm for Finding a Secondary DPP Pipe 2640 * ------------------------------------------------------------------------- 2641 * 2642 * PROBLEM: 2643 * 2644 * 1. There is a hardware limitation that a secondary DPP pipe cannot be 2645 * transferred from one MPC blending tree to the other in a single frame. 2646 * Otherwise it could cause glitches on the screen. 2647 * 2648 * For instance, we cannot transition from state 1 to state 2 in one frame. This 2649 * is because PIPE1 is transferred from PIPE0's MPC blending tree over to 2650 * PIPE2's MPC blending tree, which is not supported by hardware. 2651 * To support this transition we need to first remove PIPE1 from PIPE0's MPC 2652 * blending tree in one frame and then insert PIPE1 to PIPE2's MPC blending tree 2653 * in the next frame. This is not optimal as it will delay the flip for two 2654 * frames. 2655 * 2656 * State 1: 2657 * PIPE0 -- secondary DPP pipe --> (PIPE1) 2658 * PIPE2 -- secondary DPP pipe --> NONE 2659 * 2660 * State 2: 2661 * PIPE0 -- secondary DPP pipe --> NONE 2662 * PIPE2 -- secondary DPP pipe --> (PIPE1) 2663 * 2664 * 2. We want to in general minimize the unnecessary changes in pipe topology. 2665 * If a pipe is already added in current blending tree and there are no changes 2666 * to plane topology, we don't want to swap it with another free pipe 2667 * unnecessarily in every update. Powering up and down a pipe would require a 2668 * full update which delays the flip for 1 frame. If we use the original pipe 2669 * we don't have to toggle its power. So we can flip faster. 2670 */ 2671 int dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe( 2672 const struct resource_context *cur_res_ctx, 2673 struct resource_context *new_res_ctx, 2674 const struct resource_pool *pool, 2675 const struct pipe_ctx *new_opp_head) 2676 { 2677 const struct pipe_ctx *cur_opp_head; 2678 int free_pipe_idx; 2679 2680 cur_opp_head = &cur_res_ctx->pipe_ctx[new_opp_head->pipe_idx]; 2681 free_pipe_idx = resource_find_free_pipe_used_in_cur_mpc_blending_tree( 2682 cur_res_ctx, new_res_ctx, cur_opp_head); 2683 2684 /* Up until here if we have not found a free secondary pipe, we will 2685 * need to wait for at least one frame to complete the transition 2686 * sequence. 2687 */ 2688 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND) 2689 free_pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx( 2690 cur_res_ctx, new_res_ctx, pool); 2691 2692 /* Up until here if we have not found a free secondary pipe, we will 2693 * need to wait for at least two frames to complete the transition 2694 * sequence. It really doesn't matter which pipe we decide take from 2695 * current enabled pipes. It won't save our frame time when we swap only 2696 * one pipe or more pipes. 2697 */ 2698 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND) 2699 free_pipe_idx = resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine( 2700 cur_res_ctx, new_res_ctx, pool); 2701 2702 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND) 2703 free_pipe_idx = resource_find_any_free_pipe(new_res_ctx, pool); 2704 2705 return free_pipe_idx; 2706 } 2707 2708 static struct pipe_ctx *find_idle_secondary_pipe_check_mpo( 2709 struct resource_context *res_ctx, 2710 const struct resource_pool *pool, 2711 const struct pipe_ctx *primary_pipe) 2712 { 2713 int i; 2714 struct pipe_ctx *secondary_pipe = NULL; 2715 struct pipe_ctx *next_odm_mpo_pipe = NULL; 2716 int primary_index, preferred_pipe_idx; 2717 struct pipe_ctx *old_primary_pipe = NULL; 2718 2719 /* 2720 * Modified from find_idle_secondary_pipe 2721 * With windowed MPO and ODM, we want to avoid the case where we want a 2722 * free pipe for the left side but the free pipe is being used on the 2723 * right side. 2724 * Add check on current_state if the primary_pipe is the left side, 2725 * to check the right side ( primary_pipe->next_odm_pipe ) to see if 2726 * it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe ) 2727 * - If so, then don't use this pipe 2728 * EXCEPTION - 3 plane ( 2 MPO plane ) case 2729 * - in this case, the primary pipe has already gotten a free pipe for the 2730 * MPO window in the left 2731 * - when it tries to get a free pipe for the MPO window on the right, 2732 * it will see that it is already assigned to the right side 2733 * ( primary_pipe->next_odm_pipe ). But in this case, we want this 2734 * free pipe, since it will be for the right side. So add an 2735 * additional condition, that skipping the free pipe on the right only 2736 * applies if the primary pipe has no bottom pipe currently assigned 2737 */ 2738 if (primary_pipe) { 2739 primary_index = primary_pipe->pipe_idx; 2740 old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index]; 2741 if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe) 2742 && (!primary_pipe->bottom_pipe)) 2743 next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe; 2744 2745 preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; 2746 if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) && 2747 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) { 2748 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2749 secondary_pipe->pipe_idx = preferred_pipe_idx; 2750 } 2751 } 2752 2753 /* 2754 * search backwards for the second pipe to keep pipe 2755 * assignment more consistent 2756 */ 2757 if (!secondary_pipe) 2758 for (i = pool->pipe_count - 1; i >= 0; i--) { 2759 if ((res_ctx->pipe_ctx[i].stream == NULL) && 2760 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) { 2761 secondary_pipe = &res_ctx->pipe_ctx[i]; 2762 secondary_pipe->pipe_idx = i; 2763 break; 2764 } 2765 } 2766 2767 return secondary_pipe; 2768 } 2769 2770 static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer( 2771 struct dc_state *state, 2772 const struct resource_pool *pool, 2773 struct dc_stream_state *stream, 2774 const struct pipe_ctx *head_pipe) 2775 { 2776 struct resource_context *res_ctx = &state->res_ctx; 2777 struct pipe_ctx *idle_pipe, *pipe; 2778 struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx; 2779 int head_index; 2780 2781 if (!head_pipe) { 2782 ASSERT(0); 2783 return NULL; 2784 } 2785 2786 /* 2787 * Modified from dcn20_acquire_idle_pipe_for_layer 2788 * Check if head_pipe in old_context already has bottom_pipe allocated. 2789 * - If so, check if that pipe is available in the current context. 2790 * -- If so, reuse pipe from old_context 2791 */ 2792 head_index = head_pipe->pipe_idx; 2793 pipe = &old_ctx->pipe_ctx[head_index]; 2794 if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) { 2795 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx]; 2796 idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx; 2797 } else { 2798 idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe); 2799 if (!idle_pipe) 2800 return NULL; 2801 } 2802 2803 idle_pipe->stream = head_pipe->stream; 2804 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 2805 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 2806 2807 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 2808 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 2809 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 2810 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 2811 2812 return idle_pipe; 2813 } 2814 2815 static int find_optimal_free_pipe_as_secondary_opp_head( 2816 const struct resource_context *cur_res_ctx, 2817 struct resource_context *new_res_ctx, 2818 const struct resource_pool *pool, 2819 const struct pipe_ctx *new_otg_master) 2820 { 2821 const struct pipe_ctx *cur_otg_master; 2822 int free_pipe_idx; 2823 2824 cur_otg_master = &cur_res_ctx->pipe_ctx[new_otg_master->pipe_idx]; 2825 free_pipe_idx = resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master( 2826 cur_res_ctx, new_res_ctx, cur_otg_master); 2827 2828 /* Up until here if we have not found a free secondary pipe, we will 2829 * need to wait for at least one frame to complete the transition 2830 * sequence. 2831 */ 2832 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND) 2833 free_pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx( 2834 cur_res_ctx, new_res_ctx, pool); 2835 2836 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND) 2837 free_pipe_idx = resource_find_any_free_pipe(new_res_ctx, pool); 2838 2839 return free_pipe_idx; 2840 } 2841 2842 struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe( 2843 const struct dc_state *cur_ctx, 2844 struct dc_state *new_ctx, 2845 const struct resource_pool *pool, 2846 const struct pipe_ctx *opp_head_pipe) 2847 { 2848 2849 int free_pipe_idx; 2850 struct pipe_ctx *free_pipe; 2851 2852 if (!opp_head_pipe->stream->ctx->dc->config.enable_windowed_mpo_odm) 2853 return dcn32_acquire_idle_pipe_for_head_pipe_in_layer( 2854 new_ctx, pool, opp_head_pipe->stream, opp_head_pipe); 2855 2856 free_pipe_idx = dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe( 2857 &cur_ctx->res_ctx, &new_ctx->res_ctx, 2858 pool, opp_head_pipe); 2859 if (free_pipe_idx >= 0) { 2860 free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx]; 2861 free_pipe->pipe_idx = free_pipe_idx; 2862 free_pipe->stream = opp_head_pipe->stream; 2863 free_pipe->stream_res.tg = opp_head_pipe->stream_res.tg; 2864 free_pipe->stream_res.opp = opp_head_pipe->stream_res.opp; 2865 2866 free_pipe->plane_res.hubp = pool->hubps[free_pipe->pipe_idx]; 2867 free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx]; 2868 free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx]; 2869 free_pipe->plane_res.mpcc_inst = 2870 pool->dpps[free_pipe->pipe_idx]->inst; 2871 } else { 2872 ASSERT(opp_head_pipe); 2873 free_pipe = NULL; 2874 } 2875 2876 return free_pipe; 2877 } 2878 2879 struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head( 2880 const struct dc_state *cur_ctx, 2881 struct dc_state *new_ctx, 2882 const struct resource_pool *pool, 2883 const struct pipe_ctx *otg_master) 2884 { 2885 int free_pipe_idx = find_optimal_free_pipe_as_secondary_opp_head( 2886 &cur_ctx->res_ctx, &new_ctx->res_ctx, 2887 pool, otg_master); 2888 struct pipe_ctx *free_pipe; 2889 2890 if (free_pipe_idx >= 0) { 2891 free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx]; 2892 free_pipe->pipe_idx = free_pipe_idx; 2893 free_pipe->stream = otg_master->stream; 2894 free_pipe->stream_res.tg = otg_master->stream_res.tg; 2895 free_pipe->stream_res.dsc = NULL; 2896 free_pipe->stream_res.opp = pool->opps[free_pipe_idx]; 2897 free_pipe->plane_res.mi = pool->mis[free_pipe_idx]; 2898 free_pipe->plane_res.hubp = pool->hubps[free_pipe_idx]; 2899 free_pipe->plane_res.ipp = pool->ipps[free_pipe_idx]; 2900 free_pipe->plane_res.xfm = pool->transforms[free_pipe_idx]; 2901 free_pipe->plane_res.dpp = pool->dpps[free_pipe_idx]; 2902 free_pipe->plane_res.mpcc_inst = pool->dpps[free_pipe_idx]->inst; 2903 free_pipe->dsc_padding_params = otg_master->dsc_padding_params; 2904 if (free_pipe->stream->timing.flags.DSC == 1) { 2905 dcn20_acquire_dsc(free_pipe->stream->ctx->dc, 2906 &new_ctx->res_ctx, 2907 &free_pipe->stream_res.dsc, 2908 free_pipe_idx); 2909 ASSERT(free_pipe->stream_res.dsc); 2910 if (free_pipe->stream_res.dsc == NULL) { 2911 memset(free_pipe, 0, sizeof(*free_pipe)); 2912 free_pipe = NULL; 2913 } 2914 } 2915 } else { 2916 ASSERT(otg_master); 2917 free_pipe = NULL; 2918 } 2919 2920 return free_pipe; 2921 } 2922 2923 unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans) 2924 { 2925 /* 2926 * DCN32 and DCN321 SKUs may have different sizes for MALL 2927 * but we may not be able to access all the MALL space. 2928 * If the num_chans is power of 2, then we can access all 2929 * of the available MALL space. Otherwise, we can only 2930 * access: 2931 * 2932 * max_cab_size_in_bytes = total_cache_size_in_bytes * 2933 * ((2^floor(log2(num_chans)))/num_chans) 2934 * 2935 * Calculating the MALL sizes for all available SKUs, we 2936 * have come up with the follow simplified check. 2937 * - we have max_chans which provides the max MALL size. 2938 * Each chans supports 4MB of MALL so: 2939 * 2940 * total_cache_size_in_bytes = max_chans * 4 MB 2941 * 2942 * - we have avail_chans which shows the number of channels 2943 * we can use if we can't access the entire MALL space. 2944 * It is generally half of max_chans 2945 * - so we use the following checks: 2946 * 2947 * if (num_chans == max_chans), return max_chans 2948 * if (num_chans < max_chans), return avail_chans 2949 * 2950 * - exception is GC_11_0_0 where we can't access max_chans, 2951 * so we define max_avail_chans as the maximum available 2952 * MALL space 2953 * 2954 */ 2955 int gc_11_0_0_max_chans = 48; 2956 int gc_11_0_0_max_avail_chans = 32; 2957 int gc_11_0_0_avail_chans = 16; 2958 int gc_11_0_3_max_chans = 16; 2959 int gc_11_0_3_avail_chans = 8; 2960 int gc_11_0_2_max_chans = 8; 2961 int gc_11_0_2_avail_chans = 4; 2962 2963 if (ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev)) { 2964 return (num_chans == gc_11_0_0_max_chans) ? 2965 gc_11_0_0_max_avail_chans : gc_11_0_0_avail_chans; 2966 } else if (ASICREV_IS_GC_11_0_2(dc->ctx->asic_id.hw_internal_rev)) { 2967 return (num_chans == gc_11_0_2_max_chans) ? 2968 gc_11_0_2_max_chans : gc_11_0_2_avail_chans; 2969 } else { // if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev)) { 2970 return (num_chans == gc_11_0_3_max_chans) ? 2971 gc_11_0_3_max_chans : gc_11_0_3_avail_chans; 2972 } 2973 } 2974