1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "link_validation.h" 41 #include "accessories/link_dp_trace.h" 42 #include "protocols/link_dpcd.h" 43 #include "protocols/link_ddc.h" 44 #include "protocols/link_hpd.h" 45 #include "protocols/link_dp_phy.h" 46 #include "protocols/link_dp_capability.h" 47 #include "protocols/link_dp_training.h" 48 #include "protocols/link_edp_panel_control.h" 49 #include "protocols/link_dp_panel_replay.h" 50 #include "protocols/link_dp_dpia_bw.h" 51 #include "link/protocols/link_hdmi_frl.h" 52 53 #include "dm_helpers.h" 54 #include "link_enc_cfg.h" 55 #include "resource.h" 56 #include "dsc.h" 57 #include "dccg.h" 58 #include "clk_mgr.h" 59 #include "atomfirmware.h" 60 #include "vpg.h" 61 62 #define DC_LOGGER \ 63 dc_logger 64 #define DC_LOGGER_INIT(logger) \ 65 struct dal_logger *dc_logger = logger 66 67 #define LINK_INFO(...) \ 68 DC_LOG_HW_HOTPLUG( \ 69 __VA_ARGS__) 70 71 #define RETIMER_REDRIVER_INFO(...) \ 72 DC_LOG_RETIMER_REDRIVER( \ 73 __VA_ARGS__) 74 75 #define FRL_INFO(...) \ 76 DC_LOG_HDMI_FRL_LTP( \ 77 __VA_ARGS__) 78 79 #define MAX_MTP_SLOT_COUNT 64 80 #define LINK_TRAINING_ATTEMPTS 4 81 #define PEAK_FACTOR_X1000 1006 82 83 void link_blank_all_dp_displays(struct dc *dc) 84 { 85 unsigned int i; 86 uint8_t dpcd_power_state = '\0'; 87 enum dc_status status = DC_ERROR_UNEXPECTED; 88 89 for (i = 0; i < dc->link_count; i++) { 90 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 91 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 92 continue; 93 94 /* DP 2.0 spec requires that we read LTTPR caps first */ 95 dp_retrieve_lttpr_cap(dc->links[i]); 96 /* if any of the displays are lit up turn them off */ 97 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 98 &dpcd_power_state, sizeof(dpcd_power_state)); 99 100 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 101 link_blank_dp_stream(dc->links[i], true); 102 } 103 104 } 105 106 void link_blank_all_edp_displays(struct dc *dc) 107 { 108 unsigned int i; 109 uint8_t dpcd_power_state = '\0'; 110 enum dc_status status = DC_ERROR_UNEXPECTED; 111 112 for (i = 0; i < dc->link_count; i++) { 113 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 114 (!dc->links[i]->edp_sink_present)) 115 continue; 116 117 /* if any of the displays are lit up turn them off */ 118 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 119 &dpcd_power_state, sizeof(dpcd_power_state)); 120 121 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 122 link_blank_dp_stream(dc->links[i], true); 123 } 124 } 125 126 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 127 { 128 unsigned int j; 129 struct dc *dc = link->ctx->dc; 130 enum signal_type signal = link->connector_signal; 131 132 if ((signal == SIGNAL_TYPE_EDP) || 133 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 134 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 135 link->link_enc->funcs->get_dig_frontend && 136 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 137 int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 138 139 if (fe != ENGINE_ID_UNKNOWN) 140 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 141 if (fe == dc->res_pool->stream_enc[j]->id) { 142 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 143 dc->res_pool->stream_enc[j]); 144 break; 145 } 146 } 147 } 148 149 if (((!dc->is_switch_in_progress_dest) && ((!link->wa_flags.dp_keep_receiver_powered) || hw_init)) && 150 (link->type != dc_connection_none)) 151 dpcd_write_rx_power_ctrl(link, false); 152 } 153 } 154 155 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 156 { 157 struct pipe_ctx *pipes[MAX_PIPES]; 158 struct dc_stream_state *streams[MAX_PIPES]; 159 struct dc_state *state = link->dc->current_state; 160 uint8_t count; 161 int i; 162 struct dc_stream_update stream_update; 163 bool dpms_off = true; 164 struct link_resource link_res = {0}; 165 166 memset(&stream_update, 0, sizeof(stream_update)); 167 stream_update.dpms_off = &dpms_off; 168 169 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 170 171 /* The subsequent call to dc_commit_updates_for_stream for a full update 172 * will release the current state and swap to a new state. Releasing the 173 * current state results in the stream pointers in the pipe_ctx structs 174 * to be zero'd. Hence, cache all streams prior to dc_commit_updates_for_stream. 175 */ 176 for (i = 0; i < count; i++) 177 streams[i] = pipes[i]->stream; 178 179 for (i = 0; i < count; i++) { 180 stream_update.stream = streams[i]; 181 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 182 streams[i], &stream_update, 183 state); 184 } 185 186 /* link can be also enabled by vbios. In this case it is not recorded 187 * in pipe_ctx. Disable link phy here to make sure it is completely off 188 */ 189 if (dc_is_dp_signal(link->connector_signal)) 190 dp_disable_link_phy(link, &link_res, link->connector_signal); 191 } 192 193 void link_resume(struct dc_link *link) 194 { 195 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 196 program_hpd_filter(link); 197 } 198 199 /* This function returns true if the pipe is used to feed video signal directly 200 * to the link. 201 */ 202 static bool is_master_pipe_for_link(const struct dc_link *link, 203 const struct pipe_ctx *pipe) 204 { 205 return resource_is_pipe_type(pipe, OTG_MASTER) && 206 pipe->stream->link == link; 207 } 208 209 /* 210 * This function finds all master pipes feeding to a given link with dpms set to 211 * on in given dc state. 212 */ 213 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 214 struct dc_state *state, 215 uint8_t *count, 216 struct pipe_ctx *pipes[MAX_PIPES]) 217 { 218 int i; 219 struct pipe_ctx *pipe = NULL; 220 221 *count = 0; 222 for (i = 0; i < MAX_PIPES; i++) { 223 pipe = &state->res_ctx.pipe_ctx[i]; 224 225 if (is_master_pipe_for_link(link, pipe) && 226 pipe->stream->dpms_off == false) { 227 pipes[(*count)++] = pipe; 228 } 229 } 230 } 231 232 static struct ext_hdmi_settings create_ext_hdmi_settings( 233 uint8_t address, 234 uint8_t reg_num, 235 uint8_t reg_num_6g, 236 const struct i2c_reg_info *reg_settings, 237 const struct i2c_reg_info *reg_settings_6g 238 ) 239 { 240 struct ext_hdmi_settings result = { 241 .slv_addr = address, 242 .reg_num = reg_num, 243 .reg_num_6g = reg_num_6g, 244 }; 245 246 memcpy(result.reg_settings, reg_settings, sizeof(result.reg_settings)); 247 memcpy(result.reg_settings_6g, reg_settings_6g, sizeof(result.reg_settings_6g)); 248 return result; 249 } 250 251 static bool get_ext_hdmi_settings( 252 const struct integrated_info *info, 253 enum engine_id eng_id, 254 struct ext_hdmi_settings *settings 255 ) 256 { 257 if (!settings || !info) 258 return false; 259 260 /* 261 * Get retimer settings from sbios for passing SI eye test for DCE11 262 * The setting values are varied based on board revision and port id 263 * Therefore the setting values of each ports is passed by sbios. 264 */ 265 266 // Check if current bios contains ext Hdmi settings 267 if (!(info->gpu_cap_info & 0x20)) 268 return false; 269 270 switch (eng_id) { 271 case ENGINE_ID_DIGA: 272 *settings = create_ext_hdmi_settings( 273 info->dp0_ext_hdmi_slv_addr, 274 info->dp0_ext_hdmi_reg_num, 275 info->dp0_ext_hdmi_6g_reg_num, 276 info->dp0_ext_hdmi_reg_settings, 277 info->dp0_ext_hdmi_6g_reg_settings 278 ); 279 break; 280 case ENGINE_ID_DIGB: 281 *settings = create_ext_hdmi_settings( 282 info->dp1_ext_hdmi_slv_addr, 283 info->dp1_ext_hdmi_reg_num, 284 info->dp1_ext_hdmi_6g_reg_num, 285 info->dp1_ext_hdmi_reg_settings, 286 info->dp1_ext_hdmi_6g_reg_settings 287 ); 288 break; 289 case ENGINE_ID_DIGC: 290 *settings = create_ext_hdmi_settings( 291 info->dp2_ext_hdmi_slv_addr, 292 info->dp2_ext_hdmi_reg_num, 293 info->dp2_ext_hdmi_6g_reg_num, 294 info->dp2_ext_hdmi_reg_settings, 295 info->dp2_ext_hdmi_6g_reg_settings 296 ); 297 break; 298 case ENGINE_ID_DIGD: 299 *settings = create_ext_hdmi_settings( 300 info->dp3_ext_hdmi_slv_addr, 301 info->dp3_ext_hdmi_reg_num, 302 info->dp3_ext_hdmi_6g_reg_num, 303 info->dp3_ext_hdmi_reg_settings, 304 info->dp3_ext_hdmi_6g_reg_settings 305 ); 306 break; 307 default: 308 return false; 309 } 310 311 // Validate settings from bios integrated info table 312 if ( 313 !settings->slv_addr 314 || settings->reg_num > ARRAY_SIZE(settings->reg_settings) 315 || settings->reg_num_6g > ARRAY_SIZE(settings->reg_settings_6g) 316 ) { 317 return false; 318 } 319 320 for (size_t i = 0; i < settings->reg_num; i++) { 321 if (settings->reg_settings[i].i2c_reg_index > 0x20) 322 return false; 323 } 324 325 for (size_t i = 0; i < settings->reg_num_6g; i++) { 326 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 327 return false; 328 } 329 return true; 330 } 331 332 static bool write_i2c( 333 const struct dc_link *link, 334 uint8_t address, 335 uint8_t *buffer, 336 uint32_t length 337 ) 338 { 339 struct i2c_payload payload = { 340 .write = true, 341 .address = address, 342 .length = length, 343 .data = buffer, 344 }; 345 struct i2c_command cmd = { 346 .payloads = &payload, 347 .number_of_payloads = 1, 348 .engine = I2C_COMMAND_ENGINE_DEFAULT, 349 .speed = link->ctx->dc->caps.i2c_speed_in_khz, 350 }; 351 352 return dm_helpers_submit_i2c(link->ctx, link, &cmd); 353 } 354 355 static bool write_i2c_retimer_offset_value( 356 const struct dc_link *link, 357 uint8_t address, 358 uint8_t offset, 359 uint8_t value 360 ) 361 { 362 DC_LOGGER_INIT(link->ctx->logger); 363 uint8_t buffer[] = { offset, value }; 364 const bool success = write_i2c(link, address, buffer, sizeof(buffer)); 365 366 RETIMER_REDRIVER_INFO( 367 "Retimer write, address: 0x%x, offset: 0x%x, value: 0x%x, success: %d\n", 368 address, offset, value, success 369 ); 370 return success; 371 } 372 373 static bool write_i2c_retimer_vga( 374 const struct dc_link *link, 375 uint8_t address 376 ) 377 { 378 DC_LOGGER_INIT(link->ctx->logger); 379 const uint8_t vga_data[][2] = { 380 { 0xFF, 0x01 }, 381 { 0x00, 0x23 }, 382 { 0xFF, 0x00 }, 383 }; 384 385 for (size_t i = 0; i < ARRAY_SIZE(vga_data); i++) { 386 if (!write_i2c_retimer_offset_value(link, address, vga_data[i][0], vga_data[i][1])) { 387 DC_LOG_DEBUG("Set retimer failed, vga index: %zu\n", i); 388 return false; 389 } 390 } 391 return true; 392 } 393 394 static bool write_i2c_retimer_byte( 395 const struct dc_link *link, 396 uint8_t address, 397 uint8_t index, 398 uint8_t value 399 ) 400 { 401 DC_LOGGER_INIT(link->ctx->logger); 402 const uint8_t apply_rx_tx_change = 0x4; 403 404 if (index > 0x20) 405 return true; 406 407 if (!write_i2c_retimer_offset_value(link, address, index, value)) { 408 DC_LOG_DEBUG("Set retimer failed, 3g index: 0x%x, value: 0x%x\n", index, value); 409 return false; 410 } 411 412 // Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 413 // needs to be set to 1 on every 0x0A-0x0C write. 414 if (0x0A <= index && index <= 0x0C) { 415 uint8_t offset = 0x0A; 416 417 // Query current value from offset 0x0A 418 if (index == 0x0A) { 419 // Just written correct value, so no need to read it back 420 } else { 421 if (!link_query_ddc_data( 422 link->ddc, address, &offset, 1, &value, 1 423 )) { 424 DC_LOG_DEBUG("Set retimer failed, link_query_ddc_data\n"); 425 return false; 426 } 427 } 428 429 value |= apply_rx_tx_change; 430 if (!write_i2c_retimer_offset_value(link, address, offset, value)) { 431 DC_LOG_DEBUG("Set retimer failed, 3g offset: 0x%x, value: 0x%x\n", offset, value); 432 return false; 433 } 434 } 435 return true; 436 } 437 438 static bool write_i2c_retimer_setting( 439 const struct dc_link *link, 440 bool is_vga_mode, 441 bool is_over_340mhz, 442 struct ext_hdmi_settings *settings) 443 { 444 DC_LOGGER_INIT(link->ctx->logger); 445 const uint8_t address = settings->slv_addr >> 1; 446 447 for (size_t i = 0; i < settings->reg_num; i++) { 448 const uint8_t index = settings->reg_settings[i].i2c_reg_index; 449 uint8_t value = settings->reg_settings[i].i2c_reg_val; 450 451 if (!write_i2c_retimer_byte(link, address, index, value)) { 452 DC_LOG_DEBUG("Set retimer failed, index: %zu\n", i); 453 return false; 454 } 455 } 456 457 if (is_over_340mhz) { 458 for (size_t i = 0; i < settings->reg_num_6g; i++) { 459 const uint8_t index = settings->reg_settings_6g[i].i2c_reg_index; 460 uint8_t value = settings->reg_settings_6g[i].i2c_reg_val; 461 462 if (!write_i2c_retimer_byte(link, address, index, value)) { 463 DC_LOG_DEBUG("Set retimer failed, 6g index: %zu\n", i); 464 return false; 465 } 466 } 467 } 468 469 if (is_vga_mode) { 470 return write_i2c_retimer_vga(link, address); 471 } 472 return true; 473 } 474 475 static bool write_i2c_default_retimer_setting( 476 const struct dc_link *link, 477 bool is_vga_mode, 478 bool is_over_340mhz) 479 { 480 const uint8_t address = 0xBA >> 1; 481 482 DC_LOGGER_INIT(link->ctx->logger); 483 484 const uint8_t data[][2] = { 485 { 0x0A, 0x13 }, 486 { 0x0A, 0x17 }, 487 { 0x0B, is_over_340mhz ? 0xDA : 0xD8 }, 488 { 0x0A, 0x17 }, 489 { 0x0C, is_over_340mhz ? 0x1D : 0x91 }, 490 { 0x0A, 0x17 }, 491 }; 492 493 for (size_t i = 0; i < ARRAY_SIZE(data); i++) { 494 if (!write_i2c_retimer_offset_value(link, address, data[i][0], data[i][1])) { 495 DC_LOG_DEBUG("Set default retimer failed, index: %zu\n", i); 496 return false; 497 } 498 } 499 500 if (is_vga_mode) { 501 return write_i2c_retimer_vga(link, address); 502 } 503 return true; 504 } 505 506 static bool write_i2c_redriver_setting( 507 const struct dc_link *link, 508 bool is_over_340mhz) 509 { 510 DC_LOGGER_INIT(link->ctx->logger); 511 const uint8_t address = 0xF0 >> 1; 512 uint8_t buffer[16] = { 513 [3] = 0x4E, 514 [4] = 0x4E, 515 [5] = 0x4E, 516 [6] = is_over_340mhz ? 0x4E : 0x4A, 517 }; 518 519 const bool success = write_i2c(link, address, buffer, sizeof(buffer)); 520 521 RETIMER_REDRIVER_INFO( 522 "Redriver write, address: 0x%x, buffer: { [3]: 0x%x, 0x%x, 0x%x, 0x%x }, success: %d\n", 523 address, buffer[3], buffer[4], buffer[5], buffer[6], success 524 ); 525 526 if (!success) 527 DC_LOG_DEBUG("Set redriver failed"); 528 return success; 529 } 530 531 static struct link_encoder *get_link_encoder(struct pipe_ctx *pipe_ctx) 532 { 533 struct link_encoder *link_enc 534 = pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment 535 ? pipe_ctx->link_res.dio_link_enc 536 : link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 537 538 ASSERT(link_enc); 539 return link_enc; 540 } 541 542 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 543 { 544 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 545 struct link_encoder *link_enc = get_link_encoder(pipe_ctx); 546 struct cp_psp_stream_config config = {0}; 547 enum dp_panel_mode panel_mode = 548 dp_get_panel_mode(pipe_ctx->stream->link); 549 550 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 551 return; 552 if (link_enc == NULL) 553 return; 554 555 /* otg instance */ 556 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 557 558 /* dig front end */ 559 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 560 if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) 561 config.dig_fe = (uint8_t)pipe_ctx->stream_res.hpo_frl_stream_enc->stream_enc_inst; 562 563 /* stream encoder index */ 564 config.stream_enc_idx = (uint8_t)(pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA); 565 if (dp_is_128b_132b_signal(pipe_ctx)) 566 config.stream_enc_idx = 567 (uint8_t)(pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0); 568 if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) 569 config.stream_enc_idx = 570 (uint8_t)(pipe_ctx->stream_res.hpo_frl_stream_enc->id - ENGINE_ID_HPO_0); 571 572 /* dig back end */ 573 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 574 if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) 575 config.dig_be = (uint8_t)pipe_ctx->stream_res.hpo_frl_stream_enc->stream_enc_inst; 576 577 /* link encoder index */ 578 config.link_enc_idx = (uint8_t)(link_enc->transmitter - TRANSMITTER_UNIPHY_A); 579 if (dp_is_128b_132b_signal(pipe_ctx)) 580 config.link_enc_idx = (uint8_t)pipe_ctx->link_res.hpo_dp_link_enc->inst; 581 if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) 582 config.link_enc_idx = (uint8_t)pipe_ctx->stream->link->hpo_frl_link_enc->inst; 583 584 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 585 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 586 config.dio_output_idx = (uint8_t)(pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1); 587 else 588 config.dio_output_idx = (uint8_t)(link_enc->transmitter - TRANSMITTER_UNIPHY_A); 589 590 591 /* phy index */ 592 config.phy_idx = resource_transmitter_to_phy_idx( 593 pipe_ctx->stream->link->dc, link_enc->transmitter); 594 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 595 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 596 config.phy_idx = 0; 597 598 /* stream properties */ 599 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 600 config.mst_enabled = (pipe_ctx->stream->signal == 601 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 602 config.frl_enabled = dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) ? 1 : 0; 603 config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0; 604 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 605 1 : 0; 606 config.dpms_off = dpms_off; 607 608 /* dm stream context */ 609 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 610 611 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 612 } 613 614 void link_wait_for_unlocked(struct dc_link *link) 615 { 616 unsigned long long enter_timestamp; 617 unsigned long long finish_timestamp; 618 unsigned long long time_taken_in_ns; 619 bool waited = false; 620 621 DC_LOGGER_INIT(link->ctx->logger); 622 623 enter_timestamp = dm_get_timestamp(link->ctx); 624 625 while (link->is_link_locked) { // busy wait 626 if (!waited) { 627 DC_LOG_DC("%s: 0x%p ...", __func__, link); 628 629 waited = true; 630 } 631 632 udelay(1); 633 } 634 635 if (!waited) 636 return; 637 638 finish_timestamp = dm_get_timestamp(link->ctx); 639 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, 640 finish_timestamp, enter_timestamp); 641 642 DC_LOG_DC("%s: 0x%p took %llu ms.", __func__, 643 link, div_u64(time_taken_in_ns, 1000000)); 644 } 645 646 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 647 { 648 struct dc *dc = pipe_ctx->stream->ctx->dc; 649 650 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 651 return; 652 653 if (pipe_ctx->stream->timing.flags.DSC) 654 return; 655 656 dc->hwss.set_avmute(pipe_ctx, enable); 657 } 658 659 static void enable_mst_on_sink(struct dc_link *link, bool enable) 660 { 661 unsigned char mstmCntl = 0; 662 663 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 664 if (enable) 665 mstmCntl |= DP_MST_EN; 666 else 667 mstmCntl &= (~DP_MST_EN); 668 669 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 670 } 671 672 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 673 struct dsc_optc_config *config) 674 { 675 uint32_t precision = 1 << 28; 676 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 677 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 678 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 679 DC_LOGGER_INIT(dsc->ctx->logger); 680 681 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 682 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 683 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 684 */ 685 ll_bytes_per_pix_fraq *= 10000000; 686 ll_bytes_per_pix_fraq /= precision; 687 688 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 689 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 690 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 691 DC_LOG_DSC("\tslice_width %d", config->slice_width); 692 } 693 694 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 695 { 696 struct dc *dc = pipe_ctx->stream->ctx->dc; 697 struct dc_stream_state *stream = pipe_ctx->stream; 698 bool result = false; 699 700 if (dc_is_virtual_signal(stream->signal)) 701 result = true; 702 else 703 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 704 return result; 705 } 706 707 static bool dp_set_hblank_reduction_on_rx(struct pipe_ctx *pipe_ctx) 708 { 709 struct dc *dc = pipe_ctx->stream->ctx->dc; 710 struct dc_stream_state *stream = pipe_ctx->stream; 711 bool result = false; 712 713 if (dc_is_virtual_signal(stream->signal)) 714 result = true; 715 else 716 result = dm_helpers_dp_write_hblank_reduction(dc->ctx, stream); 717 return result; 718 } 719 720 721 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 722 * i.e. after dp_enable_dsc_on_rx() had been called 723 */ 724 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 725 { 726 /* TODO: Move this to HWSS as this is hardware programming sequence not a 727 * link layer sequence 728 */ 729 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 730 struct dc *dc = pipe_ctx->stream->ctx->dc; 731 struct dc_stream_state *stream = pipe_ctx->stream; 732 struct pipe_ctx *odm_pipe; 733 int opp_cnt = 1; 734 struct dccg *dccg = dc->res_pool->dccg; 735 /* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN 736 * register access hung. When DSCCLk is based on refclk, DSCCLk is always a 737 * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is 738 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings 739 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger 740 * this problem. We are implementing a workaround here to keep using dscclk 741 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e 742 * 48Mhz) pixel clock to avoid hitting this problem. 743 */ 744 bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) && 745 stream->timing.pix_clk_100hz > 480000; 746 DC_LOGGER_INIT(dsc->ctx->logger); 747 748 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 749 opp_cnt++; 750 751 if (enable) { 752 struct dsc_config dsc_cfg; 753 struct dsc_optc_config dsc_optc_cfg = {0}; 754 enum optc_dsc_mode optc_dsc_mode; 755 756 /* Enable DSC hw block */ 757 dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding + 758 stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 759 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 760 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 761 dsc_cfg.color_depth = stream->timing.display_color_depth; 762 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 763 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 764 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 765 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 766 dsc_cfg.dsc_padding = 0; 767 768 if (should_use_dto_dscclk) 769 dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); 770 if (!dsc->funcs->dsc_prepare_config(dsc, &dsc_cfg, &dsc_optc_cfg)) { 771 ASSERT(false); 772 return; 773 } 774 dsc->funcs->dsc_set_config(dsc); 775 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 776 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 777 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 778 779 ASSERT(odm_dsc); 780 if (!odm_dsc) 781 return; 782 if (should_use_dto_dscclk) 783 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); 784 if (!odm_dsc->funcs->dsc_prepare_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg)) { 785 ASSERT(false); 786 return; 787 } 788 odm_dsc->funcs->dsc_set_config(odm_dsc); 789 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 790 } 791 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 792 dsc_cfg.pic_width *= opp_cnt; 793 dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; 794 795 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 796 797 /* Enable DSC in encoder */ 798 if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) { 799 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 800 dsc_optc_config_log(dsc, &dsc_optc_cfg); 801 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 802 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 803 optc_dsc_mode, 804 dsc_optc_cfg.bytes_per_pixel, 805 dsc_optc_cfg.slice_width); 806 807 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 808 } 809 else if (dc_is_hdmi_frl_signal(stream->signal)) { 810 uint8_t dsc_packed_pps[128]; 811 struct dc_crtc_timing patched_crtc_timing = stream->timing; 812 813 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.hpo_frl_stream_enc->id); 814 dsc_optc_config_log(dsc, &dsc_optc_cfg); 815 816 /* if we are borrowing from hblank, h_addressable and pic_width need to be adjusted */ 817 if (dc->debug.enable_hblank_borrow) { 818 dsc_cfg.pic_width = stream->timing.h_addressable; 819 } 820 821 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 822 pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_set_dsc_config( 823 pipe_ctx->stream_res.hpo_frl_stream_enc, &patched_crtc_timing, &dsc_packed_pps[0]); 824 } 825 826 /* Enable DSC in OPTC */ 827 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 828 dsc_optc_config_log(dsc, &dsc_optc_cfg); 829 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 830 optc_dsc_mode, 831 dsc_optc_cfg.bytes_per_pixel, 832 dsc_optc_cfg.slice_width); 833 } else { 834 /* disable DSC in OPTC */ 835 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 836 pipe_ctx->stream_res.tg, 837 OPTC_DSC_DISABLED, 0, 0); 838 839 /* disable DSC in stream encoder */ 840 if (dc_is_dp_signal(stream->signal)) { 841 if (dp_is_128b_132b_signal(pipe_ctx)) 842 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 843 pipe_ctx->stream_res.hpo_dp_stream_enc, 844 false, 845 NULL, 846 true); 847 else { 848 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 849 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 850 pipe_ctx->stream_res.stream_enc, 851 OPTC_DSC_DISABLED, 0, 0); 852 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 853 pipe_ctx->stream_res.stream_enc, false, NULL, true); 854 } 855 } 856 else if (dc_is_hdmi_frl_signal(stream->signal)) 857 pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_set_dsc_config( 858 pipe_ctx->stream_res.hpo_frl_stream_enc, &stream->timing, NULL); 859 860 /* disable DSC block */ 861 for (odm_pipe = pipe_ctx; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 862 odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc); 863 /* 864 * TODO - dsc_disconnect is a double buffered register. 865 * by the time we call dsc_disable, dsc may still remain 866 * connected to OPP. In this case OPTC will no longer 867 * get correct pixel data because DSCC is off. However 868 * we also can't wait for the disconnect pending 869 * complete, because this function can be called 870 * with/without OTG master lock acquired. When the lock 871 * is acquired we will never get pending complete until 872 * we release the lock later. So there is no easy way to 873 * solve this problem especially when the lock is 874 * acquired. DSC is a front end hw block it should be 875 * programmed as part of front end sequence, where the 876 * commit sequence without lock and update sequence 877 * with lock are completely separated. However because 878 * we are programming dsc as part of back end link 879 * programming sequence, we don't know if front end OPTC 880 * master lock is acquired. The back end should be 881 * agnostic to front end lock. DSC programming shouldn't 882 * belong to this sequence. 883 */ 884 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 885 if (dccg->funcs->set_ref_dscclk) 886 dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst); 887 } 888 } 889 } 890 891 /* 892 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 893 * hence PPS info packet update need to use frame update instead of immediate update. 894 * Added parameter immediate_update for this purpose. 895 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 896 * which is the only place where a "false" would be passed in for param immediate_update. 897 * 898 * immediate_update is only applicable when DSC is enabled. 899 */ 900 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 901 { 902 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 903 struct dc_stream_state *stream = pipe_ctx->stream; 904 905 if (!pipe_ctx->stream->timing.flags.DSC) 906 return false; 907 908 if (!dsc) 909 return false; 910 911 DC_LOGGER_INIT(dsc->ctx->logger); 912 913 if (enable) { 914 struct dsc_config dsc_cfg; 915 uint8_t dsc_packed_pps[128]; 916 917 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 918 memset(dsc_packed_pps, 0, 128); 919 920 /* Enable DSC hw block */ 921 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 922 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 923 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 924 dsc_cfg.color_depth = stream->timing.display_color_depth; 925 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 926 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 927 dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; 928 929 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 930 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 931 if (dc_is_dp_signal(stream->signal)) { 932 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 933 if (dp_is_128b_132b_signal(pipe_ctx)) 934 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 935 pipe_ctx->stream_res.hpo_dp_stream_enc, 936 true, 937 &dsc_packed_pps[0], 938 immediate_update); 939 else 940 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 941 pipe_ctx->stream_res.stream_enc, 942 true, 943 &dsc_packed_pps[0], 944 immediate_update); 945 } 946 else if (dc_is_hdmi_frl_signal(stream->signal)) { 947 //TODO: bring HDMI FRL in line with DP 948 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.hpo_frl_stream_enc->id); 949 pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_set_dsc_config( 950 pipe_ctx->stream_res.hpo_frl_stream_enc, &stream->timing, &dsc_packed_pps[0]); 951 } 952 } else { 953 /* disable DSC PPS in stream encoder */ 954 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 955 if (dc_is_dp_signal(stream->signal)) { 956 if (dp_is_128b_132b_signal(pipe_ctx)) 957 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 958 pipe_ctx->stream_res.hpo_dp_stream_enc, 959 false, 960 NULL, 961 true); 962 else 963 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 964 pipe_ctx->stream_res.stream_enc, false, NULL, true); 965 } 966 else if (dc_is_hdmi_frl_signal(stream->signal)) 967 //TODO: bring HDMI FRL in line with DP 968 pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_set_dsc_config( 969 pipe_ctx->stream_res.hpo_frl_stream_enc, &stream->timing, NULL); 970 } 971 972 return true; 973 } 974 975 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 976 { 977 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 978 bool result = false; 979 980 if (!pipe_ctx->stream->timing.flags.DSC) 981 goto out; 982 if (!dsc) 983 goto out; 984 985 if (enable) { 986 { 987 link_set_dsc_on_stream(pipe_ctx, true); 988 result = true; 989 } 990 } else { 991 dp_set_dsc_on_rx(pipe_ctx, false); 992 link_set_dsc_on_stream(pipe_ctx, false); 993 result = true; 994 } 995 out: 996 return result; 997 } 998 999 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 1000 { 1001 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1002 1003 if (!pipe_ctx->stream->timing.flags.DSC) 1004 return false; 1005 if (!dsc) 1006 return false; 1007 1008 link_set_dsc_on_stream(pipe_ctx, true); 1009 link_set_dsc_pps_packet(pipe_ctx, true, false); 1010 return true; 1011 } 1012 1013 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 1014 { 1015 struct dc_stream_state *stream = pipe_ctx->stream; 1016 1017 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 1018 struct dc_link *link = stream->link; 1019 union down_spread_ctrl old_downspread; 1020 union down_spread_ctrl new_downspread; 1021 1022 memset(&old_downspread, 0, sizeof(old_downspread)); 1023 1024 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 1025 &old_downspread.raw, sizeof(old_downspread)); 1026 1027 new_downspread.raw = old_downspread.raw; 1028 1029 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1030 (stream->ignore_msa_timing_param) ? 1 : 0; 1031 1032 if (new_downspread.raw != old_downspread.raw) { 1033 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 1034 &new_downspread.raw, sizeof(new_downspread)); 1035 } 1036 1037 } else { 1038 dm_helpers_mst_enable_stream_features(stream); 1039 } 1040 } 1041 1042 static void log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 1043 { 1044 const uint32_t VCP_Y_PRECISION = 1000; 1045 uint64_t vcp_x, vcp_y; 1046 DC_LOGGER_INIT(link->ctx->logger); 1047 1048 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 1049 avg_time_slots_per_mtp = dc_fixpt_add( 1050 avg_time_slots_per_mtp, 1051 dc_fixpt_from_fraction( 1052 1, 1053 2*VCP_Y_PRECISION)); 1054 1055 vcp_x = dc_fixpt_floor( 1056 avg_time_slots_per_mtp); 1057 vcp_y = dc_fixpt_floor( 1058 dc_fixpt_mul_int( 1059 dc_fixpt_sub_int( 1060 avg_time_slots_per_mtp, 1061 dc_fixpt_floor( 1062 avg_time_slots_per_mtp)), 1063 VCP_Y_PRECISION)); 1064 1065 1066 if (link->type == dc_connection_mst_branch) 1067 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 1068 "X: %llu " 1069 "Y: %llu/%d", 1070 vcp_x, 1071 vcp_y, 1072 VCP_Y_PRECISION); 1073 else 1074 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 1075 "X: %llu " 1076 "Y: %llu/%d", 1077 vcp_x, 1078 vcp_y, 1079 VCP_Y_PRECISION); 1080 } 1081 1082 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 1083 { 1084 struct fixed31_32 mbytes_per_sec; 1085 uint32_t link_rate_in_mbytes_per_sec = dp_link_bandwidth_kbps(stream->link, 1086 &stream->link->cur_link_settings); 1087 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 1088 1089 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 1090 1091 return dc_fixpt_div_int(mbytes_per_sec, 54); 1092 } 1093 1094 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 1095 { 1096 struct fixed31_32 peak_kbps; 1097 uint32_t numerator = 0; 1098 uint32_t denominator = 1; 1099 1100 /* 1101 * The 1.006 factor (margin 5300ppm + 300ppm ~ 0.6% as per spec) is not 1102 * required when determining PBN/time slot utilization on the link between 1103 * us and the branch, since that overhead is already accounted for in 1104 * the get_pbn_per_slot function. 1105 * 1106 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1107 * common multiplier to render an integer PBN for all link rate/lane 1108 * counts combinations 1109 * calculate 1110 * peak_kbps *= (64/54) 1111 * peak_kbps /= (8 * 1000) convert to bytes 1112 */ 1113 1114 numerator = 64; 1115 denominator = 54 * 8 * 1000; 1116 kbps *= numerator; 1117 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1118 1119 return peak_kbps; 1120 } 1121 1122 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1123 { 1124 uint64_t kbps; 1125 enum dc_link_encoding_format link_encoding; 1126 1127 if (dp_is_128b_132b_signal(pipe_ctx)) 1128 link_encoding = DC_LINK_ENCODING_DP_128b_132b; 1129 else 1130 link_encoding = DC_LINK_ENCODING_DP_8b_10b; 1131 1132 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding); 1133 return get_pbn_from_bw_in_kbps(kbps); 1134 } 1135 1136 1137 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1138 static void get_lane_status( 1139 struct dc_link *link, 1140 uint32_t lane_count, 1141 union lane_status *status, 1142 union lane_align_status_updated *status_updated) 1143 { 1144 unsigned int lane; 1145 uint8_t dpcd_buf[3] = {0}; 1146 1147 if (status == NULL || status_updated == NULL) { 1148 return; 1149 } 1150 1151 core_link_read_dpcd( 1152 link, 1153 DP_LANE0_1_STATUS, 1154 dpcd_buf, 1155 sizeof(dpcd_buf)); 1156 1157 for (lane = 0; lane < lane_count; lane++) { 1158 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1159 } 1160 1161 status_updated->raw = dpcd_buf[2]; 1162 } 1163 1164 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1165 { 1166 /* 1167 * wait for ACT handled 1168 */ 1169 int i; 1170 const int act_retries = 30; 1171 enum act_return_status result = ACT_FAILED; 1172 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1173 union payload_table_update_status update_status = {0}; 1174 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1175 union lane_align_status_updated lane_status_updated; 1176 DC_LOGGER_INIT(link->ctx->logger); 1177 1178 if (!display_connected || link->aux_access_disabled) 1179 return true; 1180 for (i = 0; i < act_retries; i++) { 1181 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1182 1183 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1184 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1185 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1186 !dp_is_interlane_aligned(lane_status_updated)) { 1187 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1188 "polling for ACT handled."); 1189 result = ACT_LINK_LOST; 1190 break; 1191 } 1192 core_link_read_dpcd( 1193 link, 1194 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1195 &update_status.raw, 1196 1); 1197 1198 if (update_status.bits.ACT_HANDLED == 1) { 1199 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1200 result = ACT_SUCCESS; 1201 break; 1202 } 1203 1204 fsleep(5000); 1205 } 1206 1207 if (result == ACT_FAILED) { 1208 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1209 "continue on. Something is wrong with the branch."); 1210 } 1211 1212 return (result == ACT_SUCCESS); 1213 } 1214 1215 static void update_mst_stream_alloc_table( 1216 struct dc_link *link, 1217 struct stream_encoder *stream_enc, 1218 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1219 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1220 { 1221 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1222 struct link_mst_stream_allocation *dc_alloc; 1223 1224 int i; 1225 int j; 1226 1227 /* if DRM proposed_table has more than one new payload */ 1228 ASSERT(proposed_table->stream_count - 1229 link->mst_stream_alloc_table.stream_count < 2); 1230 1231 /* copy proposed_table to link, add stream encoder */ 1232 for (i = 0; i < proposed_table->stream_count; i++) { 1233 1234 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1235 dc_alloc = 1236 &link->mst_stream_alloc_table.stream_allocations[j]; 1237 1238 if (dc_alloc->vcp_id == 1239 proposed_table->stream_allocations[i].vcp_id) { 1240 1241 work_table[i] = *dc_alloc; 1242 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1243 break; /* exit j loop */ 1244 } 1245 } 1246 1247 /* new vcp_id */ 1248 if (j == link->mst_stream_alloc_table.stream_count) { 1249 work_table[i].vcp_id = 1250 proposed_table->stream_allocations[i].vcp_id; 1251 work_table[i].slot_count = 1252 proposed_table->stream_allocations[i].slot_count; 1253 work_table[i].stream_enc = stream_enc; 1254 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1255 } 1256 } 1257 1258 /* update link->mst_stream_alloc_table with work_table */ 1259 link->mst_stream_alloc_table.stream_count = 1260 proposed_table->stream_count; 1261 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1262 link->mst_stream_alloc_table.stream_allocations[i] = 1263 work_table[i]; 1264 } 1265 1266 static void remove_stream_from_alloc_table( 1267 struct dc_link *link, 1268 struct stream_encoder *dio_stream_enc, 1269 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1270 { 1271 int i = 0; 1272 struct link_mst_stream_allocation_table *table = 1273 &link->mst_stream_alloc_table; 1274 1275 if (hpo_dp_stream_enc) { 1276 for (; i < table->stream_count; i++) 1277 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1278 break; 1279 } else { 1280 for (; i < table->stream_count; i++) 1281 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1282 break; 1283 } 1284 1285 if (i < table->stream_count) { 1286 i++; 1287 for (; i < table->stream_count; i++) 1288 table->stream_allocations[i-1] = table->stream_allocations[i]; 1289 memset(&table->stream_allocations[table->stream_count-1], 0, 1290 sizeof(struct link_mst_stream_allocation)); 1291 table->stream_count--; 1292 } 1293 } 1294 1295 static void print_mst_streams(struct dc_link *link) 1296 { 1297 int i; 1298 1299 DC_LOGGER_INIT(link->ctx->logger); 1300 1301 DC_LOG_MST("%s stream_count: %d:\n", 1302 __func__, 1303 link->mst_stream_alloc_table.stream_count); 1304 1305 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1306 DC_LOG_MST("stream_enc[%d]: %p\n", i, 1307 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc); 1308 DC_LOG_MST("stream[%d].hpo_dp_stream_enc: %p\n", i, 1309 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc); 1310 DC_LOG_MST("stream[%d].vcp_id: %d\n", i, 1311 link->mst_stream_alloc_table.stream_allocations[i].vcp_id); 1312 DC_LOG_MST("stream[%d].slot_count: %d\n", i, 1313 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1314 } 1315 } 1316 1317 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1318 { 1319 struct dc_stream_state *stream = pipe_ctx->stream; 1320 struct dc_link *link = stream->link; 1321 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1322 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1323 bool mst_mode = (link->type == dc_connection_mst_branch); 1324 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1325 const struct dc_link_settings empty_link_settings = {0}; 1326 DC_LOGGER_INIT(link->ctx->logger); 1327 1328 /* deallocate_mst_payload is called before disable link. When mode or 1329 * disable/enable monitor, new stream is created which is not in link 1330 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1331 * should not done. For new mode set, map_resources will get engine 1332 * for new stream, so stream_enc->id should be validated until here. 1333 */ 1334 1335 /* slot X.Y */ 1336 if (link_hwss->ext.set_throttled_vcp_size) 1337 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1338 if (link_hwss->ext.set_hblank_min_symbol_width) 1339 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1340 &empty_link_settings, 1341 avg_time_slots_per_mtp); 1342 1343 if (mst_mode) { 1344 /* when link is in mst mode, reply on mst manager to remove 1345 * payload 1346 */ 1347 if (dm_helpers_dp_mst_write_payload_allocation_table( 1348 stream->ctx, 1349 stream, 1350 &proposed_table, 1351 false)) 1352 update_mst_stream_alloc_table( 1353 link, 1354 pipe_ctx->stream_res.stream_enc, 1355 pipe_ctx->stream_res.hpo_dp_stream_enc, 1356 &proposed_table); 1357 else 1358 DC_LOG_WARNING("Failed to update MST allocation table for idx %d\n", 1359 pipe_ctx->pipe_idx); 1360 } else { 1361 /* when link is no longer in mst mode (mst hub unplugged), 1362 * remove payload with default dc logic 1363 */ 1364 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1365 pipe_ctx->stream_res.hpo_dp_stream_enc); 1366 } 1367 1368 print_mst_streams(link); 1369 1370 /* update mst stream allocation table hardware state */ 1371 if (link_hwss->ext.update_stream_allocation_table == NULL || 1372 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1373 DC_LOG_DEBUG("Unknown encoding format\n"); 1374 return DC_ERROR_UNEXPECTED; 1375 } 1376 1377 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1378 &link->mst_stream_alloc_table); 1379 1380 if (mst_mode) 1381 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1382 stream->ctx, 1383 stream); 1384 1385 dm_helpers_dp_mst_update_mst_mgr_for_deallocation( 1386 stream->ctx, 1387 stream); 1388 1389 return DC_OK; 1390 } 1391 1392 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1393 * because stream_encoder is not exposed to dm 1394 */ 1395 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1396 { 1397 struct dc_stream_state *stream = pipe_ctx->stream; 1398 struct dc_link *link = stream->link; 1399 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1400 struct fixed31_32 avg_time_slots_per_mtp; 1401 struct fixed31_32 pbn; 1402 struct fixed31_32 pbn_per_slot; 1403 enum act_return_status ret; 1404 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1405 DC_LOGGER_INIT(link->ctx->logger); 1406 1407 /* enable_link_dp_mst already check link->enabled_stream_count 1408 * and stream is in link->stream[]. This is called during set mode, 1409 * stream_enc is available. 1410 */ 1411 1412 /* get calculate VC payload for stream: stream_alloc */ 1413 if (dm_helpers_dp_mst_write_payload_allocation_table( 1414 stream->ctx, 1415 stream, 1416 &proposed_table, 1417 true)) 1418 update_mst_stream_alloc_table( 1419 link, 1420 pipe_ctx->stream_res.stream_enc, 1421 pipe_ctx->stream_res.hpo_dp_stream_enc, 1422 &proposed_table); 1423 else 1424 DC_LOG_WARNING("Failed to update MST allocation table for idx %d\n", 1425 pipe_ctx->pipe_idx); 1426 1427 print_mst_streams(link); 1428 1429 ASSERT(proposed_table.stream_count > 0); 1430 1431 /* program DP source TX for payload */ 1432 if (link_hwss->ext.update_stream_allocation_table == NULL || 1433 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1434 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1435 return DC_ERROR_UNEXPECTED; 1436 } 1437 1438 link_hwss->ext.update_stream_allocation_table(link, 1439 &pipe_ctx->link_res, 1440 &link->mst_stream_alloc_table); 1441 1442 /* send down message */ 1443 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1444 stream->ctx, 1445 stream); 1446 1447 if (ret != ACT_LINK_LOST) 1448 dm_helpers_dp_mst_send_payload_allocation( 1449 stream->ctx, 1450 stream); 1451 1452 /* slot X.Y for only current stream */ 1453 pbn_per_slot = get_pbn_per_slot(stream); 1454 if (pbn_per_slot.value == 0) { 1455 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1456 return DC_UNSUPPORTED_VALUE; 1457 } 1458 pbn = get_pbn_from_timing(pipe_ctx); 1459 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1460 1461 log_vcp_x_y(link, avg_time_slots_per_mtp); 1462 1463 if (link_hwss->ext.set_throttled_vcp_size) 1464 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1465 if (link_hwss->ext.set_hblank_min_symbol_width) 1466 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1467 &link->cur_link_settings, 1468 avg_time_slots_per_mtp); 1469 1470 return DC_OK; 1471 } 1472 1473 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1474 const struct dc_stream_state *stream, 1475 const struct dc_link *link) 1476 { 1477 struct fixed31_32 link_bw_effective = 1478 dc_fixpt_from_int( 1479 dp_link_bandwidth_kbps(link, &link->cur_link_settings)); 1480 struct fixed31_32 timeslot_bw_effective = 1481 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1482 struct fixed31_32 timing_bw = 1483 dc_fixpt_from_int( 1484 dc_bandwidth_in_kbps_from_timing(&stream->timing, 1485 dc_link_get_highest_encoding_format(link))); 1486 struct fixed31_32 avg_time_slots_per_mtp = 1487 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1488 1489 return avg_time_slots_per_mtp; 1490 } 1491 1492 1493 static bool write_128b_132b_sst_payload_allocation_table( 1494 const struct dc_stream_state *stream, 1495 struct dc_link *link, 1496 struct link_mst_stream_allocation_table *proposed_table, 1497 bool allocate) 1498 { 1499 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1500 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1501 bool result = false; 1502 uint8_t req_slot_count = 0; 1503 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1504 union payload_table_update_status update_status = { 0 }; 1505 const uint32_t max_retries = 30; 1506 uint32_t retries = 0; 1507 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1508 DC_LOGGER_INIT(link->ctx->logger); 1509 1510 if (allocate) { 1511 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1512 req_slot_count = (uint8_t)dc_fixpt_ceil(avg_time_slots_per_mtp); 1513 /// Validation should filter out modes that exceed link BW 1514 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1515 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1516 return false; 1517 } else { 1518 /// Leave req_slot_count = 0 if allocate is false. 1519 } 1520 1521 proposed_table->stream_count = 1; /// Always 1 stream for SST 1522 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1523 proposed_table->stream_allocations[0].vcp_id = vc_id; 1524 1525 if (!display_connected || link->aux_access_disabled) 1526 return true; 1527 1528 /// Write DPCD 2C0 = 1 to start updating 1529 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1530 core_link_write_dpcd( 1531 link, 1532 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1533 &update_status.raw, 1534 1); 1535 1536 /// Program the changes in DPCD 1C0 - 1C2 1537 ASSERT(vc_id == 1); 1538 core_link_write_dpcd( 1539 link, 1540 DP_PAYLOAD_ALLOCATE_SET, 1541 &vc_id, 1542 1); 1543 1544 ASSERT(start_time_slot == 0); 1545 core_link_write_dpcd( 1546 link, 1547 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1548 &start_time_slot, 1549 1); 1550 1551 core_link_write_dpcd( 1552 link, 1553 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1554 &req_slot_count, 1555 1); 1556 1557 /// Poll till DPCD 2C0 read 1 1558 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1559 1560 while (retries < max_retries) { 1561 if (core_link_read_dpcd( 1562 link, 1563 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1564 &update_status.raw, 1565 1) == DC_OK) { 1566 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1567 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1568 result = true; 1569 break; 1570 } 1571 } else { 1572 union dpcd_rev dpcdRev = {0}; 1573 1574 if (core_link_read_dpcd( 1575 link, 1576 DP_DPCD_REV, 1577 &dpcdRev.raw, 1578 1) != DC_OK) { 1579 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1580 "of sink while polling payload table " 1581 "updated status bit."); 1582 break; 1583 } 1584 } 1585 retries++; 1586 fsleep(5000); 1587 } 1588 1589 if (!result && retries == max_retries) { 1590 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1591 "continue on. Something is wrong with the branch."); 1592 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1593 } 1594 1595 return result; 1596 } 1597 1598 /* 1599 * Payload allocation/deallocation for SST introduced in DP2.0 1600 */ 1601 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1602 bool allocate) 1603 { 1604 struct dc_stream_state *stream = pipe_ctx->stream; 1605 struct dc_link *link = stream->link; 1606 struct link_mst_stream_allocation_table proposed_table = {0}; 1607 struct fixed31_32 avg_time_slots_per_mtp; 1608 const struct dc_link_settings empty_link_settings = {0}; 1609 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1610 DC_LOGGER_INIT(link->ctx->logger); 1611 1612 /* slot X.Y for SST payload deallocate */ 1613 if (!allocate) { 1614 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1615 1616 log_vcp_x_y(link, avg_time_slots_per_mtp); 1617 1618 if (link_hwss->ext.set_throttled_vcp_size) 1619 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1620 avg_time_slots_per_mtp); 1621 if (link_hwss->ext.set_hblank_min_symbol_width) 1622 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1623 &empty_link_settings, 1624 avg_time_slots_per_mtp); 1625 } 1626 1627 /* calculate VC payload and update branch with new payload allocation table*/ 1628 if (!write_128b_132b_sst_payload_allocation_table( 1629 stream, 1630 link, 1631 &proposed_table, 1632 allocate)) { 1633 DC_LOG_ERROR("SST Update Payload: Failed to update " 1634 "allocation table for " 1635 "pipe idx: %d\n", 1636 pipe_ctx->pipe_idx); 1637 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1638 } 1639 1640 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1641 1642 ASSERT(proposed_table.stream_count == 1); 1643 1644 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1645 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1646 "vcp_id: %d " 1647 "slot_count: %d\n", 1648 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1649 proposed_table.stream_allocations[0].vcp_id, 1650 proposed_table.stream_allocations[0].slot_count); 1651 1652 /* program DP source TX for payload */ 1653 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1654 &proposed_table); 1655 1656 /* poll for ACT handled */ 1657 if (!poll_for_allocation_change_trigger(link)) { 1658 // Failures will result in blackscreen and errors logged 1659 BREAK_TO_DEBUGGER(); 1660 } 1661 1662 /* slot X.Y for SST payload allocate */ 1663 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1664 DP_128b_132b_ENCODING) { 1665 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1666 1667 log_vcp_x_y(link, avg_time_slots_per_mtp); 1668 1669 if (link_hwss->ext.set_throttled_vcp_size) 1670 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1671 avg_time_slots_per_mtp); 1672 if (link_hwss->ext.set_hblank_min_symbol_width) 1673 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1674 &link->cur_link_settings, 1675 avg_time_slots_per_mtp); 1676 } 1677 1678 /* Always return DC_OK. 1679 * If part of sequence fails, log failure(s) and show blackscreen 1680 */ 1681 return DC_OK; 1682 } 1683 1684 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1685 { 1686 struct dc_stream_state *stream = pipe_ctx->stream; 1687 struct dc_link *link = stream->link; 1688 struct fixed31_32 avg_time_slots_per_mtp; 1689 struct fixed31_32 pbn; 1690 struct fixed31_32 pbn_per_slot; 1691 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1692 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1693 DC_LOGGER_INIT(link->ctx->logger); 1694 1695 /* decrease throttled vcp size */ 1696 pbn_per_slot = get_pbn_per_slot(stream); 1697 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1698 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1699 1700 if (link_hwss->ext.set_throttled_vcp_size) 1701 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1702 if (link_hwss->ext.set_hblank_min_symbol_width) 1703 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1704 &link->cur_link_settings, 1705 avg_time_slots_per_mtp); 1706 1707 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1708 dm_helpers_dp_mst_send_payload_allocation( 1709 stream->ctx, 1710 stream); 1711 1712 /* notify immediate branch device table update */ 1713 if (dm_helpers_dp_mst_write_payload_allocation_table( 1714 stream->ctx, 1715 stream, 1716 &proposed_table, 1717 true)) { 1718 /* update mst stream allocation table software state */ 1719 update_mst_stream_alloc_table( 1720 link, 1721 pipe_ctx->stream_res.stream_enc, 1722 pipe_ctx->stream_res.hpo_dp_stream_enc, 1723 &proposed_table); 1724 } else { 1725 DC_LOG_WARNING("Failed to update MST allocation table for idx %d\n", 1726 pipe_ctx->pipe_idx); 1727 } 1728 1729 print_mst_streams(link); 1730 1731 ASSERT(proposed_table.stream_count > 0); 1732 1733 /* update mst stream allocation table hardware state */ 1734 if (link_hwss->ext.update_stream_allocation_table == NULL || 1735 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1736 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1737 return DC_ERROR_UNEXPECTED; 1738 } 1739 1740 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1741 &link->mst_stream_alloc_table); 1742 1743 /* poll for immediate branch device ACT handled */ 1744 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1745 stream->ctx, 1746 stream); 1747 1748 return DC_OK; 1749 } 1750 1751 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1752 { 1753 struct dc_stream_state *stream = pipe_ctx->stream; 1754 struct dc_link *link = stream->link; 1755 struct fixed31_32 avg_time_slots_per_mtp; 1756 struct fixed31_32 pbn; 1757 struct fixed31_32 pbn_per_slot; 1758 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1759 enum act_return_status ret; 1760 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1761 DC_LOGGER_INIT(link->ctx->logger); 1762 1763 /* notify immediate branch device table update */ 1764 if (dm_helpers_dp_mst_write_payload_allocation_table( 1765 stream->ctx, 1766 stream, 1767 &proposed_table, 1768 true)) { 1769 /* update mst stream allocation table software state */ 1770 update_mst_stream_alloc_table( 1771 link, 1772 pipe_ctx->stream_res.stream_enc, 1773 pipe_ctx->stream_res.hpo_dp_stream_enc, 1774 &proposed_table); 1775 } 1776 1777 print_mst_streams(link); 1778 1779 ASSERT(proposed_table.stream_count > 0); 1780 1781 /* update mst stream allocation table hardware state */ 1782 if (link_hwss->ext.update_stream_allocation_table == NULL || 1783 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1784 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1785 return DC_ERROR_UNEXPECTED; 1786 } 1787 1788 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1789 &link->mst_stream_alloc_table); 1790 1791 /* poll for immediate branch device ACT handled */ 1792 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1793 stream->ctx, 1794 stream); 1795 1796 if (ret != ACT_LINK_LOST) { 1797 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1798 dm_helpers_dp_mst_send_payload_allocation( 1799 stream->ctx, 1800 stream); 1801 } 1802 1803 /* increase throttled vcp size */ 1804 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1805 pbn_per_slot = get_pbn_per_slot(stream); 1806 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1807 1808 if (link_hwss->ext.set_throttled_vcp_size) 1809 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1810 if (link_hwss->ext.set_hblank_min_symbol_width) 1811 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1812 &link->cur_link_settings, 1813 avg_time_slots_per_mtp); 1814 1815 return DC_OK; 1816 } 1817 1818 static void disable_link_dp(struct dc_link *link, 1819 const struct link_resource *link_res, 1820 enum signal_type signal) 1821 { 1822 struct dc_link_settings link_settings = link->cur_link_settings; 1823 1824 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1825 link->mst_stream_alloc_table.stream_count > 0) 1826 /* disable MST link only when last vc payload is deallocated */ 1827 return; 1828 1829 dp_disable_link_phy(link, link_res, signal); 1830 1831 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1832 if (!link->skip_implict_edp_power_control) 1833 link->dc->hwss.edp_power_control(link, false); 1834 } 1835 1836 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && link->sink_count == 0) 1837 /* set the sink to SST mode after disabling the link */ 1838 enable_mst_on_sink(link, false); 1839 1840 if (link_dp_get_encoding_format(&link_settings) == 1841 DP_8b_10b_ENCODING) { 1842 dp_set_fec_enable(link, link_res, false); 1843 dp_set_fec_ready(link, link_res, false); 1844 } 1845 } 1846 1847 static void disable_link(struct dc_link *link, 1848 const struct link_resource *link_res, 1849 enum signal_type signal) 1850 { 1851 if (dc_is_dp_signal(signal)) { 1852 disable_link_dp(link, link_res, signal); 1853 } else if (signal == SIGNAL_TYPE_VIRTUAL) { 1854 link->dc->hwss.disable_link_output(link, link_res, SIGNAL_TYPE_DISPLAY_PORT); 1855 } else { 1856 link->dc->hwss.disable_link_output(link, link_res, signal); 1857 } 1858 1859 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1860 /* MST disable link only when no stream use the link */ 1861 if (link->mst_stream_alloc_table.stream_count <= 0) 1862 link->link_status.link_active = false; 1863 } else { 1864 link->link_status.link_active = false; 1865 } 1866 } 1867 1868 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1869 { 1870 struct dc_stream_state *stream = pipe_ctx->stream; 1871 struct dc_link *link = stream->link; 1872 enum dc_color_depth display_color_depth; 1873 enum engine_id eng_id; 1874 struct ext_hdmi_settings settings = {0}; 1875 bool is_over_340mhz = false; 1876 bool is_vga_mode = (stream->timing.h_addressable == 640) 1877 && (stream->timing.v_addressable == 480); 1878 struct dc *dc = pipe_ctx->stream->ctx->dc; 1879 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1880 1881 if (stream->phy_pix_clk == 0) 1882 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1883 if (stream->phy_pix_clk > 340000) 1884 is_over_340mhz = true; 1885 if (dc_is_tmds_signal(stream->signal) && stream->phy_pix_clk > 6000000UL) { 1886 ASSERT(false); 1887 return; 1888 } 1889 1890 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1891 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1892 AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1893 if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1894 /* DP159, Retimer settings */ 1895 eng_id = pipe_ctx->stream_res.stream_enc->id; 1896 1897 if (get_ext_hdmi_settings(stream->ctx->dc_bios->integrated_info, eng_id, &settings)) { 1898 write_i2c_retimer_setting(link, is_vga_mode, is_over_340mhz, &settings); 1899 } else { 1900 write_i2c_default_retimer_setting(link, is_vga_mode, is_over_340mhz); 1901 } 1902 } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 1903 /* PI3EQX1204, Redriver settings */ 1904 write_i2c_redriver_setting(link, is_over_340mhz); 1905 } 1906 } 1907 1908 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1909 write_scdc_data( 1910 stream->link->ddc, 1911 stream->phy_pix_clk, 1912 (stream->timing.flags.LTE_340MCSC_SCRAMBLE != 0)); 1913 1914 if (dc->debug.enable_hdmi_idcc) { 1915 union hdmi_idcc_source_id source_id; 1916 1917 source_id.raw = 0xff; 1918 write_idcc_data(stream->link->ddc, HDMI_IDCC_SCOPE_WRITE, 1919 &source_id.raw, 0, 1); 1920 } 1921 memset(&stream->link->cur_link_settings, 0, 1922 sizeof(struct dc_link_settings)); 1923 1924 display_color_depth = stream->timing.display_color_depth; 1925 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1926 display_color_depth = COLOR_DEPTH_888; 1927 1928 /* We need to enable stream encoder for TMDS first to apply 1/4 TMDS 1929 * character clock in case that beyond 340MHz. 1930 */ 1931 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) 1932 link_hwss->setup_stream_encoder(pipe_ctx); 1933 1934 dc->hwss.enable_tmds_link_output( 1935 link, 1936 &pipe_ctx->link_res, 1937 pipe_ctx->stream->signal, 1938 pipe_ctx->clock_source->id, 1939 display_color_depth, 1940 stream->phy_pix_clk); 1941 1942 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1943 read_scdc_data(link->ddc); 1944 } 1945 1946 static enum dc_status enable_link_hdmi_frl(struct pipe_ctx *pipe_ctx) 1947 { 1948 enum link_result link_stat = LINK_RESULT_UNKNOWN; 1949 enum dc_status status = DC_OK; 1950 struct dc_stream_state *stream = pipe_ctx->stream; 1951 struct dc *core_dc = pipe_ctx->stream->ctx->dc; 1952 enum clock_source_id frl_phy_clock_source_id; 1953 bool frl_poll_start = true; 1954 1955 DC_LOGGER_INIT(stream->ctx->logger); 1956 1957 if ((!stream->link->link_enc) || 1958 (!stream->link->hpo_frl_link_enc) || 1959 (!core_dc->res_pool->dccg->funcs->enable_hdmicharclk) || 1960 (!(pipe_ctx->stream_res.hpo_frl_stream_enc))) 1961 return DC_ERROR_UNEXPECTED; 1962 1963 /* get link settings for video mode timing */ 1964 hdmi_frl_decide_link_settings(stream, &stream->link->frl_link_settings, &pipe_ctx->dsc_padding_params); 1965 1966 switch (stream->link->frl_link_settings.frl_link_rate) { 1967 case HDMI_FRL_LINK_RATE_3GBPS: 1968 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 166667; 1969 break; 1970 case HDMI_FRL_LINK_RATE_6GBPS: 1971 case HDMI_FRL_LINK_RATE_6GBPS_4LANE: 1972 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 333333; 1973 break; 1974 case HDMI_FRL_LINK_RATE_8GBPS: 1975 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 444444; 1976 break; 1977 case HDMI_FRL_LINK_RATE_10GBPS: 1978 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 555555; 1979 break; 1980 case HDMI_FRL_LINK_RATE_12GBPS: 1981 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 666667; 1982 break; 1983 case HDMI_FRL_LINK_RATE_16GBPS: 1984 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 888889; 1985 break; 1986 case HDMI_FRL_LINK_RATE_20GBPS: 1987 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 1111111; 1988 break; 1989 case HDMI_FRL_LINK_RATE_24GBPS: 1990 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 1333333; 1991 break; 1992 default: 1993 break; 1994 } 1995 1996 stream->phy_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; 1997 1998 memset(&stream->link->cur_link_settings, 0, 1999 sizeof(struct dc_link_settings)); 2000 2001 /* Find proper clock source in HDMI FRL mode for phy used for DCCG */ 2002 frl_phy_clock_source_id = hdmi_frl_find_matching_phypll(stream->link); 2003 2004 FRL_INFO("FRL LINK TRAINING: LTS:P Start\n"); 2005 /* Setup FRL PHY, enable HDMI character clock and HPO link encoder */ 2006 core_dc->hwss.setup_hdmi_frl_link(stream->link, 2007 (pipe_ctx->stream_res.hpo_frl_stream_enc->id - ENGINE_ID_HPO_0), 2008 frl_phy_clock_source_id); 2009 2010 link_stat = hdmi_frl_perform_link_training_with_retries(stream->link); 2011 2012 if (core_dc->res_pool->dccg->funcs->set_valid_pixel_rate) 2013 core_dc->res_pool->dccg->funcs->set_valid_pixel_rate( 2014 core_dc->res_pool->dccg, 2015 core_dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(core_dc->clk_mgr), 2016 pipe_ctx->stream_res.tg->inst, 2017 (stream->timing.pix_clk_100hz / 10)); 2018 2019 /* Enable FRL packet transmission */ 2020 if (link_stat == LINK_RESULT_SUCCESS) { 2021 stream->link->hpo_frl_link_enc->funcs->enable_output( 2022 stream->link->hpo_frl_link_enc); 2023 if (stream->link->frl_flags.apply_vsdb_rcc_wa) 2024 stream->link->hpo_frl_link_enc->funcs->apply_vsdb_rcc_wa(stream->link->hpo_frl_link_enc); 2025 if (frl_poll_start) 2026 hdmi_frl_poll_start(stream->link->ddc); 2027 2028 FRL_INFO("FRL LINK TRAINING: LTS:P Success\n"); 2029 2030 /* Set HDMISTREAMCLK source to DTBCLK0 and bypass DTO */ 2031 if (core_dc->res_pool->dccg->funcs->set_hdmistreamclk) { 2032 core_dc->res_pool->dccg->funcs->set_hdmistreamclk( 2033 core_dc->res_pool->dccg, 2034 DTBCLK0, 2035 pipe_ctx->stream_res.tg->inst); 2036 } 2037 2038 pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_enable( 2039 pipe_ctx->stream_res.hpo_frl_stream_enc, 2040 pipe_ctx->stream_res.tg->inst); 2041 } else { 2042 status = DC_FAIL_HDMI_FRL_LINK_TRAINING; 2043 stream->link->frl_link_settings.frl_link_rate = 0; 2044 } 2045 2046 return status; 2047 } 2048 2049 static enum dc_status enable_link_dp(struct dc_state *state, 2050 struct pipe_ctx *pipe_ctx) 2051 { 2052 struct dc_stream_state *stream = pipe_ctx->stream; 2053 enum dc_status status; 2054 bool skip_video_pattern; 2055 struct dc_link *link = stream->link; 2056 const struct dc_link_settings *link_settings = 2057 &pipe_ctx->link_config.dp_link_settings; 2058 bool fec_enable; 2059 int i; 2060 bool apply_seamless_boot_optimization = false; 2061 uint32_t bl_oled_enable_delay = 50; // in ms 2062 uint32_t post_oui_delay = 30; // 30ms 2063 /* Reduce link bandwidth between failed link training attempts. */ 2064 bool do_fallback = false; 2065 int lt_attempts = LINK_TRAINING_ATTEMPTS; 2066 2067 // Increase retry count if attempting DP1.x on FIXED_VS link 2068 if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 2069 link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2070 lt_attempts = 10; 2071 2072 // check for seamless boot 2073 for (i = 0; i < state->stream_count; i++) { 2074 if (state->streams[i]->apply_seamless_boot_optimization) { 2075 apply_seamless_boot_optimization = true; 2076 break; 2077 } 2078 } 2079 2080 /* Train with fallback when enabling DPIA link. Conventional links are 2081 * trained with fallback during sink detection. 2082 */ 2083 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 2084 !link->dc->config.enable_dpia_pre_training) 2085 do_fallback = true; 2086 2087 /* 2088 * Temporary w/a to get DP2.0 link rates to work with SST. 2089 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 2090 */ 2091 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 2092 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2093 link->dc->debug.set_mst_en_for_sst) { 2094 enable_mst_on_sink(link, true); 2095 } else if (link->dpcd_caps.is_mst_capable && 2096 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2097 /* disable mst on sink */ 2098 enable_mst_on_sink(link, false); 2099 } 2100 2101 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 2102 /*in case it is not on*/ 2103 if (!link->dc->config.edp_no_power_sequencing) 2104 link->dc->hwss.edp_power_control(link, true); 2105 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 2106 } 2107 2108 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 2109 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 2110 } else { 2111 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 2112 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 2113 if (state->clk_mgr && !apply_seamless_boot_optimization) 2114 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 2115 state, false); 2116 } 2117 2118 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 2119 dpcd_set_source_specific_data(link); 2120 if (link->dpcd_sink_ext_caps.raw != 0) { 2121 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 2122 msleep(post_oui_delay); 2123 } 2124 2125 // similarly, mode switch can cause loss of cable ID 2126 dpcd_write_cable_id_to_dprx(link); 2127 2128 skip_video_pattern = true; 2129 2130 if (link_settings->link_rate == LINK_RATE_LOW) 2131 skip_video_pattern = false; 2132 2133 if (stream->sink_patches.oled_optimize_display_on) 2134 set_default_brightness_aux(link); 2135 2136 if (perform_link_training_with_retries(link_settings, 2137 skip_video_pattern, 2138 lt_attempts, 2139 pipe_ctx, 2140 pipe_ctx->stream->signal, 2141 do_fallback)) { 2142 status = DC_OK; 2143 } else { 2144 status = DC_FAIL_DP_LINK_TRAINING; 2145 } 2146 2147 if (link->preferred_training_settings.fec_enable) 2148 fec_enable = *link->preferred_training_settings.fec_enable; 2149 else 2150 fec_enable = true; 2151 2152 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2153 dp_set_fec_enable(link, &pipe_ctx->link_res, fec_enable); 2154 2155 // during mode set we do DP_SET_POWER off then on, aux writes are lost 2156 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2157 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2158 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2159 if (!stream->sink_patches.oled_optimize_display_on) { 2160 set_default_brightness_aux(link); 2161 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2162 msleep(bl_oled_enable_delay); 2163 edp_backlight_enable_aux(link, true); 2164 } else { 2165 edp_backlight_enable_aux(link, true); 2166 } 2167 } 2168 2169 return status; 2170 } 2171 2172 static enum dc_status enable_link_edp( 2173 struct dc_state *state, 2174 struct pipe_ctx *pipe_ctx) 2175 { 2176 return enable_link_dp(state, pipe_ctx); 2177 } 2178 2179 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2180 { 2181 struct dc_stream_state *stream = pipe_ctx->stream; 2182 struct dc_link *link = stream->link; 2183 struct dc *dc = stream->ctx->dc; 2184 2185 if (stream->phy_pix_clk == 0) 2186 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2187 2188 memset(&stream->link->cur_link_settings, 0, 2189 sizeof(struct dc_link_settings)); 2190 dc->hwss.enable_lvds_link_output( 2191 link, 2192 &pipe_ctx->link_res, 2193 pipe_ctx->clock_source->id, 2194 stream->phy_pix_clk); 2195 2196 } 2197 2198 static enum dc_status enable_link_dp_mst( 2199 struct dc_state *state, 2200 struct pipe_ctx *pipe_ctx) 2201 { 2202 struct dc_link *link = pipe_ctx->stream->link; 2203 unsigned char mstm_cntl = 0; 2204 2205 /* sink signal type after MST branch is MST. Multiple MST sinks 2206 * share one link. Link DP PHY is enable or training only once. 2207 */ 2208 if (link->link_status.link_active) 2209 return DC_OK; 2210 2211 /* clear payload table */ 2212 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1); 2213 if (mstm_cntl & DP_MST_EN) 2214 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2215 2216 /* to make sure the pending down rep can be processed 2217 * before enabling the link 2218 */ 2219 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2220 2221 /* set the sink to MST mode before enabling the link */ 2222 enable_mst_on_sink(link, true); 2223 2224 return enable_link_dp(state, pipe_ctx); 2225 } 2226 2227 static enum dc_status enable_link_analog(struct pipe_ctx *pipe_ctx) 2228 { 2229 struct dc_link *link = pipe_ctx->stream->link; 2230 2231 link->dc->hwss.enable_analog_link_output( 2232 link, pipe_ctx->stream->timing.pix_clk_100hz); 2233 2234 return DC_OK; 2235 } 2236 2237 static enum dc_status enable_link_virtual(struct pipe_ctx *pipe_ctx) 2238 { 2239 struct dc_link *link = pipe_ctx->stream->link; 2240 2241 link->dc->hwss.enable_dp_link_output(link, 2242 &pipe_ctx->link_res, 2243 SIGNAL_TYPE_DISPLAY_PORT, 2244 pipe_ctx->clock_source->id, 2245 &pipe_ctx->link_config.dp_link_settings); 2246 return DC_OK; 2247 } 2248 2249 static enum dc_status enable_link( 2250 struct dc_state *state, 2251 struct pipe_ctx *pipe_ctx) 2252 { 2253 enum dc_status status = DC_ERROR_UNEXPECTED; 2254 struct dc_stream_state *stream = pipe_ctx->stream; 2255 struct dc_link *link = NULL; 2256 2257 if (stream == NULL) 2258 return DC_ERROR_UNEXPECTED; 2259 link = stream->link; 2260 2261 /* There's some scenarios where driver is unloaded with display 2262 * still enabled. When driver is reloaded, it may cause a display 2263 * to not light up if there is a mismatch between old and new 2264 * link settings. Need to call disable first before enabling at 2265 * new link settings. 2266 */ 2267 if (link->link_status.link_active) 2268 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2269 2270 switch (pipe_ctx->stream->signal) { 2271 case SIGNAL_TYPE_DISPLAY_PORT: 2272 status = enable_link_dp(state, pipe_ctx); 2273 break; 2274 case SIGNAL_TYPE_EDP: 2275 status = enable_link_edp(state, pipe_ctx); 2276 break; 2277 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2278 status = enable_link_dp_mst(state, pipe_ctx); 2279 msleep(200); 2280 break; 2281 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2282 case SIGNAL_TYPE_DVI_DUAL_LINK: 2283 case SIGNAL_TYPE_HDMI_TYPE_A: 2284 enable_link_hdmi(pipe_ctx); 2285 status = DC_OK; 2286 break; 2287 case SIGNAL_TYPE_HDMI_FRL: 2288 if (link->local_sink && 2289 link->local_sink->edid_caps.panel_patch.delay_hdmi_link_training && 2290 stream->timing.pix_clk_100hz == 6627500) { 2291 msleep(link->local_sink->edid_caps.panel_patch.delay_hdmi_link_training); 2292 } 2293 status = enable_link_hdmi_frl(pipe_ctx); 2294 break; 2295 case SIGNAL_TYPE_LVDS: 2296 enable_link_lvds(pipe_ctx); 2297 status = DC_OK; 2298 break; 2299 case SIGNAL_TYPE_RGB: 2300 status = enable_link_analog(pipe_ctx); 2301 break; 2302 case SIGNAL_TYPE_VIRTUAL: 2303 status = enable_link_virtual(pipe_ctx); 2304 break; 2305 default: 2306 break; 2307 } 2308 2309 if (status == DC_OK) { 2310 pipe_ctx->stream->link->link_status.link_active = true; 2311 } 2312 2313 return status; 2314 } 2315 2316 static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, int stream_bw) 2317 { 2318 ASSERT(stream->sink); 2319 2320 struct dc_link *link; 2321 int req_bw = stream_bw; 2322 2323 if (!stream->sink) 2324 return false; 2325 2326 link = stream->sink->link; 2327 2328 DC_LOGGER_INIT(link->ctx->logger); 2329 2330 if (!link->dpia_bw_alloc_config.bw_alloc_enabled) 2331 return false; 2332 2333 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2334 int sink_index = -1; 2335 unsigned int i = 0; 2336 2337 for (i = 0; i < link->sink_count; i++) { 2338 if (link->remote_sinks[i] == NULL) 2339 continue; 2340 2341 if (stream->sink->sink_id != link->remote_sinks[i]->sink_id) { 2342 DC_LOG_DEBUG("%s: add remote_sink=%s, request_bw=%d\n", __func__, 2343 (const char *)(&link->remote_sinks[i]->edid_caps.display_name[0]), 2344 link->dpia_bw_alloc_config.remote_sink_req_bw[i]); 2345 2346 req_bw += link->dpia_bw_alloc_config.remote_sink_req_bw[i]; 2347 } else 2348 sink_index = i; 2349 } 2350 2351 if (sink_index >= 0) 2352 link->dpia_bw_alloc_config.remote_sink_req_bw[sink_index] = stream_bw; 2353 else 2354 DC_LOG_WARNING("%s: stream sink_id=%u not found in remote_sinks[]\n", 2355 __func__, stream->sink->sink_id); 2356 2357 if (req_bw) { 2358 link->dpia_bw_alloc_config.dp_overhead = link_dpia_get_dp_overhead(link); 2359 req_bw += link->dpia_bw_alloc_config.dp_overhead; 2360 } else 2361 link->dpia_bw_alloc_config.dp_overhead = 0; 2362 } 2363 2364 link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, req_bw); 2365 2366 return true; 2367 } 2368 2369 static bool allocate_usb4_bandwidth(struct dc_stream_state *stream) 2370 { 2371 ASSERT(stream->sink); 2372 2373 bool ret; 2374 int bw; 2375 2376 if (!stream->sink) 2377 return false; 2378 2379 bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, 2380 dc_link_get_highest_encoding_format(stream->sink->link)); 2381 2382 ret = allocate_usb4_bandwidth_for_stream(stream, bw); 2383 2384 return ret; 2385 } 2386 2387 static bool deallocate_usb4_bandwidth(struct dc_stream_state *stream) 2388 { 2389 bool ret; 2390 2391 ret = allocate_usb4_bandwidth_for_stream(stream, 0); 2392 2393 return ret; 2394 } 2395 2396 static struct vpg *get_vpg(struct pipe_ctx *pipe_ctx) 2397 { 2398 if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) 2399 return pipe_ctx->stream_res.hpo_frl_stream_enc->vpg; 2400 else if (dp_is_128b_132b_signal(pipe_ctx)) 2401 return pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2402 else 2403 return pipe_ctx->stream_res.stream_enc->vpg; 2404 } 2405 2406 enum dc_status link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2407 { 2408 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2409 struct dc_stream_state *stream = pipe_ctx->stream; 2410 struct dc *dc = stream->ctx->dc; 2411 struct dc_link *link = stream->link; 2412 struct vpg *vpg = get_vpg(pipe_ctx); 2413 enum dp_panel_mode panel_mode_dp = dp_get_panel_mode(link); 2414 2415 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2416 2417 if (dc_is_virtual_signal(stream->signal)) 2418 /* No real hardware to program for virtual signals. */ 2419 return DC_DPMS_SKIPPED_HANDSHAKE; 2420 2421 if (stream->sink) { 2422 if (stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2423 stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2424 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d sink_count=%d\n", __func__, 2425 stream->sink->edid_caps.display_name, 2426 stream->signal, link->link_index, link->sink_count); 2427 } 2428 } 2429 2430 link_wait_for_unlocked(link); 2431 2432 if (stream->sink && !stream->sink->edid_caps.panel_patch.skip_avmute) { 2433 if (dc_is_hdmi_signal(stream->signal)) 2434 set_avmute(pipe_ctx, true); 2435 } 2436 2437 dc->hwss.disable_audio_stream(pipe_ctx); 2438 2439 update_psp_stream_config(pipe_ctx, true); 2440 dc->hwss.blank_stream(pipe_ctx); 2441 2442 if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation && 2443 stream->sink) 2444 deallocate_usb4_bandwidth(stream); 2445 2446 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2447 deallocate_mst_payload(pipe_ctx); 2448 else if (dc_is_dp_sst_signal(stream->signal) && 2449 dp_is_128b_132b_signal(pipe_ctx)) 2450 update_sst_payload(pipe_ctx, false); 2451 2452 if (dc_is_hdmi_signal(stream->signal)) { 2453 struct ext_hdmi_settings settings = {0}; 2454 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2455 2456 unsigned short masked_chip_caps = link->chip_caps & 2457 AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2458 //Need to inform that sink is going to use legacy HDMI mode. 2459 write_scdc_data( 2460 link->ddc, 2461 165000,//vbios only handles 165Mhz. 2462 false); 2463 if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2464 /* DP159, Retimer settings */ 2465 if (get_ext_hdmi_settings(stream->ctx->dc_bios->integrated_info, eng_id, &settings)) 2466 write_i2c_retimer_setting(link, false, false, &settings); 2467 else 2468 write_i2c_default_retimer_setting(link, false, false); 2469 } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2470 /* PI3EQX1204, Redriver settings */ 2471 write_i2c_redriver_setting(link, false); 2472 } 2473 } 2474 2475 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2476 !dp_is_128b_132b_signal(pipe_ctx)) { 2477 2478 /* In DP1.x SST mode, our encoder will go to TPS1 2479 * when link is on but stream is off. 2480 * Disabling link before stream will avoid exposing TPS1 pattern 2481 * during the disable sequence as it will confuse some receivers 2482 * state machine. 2483 * In DP2 or MST mode, our encoder will stay video active 2484 */ 2485 disable_link(link, &pipe_ctx->link_res, stream->signal); 2486 dc->hwss.disable_stream(pipe_ctx); 2487 } else { 2488 dc->hwss.disable_stream(pipe_ctx); 2489 disable_link(link, &pipe_ctx->link_res, stream->signal); 2490 } 2491 edp_set_panel_assr(link, pipe_ctx, &panel_mode_dp, false); 2492 2493 if (stream->timing.flags.DSC) { 2494 if (dc_is_dp_signal(stream->signal)) 2495 link_set_dsc_enable(pipe_ctx, false); 2496 else if (dc_is_hdmi_frl_signal(stream->signal)) 2497 link_set_dsc_on_stream(pipe_ctx, false); 2498 } 2499 if (dp_is_128b_132b_signal(pipe_ctx)) { 2500 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2501 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2502 } 2503 2504 if (vpg && vpg->funcs->vpg_powerdown) 2505 vpg->funcs->vpg_powerdown(vpg); 2506 2507 /* for psp not exist case */ 2508 if (link->connector_signal == SIGNAL_TYPE_EDP && dc->debug.psp_disabled_wa) { 2509 /* reset internal save state to default since eDP is off */ 2510 enum dp_panel_mode panel_mode = dp_get_panel_mode(link); 2511 /* since current psp not loaded, we need to reset it to default */ 2512 link->panel_mode = panel_mode; 2513 } 2514 2515 return DC_DPMS_SUCCESS; 2516 } 2517 2518 static enum dc_status link_set_dpms_on_pre_enable_link( 2519 struct dc_state *state, 2520 struct pipe_ctx *pipe_ctx 2521 ) 2522 { 2523 // Used conditionally in ifdef'ed diagnostic builds 2524 (void) state; 2525 2526 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2527 struct dc_stream_state *stream = pipe_ctx->stream; 2528 struct dc *dc = stream->ctx->dc; 2529 struct dc_link *link = stream->link; 2530 2531 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2532 struct vpg *vpg = get_vpg(pipe_ctx); 2533 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2534 bool apply_edp_fast_boot_optimization = 2535 stream->apply_edp_fast_boot_optimization; 2536 2537 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2538 2539 if (dc_is_virtual_signal(stream->signal)) 2540 /* No real hardware to program for virtual signals. */ 2541 return DC_DPMS_SKIPPED_HANDSHAKE; 2542 2543 if (stream->sink) { 2544 if (stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2545 stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2546 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d sink_count=%d\n", __func__, 2547 stream->sink->edid_caps.display_name, 2548 stream->signal, 2549 link->link_index, 2550 link->sink_count); 2551 } 2552 } 2553 2554 link_wait_for_unlocked(link); 2555 2556 if (!dc_is_virtual_signal(stream->signal) 2557 && !dc_is_hdmi_frl_signal(stream->signal) 2558 && !dp_is_128b_132b_signal(pipe_ctx)) { 2559 struct link_encoder *link_enc = get_link_encoder(pipe_ctx); 2560 2561 if (link_enc) 2562 link_enc->funcs->setup( 2563 link_enc, 2564 stream->signal); 2565 } 2566 2567 link->link_state_valid = true; 2568 2569 if (dc_is_hdmi_frl_signal(stream->signal)) 2570 hdmi_frl_decide_link_settings(stream, &link->frl_link_settings, &pipe_ctx->dsc_padding_params); 2571 2572 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2573 if (dp_is_128b_132b_signal(pipe_ctx)) 2574 otg_out_dest = OUT_MUX_HPO_DP; 2575 else if (dc_is_hdmi_frl_signal(stream->signal)) 2576 otg_out_dest = OUT_MUX_HPO_FRL; 2577 else 2578 otg_out_dest = OUT_MUX_DIO; 2579 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2580 } 2581 2582 link_hwss->setup_stream_attribute(pipe_ctx); 2583 2584 stream->apply_edp_fast_boot_optimization = false; 2585 2586 // Enable VPG before building infoframe 2587 if (vpg && vpg->funcs->vpg_poweron) 2588 vpg->funcs->vpg_poweron(vpg); 2589 2590 resource_build_info_frame(pipe_ctx); 2591 dc->hwss.update_info_frame(pipe_ctx); 2592 2593 if (dc_is_dp_signal(stream->signal)) 2594 dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2595 2596 /* Do not touch link on seamless boot optimization. */ 2597 if (stream->apply_seamless_boot_optimization) { 2598 stream->dpms_off = false; 2599 2600 /* Still enable stream features & audio on seamless boot for DP external displays */ 2601 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2602 enable_stream_features(pipe_ctx); 2603 dc->hwss.enable_audio_stream(pipe_ctx); 2604 } 2605 2606 update_psp_stream_config(pipe_ctx, false); 2607 2608 /* Seamless boot: hardware already enabled by BIOS; skip link training. */ 2609 return DC_DPMS_SKIPPED_HANDSHAKE; 2610 } 2611 2612 /* eDP lit up by bios already, no need to enable again. */ 2613 if (stream->signal == SIGNAL_TYPE_EDP && 2614 apply_edp_fast_boot_optimization && 2615 !stream->timing.flags.DSC && 2616 !pipe_ctx->next_odm_pipe) { 2617 stream->dpms_off = false; 2618 update_psp_stream_config(pipe_ctx, false); 2619 2620 if (link->is_dds) { 2621 uint32_t post_oui_delay = 30; // 30ms 2622 2623 dpcd_set_source_specific_data(link); 2624 msleep(post_oui_delay); 2625 } 2626 2627 /* eDP already lit by BIOS; skip standard enable steps. */ 2628 return DC_DPMS_SKIPPED_HANDSHAKE; 2629 } 2630 2631 if (stream->dpms_off) 2632 /* 2633 * Stream is configured as DPMS-off; skip link enable. 2634 * Hardware will NOT be in a fully enabled state after this early exit. 2635 */ 2636 return DC_DPMS_FAILED_INCOMPLETE; 2637 2638 /* For Dp tunneling link, a pending HPD means that we have a race condition between processing 2639 * current link and processing the pending HPD. If we enable the link now, we may end up with a 2640 * link that is not actually connected to a sink. So we skip enabling the link in this case. 2641 */ 2642 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->is_hpd_pending) { 2643 DC_LOG_DEBUG("%s, Link%d HPD is pending, not enable it.\n", __func__, link->link_index); 2644 /* 2645 * Pending HPD on USB4 DPIA link: skip enable to avoid race condition. 2646 * Hardware will NOT be in a fully enabled state after this early exit. 2647 */ 2648 return DC_DPMS_FAILED_INCOMPLETE; 2649 } 2650 2651 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2652 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2653 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2654 * will be automatically set at a later time when the video is enabled 2655 * (DP_VID_STREAM_EN = 1). 2656 */ 2657 if (stream->timing.flags.DSC) { 2658 if (dc_is_dp_signal(stream->signal) || 2659 dc_is_virtual_signal(stream->signal)) 2660 link_set_dsc_enable(pipe_ctx, true); 2661 } 2662 2663 if (link->replay_settings.config.replay_supported && !dc_is_embedded_signal(link->connector_signal)) 2664 dp_setup_replay(link, stream); 2665 2666 return DC_DPMS_SUCCESS; 2667 } 2668 2669 static enum dc_status link_set_dpms_on_enable_link( 2670 struct dc_state *state, 2671 struct pipe_ctx *pipe_ctx 2672 ) 2673 { 2674 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2675 struct dc_stream_state *stream = pipe_ctx->stream; 2676 struct dc_link *link = stream->link; 2677 const enum dc_status status = enable_link(state, pipe_ctx); 2678 2679 if (status == DC_OK) 2680 return DC_DPMS_SUCCESS; 2681 2682 DC_LOG_WARNING("enabling link %u failed: %d\n", link->link_index, status); 2683 2684 /* Abort stream enable *unless* the failure was due to 2685 * DP link training - some DP monitors will recover and 2686 * show the stream anyway. But MST displays can't proceed 2687 * without link training. 2688 */ 2689 switch (status) { 2690 case DC_FAIL_DP_LINK_TRAINING: 2691 case DC_FAIL_HDMI_FRL_LINK_TRAINING: 2692 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) 2693 return DC_DPMS_SUCCESS; 2694 break; 2695 2696 default: 2697 break; 2698 } 2699 2700 if (!link->link_status.link_active) 2701 disable_link(link, &pipe_ctx->link_res, stream->signal); 2702 2703 /* 2704 * Link enable failed; do NOT set skip_remaining so that post_enable_link 2705 * still runs and leaves hardware in a consistent state. 2706 */ 2707 return DC_DPMS_FAILED_HANDSHAKE; 2708 } 2709 2710 static enum dc_status link_set_dpms_on_post_enable_link( 2711 struct dc_state *state, 2712 struct pipe_ctx *pipe_ctx 2713 ) 2714 { 2715 // Used conditionally in ifdef'ed diagnostic builds 2716 (void) state; 2717 2718 struct dc_stream_state *stream = pipe_ctx->stream; 2719 struct dc_link *link = stream->link; 2720 struct hw_sequencer_funcs *hwss = &stream->ctx->dc->hwss; 2721 2722 if (stream->timing.flags.DSC && dc_is_hdmi_frl_signal(stream->signal)) 2723 //TODO: bring HDMI FRL in line with DP 2724 link_set_dsc_on_stream(pipe_ctx, true); 2725 2726 /* turn off otg test pattern if enable */ 2727 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2728 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2729 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2730 COLOR_DEPTH_UNDEFINED); 2731 2732 /* This second call is needed to reconfigure the DIG 2733 * as a workaround for the incorrect value being applied 2734 * from transmitter control. 2735 */ 2736 if (!(dc_is_virtual_signal(stream->signal) || 2737 dc_is_hdmi_frl_signal(stream->signal) || 2738 dp_is_128b_132b_signal(pipe_ctx))) { 2739 struct link_encoder *link_enc = get_link_encoder(pipe_ctx); 2740 2741 if (link_enc) 2742 link_enc->funcs->setup( 2743 link_enc, 2744 stream->signal); 2745 } 2746 2747 hwss->enable_stream(pipe_ctx); 2748 2749 /* Set DPS PPS SDP (AKA "info frames") */ 2750 if (stream->timing.flags.DSC) { 2751 if (dc_is_dp_signal(stream->signal) || 2752 dc_is_virtual_signal(stream->signal)) { 2753 dp_set_dsc_on_rx(pipe_ctx, true); 2754 link_set_dsc_pps_packet(pipe_ctx, true, true); 2755 } 2756 } 2757 2758 if (dc_is_dp_signal(stream->signal)) 2759 dp_set_hblank_reduction_on_rx(pipe_ctx); 2760 2761 if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation) 2762 allocate_usb4_bandwidth(stream); 2763 2764 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2765 allocate_mst_payload(pipe_ctx); 2766 else if (dc_is_dp_sst_signal(stream->signal) && 2767 dp_is_128b_132b_signal(pipe_ctx)) 2768 update_sst_payload(pipe_ctx, true); 2769 2770 /* Corruption was observed on systems with display mux when stream gets 2771 * enabled after the mux switch. Having a small delay between link 2772 * training and stream unblank resolves the corruption issue. 2773 * This is workaround. 2774 */ 2775 if (stream->signal == SIGNAL_TYPE_EDP && 2776 link->is_display_mux_present) 2777 msleep(20); 2778 2779 hwss->unblank_stream(pipe_ctx, 2780 &link->cur_link_settings); 2781 2782 if (stream->sink_patches.delay_ignore_msa > 0) 2783 msleep(stream->sink_patches.delay_ignore_msa); 2784 2785 if (dc_is_dp_signal(stream->signal)) 2786 enable_stream_features(pipe_ctx); 2787 update_psp_stream_config(pipe_ctx, false); 2788 2789 hwss->enable_audio_stream(pipe_ctx); 2790 2791 if (dc_is_hdmi_signal(stream->signal)) 2792 set_avmute(pipe_ctx, false); 2793 2794 return DC_DPMS_SUCCESS; 2795 } 2796 2797 enum dc_status link_set_dpms_on( 2798 struct dc_state *state, 2799 struct pipe_ctx *pipe_ctx 2800 ) 2801 { 2802 enum dc_status result = DC_DPMS_SUCCESS; 2803 2804 typedef enum dc_status (*step)(struct dc_state *, struct pipe_ctx *); 2805 const step steps[] = { 2806 link_set_dpms_on_pre_enable_link, 2807 link_set_dpms_on_enable_link, 2808 link_set_dpms_on_post_enable_link, 2809 }; 2810 2811 for (size_t i = 0; i < ARRAY_SIZE(steps); i++) { 2812 const enum dc_status step_result = steps[i](state, pipe_ctx); 2813 2814 switch (step_result) { 2815 case DC_DPMS_SUCCESS: 2816 case DC_DPMS_FAILED_HANDSHAKE: 2817 // Enum is ordered from "best" to "worst" results 2818 result = max(result, step_result); 2819 break; 2820 2821 case DC_DPMS_SKIPPED_HANDSHAKE: 2822 return step_result; 2823 2824 case DC_DPMS_FAILED_INCOMPLETE: 2825 ASSERT(false); 2826 return step_result; 2827 2828 default: 2829 ASSERT(false); 2830 return step_result; 2831 } 2832 } 2833 2834 return result; 2835 } 2836