1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2023 Intel Corporation
4 */
5
6 #include "i915_drv.h"
7 #include "i915_reg.h"
8 #include "intel_de.h"
9 #include "intel_display_irq.h"
10 #include "intel_display_types.h"
11 #include "intel_dp_aux.h"
12 #include "intel_gmbus.h"
13 #include "intel_hotplug.h"
14 #include "intel_hotplug_irq.h"
15
16 typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
17 typedef u32 (*hotplug_enables_func)(struct intel_encoder *encoder);
18 typedef u32 (*hotplug_mask_func)(enum hpd_pin pin);
19
20 static const u32 hpd_ilk[HPD_NUM_PINS] = {
21 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
22 };
23
24 static const u32 hpd_ivb[HPD_NUM_PINS] = {
25 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
26 };
27
28 static const u32 hpd_bdw[HPD_NUM_PINS] = {
29 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
30 };
31
32 static const u32 hpd_ibx[HPD_NUM_PINS] = {
33 [HPD_CRT] = SDE_CRT_HOTPLUG,
34 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
35 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
36 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
37 [HPD_PORT_D] = SDE_PORTD_HOTPLUG,
38 };
39
40 static const u32 hpd_cpt[HPD_NUM_PINS] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
46 };
47
48 static const u32 hpd_spt[HPD_NUM_PINS] = {
49 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
53 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT,
54 };
55
56 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN,
63 };
64
65 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
72 };
73
74 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
81 };
82
83 static const u32 hpd_bxt[HPD_NUM_PINS] = {
84 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
85 [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B),
86 [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C),
87 };
88
89 static const u32 hpd_gen11[HPD_NUM_PINS] = {
90 [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1),
91 [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2),
92 [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3),
93 [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4),
94 [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5),
95 [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6),
96 };
97
98 static const u32 hpd_xelpdp[HPD_NUM_PINS] = {
99 [HPD_PORT_TC1] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC1) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC1),
100 [HPD_PORT_TC2] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC2) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC2),
101 [HPD_PORT_TC3] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC3) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC3),
102 [HPD_PORT_TC4] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC4) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC4),
103 };
104
105 static const u32 hpd_icp[HPD_NUM_PINS] = {
106 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
107 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
108 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
109 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
110 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
111 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
112 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
113 [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5),
114 [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6),
115 };
116
117 static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
118 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
119 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
120 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
121 [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
122 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
123 };
124
125 static const u32 hpd_mtp[HPD_NUM_PINS] = {
126 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
127 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
128 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
129 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
130 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
131 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
132 };
133
intel_hpd_init_pins(struct drm_i915_private * dev_priv)134 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
135 {
136 struct intel_hotplug *hpd = &dev_priv->display.hotplug;
137
138 if (HAS_GMCH(dev_priv)) {
139 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
140 IS_CHERRYVIEW(dev_priv))
141 hpd->hpd = hpd_status_g4x;
142 else
143 hpd->hpd = hpd_status_i915;
144 return;
145 }
146
147 if (DISPLAY_VER(dev_priv) >= 14)
148 hpd->hpd = hpd_xelpdp;
149 else if (DISPLAY_VER(dev_priv) >= 11)
150 hpd->hpd = hpd_gen11;
151 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
152 hpd->hpd = hpd_bxt;
153 else if (DISPLAY_VER(dev_priv) == 9)
154 hpd->hpd = NULL; /* no north HPD on SKL */
155 else if (DISPLAY_VER(dev_priv) >= 8)
156 hpd->hpd = hpd_bdw;
157 else if (DISPLAY_VER(dev_priv) >= 7)
158 hpd->hpd = hpd_ivb;
159 else
160 hpd->hpd = hpd_ilk;
161
162 if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
163 (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
164 return;
165
166 if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
167 hpd->pch_hpd = hpd_mtp;
168 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
169 hpd->pch_hpd = hpd_sde_dg1;
170 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
171 hpd->pch_hpd = hpd_icp;
172 else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
173 hpd->pch_hpd = hpd_spt;
174 else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv))
175 hpd->pch_hpd = hpd_cpt;
176 else if (HAS_PCH_IBX(dev_priv))
177 hpd->pch_hpd = hpd_ibx;
178 else
179 MISSING_CASE(INTEL_PCH_TYPE(dev_priv));
180 }
181
182 /* For display hotplug interrupt */
i915_hotplug_interrupt_update_locked(struct drm_i915_private * dev_priv,u32 mask,u32 bits)183 void i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
184 u32 mask, u32 bits)
185 {
186 lockdep_assert_held(&dev_priv->irq_lock);
187 drm_WARN_ON(&dev_priv->drm, bits & ~mask);
188
189 intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_EN(dev_priv), mask,
190 bits);
191 }
192
193 /**
194 * i915_hotplug_interrupt_update - update hotplug interrupt enable
195 * @dev_priv: driver private
196 * @mask: bits to update
197 * @bits: bits to enable
198 * NOTE: the HPD enable bits are modified both inside and outside
199 * of an interrupt context. To avoid that read-modify-write cycles
200 * interfer, these bits are protected by a spinlock. Since this
201 * function is usually not called from a context where the lock is
202 * held already, this function acquires the lock itself. A non-locking
203 * version is also available.
204 */
i915_hotplug_interrupt_update(struct drm_i915_private * dev_priv,u32 mask,u32 bits)205 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
206 u32 mask,
207 u32 bits)
208 {
209 spin_lock_irq(&dev_priv->irq_lock);
210 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
211 spin_unlock_irq(&dev_priv->irq_lock);
212 }
213
gen11_port_hotplug_long_detect(enum hpd_pin pin,u32 val)214 static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
215 {
216 switch (pin) {
217 case HPD_PORT_TC1:
218 case HPD_PORT_TC2:
219 case HPD_PORT_TC3:
220 case HPD_PORT_TC4:
221 case HPD_PORT_TC5:
222 case HPD_PORT_TC6:
223 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(pin);
224 default:
225 return false;
226 }
227 }
228
bxt_port_hotplug_long_detect(enum hpd_pin pin,u32 val)229 static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
230 {
231 switch (pin) {
232 case HPD_PORT_A:
233 return val & PORTA_HOTPLUG_LONG_DETECT;
234 case HPD_PORT_B:
235 return val & PORTB_HOTPLUG_LONG_DETECT;
236 case HPD_PORT_C:
237 return val & PORTC_HOTPLUG_LONG_DETECT;
238 default:
239 return false;
240 }
241 }
242
icp_ddi_port_hotplug_long_detect(enum hpd_pin pin,u32 val)243 static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
244 {
245 switch (pin) {
246 case HPD_PORT_A:
247 case HPD_PORT_B:
248 case HPD_PORT_C:
249 case HPD_PORT_D:
250 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(pin);
251 default:
252 return false;
253 }
254 }
255
icp_tc_port_hotplug_long_detect(enum hpd_pin pin,u32 val)256 static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
257 {
258 switch (pin) {
259 case HPD_PORT_TC1:
260 case HPD_PORT_TC2:
261 case HPD_PORT_TC3:
262 case HPD_PORT_TC4:
263 case HPD_PORT_TC5:
264 case HPD_PORT_TC6:
265 return val & ICP_TC_HPD_LONG_DETECT(pin);
266 default:
267 return false;
268 }
269 }
270
spt_port_hotplug2_long_detect(enum hpd_pin pin,u32 val)271 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
272 {
273 switch (pin) {
274 case HPD_PORT_E:
275 return val & PORTE_HOTPLUG_LONG_DETECT;
276 default:
277 return false;
278 }
279 }
280
spt_port_hotplug_long_detect(enum hpd_pin pin,u32 val)281 static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
282 {
283 switch (pin) {
284 case HPD_PORT_A:
285 return val & PORTA_HOTPLUG_LONG_DETECT;
286 case HPD_PORT_B:
287 return val & PORTB_HOTPLUG_LONG_DETECT;
288 case HPD_PORT_C:
289 return val & PORTC_HOTPLUG_LONG_DETECT;
290 case HPD_PORT_D:
291 return val & PORTD_HOTPLUG_LONG_DETECT;
292 default:
293 return false;
294 }
295 }
296
ilk_port_hotplug_long_detect(enum hpd_pin pin,u32 val)297 static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
298 {
299 switch (pin) {
300 case HPD_PORT_A:
301 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
302 default:
303 return false;
304 }
305 }
306
pch_port_hotplug_long_detect(enum hpd_pin pin,u32 val)307 static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
308 {
309 switch (pin) {
310 case HPD_PORT_B:
311 return val & PORTB_HOTPLUG_LONG_DETECT;
312 case HPD_PORT_C:
313 return val & PORTC_HOTPLUG_LONG_DETECT;
314 case HPD_PORT_D:
315 return val & PORTD_HOTPLUG_LONG_DETECT;
316 default:
317 return false;
318 }
319 }
320
i9xx_port_hotplug_long_detect(enum hpd_pin pin,u32 val)321 static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
322 {
323 switch (pin) {
324 case HPD_PORT_B:
325 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
326 case HPD_PORT_C:
327 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
328 case HPD_PORT_D:
329 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
330 default:
331 return false;
332 }
333 }
334
335 /*
336 * Get a bit mask of pins that have triggered, and which ones may be long.
337 * This can be called multiple times with the same masks to accumulate
338 * hotplug detection results from several registers.
339 *
340 * Note that the caller is expected to zero out the masks initially.
341 */
intel_get_hpd_pins(struct drm_i915_private * dev_priv,u32 * pin_mask,u32 * long_mask,u32 hotplug_trigger,u32 dig_hotplug_reg,const u32 hpd[HPD_NUM_PINS],bool long_pulse_detect (enum hpd_pin pin,u32 val))342 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
343 u32 *pin_mask, u32 *long_mask,
344 u32 hotplug_trigger, u32 dig_hotplug_reg,
345 const u32 hpd[HPD_NUM_PINS],
346 bool long_pulse_detect(enum hpd_pin pin, u32 val))
347 {
348 enum hpd_pin pin;
349
350 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
351
352 for_each_hpd_pin(pin) {
353 if ((hpd[pin] & hotplug_trigger) == 0)
354 continue;
355
356 *pin_mask |= BIT(pin);
357
358 if (long_pulse_detect(pin, dig_hotplug_reg))
359 *long_mask |= BIT(pin);
360 }
361
362 drm_dbg(&dev_priv->drm,
363 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
364 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
365 }
366
intel_hpd_enabled_irqs(struct drm_i915_private * dev_priv,const u32 hpd[HPD_NUM_PINS])367 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
368 const u32 hpd[HPD_NUM_PINS])
369 {
370 struct intel_encoder *encoder;
371 u32 enabled_irqs = 0;
372
373 for_each_intel_encoder(&dev_priv->drm, encoder)
374 if (dev_priv->display.hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
375 enabled_irqs |= hpd[encoder->hpd_pin];
376
377 return enabled_irqs;
378 }
379
intel_hpd_hotplug_irqs(struct drm_i915_private * dev_priv,const u32 hpd[HPD_NUM_PINS])380 static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
381 const u32 hpd[HPD_NUM_PINS])
382 {
383 struct intel_encoder *encoder;
384 u32 hotplug_irqs = 0;
385
386 for_each_intel_encoder(&dev_priv->drm, encoder)
387 hotplug_irqs |= hpd[encoder->hpd_pin];
388
389 return hotplug_irqs;
390 }
391
intel_hpd_hotplug_mask(struct drm_i915_private * i915,hotplug_mask_func hotplug_mask)392 static u32 intel_hpd_hotplug_mask(struct drm_i915_private *i915,
393 hotplug_mask_func hotplug_mask)
394 {
395 enum hpd_pin pin;
396 u32 hotplug = 0;
397
398 for_each_hpd_pin(pin)
399 hotplug |= hotplug_mask(pin);
400
401 return hotplug;
402 }
403
intel_hpd_hotplug_enables(struct drm_i915_private * i915,hotplug_enables_func hotplug_enables)404 static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
405 hotplug_enables_func hotplug_enables)
406 {
407 struct intel_encoder *encoder;
408 u32 hotplug = 0;
409
410 for_each_intel_encoder(&i915->drm, encoder)
411 hotplug |= hotplug_enables(encoder);
412
413 return hotplug;
414 }
415
i9xx_hpd_irq_ack(struct drm_i915_private * dev_priv)416 u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
417 {
418 u32 hotplug_status = 0, hotplug_status_mask;
419 int i;
420
421 if (IS_G4X(dev_priv) ||
422 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
423 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
424 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
425 else
426 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
427
428 /*
429 * We absolutely have to clear all the pending interrupt
430 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
431 * interrupt bit won't have an edge, and the i965/g4x
432 * edge triggered IIR will not notice that an interrupt
433 * is still pending. We can't use PORT_HOTPLUG_EN to
434 * guarantee the edge as the act of toggling the enable
435 * bits can itself generate a new hotplug interrupt :(
436 */
437 for (i = 0; i < 10; i++) {
438 u32 tmp = intel_uncore_read(&dev_priv->uncore,
439 PORT_HOTPLUG_STAT(dev_priv)) & hotplug_status_mask;
440
441 if (tmp == 0)
442 return hotplug_status;
443
444 hotplug_status |= tmp;
445 intel_uncore_write(&dev_priv->uncore,
446 PORT_HOTPLUG_STAT(dev_priv),
447 hotplug_status);
448 }
449
450 drm_WARN_ONCE(&dev_priv->drm, 1,
451 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
452 intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT(dev_priv)));
453
454 return hotplug_status;
455 }
456
i9xx_hpd_irq_handler(struct drm_i915_private * dev_priv,u32 hotplug_status)457 void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_status)
458 {
459 struct intel_display *display = &dev_priv->display;
460 u32 pin_mask = 0, long_mask = 0;
461 u32 hotplug_trigger;
462
463 if (IS_G4X(dev_priv) ||
464 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
465 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
466 else
467 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
468
469 if (hotplug_trigger) {
470 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
471 hotplug_trigger, hotplug_trigger,
472 dev_priv->display.hotplug.hpd,
473 i9xx_port_hotplug_long_detect);
474
475 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
476 }
477
478 if ((IS_G4X(dev_priv) ||
479 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
480 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
481 intel_dp_aux_irq_handler(display);
482 }
483
ibx_hpd_irq_handler(struct drm_i915_private * dev_priv,u32 hotplug_trigger)484 void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
485 {
486 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
487
488 /*
489 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
490 * unless we touch the hotplug register, even if hotplug_trigger is
491 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
492 * errors.
493 */
494 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
495 if (!hotplug_trigger) {
496 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
497 PORTD_HOTPLUG_STATUS_MASK |
498 PORTC_HOTPLUG_STATUS_MASK |
499 PORTB_HOTPLUG_STATUS_MASK;
500 dig_hotplug_reg &= ~mask;
501 }
502
503 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
504 if (!hotplug_trigger)
505 return;
506
507 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
508 hotplug_trigger, dig_hotplug_reg,
509 dev_priv->display.hotplug.pch_hpd,
510 pch_port_hotplug_long_detect);
511
512 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
513 }
514
xelpdp_pica_irq_handler(struct drm_i915_private * i915,u32 iir)515 void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
516 {
517 struct intel_display *display = &i915->display;
518 enum hpd_pin pin;
519 u32 hotplug_trigger = iir & (XELPDP_DP_ALT_HOTPLUG_MASK | XELPDP_TBT_HOTPLUG_MASK);
520 u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
521 u32 pin_mask = 0, long_mask = 0;
522
523 if (DISPLAY_VER(i915) >= 20)
524 trigger_aux |= iir & XE2LPD_AUX_DDI_MASK;
525
526 for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
527 u32 val;
528
529 if (!(i915->display.hotplug.hpd[pin] & hotplug_trigger))
530 continue;
531
532 pin_mask |= BIT(pin);
533
534 val = intel_de_read(i915, XELPDP_PORT_HOTPLUG_CTL(pin));
535 intel_de_write(i915, XELPDP_PORT_HOTPLUG_CTL(pin), val);
536
537 if (val & (XELPDP_DP_ALT_HPD_LONG_DETECT | XELPDP_TBT_HPD_LONG_DETECT))
538 long_mask |= BIT(pin);
539 }
540
541 if (pin_mask) {
542 drm_dbg(&i915->drm,
543 "pica hotplug event received, stat 0x%08x, pins 0x%08x, long 0x%08x\n",
544 hotplug_trigger, pin_mask, long_mask);
545
546 intel_hpd_irq_handler(i915, pin_mask, long_mask);
547 }
548
549 if (trigger_aux)
550 intel_dp_aux_irq_handler(display);
551
552 if (!pin_mask && !trigger_aux)
553 drm_err(&i915->drm,
554 "Unexpected DE HPD/AUX interrupt 0x%08x\n", iir);
555 }
556
icp_irq_handler(struct drm_i915_private * dev_priv,u32 pch_iir)557 void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
558 {
559 u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
560 u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;
561 u32 pin_mask = 0, long_mask = 0;
562
563 if (ddi_hotplug_trigger) {
564 u32 dig_hotplug_reg;
565
566 /* Locking due to DSI native GPIO sequences */
567 spin_lock(&dev_priv->irq_lock);
568 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_DDI, 0, 0);
569 spin_unlock(&dev_priv->irq_lock);
570
571 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
572 ddi_hotplug_trigger, dig_hotplug_reg,
573 dev_priv->display.hotplug.pch_hpd,
574 icp_ddi_port_hotplug_long_detect);
575 }
576
577 if (tc_hotplug_trigger) {
578 u32 dig_hotplug_reg;
579
580 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_TC, 0, 0);
581
582 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
583 tc_hotplug_trigger, dig_hotplug_reg,
584 dev_priv->display.hotplug.pch_hpd,
585 icp_tc_port_hotplug_long_detect);
586 }
587
588 if (pin_mask)
589 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
590
591 if (pch_iir & SDE_GMBUS_ICP)
592 intel_gmbus_irq_handler(dev_priv);
593 }
594
spt_irq_handler(struct drm_i915_private * dev_priv,u32 pch_iir)595 void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
596 {
597 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
598 ~SDE_PORTE_HOTPLUG_SPT;
599 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
600 u32 pin_mask = 0, long_mask = 0;
601
602 if (hotplug_trigger) {
603 u32 dig_hotplug_reg;
604
605 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG, 0, 0);
606
607 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
608 hotplug_trigger, dig_hotplug_reg,
609 dev_priv->display.hotplug.pch_hpd,
610 spt_port_hotplug_long_detect);
611 }
612
613 if (hotplug2_trigger) {
614 u32 dig_hotplug_reg;
615
616 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG2, 0, 0);
617
618 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
619 hotplug2_trigger, dig_hotplug_reg,
620 dev_priv->display.hotplug.pch_hpd,
621 spt_port_hotplug2_long_detect);
622 }
623
624 if (pin_mask)
625 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
626
627 if (pch_iir & SDE_GMBUS_CPT)
628 intel_gmbus_irq_handler(dev_priv);
629 }
630
ilk_hpd_irq_handler(struct drm_i915_private * dev_priv,u32 hotplug_trigger)631 void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
632 {
633 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
634
635 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, 0, 0);
636
637 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
638 hotplug_trigger, dig_hotplug_reg,
639 dev_priv->display.hotplug.hpd,
640 ilk_port_hotplug_long_detect);
641
642 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
643 }
644
bxt_hpd_irq_handler(struct drm_i915_private * dev_priv,u32 hotplug_trigger)645 void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
646 {
647 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
648
649 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG, 0, 0);
650
651 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
652 hotplug_trigger, dig_hotplug_reg,
653 dev_priv->display.hotplug.hpd,
654 bxt_port_hotplug_long_detect);
655
656 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
657 }
658
gen11_hpd_irq_handler(struct drm_i915_private * dev_priv,u32 iir)659 void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
660 {
661 u32 pin_mask = 0, long_mask = 0;
662 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
663 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
664
665 if (trigger_tc) {
666 u32 dig_hotplug_reg;
667
668 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, 0, 0);
669
670 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
671 trigger_tc, dig_hotplug_reg,
672 dev_priv->display.hotplug.hpd,
673 gen11_port_hotplug_long_detect);
674 }
675
676 if (trigger_tbt) {
677 u32 dig_hotplug_reg;
678
679 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, 0, 0);
680
681 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
682 trigger_tbt, dig_hotplug_reg,
683 dev_priv->display.hotplug.hpd,
684 gen11_port_hotplug_long_detect);
685 }
686
687 if (pin_mask)
688 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
689 else
690 drm_err(&dev_priv->drm,
691 "Unexpected DE HPD interrupt 0x%08x\n", iir);
692 }
693
ibx_hotplug_mask(enum hpd_pin hpd_pin)694 static u32 ibx_hotplug_mask(enum hpd_pin hpd_pin)
695 {
696 switch (hpd_pin) {
697 case HPD_PORT_A:
698 return PORTA_HOTPLUG_ENABLE;
699 case HPD_PORT_B:
700 return PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_MASK;
701 case HPD_PORT_C:
702 return PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_MASK;
703 case HPD_PORT_D:
704 return PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_MASK;
705 default:
706 return 0;
707 }
708 }
709
ibx_hotplug_enables(struct intel_encoder * encoder)710 static u32 ibx_hotplug_enables(struct intel_encoder *encoder)
711 {
712 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
713
714 switch (encoder->hpd_pin) {
715 case HPD_PORT_A:
716 /*
717 * When CPU and PCH are on the same package, port A
718 * HPD must be enabled in both north and south.
719 */
720 return HAS_PCH_LPT_LP(i915) ?
721 PORTA_HOTPLUG_ENABLE : 0;
722 case HPD_PORT_B:
723 return PORTB_HOTPLUG_ENABLE |
724 PORTB_PULSE_DURATION_2ms;
725 case HPD_PORT_C:
726 return PORTC_HOTPLUG_ENABLE |
727 PORTC_PULSE_DURATION_2ms;
728 case HPD_PORT_D:
729 return PORTD_HOTPLUG_ENABLE |
730 PORTD_PULSE_DURATION_2ms;
731 default:
732 return 0;
733 }
734 }
735
ibx_hpd_detection_setup(struct drm_i915_private * dev_priv)736 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
737 {
738 /*
739 * Enable digital hotplug on the PCH, and configure the DP short pulse
740 * duration to 2ms (which is the minimum in the Display Port spec).
741 * The pulse duration bits are reserved on LPT+.
742 */
743 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
744 intel_hpd_hotplug_mask(dev_priv, ibx_hotplug_mask),
745 intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables));
746 }
747
ibx_hpd_enable_detection(struct intel_encoder * encoder)748 static void ibx_hpd_enable_detection(struct intel_encoder *encoder)
749 {
750 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
751
752 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG,
753 ibx_hotplug_mask(encoder->hpd_pin),
754 ibx_hotplug_enables(encoder));
755 }
756
ibx_hpd_irq_setup(struct drm_i915_private * dev_priv)757 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
758 {
759 u32 hotplug_irqs, enabled_irqs;
760
761 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
762 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
763
764 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
765
766 ibx_hpd_detection_setup(dev_priv);
767 }
768
icp_ddi_hotplug_mask(enum hpd_pin hpd_pin)769 static u32 icp_ddi_hotplug_mask(enum hpd_pin hpd_pin)
770 {
771 switch (hpd_pin) {
772 case HPD_PORT_A:
773 case HPD_PORT_B:
774 case HPD_PORT_C:
775 case HPD_PORT_D:
776 return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin);
777 default:
778 return 0;
779 }
780 }
781
icp_ddi_hotplug_enables(struct intel_encoder * encoder)782 static u32 icp_ddi_hotplug_enables(struct intel_encoder *encoder)
783 {
784 return icp_ddi_hotplug_mask(encoder->hpd_pin);
785 }
786
icp_tc_hotplug_mask(enum hpd_pin hpd_pin)787 static u32 icp_tc_hotplug_mask(enum hpd_pin hpd_pin)
788 {
789 switch (hpd_pin) {
790 case HPD_PORT_TC1:
791 case HPD_PORT_TC2:
792 case HPD_PORT_TC3:
793 case HPD_PORT_TC4:
794 case HPD_PORT_TC5:
795 case HPD_PORT_TC6:
796 return ICP_TC_HPD_ENABLE(hpd_pin);
797 default:
798 return 0;
799 }
800 }
801
icp_tc_hotplug_enables(struct intel_encoder * encoder)802 static u32 icp_tc_hotplug_enables(struct intel_encoder *encoder)
803 {
804 return icp_tc_hotplug_mask(encoder->hpd_pin);
805 }
806
icp_ddi_hpd_detection_setup(struct drm_i915_private * dev_priv)807 static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
808 {
809 intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_DDI,
810 intel_hpd_hotplug_mask(dev_priv, icp_ddi_hotplug_mask),
811 intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables));
812 }
813
icp_ddi_hpd_enable_detection(struct intel_encoder * encoder)814 static void icp_ddi_hpd_enable_detection(struct intel_encoder *encoder)
815 {
816 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
817
818 intel_uncore_rmw(&i915->uncore, SHOTPLUG_CTL_DDI,
819 icp_ddi_hotplug_mask(encoder->hpd_pin),
820 icp_ddi_hotplug_enables(encoder));
821 }
822
icp_tc_hpd_detection_setup(struct drm_i915_private * dev_priv)823 static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
824 {
825 intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_TC,
826 intel_hpd_hotplug_mask(dev_priv, icp_tc_hotplug_mask),
827 intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables));
828 }
829
icp_tc_hpd_enable_detection(struct intel_encoder * encoder)830 static void icp_tc_hpd_enable_detection(struct intel_encoder *encoder)
831 {
832 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
833
834 intel_uncore_rmw(&i915->uncore, SHOTPLUG_CTL_TC,
835 icp_tc_hotplug_mask(encoder->hpd_pin),
836 icp_tc_hotplug_enables(encoder));
837 }
838
icp_hpd_enable_detection(struct intel_encoder * encoder)839 static void icp_hpd_enable_detection(struct intel_encoder *encoder)
840 {
841 icp_ddi_hpd_enable_detection(encoder);
842 icp_tc_hpd_enable_detection(encoder);
843 }
844
icp_hpd_irq_setup(struct drm_i915_private * dev_priv)845 static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
846 {
847 u32 hotplug_irqs, enabled_irqs;
848
849 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
850 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
851
852 if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
853 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
854 else
855 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
856
857 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
858
859 icp_ddi_hpd_detection_setup(dev_priv);
860 icp_tc_hpd_detection_setup(dev_priv);
861 }
862
gen11_hotplug_mask(enum hpd_pin hpd_pin)863 static u32 gen11_hotplug_mask(enum hpd_pin hpd_pin)
864 {
865 switch (hpd_pin) {
866 case HPD_PORT_TC1:
867 case HPD_PORT_TC2:
868 case HPD_PORT_TC3:
869 case HPD_PORT_TC4:
870 case HPD_PORT_TC5:
871 case HPD_PORT_TC6:
872 return GEN11_HOTPLUG_CTL_ENABLE(hpd_pin);
873 default:
874 return 0;
875 }
876 }
877
gen11_hotplug_enables(struct intel_encoder * encoder)878 static u32 gen11_hotplug_enables(struct intel_encoder *encoder)
879 {
880 return gen11_hotplug_mask(encoder->hpd_pin);
881 }
882
dg1_hpd_invert(struct drm_i915_private * i915)883 static void dg1_hpd_invert(struct drm_i915_private *i915)
884 {
885 u32 val = (INVERT_DDIA_HPD |
886 INVERT_DDIB_HPD |
887 INVERT_DDIC_HPD |
888 INVERT_DDID_HPD);
889 intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN1, 0, val);
890 }
891
dg1_hpd_enable_detection(struct intel_encoder * encoder)892 static void dg1_hpd_enable_detection(struct intel_encoder *encoder)
893 {
894 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
895
896 dg1_hpd_invert(i915);
897 icp_hpd_enable_detection(encoder);
898 }
899
dg1_hpd_irq_setup(struct drm_i915_private * dev_priv)900 static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
901 {
902 dg1_hpd_invert(dev_priv);
903 icp_hpd_irq_setup(dev_priv);
904 }
905
gen11_tc_hpd_detection_setup(struct drm_i915_private * dev_priv)906 static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
907 {
908 intel_uncore_rmw(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL,
909 intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask),
910 intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables));
911 }
912
gen11_tc_hpd_enable_detection(struct intel_encoder * encoder)913 static void gen11_tc_hpd_enable_detection(struct intel_encoder *encoder)
914 {
915 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
916
917 intel_uncore_rmw(&i915->uncore, GEN11_TC_HOTPLUG_CTL,
918 gen11_hotplug_mask(encoder->hpd_pin),
919 gen11_hotplug_enables(encoder));
920 }
921
gen11_tbt_hpd_detection_setup(struct drm_i915_private * dev_priv)922 static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
923 {
924 intel_uncore_rmw(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL,
925 intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask),
926 intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables));
927 }
928
gen11_tbt_hpd_enable_detection(struct intel_encoder * encoder)929 static void gen11_tbt_hpd_enable_detection(struct intel_encoder *encoder)
930 {
931 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
932
933 intel_uncore_rmw(&i915->uncore, GEN11_TBT_HOTPLUG_CTL,
934 gen11_hotplug_mask(encoder->hpd_pin),
935 gen11_hotplug_enables(encoder));
936 }
937
gen11_hpd_enable_detection(struct intel_encoder * encoder)938 static void gen11_hpd_enable_detection(struct intel_encoder *encoder)
939 {
940 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
941
942 gen11_tc_hpd_enable_detection(encoder);
943 gen11_tbt_hpd_enable_detection(encoder);
944
945 if (INTEL_PCH_TYPE(i915) >= PCH_ICP)
946 icp_hpd_enable_detection(encoder);
947 }
948
gen11_hpd_irq_setup(struct drm_i915_private * dev_priv)949 static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
950 {
951 u32 hotplug_irqs, enabled_irqs;
952
953 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
954 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
955
956 intel_uncore_rmw(&dev_priv->uncore, GEN11_DE_HPD_IMR, hotplug_irqs,
957 ~enabled_irqs & hotplug_irqs);
958 intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
959
960 gen11_tc_hpd_detection_setup(dev_priv);
961 gen11_tbt_hpd_detection_setup(dev_priv);
962
963 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
964 icp_hpd_irq_setup(dev_priv);
965 }
966
mtp_ddi_hotplug_mask(enum hpd_pin hpd_pin)967 static u32 mtp_ddi_hotplug_mask(enum hpd_pin hpd_pin)
968 {
969 switch (hpd_pin) {
970 case HPD_PORT_A:
971 case HPD_PORT_B:
972 return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin);
973 default:
974 return 0;
975 }
976 }
977
mtp_ddi_hotplug_enables(struct intel_encoder * encoder)978 static u32 mtp_ddi_hotplug_enables(struct intel_encoder *encoder)
979 {
980 return mtp_ddi_hotplug_mask(encoder->hpd_pin);
981 }
982
mtp_tc_hotplug_mask(enum hpd_pin hpd_pin)983 static u32 mtp_tc_hotplug_mask(enum hpd_pin hpd_pin)
984 {
985 switch (hpd_pin) {
986 case HPD_PORT_TC1:
987 case HPD_PORT_TC2:
988 case HPD_PORT_TC3:
989 case HPD_PORT_TC4:
990 return ICP_TC_HPD_ENABLE(hpd_pin);
991 default:
992 return 0;
993 }
994 }
995
mtp_tc_hotplug_enables(struct intel_encoder * encoder)996 static u32 mtp_tc_hotplug_enables(struct intel_encoder *encoder)
997 {
998 return mtp_tc_hotplug_mask(encoder->hpd_pin);
999 }
1000
mtp_ddi_hpd_detection_setup(struct drm_i915_private * i915)1001 static void mtp_ddi_hpd_detection_setup(struct drm_i915_private *i915)
1002 {
1003 intel_de_rmw(i915, SHOTPLUG_CTL_DDI,
1004 intel_hpd_hotplug_mask(i915, mtp_ddi_hotplug_mask),
1005 intel_hpd_hotplug_enables(i915, mtp_ddi_hotplug_enables));
1006 }
1007
mtp_ddi_hpd_enable_detection(struct intel_encoder * encoder)1008 static void mtp_ddi_hpd_enable_detection(struct intel_encoder *encoder)
1009 {
1010 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1011
1012 intel_de_rmw(i915, SHOTPLUG_CTL_DDI,
1013 mtp_ddi_hotplug_mask(encoder->hpd_pin),
1014 mtp_ddi_hotplug_enables(encoder));
1015 }
1016
mtp_tc_hpd_detection_setup(struct drm_i915_private * i915)1017 static void mtp_tc_hpd_detection_setup(struct drm_i915_private *i915)
1018 {
1019 intel_de_rmw(i915, SHOTPLUG_CTL_TC,
1020 intel_hpd_hotplug_mask(i915, mtp_tc_hotplug_mask),
1021 intel_hpd_hotplug_enables(i915, mtp_tc_hotplug_enables));
1022 }
1023
mtp_tc_hpd_enable_detection(struct intel_encoder * encoder)1024 static void mtp_tc_hpd_enable_detection(struct intel_encoder *encoder)
1025 {
1026 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1027
1028 intel_de_rmw(i915, SHOTPLUG_CTL_DDI,
1029 mtp_tc_hotplug_mask(encoder->hpd_pin),
1030 mtp_tc_hotplug_enables(encoder));
1031 }
1032
mtp_hpd_invert(struct drm_i915_private * i915)1033 static void mtp_hpd_invert(struct drm_i915_private *i915)
1034 {
1035 u32 val = (INVERT_DDIA_HPD |
1036 INVERT_DDIB_HPD |
1037 INVERT_DDIC_HPD |
1038 INVERT_TC1_HPD |
1039 INVERT_TC2_HPD |
1040 INVERT_TC3_HPD |
1041 INVERT_TC4_HPD |
1042 INVERT_DDID_HPD_MTP |
1043 INVERT_DDIE_HPD);
1044 intel_de_rmw(i915, SOUTH_CHICKEN1, 0, val);
1045 }
1046
mtp_hpd_enable_detection(struct intel_encoder * encoder)1047 static void mtp_hpd_enable_detection(struct intel_encoder *encoder)
1048 {
1049 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1050
1051 mtp_hpd_invert(i915);
1052 mtp_ddi_hpd_enable_detection(encoder);
1053 mtp_tc_hpd_enable_detection(encoder);
1054 }
1055
mtp_hpd_irq_setup(struct drm_i915_private * i915)1056 static void mtp_hpd_irq_setup(struct drm_i915_private *i915)
1057 {
1058 u32 hotplug_irqs, enabled_irqs;
1059
1060 enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd);
1061 hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd);
1062
1063 intel_de_write(i915, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
1064
1065 mtp_hpd_invert(i915);
1066 ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
1067
1068 mtp_ddi_hpd_detection_setup(i915);
1069 mtp_tc_hpd_detection_setup(i915);
1070 }
1071
xe2lpd_sde_hpd_irq_setup(struct drm_i915_private * i915)1072 static void xe2lpd_sde_hpd_irq_setup(struct drm_i915_private *i915)
1073 {
1074 u32 hotplug_irqs, enabled_irqs;
1075
1076 enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd);
1077 hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd);
1078
1079 ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
1080
1081 mtp_ddi_hpd_detection_setup(i915);
1082 mtp_tc_hpd_detection_setup(i915);
1083 }
1084
is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)1085 static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
1086 {
1087 return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4;
1088 }
1089
_xelpdp_pica_hpd_detection_setup(struct drm_i915_private * i915,enum hpd_pin hpd_pin,bool enable)1090 static void _xelpdp_pica_hpd_detection_setup(struct drm_i915_private *i915,
1091 enum hpd_pin hpd_pin, bool enable)
1092 {
1093 u32 mask = XELPDP_TBT_HOTPLUG_ENABLE |
1094 XELPDP_DP_ALT_HOTPLUG_ENABLE;
1095
1096 if (!is_xelpdp_pica_hpd_pin(hpd_pin))
1097 return;
1098
1099 intel_de_rmw(i915, XELPDP_PORT_HOTPLUG_CTL(hpd_pin),
1100 mask, enable ? mask : 0);
1101 }
1102
xelpdp_pica_hpd_enable_detection(struct intel_encoder * encoder)1103 static void xelpdp_pica_hpd_enable_detection(struct intel_encoder *encoder)
1104 {
1105 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1106
1107 _xelpdp_pica_hpd_detection_setup(i915, encoder->hpd_pin, true);
1108 }
1109
xelpdp_pica_hpd_detection_setup(struct drm_i915_private * i915)1110 static void xelpdp_pica_hpd_detection_setup(struct drm_i915_private *i915)
1111 {
1112 struct intel_encoder *encoder;
1113 u32 available_pins = 0;
1114 enum hpd_pin pin;
1115
1116 BUILD_BUG_ON(BITS_PER_TYPE(available_pins) < HPD_NUM_PINS);
1117
1118 for_each_intel_encoder(&i915->drm, encoder)
1119 available_pins |= BIT(encoder->hpd_pin);
1120
1121 for_each_hpd_pin(pin)
1122 _xelpdp_pica_hpd_detection_setup(i915, pin, available_pins & BIT(pin));
1123 }
1124
xelpdp_hpd_enable_detection(struct intel_encoder * encoder)1125 static void xelpdp_hpd_enable_detection(struct intel_encoder *encoder)
1126 {
1127 xelpdp_pica_hpd_enable_detection(encoder);
1128 mtp_hpd_enable_detection(encoder);
1129 }
1130
xelpdp_hpd_irq_setup(struct drm_i915_private * i915)1131 static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915)
1132 {
1133 u32 hotplug_irqs, enabled_irqs;
1134
1135 enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.hpd);
1136 hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.hpd);
1137
1138 intel_de_rmw(i915, PICAINTERRUPT_IMR, hotplug_irqs,
1139 ~enabled_irqs & hotplug_irqs);
1140 intel_uncore_posting_read(&i915->uncore, PICAINTERRUPT_IMR);
1141
1142 xelpdp_pica_hpd_detection_setup(i915);
1143
1144 if (INTEL_PCH_TYPE(i915) >= PCH_LNL)
1145 xe2lpd_sde_hpd_irq_setup(i915);
1146 else if (INTEL_PCH_TYPE(i915) >= PCH_MTL)
1147 mtp_hpd_irq_setup(i915);
1148 }
1149
spt_hotplug_mask(enum hpd_pin hpd_pin)1150 static u32 spt_hotplug_mask(enum hpd_pin hpd_pin)
1151 {
1152 switch (hpd_pin) {
1153 case HPD_PORT_A:
1154 return PORTA_HOTPLUG_ENABLE;
1155 case HPD_PORT_B:
1156 return PORTB_HOTPLUG_ENABLE;
1157 case HPD_PORT_C:
1158 return PORTC_HOTPLUG_ENABLE;
1159 case HPD_PORT_D:
1160 return PORTD_HOTPLUG_ENABLE;
1161 default:
1162 return 0;
1163 }
1164 }
1165
spt_hotplug_enables(struct intel_encoder * encoder)1166 static u32 spt_hotplug_enables(struct intel_encoder *encoder)
1167 {
1168 return spt_hotplug_mask(encoder->hpd_pin);
1169 }
1170
spt_hotplug2_mask(enum hpd_pin hpd_pin)1171 static u32 spt_hotplug2_mask(enum hpd_pin hpd_pin)
1172 {
1173 switch (hpd_pin) {
1174 case HPD_PORT_E:
1175 return PORTE_HOTPLUG_ENABLE;
1176 default:
1177 return 0;
1178 }
1179 }
1180
spt_hotplug2_enables(struct intel_encoder * encoder)1181 static u32 spt_hotplug2_enables(struct intel_encoder *encoder)
1182 {
1183 return spt_hotplug2_mask(encoder->hpd_pin);
1184 }
1185
spt_hpd_detection_setup(struct drm_i915_private * dev_priv)1186 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
1187 {
1188 /* Display WA #1179 WaHardHangonHotPlug: cnp */
1189 if (HAS_PCH_CNP(dev_priv)) {
1190 intel_uncore_rmw(&dev_priv->uncore, SOUTH_CHICKEN1, CHASSIS_CLK_REQ_DURATION_MASK,
1191 CHASSIS_CLK_REQ_DURATION(0xf));
1192 }
1193
1194 /* Enable digital hotplug on the PCH */
1195 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
1196 intel_hpd_hotplug_mask(dev_priv, spt_hotplug_mask),
1197 intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables));
1198
1199 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG2,
1200 intel_hpd_hotplug_mask(dev_priv, spt_hotplug2_mask),
1201 intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables));
1202 }
1203
spt_hpd_enable_detection(struct intel_encoder * encoder)1204 static void spt_hpd_enable_detection(struct intel_encoder *encoder)
1205 {
1206 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1207
1208 /* Display WA #1179 WaHardHangonHotPlug: cnp */
1209 if (HAS_PCH_CNP(i915)) {
1210 intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN1,
1211 CHASSIS_CLK_REQ_DURATION_MASK,
1212 CHASSIS_CLK_REQ_DURATION(0xf));
1213 }
1214
1215 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG,
1216 spt_hotplug_mask(encoder->hpd_pin),
1217 spt_hotplug_enables(encoder));
1218
1219 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG2,
1220 spt_hotplug2_mask(encoder->hpd_pin),
1221 spt_hotplug2_enables(encoder));
1222 }
1223
spt_hpd_irq_setup(struct drm_i915_private * dev_priv)1224 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
1225 {
1226 u32 hotplug_irqs, enabled_irqs;
1227
1228 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1229 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
1230
1231 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
1232 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
1233
1234 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
1235
1236 spt_hpd_detection_setup(dev_priv);
1237 }
1238
ilk_hotplug_mask(enum hpd_pin hpd_pin)1239 static u32 ilk_hotplug_mask(enum hpd_pin hpd_pin)
1240 {
1241 switch (hpd_pin) {
1242 case HPD_PORT_A:
1243 return DIGITAL_PORTA_HOTPLUG_ENABLE |
1244 DIGITAL_PORTA_PULSE_DURATION_MASK;
1245 default:
1246 return 0;
1247 }
1248 }
1249
ilk_hotplug_enables(struct intel_encoder * encoder)1250 static u32 ilk_hotplug_enables(struct intel_encoder *encoder)
1251 {
1252 switch (encoder->hpd_pin) {
1253 case HPD_PORT_A:
1254 return DIGITAL_PORTA_HOTPLUG_ENABLE |
1255 DIGITAL_PORTA_PULSE_DURATION_2ms;
1256 default:
1257 return 0;
1258 }
1259 }
1260
ilk_hpd_detection_setup(struct drm_i915_private * dev_priv)1261 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
1262 {
1263 /*
1264 * Enable digital hotplug on the CPU, and configure the DP short pulse
1265 * duration to 2ms (which is the minimum in the Display Port spec)
1266 * The pulse duration bits are reserved on HSW+.
1267 */
1268 intel_uncore_rmw(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL,
1269 intel_hpd_hotplug_mask(dev_priv, ilk_hotplug_mask),
1270 intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables));
1271 }
1272
ilk_hpd_enable_detection(struct intel_encoder * encoder)1273 static void ilk_hpd_enable_detection(struct intel_encoder *encoder)
1274 {
1275 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1276
1277 intel_uncore_rmw(&i915->uncore, DIGITAL_PORT_HOTPLUG_CNTRL,
1278 ilk_hotplug_mask(encoder->hpd_pin),
1279 ilk_hotplug_enables(encoder));
1280
1281 ibx_hpd_enable_detection(encoder);
1282 }
1283
ilk_hpd_irq_setup(struct drm_i915_private * dev_priv)1284 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
1285 {
1286 u32 hotplug_irqs, enabled_irqs;
1287
1288 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
1289 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
1290
1291 if (DISPLAY_VER(dev_priv) >= 8)
1292 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
1293 else
1294 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
1295
1296 ilk_hpd_detection_setup(dev_priv);
1297
1298 ibx_hpd_irq_setup(dev_priv);
1299 }
1300
bxt_hotplug_mask(enum hpd_pin hpd_pin)1301 static u32 bxt_hotplug_mask(enum hpd_pin hpd_pin)
1302 {
1303 switch (hpd_pin) {
1304 case HPD_PORT_A:
1305 return PORTA_HOTPLUG_ENABLE | BXT_DDIA_HPD_INVERT;
1306 case HPD_PORT_B:
1307 return PORTB_HOTPLUG_ENABLE | BXT_DDIB_HPD_INVERT;
1308 case HPD_PORT_C:
1309 return PORTC_HOTPLUG_ENABLE | BXT_DDIC_HPD_INVERT;
1310 default:
1311 return 0;
1312 }
1313 }
1314
bxt_hotplug_enables(struct intel_encoder * encoder)1315 static u32 bxt_hotplug_enables(struct intel_encoder *encoder)
1316 {
1317 u32 hotplug;
1318
1319 switch (encoder->hpd_pin) {
1320 case HPD_PORT_A:
1321 hotplug = PORTA_HOTPLUG_ENABLE;
1322 if (intel_bios_encoder_hpd_invert(encoder->devdata))
1323 hotplug |= BXT_DDIA_HPD_INVERT;
1324 return hotplug;
1325 case HPD_PORT_B:
1326 hotplug = PORTB_HOTPLUG_ENABLE;
1327 if (intel_bios_encoder_hpd_invert(encoder->devdata))
1328 hotplug |= BXT_DDIB_HPD_INVERT;
1329 return hotplug;
1330 case HPD_PORT_C:
1331 hotplug = PORTC_HOTPLUG_ENABLE;
1332 if (intel_bios_encoder_hpd_invert(encoder->devdata))
1333 hotplug |= BXT_DDIC_HPD_INVERT;
1334 return hotplug;
1335 default:
1336 return 0;
1337 }
1338 }
1339
bxt_hpd_detection_setup(struct drm_i915_private * dev_priv)1340 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
1341 {
1342 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
1343 intel_hpd_hotplug_mask(dev_priv, bxt_hotplug_mask),
1344 intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables));
1345 }
1346
bxt_hpd_enable_detection(struct intel_encoder * encoder)1347 static void bxt_hpd_enable_detection(struct intel_encoder *encoder)
1348 {
1349 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1350
1351 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG,
1352 bxt_hotplug_mask(encoder->hpd_pin),
1353 bxt_hotplug_enables(encoder));
1354 }
1355
bxt_hpd_irq_setup(struct drm_i915_private * dev_priv)1356 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
1357 {
1358 u32 hotplug_irqs, enabled_irqs;
1359
1360 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
1361 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
1362
1363 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
1364
1365 bxt_hpd_detection_setup(dev_priv);
1366 }
1367
g45_hpd_peg_band_gap_wa(struct drm_i915_private * i915)1368 static void g45_hpd_peg_band_gap_wa(struct drm_i915_private *i915)
1369 {
1370 /*
1371 * For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1372 * 0xd. Failure to do so will result in spurious interrupts being
1373 * generated on the port when a cable is not attached.
1374 */
1375 intel_de_rmw(i915, PEG_BAND_GAP_DATA, 0xf, 0xd);
1376 }
1377
i915_hpd_enable_detection(struct intel_encoder * encoder)1378 static void i915_hpd_enable_detection(struct intel_encoder *encoder)
1379 {
1380 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1381 u32 hotplug_en = hpd_mask_i915[encoder->hpd_pin];
1382
1383 if (IS_G45(i915))
1384 g45_hpd_peg_band_gap_wa(i915);
1385
1386 /* HPD sense and interrupt enable are one and the same */
1387 i915_hotplug_interrupt_update(i915, hotplug_en, hotplug_en);
1388 }
1389
i915_hpd_irq_setup(struct drm_i915_private * dev_priv)1390 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
1391 {
1392 u32 hotplug_en;
1393
1394 lockdep_assert_held(&dev_priv->irq_lock);
1395
1396 /*
1397 * Note HDMI and DP share hotplug bits. Enable bits are the same for all
1398 * generations.
1399 */
1400 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
1401 /*
1402 * Programming the CRT detection parameters tends to generate a spurious
1403 * hotplug event about three seconds later. So just do it once.
1404 */
1405 if (IS_G4X(dev_priv))
1406 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1407 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1408
1409 if (IS_G45(dev_priv))
1410 g45_hpd_peg_band_gap_wa(dev_priv);
1411
1412 /* Ignore TV since it's buggy */
1413 i915_hotplug_interrupt_update_locked(dev_priv,
1414 HOTPLUG_INT_EN_MASK |
1415 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
1416 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
1417 hotplug_en);
1418 }
1419
1420 struct intel_hotplug_funcs {
1421 /* Enable HPD sense and interrupts for all present encoders */
1422 void (*hpd_irq_setup)(struct drm_i915_private *i915);
1423 /* Enable HPD sense for a single encoder */
1424 void (*hpd_enable_detection)(struct intel_encoder *encoder);
1425 };
1426
1427 #define HPD_FUNCS(platform) \
1428 static const struct intel_hotplug_funcs platform##_hpd_funcs = { \
1429 .hpd_irq_setup = platform##_hpd_irq_setup, \
1430 .hpd_enable_detection = platform##_hpd_enable_detection, \
1431 }
1432
1433 HPD_FUNCS(i915);
1434 HPD_FUNCS(xelpdp);
1435 HPD_FUNCS(dg1);
1436 HPD_FUNCS(gen11);
1437 HPD_FUNCS(bxt);
1438 HPD_FUNCS(icp);
1439 HPD_FUNCS(spt);
1440 HPD_FUNCS(ilk);
1441 #undef HPD_FUNCS
1442
intel_hpd_enable_detection(struct intel_encoder * encoder)1443 void intel_hpd_enable_detection(struct intel_encoder *encoder)
1444 {
1445 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1446
1447 if (i915->display.funcs.hotplug)
1448 i915->display.funcs.hotplug->hpd_enable_detection(encoder);
1449 }
1450
intel_hpd_irq_setup(struct drm_i915_private * i915)1451 void intel_hpd_irq_setup(struct drm_i915_private *i915)
1452 {
1453 if (i915->display.irq.display_irqs_enabled && i915->display.funcs.hotplug)
1454 i915->display.funcs.hotplug->hpd_irq_setup(i915);
1455 }
1456
intel_hotplug_irq_init(struct drm_i915_private * i915)1457 void intel_hotplug_irq_init(struct drm_i915_private *i915)
1458 {
1459 intel_hpd_init_pins(i915);
1460
1461 intel_hpd_init_early(i915);
1462
1463 if (HAS_GMCH(i915)) {
1464 if (I915_HAS_HOTPLUG(i915))
1465 i915->display.funcs.hotplug = &i915_hpd_funcs;
1466 } else {
1467 if (HAS_PCH_DG2(i915))
1468 i915->display.funcs.hotplug = &icp_hpd_funcs;
1469 else if (HAS_PCH_DG1(i915))
1470 i915->display.funcs.hotplug = &dg1_hpd_funcs;
1471 else if (DISPLAY_VER(i915) >= 14)
1472 i915->display.funcs.hotplug = &xelpdp_hpd_funcs;
1473 else if (DISPLAY_VER(i915) >= 11)
1474 i915->display.funcs.hotplug = &gen11_hpd_funcs;
1475 else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
1476 i915->display.funcs.hotplug = &bxt_hpd_funcs;
1477 else if (INTEL_PCH_TYPE(i915) >= PCH_ICP)
1478 i915->display.funcs.hotplug = &icp_hpd_funcs;
1479 else if (INTEL_PCH_TYPE(i915) >= PCH_SPT)
1480 i915->display.funcs.hotplug = &spt_hpd_funcs;
1481 else
1482 i915->display.funcs.hotplug = &ilk_hpd_funcs;
1483 }
1484 }
1485