1 /*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #include <linux/device.h>
33 #include <linux/netdevice.h>
34 #include "en.h"
35 #include "en/port.h"
36 #include "en/port_buffer.h"
37
38 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
39
40 #define MLX5E_100MB (100000)
41 #define MLX5E_1GB (1000000)
42
43 #define MLX5E_CEE_STATE_UP 1
44 #define MLX5E_CEE_STATE_DOWN 0
45
46 /* Max supported cable length is 1000 meters */
47 #define MLX5E_MAX_CABLE_LENGTH 1000
48
49 enum {
50 MLX5E_VENDOR_TC_GROUP_NUM = 7,
51 MLX5E_LOWEST_PRIO_GROUP = 0,
52 };
53
54 enum {
55 MLX5_DCB_CHG_RESET,
56 MLX5_DCB_NO_CHG,
57 MLX5_DCB_CHG_NO_RESET,
58 };
59
60 #define MLX5_DSCP_SUPPORTED(mdev) (MLX5_CAP_GEN(mdev, qcam_reg) && \
61 MLX5_CAP_QCAM_REG(mdev, qpts) && \
62 MLX5_CAP_QCAM_REG(mdev, qpdpm))
63
64 static int mlx5e_set_trust_state(struct mlx5e_priv *priv, u8 trust_state);
65 static int mlx5e_set_dscp2prio(struct mlx5e_priv *priv, u8 dscp, u8 prio);
66
67 /* If dcbx mode is non-host set the dcbx mode to host.
68 */
mlx5e_dcbnl_set_dcbx_mode(struct mlx5e_priv * priv,enum mlx5_dcbx_oper_mode mode)69 static int mlx5e_dcbnl_set_dcbx_mode(struct mlx5e_priv *priv,
70 enum mlx5_dcbx_oper_mode mode)
71 {
72 struct mlx5_core_dev *mdev = priv->mdev;
73 u32 param[MLX5_ST_SZ_DW(dcbx_param)];
74 int err;
75
76 err = mlx5_query_port_dcbx_param(mdev, param);
77 if (err)
78 return err;
79
80 MLX5_SET(dcbx_param, param, version_admin, mode);
81 if (mode != MLX5E_DCBX_PARAM_VER_OPER_HOST)
82 MLX5_SET(dcbx_param, param, willing_admin, 1);
83
84 return mlx5_set_port_dcbx_param(mdev, param);
85 }
86
mlx5e_dcbnl_switch_to_host_mode(struct mlx5e_priv * priv)87 static int mlx5e_dcbnl_switch_to_host_mode(struct mlx5e_priv *priv)
88 {
89 struct mlx5e_dcbx *dcbx = &priv->dcbx;
90 int err;
91
92 if (!MLX5_CAP_GEN(priv->mdev, dcbx))
93 return 0;
94
95 if (dcbx->mode == MLX5E_DCBX_PARAM_VER_OPER_HOST)
96 return 0;
97
98 err = mlx5e_dcbnl_set_dcbx_mode(priv, MLX5E_DCBX_PARAM_VER_OPER_HOST);
99 if (err)
100 return err;
101
102 dcbx->mode = MLX5E_DCBX_PARAM_VER_OPER_HOST;
103 return 0;
104 }
105
mlx5e_dcbnl_ieee_getets(struct net_device * netdev,struct ieee_ets * ets)106 static int mlx5e_dcbnl_ieee_getets(struct net_device *netdev,
107 struct ieee_ets *ets)
108 {
109 struct mlx5e_priv *priv = netdev_priv(netdev);
110 struct mlx5_core_dev *mdev = priv->mdev;
111 u8 tc_group[IEEE_8021QAZ_MAX_TCS];
112 bool is_tc_group_6_exist = false;
113 bool is_zero_bw_ets_tc = false;
114 int err = 0;
115 int i;
116
117 if (!MLX5_CAP_GEN(priv->mdev, ets))
118 return -EOPNOTSUPP;
119
120 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
121 err = mlx5_query_port_prio_tc(mdev, i, &ets->prio_tc[i]);
122 if (err)
123 return err;
124 }
125
126 ets->ets_cap = mlx5_max_tc(priv->mdev) + 1;
127 for (i = 0; i < ets->ets_cap; i++) {
128 err = mlx5_query_port_tc_group(mdev, i, &tc_group[i]);
129 if (err)
130 return err;
131
132 err = mlx5_query_port_tc_bw_alloc(mdev, i, &ets->tc_tx_bw[i]);
133 if (err)
134 return err;
135
136 if (ets->tc_tx_bw[i] < MLX5E_MAX_BW_ALLOC &&
137 tc_group[i] == (MLX5E_LOWEST_PRIO_GROUP + 1))
138 is_zero_bw_ets_tc = true;
139
140 if (tc_group[i] == (MLX5E_VENDOR_TC_GROUP_NUM - 1))
141 is_tc_group_6_exist = true;
142 }
143
144 /* Report 0% ets tc if exits*/
145 if (is_zero_bw_ets_tc) {
146 for (i = 0; i < ets->ets_cap; i++)
147 if (tc_group[i] == MLX5E_LOWEST_PRIO_GROUP)
148 ets->tc_tx_bw[i] = 0;
149 }
150
151 /* Update tc_tsa based on fw setting*/
152 for (i = 0; i < ets->ets_cap; i++) {
153 if (ets->tc_tx_bw[i] < MLX5E_MAX_BW_ALLOC)
154 priv->dcbx.tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
155 else if (tc_group[i] == MLX5E_VENDOR_TC_GROUP_NUM &&
156 !is_tc_group_6_exist)
157 priv->dcbx.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
158 }
159 memcpy(ets->tc_tsa, priv->dcbx.tc_tsa, sizeof(ets->tc_tsa));
160
161 return err;
162 }
163
mlx5e_build_tc_group(struct ieee_ets * ets,u8 * tc_group,int max_tc)164 static void mlx5e_build_tc_group(struct ieee_ets *ets, u8 *tc_group, int max_tc)
165 {
166 bool any_tc_mapped_to_ets = false;
167 bool ets_zero_bw = false;
168 int strict_group;
169 int i;
170
171 for (i = 0; i <= max_tc; i++) {
172 if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS) {
173 any_tc_mapped_to_ets = true;
174 if (!ets->tc_tx_bw[i])
175 ets_zero_bw = true;
176 }
177 }
178
179 /* strict group has higher priority than ets group */
180 strict_group = MLX5E_LOWEST_PRIO_GROUP;
181 if (any_tc_mapped_to_ets)
182 strict_group++;
183 if (ets_zero_bw)
184 strict_group++;
185
186 for (i = 0; i <= max_tc; i++) {
187 switch (ets->tc_tsa[i]) {
188 case IEEE_8021QAZ_TSA_VENDOR:
189 tc_group[i] = MLX5E_VENDOR_TC_GROUP_NUM;
190 break;
191 case IEEE_8021QAZ_TSA_STRICT:
192 tc_group[i] = strict_group++;
193 break;
194 case IEEE_8021QAZ_TSA_ETS:
195 tc_group[i] = MLX5E_LOWEST_PRIO_GROUP;
196 if (ets->tc_tx_bw[i] && ets_zero_bw)
197 tc_group[i] = MLX5E_LOWEST_PRIO_GROUP + 1;
198 break;
199 }
200 }
201 }
202
mlx5e_build_tc_tx_bw(struct ieee_ets * ets,u8 * tc_tx_bw,u8 * tc_group,int max_tc)203 static void mlx5e_build_tc_tx_bw(struct ieee_ets *ets, u8 *tc_tx_bw,
204 u8 *tc_group, int max_tc)
205 {
206 int bw_for_ets_zero_bw_tc = 0;
207 int last_ets_zero_bw_tc = -1;
208 int num_ets_zero_bw = 0;
209 int i;
210
211 for (i = 0; i <= max_tc; i++) {
212 if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS &&
213 !ets->tc_tx_bw[i]) {
214 num_ets_zero_bw++;
215 last_ets_zero_bw_tc = i;
216 }
217 }
218
219 if (num_ets_zero_bw)
220 bw_for_ets_zero_bw_tc = MLX5E_MAX_BW_ALLOC / num_ets_zero_bw;
221
222 for (i = 0; i <= max_tc; i++) {
223 switch (ets->tc_tsa[i]) {
224 case IEEE_8021QAZ_TSA_VENDOR:
225 tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
226 break;
227 case IEEE_8021QAZ_TSA_STRICT:
228 tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
229 break;
230 case IEEE_8021QAZ_TSA_ETS:
231 tc_tx_bw[i] = ets->tc_tx_bw[i] ?
232 ets->tc_tx_bw[i] :
233 bw_for_ets_zero_bw_tc;
234 break;
235 }
236 }
237
238 /* Make sure the total bw for ets zero bw group is 100% */
239 if (last_ets_zero_bw_tc != -1)
240 tc_tx_bw[last_ets_zero_bw_tc] +=
241 MLX5E_MAX_BW_ALLOC % num_ets_zero_bw;
242 }
243
244 /* If there are ETS BW 0,
245 * Set ETS group # to 1 for all ETS non zero BW tcs. Their sum must be 100%.
246 * Set group #0 to all the ETS BW 0 tcs and
247 * equally splits the 100% BW between them
248 * Report both group #0 and #1 as ETS type.
249 * All the tcs in group #0 will be reported with 0% BW.
250 */
mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv * priv,struct ieee_ets * ets)251 static int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets)
252 {
253 struct mlx5_core_dev *mdev = priv->mdev;
254 u8 tc_tx_bw[IEEE_8021QAZ_MAX_TCS];
255 u8 tc_group[IEEE_8021QAZ_MAX_TCS];
256 int max_tc = mlx5_max_tc(mdev);
257 int err, i;
258
259 mlx5e_build_tc_group(ets, tc_group, max_tc);
260 mlx5e_build_tc_tx_bw(ets, tc_tx_bw, tc_group, max_tc);
261
262 err = mlx5_set_port_prio_tc(mdev, ets->prio_tc);
263 if (err)
264 return err;
265
266 err = mlx5_set_port_tc_group(mdev, tc_group);
267 if (err)
268 return err;
269
270 err = mlx5_set_port_tc_bw_alloc(mdev, tc_tx_bw);
271
272 if (err)
273 return err;
274
275 memcpy(priv->dcbx.tc_tsa, ets->tc_tsa, sizeof(ets->tc_tsa));
276
277 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
278 netdev_dbg(priv->netdev, "%s: prio_%d <=> tc_%d\n",
279 __func__, i, ets->prio_tc[i]);
280 netdev_dbg(priv->netdev, "%s: tc_%d <=> tx_bw_%d%%, group_%d\n",
281 __func__, i, tc_tx_bw[i], tc_group[i]);
282 }
283
284 return err;
285 }
286
mlx5e_dbcnl_validate_ets(struct net_device * netdev,struct ieee_ets * ets,bool zero_sum_allowed)287 static int mlx5e_dbcnl_validate_ets(struct net_device *netdev,
288 struct ieee_ets *ets,
289 bool zero_sum_allowed)
290 {
291 bool have_ets_tc = false;
292 int bw_sum = 0;
293 int i;
294
295 /* Validate Priority */
296 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
297 if (ets->prio_tc[i] >= MLX5E_MAX_PRIORITY) {
298 netdev_err(netdev,
299 "Failed to validate ETS: priority value greater than max(%d)\n",
300 MLX5E_MAX_PRIORITY);
301 return -EINVAL;
302 }
303 }
304
305 /* Validate Bandwidth Sum */
306 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
307 if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS) {
308 have_ets_tc = true;
309 bw_sum += ets->tc_tx_bw[i];
310 }
311 }
312
313 if (have_ets_tc && bw_sum != 100) {
314 if (bw_sum || (!bw_sum && !zero_sum_allowed))
315 netdev_err(netdev,
316 "Failed to validate ETS: BW sum is illegal\n");
317 return -EINVAL;
318 }
319 return 0;
320 }
321
mlx5e_dcbnl_ieee_setets(struct net_device * netdev,struct ieee_ets * ets)322 static int mlx5e_dcbnl_ieee_setets(struct net_device *netdev,
323 struct ieee_ets *ets)
324 {
325 struct mlx5e_priv *priv = netdev_priv(netdev);
326 int err;
327
328 if (!MLX5_CAP_GEN(priv->mdev, ets))
329 return -EOPNOTSUPP;
330
331 err = mlx5e_dbcnl_validate_ets(netdev, ets, false);
332 if (err)
333 return err;
334
335 err = mlx5e_dcbnl_ieee_setets_core(priv, ets);
336 if (err)
337 return err;
338
339 return 0;
340 }
341
mlx5e_dcbnl_ieee_getpfc(struct net_device * dev,struct ieee_pfc * pfc)342 static int mlx5e_dcbnl_ieee_getpfc(struct net_device *dev,
343 struct ieee_pfc *pfc)
344 {
345 struct mlx5e_priv *priv = netdev_priv(dev);
346 struct mlx5_core_dev *mdev = priv->mdev;
347 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
348 int i;
349
350 pfc->pfc_cap = mlx5_max_tc(mdev) + 1;
351 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
352 pfc->requests[i] = PPORT_PER_PRIO_GET(pstats, i, tx_pause);
353 pfc->indications[i] = PPORT_PER_PRIO_GET(pstats, i, rx_pause);
354 }
355
356 if (MLX5_BUFFER_SUPPORTED(mdev))
357 pfc->delay = priv->dcbx.cable_len;
358
359 return mlx5_query_port_pfc(mdev, &pfc->pfc_en, NULL);
360 }
361
mlx5e_dcbnl_ieee_setpfc(struct net_device * dev,struct ieee_pfc * pfc)362 static int mlx5e_dcbnl_ieee_setpfc(struct net_device *dev,
363 struct ieee_pfc *pfc)
364 {
365 u8 buffer_ownership = MLX5_BUF_OWNERSHIP_UNKNOWN;
366 struct mlx5e_priv *priv = netdev_priv(dev);
367 struct mlx5_core_dev *mdev = priv->mdev;
368 u32 old_cable_len = priv->dcbx.cable_len;
369 struct ieee_pfc pfc_new;
370 u32 changed = 0;
371 u8 curr_pfc_en;
372 int ret = 0;
373
374 /* pfc_en */
375 mlx5_query_port_pfc(mdev, &curr_pfc_en, NULL);
376 if (pfc->pfc_en != curr_pfc_en) {
377 ret = mlx5_set_port_pfc(mdev, pfc->pfc_en, pfc->pfc_en);
378 if (ret)
379 return ret;
380 mlx5_toggle_port_link(mdev);
381 changed |= MLX5E_PORT_BUFFER_PFC;
382 }
383
384 if (pfc->delay &&
385 pfc->delay < MLX5E_MAX_CABLE_LENGTH &&
386 pfc->delay != priv->dcbx.cable_len) {
387 priv->dcbx.cable_len = pfc->delay;
388 changed |= MLX5E_PORT_BUFFER_CABLE_LEN;
389 }
390
391 if (MLX5_BUFFER_SUPPORTED(mdev)) {
392 pfc_new.pfc_en = (changed & MLX5E_PORT_BUFFER_PFC) ? pfc->pfc_en : curr_pfc_en;
393 ret = mlx5_query_port_buffer_ownership(mdev,
394 &buffer_ownership);
395 if (ret)
396 netdev_err(dev,
397 "%s, Failed to get buffer ownership: %d\n",
398 __func__, ret);
399
400 if (buffer_ownership == MLX5_BUF_OWNERSHIP_SW_OWNED)
401 ret = mlx5e_port_manual_buffer_config(priv, changed,
402 dev->mtu, &pfc_new,
403 NULL, NULL);
404
405 if (ret && (changed & MLX5E_PORT_BUFFER_CABLE_LEN))
406 priv->dcbx.cable_len = old_cable_len;
407 }
408
409 if (!ret) {
410 netdev_dbg(dev,
411 "%s: PFC per priority bit mask: 0x%x\n",
412 __func__, pfc->pfc_en);
413 }
414 return ret;
415 }
416
mlx5e_dcbnl_getdcbx(struct net_device * dev)417 static u8 mlx5e_dcbnl_getdcbx(struct net_device *dev)
418 {
419 struct mlx5e_priv *priv = netdev_priv(dev);
420
421 return priv->dcbx.cap;
422 }
423
mlx5e_dcbnl_setdcbx(struct net_device * dev,u8 mode)424 static u8 mlx5e_dcbnl_setdcbx(struct net_device *dev, u8 mode)
425 {
426 struct mlx5e_priv *priv = netdev_priv(dev);
427 struct mlx5e_dcbx *dcbx = &priv->dcbx;
428
429 if (mode & DCB_CAP_DCBX_LLD_MANAGED)
430 return 1;
431
432 if ((!mode) && MLX5_CAP_GEN(priv->mdev, dcbx)) {
433 if (dcbx->mode == MLX5E_DCBX_PARAM_VER_OPER_AUTO)
434 return 0;
435
436 /* set dcbx to fw controlled */
437 if (!mlx5e_dcbnl_set_dcbx_mode(priv, MLX5E_DCBX_PARAM_VER_OPER_AUTO)) {
438 dcbx->mode = MLX5E_DCBX_PARAM_VER_OPER_AUTO;
439 dcbx->cap &= ~DCB_CAP_DCBX_HOST;
440 return 0;
441 }
442
443 return 1;
444 }
445
446 if (!(mode & DCB_CAP_DCBX_HOST))
447 return 1;
448
449 if (mlx5e_dcbnl_switch_to_host_mode(netdev_priv(dev)))
450 return 1;
451
452 dcbx->cap = mode;
453
454 return 0;
455 }
456
mlx5e_dcbnl_ieee_setapp(struct net_device * dev,struct dcb_app * app)457 static int mlx5e_dcbnl_ieee_setapp(struct net_device *dev, struct dcb_app *app)
458 {
459 struct mlx5e_priv *priv = netdev_priv(dev);
460 struct dcb_app temp;
461 bool is_new;
462 int err;
463
464 if (!MLX5_CAP_GEN(priv->mdev, vport_group_manager) ||
465 !MLX5_DSCP_SUPPORTED(priv->mdev))
466 return -EOPNOTSUPP;
467
468 if ((app->selector != IEEE_8021QAZ_APP_SEL_DSCP) ||
469 (app->protocol >= MLX5E_MAX_DSCP))
470 return -EINVAL;
471
472 /* Save the old entry info */
473 temp.selector = IEEE_8021QAZ_APP_SEL_DSCP;
474 temp.protocol = app->protocol;
475 temp.priority = priv->dcbx_dp.dscp2prio[app->protocol];
476
477 /* Check if need to switch to dscp trust state */
478 if (!priv->dcbx.dscp_app_cnt) {
479 err = mlx5e_set_trust_state(priv, MLX5_QPTS_TRUST_DSCP);
480 if (err)
481 return err;
482 }
483
484 /* Skip the fw command if new and old mapping are the same */
485 if (app->priority != priv->dcbx_dp.dscp2prio[app->protocol]) {
486 err = mlx5e_set_dscp2prio(priv, app->protocol, app->priority);
487 if (err)
488 goto fw_err;
489 }
490
491 /* Delete the old entry if exists */
492 is_new = false;
493 err = dcb_ieee_delapp(dev, &temp);
494 if (err)
495 is_new = true;
496
497 /* Add new entry and update counter */
498 err = dcb_ieee_setapp(dev, app);
499 if (err)
500 return err;
501
502 if (is_new)
503 priv->dcbx.dscp_app_cnt++;
504
505 return err;
506
507 fw_err:
508 mlx5e_set_trust_state(priv, MLX5_QPTS_TRUST_PCP);
509 return err;
510 }
511
mlx5e_dcbnl_ieee_delapp(struct net_device * dev,struct dcb_app * app)512 static int mlx5e_dcbnl_ieee_delapp(struct net_device *dev, struct dcb_app *app)
513 {
514 struct mlx5e_priv *priv = netdev_priv(dev);
515 int err;
516
517 if (!MLX5_CAP_GEN(priv->mdev, vport_group_manager) ||
518 !MLX5_DSCP_SUPPORTED(priv->mdev))
519 return -EOPNOTSUPP;
520
521 if ((app->selector != IEEE_8021QAZ_APP_SEL_DSCP) ||
522 (app->protocol >= MLX5E_MAX_DSCP))
523 return -EINVAL;
524
525 /* Skip if no dscp app entry */
526 if (!priv->dcbx.dscp_app_cnt)
527 return -ENOENT;
528
529 /* Check if the entry matches fw setting */
530 if (app->priority != priv->dcbx_dp.dscp2prio[app->protocol])
531 return -ENOENT;
532
533 /* Delete the app entry */
534 err = dcb_ieee_delapp(dev, app);
535 if (err)
536 return err;
537
538 /* Reset the priority mapping back to zero */
539 err = mlx5e_set_dscp2prio(priv, app->protocol, 0);
540 if (err)
541 goto fw_err;
542
543 priv->dcbx.dscp_app_cnt--;
544
545 /* Check if need to switch to pcp trust state */
546 if (!priv->dcbx.dscp_app_cnt)
547 err = mlx5e_set_trust_state(priv, MLX5_QPTS_TRUST_PCP);
548
549 return err;
550
551 fw_err:
552 mlx5e_set_trust_state(priv, MLX5_QPTS_TRUST_PCP);
553 return err;
554 }
555
mlx5e_dcbnl_ieee_getmaxrate(struct net_device * netdev,struct ieee_maxrate * maxrate)556 static int mlx5e_dcbnl_ieee_getmaxrate(struct net_device *netdev,
557 struct ieee_maxrate *maxrate)
558 {
559 struct mlx5e_priv *priv = netdev_priv(netdev);
560 struct mlx5_core_dev *mdev = priv->mdev;
561 u8 max_bw_value[IEEE_8021QAZ_MAX_TCS];
562 u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS];
563 int err;
564 int i;
565
566 err = mlx5_query_port_ets_rate_limit(mdev, max_bw_value, max_bw_unit);
567 if (err)
568 return err;
569
570 memset(maxrate->tc_maxrate, 0, sizeof(maxrate->tc_maxrate));
571
572 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
573 switch (max_bw_unit[i]) {
574 case MLX5_100_MBPS_UNIT:
575 maxrate->tc_maxrate[i] = max_bw_value[i] * MLX5E_100MB;
576 break;
577 case MLX5_GBPS_UNIT:
578 maxrate->tc_maxrate[i] = max_bw_value[i] * MLX5E_1GB;
579 break;
580 case MLX5_BW_NO_LIMIT:
581 break;
582 default:
583 WARN(true, "non-supported BW unit");
584 break;
585 }
586 }
587
588 return 0;
589 }
590
mlx5e_dcbnl_ieee_setmaxrate(struct net_device * netdev,struct ieee_maxrate * maxrate)591 static int mlx5e_dcbnl_ieee_setmaxrate(struct net_device *netdev,
592 struct ieee_maxrate *maxrate)
593 {
594 struct mlx5e_priv *priv = netdev_priv(netdev);
595 struct mlx5_core_dev *mdev = priv->mdev;
596 u8 max_bw_value[IEEE_8021QAZ_MAX_TCS];
597 u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS];
598 __u64 upper_limit_mbps = roundup(255 * MLX5E_100MB, MLX5E_1GB);
599 int i;
600
601 memset(max_bw_value, 0, sizeof(max_bw_value));
602 memset(max_bw_unit, 0, sizeof(max_bw_unit));
603
604 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
605 if (!maxrate->tc_maxrate[i]) {
606 max_bw_unit[i] = MLX5_BW_NO_LIMIT;
607 continue;
608 }
609 if (maxrate->tc_maxrate[i] < upper_limit_mbps) {
610 max_bw_value[i] = div_u64(maxrate->tc_maxrate[i],
611 MLX5E_100MB);
612 max_bw_value[i] = max_bw_value[i] ? max_bw_value[i] : 1;
613 max_bw_unit[i] = MLX5_100_MBPS_UNIT;
614 } else {
615 max_bw_value[i] = div_u64(maxrate->tc_maxrate[i],
616 MLX5E_1GB);
617 max_bw_unit[i] = MLX5_GBPS_UNIT;
618 }
619 }
620
621 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
622 netdev_dbg(netdev, "%s: tc_%d <=> max_bw %d Gbps\n",
623 __func__, i, max_bw_value[i]);
624 }
625
626 return mlx5_modify_port_ets_rate_limit(mdev, max_bw_value, max_bw_unit);
627 }
628
mlx5e_dcbnl_setall(struct net_device * netdev)629 static u8 mlx5e_dcbnl_setall(struct net_device *netdev)
630 {
631 struct mlx5e_priv *priv = netdev_priv(netdev);
632 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
633 struct mlx5_core_dev *mdev = priv->mdev;
634 struct ieee_ets ets;
635 struct ieee_pfc pfc;
636 int err = -EOPNOTSUPP;
637 int i;
638
639 if (!MLX5_CAP_GEN(mdev, ets))
640 goto out;
641
642 memset(&ets, 0, sizeof(ets));
643 memset(&pfc, 0, sizeof(pfc));
644
645 ets.ets_cap = IEEE_8021QAZ_MAX_TCS;
646 for (i = 0; i < CEE_DCBX_MAX_PGS; i++) {
647 ets.tc_tx_bw[i] = cee_cfg->pg_bw_pct[i];
648 ets.tc_rx_bw[i] = cee_cfg->pg_bw_pct[i];
649 ets.tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
650 ets.prio_tc[i] = cee_cfg->prio_to_pg_map[i];
651 netdev_dbg(netdev,
652 "%s: Priority group %d: tx_bw %d, rx_bw %d, prio_tc %d\n",
653 __func__, i, ets.tc_tx_bw[i], ets.tc_rx_bw[i],
654 ets.prio_tc[i]);
655 }
656
657 err = mlx5e_dbcnl_validate_ets(netdev, &ets, true);
658 if (err)
659 goto out;
660
661 err = mlx5e_dcbnl_ieee_setets_core(priv, &ets);
662 if (err) {
663 netdev_err(netdev,
664 "%s, Failed to set ETS: %d\n", __func__, err);
665 goto out;
666 }
667
668 /* Set PFC */
669 pfc.pfc_cap = mlx5_max_tc(mdev) + 1;
670 if (!cee_cfg->pfc_enable)
671 pfc.pfc_en = 0;
672 else
673 for (i = 0; i < CEE_DCBX_MAX_PRIO; i++)
674 pfc.pfc_en |= cee_cfg->pfc_setting[i] << i;
675
676 err = mlx5e_dcbnl_ieee_setpfc(netdev, &pfc);
677 if (err) {
678 netdev_err(netdev,
679 "%s, Failed to set PFC: %d\n", __func__, err);
680 goto out;
681 }
682 out:
683 return err ? MLX5_DCB_NO_CHG : MLX5_DCB_CHG_RESET;
684 }
685
mlx5e_dcbnl_getstate(struct net_device * netdev)686 static u8 mlx5e_dcbnl_getstate(struct net_device *netdev)
687 {
688 return MLX5E_CEE_STATE_UP;
689 }
690
mlx5e_dcbnl_getpermhwaddr(struct net_device * netdev,u8 * perm_addr)691 static void mlx5e_dcbnl_getpermhwaddr(struct net_device *netdev,
692 u8 *perm_addr)
693 {
694 struct mlx5e_priv *priv = netdev_priv(netdev);
695
696 if (!perm_addr)
697 return;
698
699 memset(perm_addr, 0xff, MAX_ADDR_LEN);
700
701 mlx5_query_mac_address(priv->mdev, perm_addr);
702 }
703
mlx5e_dcbnl_setpgtccfgtx(struct net_device * netdev,int priority,u8 prio_type,u8 pgid,u8 bw_pct,u8 up_map)704 static void mlx5e_dcbnl_setpgtccfgtx(struct net_device *netdev,
705 int priority, u8 prio_type,
706 u8 pgid, u8 bw_pct, u8 up_map)
707 {
708 struct mlx5e_priv *priv = netdev_priv(netdev);
709 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
710
711 if (priority >= CEE_DCBX_MAX_PRIO) {
712 netdev_err(netdev,
713 "%s, priority is out of range\n", __func__);
714 return;
715 }
716
717 if (pgid >= CEE_DCBX_MAX_PGS) {
718 netdev_err(netdev,
719 "%s, priority group is out of range\n", __func__);
720 return;
721 }
722
723 cee_cfg->prio_to_pg_map[priority] = pgid;
724 }
725
mlx5e_dcbnl_setpgbwgcfgtx(struct net_device * netdev,int pgid,u8 bw_pct)726 static void mlx5e_dcbnl_setpgbwgcfgtx(struct net_device *netdev,
727 int pgid, u8 bw_pct)
728 {
729 struct mlx5e_priv *priv = netdev_priv(netdev);
730 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
731
732 if (pgid >= CEE_DCBX_MAX_PGS) {
733 netdev_err(netdev,
734 "%s, priority group is out of range\n", __func__);
735 return;
736 }
737
738 cee_cfg->pg_bw_pct[pgid] = bw_pct;
739 }
740
mlx5e_dcbnl_getpgtccfgtx(struct net_device * netdev,int priority,u8 * prio_type,u8 * pgid,u8 * bw_pct,u8 * up_map)741 static void mlx5e_dcbnl_getpgtccfgtx(struct net_device *netdev,
742 int priority, u8 *prio_type,
743 u8 *pgid, u8 *bw_pct, u8 *up_map)
744 {
745 struct mlx5e_priv *priv = netdev_priv(netdev);
746 struct mlx5_core_dev *mdev = priv->mdev;
747
748 if (!MLX5_CAP_GEN(priv->mdev, ets)) {
749 netdev_err(netdev, "%s, ets is not supported\n", __func__);
750 return;
751 }
752
753 if (priority >= CEE_DCBX_MAX_PRIO) {
754 netdev_err(netdev,
755 "%s, priority is out of range\n", __func__);
756 return;
757 }
758
759 *prio_type = 0;
760 *bw_pct = 0;
761 *up_map = 0;
762
763 if (mlx5_query_port_prio_tc(mdev, priority, pgid))
764 *pgid = 0;
765 }
766
mlx5e_dcbnl_getpgbwgcfgtx(struct net_device * netdev,int pgid,u8 * bw_pct)767 static void mlx5e_dcbnl_getpgbwgcfgtx(struct net_device *netdev,
768 int pgid, u8 *bw_pct)
769 {
770 struct ieee_ets ets;
771
772 if (pgid >= CEE_DCBX_MAX_PGS) {
773 netdev_err(netdev,
774 "%s, priority group is out of range\n", __func__);
775 return;
776 }
777
778 mlx5e_dcbnl_ieee_getets(netdev, &ets);
779 *bw_pct = ets.tc_tx_bw[pgid];
780 }
781
mlx5e_dcbnl_setpfccfg(struct net_device * netdev,int priority,u8 setting)782 static void mlx5e_dcbnl_setpfccfg(struct net_device *netdev,
783 int priority, u8 setting)
784 {
785 struct mlx5e_priv *priv = netdev_priv(netdev);
786 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
787
788 if (priority >= CEE_DCBX_MAX_PRIO) {
789 netdev_err(netdev,
790 "%s, priority is out of range\n", __func__);
791 return;
792 }
793
794 if (setting > 1)
795 return;
796
797 cee_cfg->pfc_setting[priority] = setting;
798 }
799
800 static int
mlx5e_dcbnl_get_priority_pfc(struct net_device * netdev,int priority,u8 * setting)801 mlx5e_dcbnl_get_priority_pfc(struct net_device *netdev,
802 int priority, u8 *setting)
803 {
804 struct ieee_pfc pfc;
805 int err;
806
807 err = mlx5e_dcbnl_ieee_getpfc(netdev, &pfc);
808
809 if (err)
810 *setting = 0;
811 else
812 *setting = (pfc.pfc_en >> priority) & 0x01;
813
814 return err;
815 }
816
mlx5e_dcbnl_getpfccfg(struct net_device * netdev,int priority,u8 * setting)817 static void mlx5e_dcbnl_getpfccfg(struct net_device *netdev,
818 int priority, u8 *setting)
819 {
820 if (priority >= CEE_DCBX_MAX_PRIO) {
821 netdev_err(netdev,
822 "%s, priority is out of range\n", __func__);
823 return;
824 }
825
826 if (!setting)
827 return;
828
829 mlx5e_dcbnl_get_priority_pfc(netdev, priority, setting);
830 }
831
mlx5e_dcbnl_getcap(struct net_device * netdev,int capid,u8 * cap)832 static u8 mlx5e_dcbnl_getcap(struct net_device *netdev,
833 int capid, u8 *cap)
834 {
835 struct mlx5e_priv *priv = netdev_priv(netdev);
836 struct mlx5_core_dev *mdev = priv->mdev;
837 u8 rval = 0;
838
839 switch (capid) {
840 case DCB_CAP_ATTR_PG:
841 *cap = true;
842 break;
843 case DCB_CAP_ATTR_PFC:
844 *cap = true;
845 break;
846 case DCB_CAP_ATTR_UP2TC:
847 *cap = false;
848 break;
849 case DCB_CAP_ATTR_PG_TCS:
850 *cap = 1 << mlx5_max_tc(mdev);
851 break;
852 case DCB_CAP_ATTR_PFC_TCS:
853 *cap = 1 << mlx5_max_tc(mdev);
854 break;
855 case DCB_CAP_ATTR_GSP:
856 *cap = false;
857 break;
858 case DCB_CAP_ATTR_BCN:
859 *cap = false;
860 break;
861 case DCB_CAP_ATTR_DCBX:
862 *cap = priv->dcbx.cap |
863 DCB_CAP_DCBX_VER_CEE |
864 DCB_CAP_DCBX_VER_IEEE;
865 break;
866 default:
867 *cap = 0;
868 rval = 1;
869 break;
870 }
871
872 return rval;
873 }
874
mlx5e_dcbnl_getnumtcs(struct net_device * netdev,int tcs_id,u8 * num)875 static int mlx5e_dcbnl_getnumtcs(struct net_device *netdev,
876 int tcs_id, u8 *num)
877 {
878 struct mlx5e_priv *priv = netdev_priv(netdev);
879 struct mlx5_core_dev *mdev = priv->mdev;
880
881 switch (tcs_id) {
882 case DCB_NUMTCS_ATTR_PG:
883 case DCB_NUMTCS_ATTR_PFC:
884 *num = mlx5_max_tc(mdev) + 1;
885 break;
886 default:
887 return -EINVAL;
888 }
889
890 return 0;
891 }
892
mlx5e_dcbnl_getpfcstate(struct net_device * netdev)893 static u8 mlx5e_dcbnl_getpfcstate(struct net_device *netdev)
894 {
895 struct ieee_pfc pfc;
896
897 if (mlx5e_dcbnl_ieee_getpfc(netdev, &pfc))
898 return MLX5E_CEE_STATE_DOWN;
899
900 return pfc.pfc_en ? MLX5E_CEE_STATE_UP : MLX5E_CEE_STATE_DOWN;
901 }
902
mlx5e_dcbnl_setpfcstate(struct net_device * netdev,u8 state)903 static void mlx5e_dcbnl_setpfcstate(struct net_device *netdev, u8 state)
904 {
905 struct mlx5e_priv *priv = netdev_priv(netdev);
906 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
907
908 if ((state != MLX5E_CEE_STATE_UP) && (state != MLX5E_CEE_STATE_DOWN))
909 return;
910
911 cee_cfg->pfc_enable = state;
912 }
913
mlx5e_dcbnl_getbuffer(struct net_device * dev,struct dcbnl_buffer * dcb_buffer)914 static int mlx5e_dcbnl_getbuffer(struct net_device *dev,
915 struct dcbnl_buffer *dcb_buffer)
916 {
917 struct mlx5e_priv *priv = netdev_priv(dev);
918 struct mlx5_core_dev *mdev = priv->mdev;
919 struct mlx5e_port_buffer port_buffer;
920 u8 buffer[MLX5E_MAX_PRIORITY];
921 int i, err;
922
923 if (!MLX5_BUFFER_SUPPORTED(mdev))
924 return -EOPNOTSUPP;
925
926 err = mlx5e_port_query_priority2buffer(mdev, buffer);
927 if (err)
928 return err;
929
930 for (i = 0; i < MLX5E_MAX_PRIORITY; i++)
931 dcb_buffer->prio2buffer[i] = buffer[i];
932
933 err = mlx5e_port_query_buffer(priv, &port_buffer);
934 if (err)
935 return err;
936
937 for (i = 0; i < MLX5E_MAX_NETWORK_BUFFER; i++)
938 dcb_buffer->buffer_size[i] = port_buffer.buffer[i].size;
939 dcb_buffer->total_size = port_buffer.port_buffer_size -
940 port_buffer.internal_buffers_size;
941
942 return 0;
943 }
944
mlx5e_dcbnl_setbuffer(struct net_device * dev,struct dcbnl_buffer * dcb_buffer)945 static int mlx5e_dcbnl_setbuffer(struct net_device *dev,
946 struct dcbnl_buffer *dcb_buffer)
947 {
948 struct mlx5e_priv *priv = netdev_priv(dev);
949 struct mlx5_core_dev *mdev = priv->mdev;
950 struct mlx5e_port_buffer port_buffer;
951 u8 old_prio2buffer[MLX5E_MAX_PRIORITY];
952 u32 *buffer_size = NULL;
953 u8 *prio2buffer = NULL;
954 u32 changed = 0;
955 int i, err;
956
957 if (!MLX5_BUFFER_SUPPORTED(mdev))
958 return -EOPNOTSUPP;
959
960 for (i = 0; i < DCBX_MAX_BUFFERS; i++)
961 mlx5_core_dbg(mdev, "buffer[%d]=%d\n", i, dcb_buffer->buffer_size[i]);
962
963 for (i = 0; i < MLX5E_MAX_PRIORITY; i++)
964 mlx5_core_dbg(mdev, "priority %d buffer%d\n", i, dcb_buffer->prio2buffer[i]);
965
966 err = mlx5e_port_query_priority2buffer(mdev, old_prio2buffer);
967 if (err)
968 return err;
969
970 for (i = 0; i < MLX5E_MAX_PRIORITY; i++) {
971 if (dcb_buffer->prio2buffer[i] != old_prio2buffer[i]) {
972 changed |= MLX5E_PORT_BUFFER_PRIO2BUFFER;
973 prio2buffer = dcb_buffer->prio2buffer;
974 break;
975 }
976 }
977
978 err = mlx5e_port_query_buffer(priv, &port_buffer);
979 if (err)
980 return err;
981
982 for (i = 0; i < MLX5E_MAX_NETWORK_BUFFER; i++) {
983 if (port_buffer.buffer[i].size != dcb_buffer->buffer_size[i]) {
984 changed |= MLX5E_PORT_BUFFER_SIZE;
985 buffer_size = dcb_buffer->buffer_size;
986 break;
987 }
988 }
989
990 if (!changed)
991 return 0;
992
993 err = mlx5e_port_manual_buffer_config(priv, changed, dev->mtu, NULL,
994 buffer_size, prio2buffer);
995 return err;
996 }
997
998 static const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops = {
999 .ieee_getets = mlx5e_dcbnl_ieee_getets,
1000 .ieee_setets = mlx5e_dcbnl_ieee_setets,
1001 .ieee_getmaxrate = mlx5e_dcbnl_ieee_getmaxrate,
1002 .ieee_setmaxrate = mlx5e_dcbnl_ieee_setmaxrate,
1003 .ieee_getpfc = mlx5e_dcbnl_ieee_getpfc,
1004 .ieee_setpfc = mlx5e_dcbnl_ieee_setpfc,
1005 .ieee_setapp = mlx5e_dcbnl_ieee_setapp,
1006 .ieee_delapp = mlx5e_dcbnl_ieee_delapp,
1007 .getdcbx = mlx5e_dcbnl_getdcbx,
1008 .setdcbx = mlx5e_dcbnl_setdcbx,
1009 .dcbnl_getbuffer = mlx5e_dcbnl_getbuffer,
1010 .dcbnl_setbuffer = mlx5e_dcbnl_setbuffer,
1011
1012 /* CEE interfaces */
1013 .setall = mlx5e_dcbnl_setall,
1014 .getstate = mlx5e_dcbnl_getstate,
1015 .getpermhwaddr = mlx5e_dcbnl_getpermhwaddr,
1016
1017 .setpgtccfgtx = mlx5e_dcbnl_setpgtccfgtx,
1018 .setpgbwgcfgtx = mlx5e_dcbnl_setpgbwgcfgtx,
1019 .getpgtccfgtx = mlx5e_dcbnl_getpgtccfgtx,
1020 .getpgbwgcfgtx = mlx5e_dcbnl_getpgbwgcfgtx,
1021
1022 .setpfccfg = mlx5e_dcbnl_setpfccfg,
1023 .getpfccfg = mlx5e_dcbnl_getpfccfg,
1024 .getcap = mlx5e_dcbnl_getcap,
1025 .getnumtcs = mlx5e_dcbnl_getnumtcs,
1026 .getpfcstate = mlx5e_dcbnl_getpfcstate,
1027 .setpfcstate = mlx5e_dcbnl_setpfcstate,
1028 };
1029
mlx5e_dcbnl_build_netdev(struct net_device * netdev)1030 void mlx5e_dcbnl_build_netdev(struct net_device *netdev)
1031 {
1032 struct mlx5e_priv *priv = netdev_priv(netdev);
1033 struct mlx5_core_dev *mdev = priv->mdev;
1034
1035 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
1036 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
1037 }
1038
mlx5e_dcbnl_query_dcbx_mode(struct mlx5e_priv * priv,enum mlx5_dcbx_oper_mode * mode)1039 static void mlx5e_dcbnl_query_dcbx_mode(struct mlx5e_priv *priv,
1040 enum mlx5_dcbx_oper_mode *mode)
1041 {
1042 u32 out[MLX5_ST_SZ_DW(dcbx_param)];
1043
1044 *mode = MLX5E_DCBX_PARAM_VER_OPER_HOST;
1045
1046 if (!mlx5_query_port_dcbx_param(priv->mdev, out))
1047 *mode = MLX5_GET(dcbx_param, out, version_oper);
1048
1049 /* From driver's point of view, we only care if the mode
1050 * is host (HOST) or non-host (AUTO)
1051 */
1052 if (*mode != MLX5E_DCBX_PARAM_VER_OPER_HOST)
1053 *mode = MLX5E_DCBX_PARAM_VER_OPER_AUTO;
1054 }
1055
mlx5e_ets_init(struct mlx5e_priv * priv)1056 static void mlx5e_ets_init(struct mlx5e_priv *priv)
1057 {
1058 struct ieee_ets ets;
1059 int err;
1060 int i;
1061
1062 if (!MLX5_CAP_GEN(priv->mdev, ets))
1063 return;
1064
1065 memset(&ets, 0, sizeof(ets));
1066 ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
1067 for (i = 0; i < ets.ets_cap; i++) {
1068 ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
1069 ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
1070 ets.prio_tc[i] = i;
1071 }
1072
1073 if (ets.ets_cap > 1) {
1074 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
1075 ets.prio_tc[0] = 1;
1076 ets.prio_tc[1] = 0;
1077 }
1078
1079 err = mlx5e_dcbnl_ieee_setets_core(priv, &ets);
1080 if (err)
1081 netdev_err(priv->netdev,
1082 "%s, Failed to init ETS: %d\n", __func__, err);
1083 }
1084
1085 enum {
1086 INIT,
1087 DELETE,
1088 };
1089
mlx5e_dcbnl_dscp_app(struct mlx5e_priv * priv,int action)1090 static void mlx5e_dcbnl_dscp_app(struct mlx5e_priv *priv, int action)
1091 {
1092 struct dcb_app temp;
1093 int i;
1094
1095 if (!MLX5_CAP_GEN(priv->mdev, vport_group_manager))
1096 return;
1097
1098 if (!MLX5_DSCP_SUPPORTED(priv->mdev))
1099 return;
1100
1101 /* No SEL_DSCP entry in non DSCP state */
1102 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_DSCP)
1103 return;
1104
1105 temp.selector = IEEE_8021QAZ_APP_SEL_DSCP;
1106 for (i = 0; i < MLX5E_MAX_DSCP; i++) {
1107 temp.protocol = i;
1108 temp.priority = priv->dcbx_dp.dscp2prio[i];
1109 if (action == INIT)
1110 dcb_ieee_setapp(priv->netdev, &temp);
1111 else
1112 dcb_ieee_delapp(priv->netdev, &temp);
1113 }
1114
1115 priv->dcbx.dscp_app_cnt = (action == INIT) ? MLX5E_MAX_DSCP : 0;
1116 }
1117
mlx5e_dcbnl_init_app(struct mlx5e_priv * priv)1118 void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv)
1119 {
1120 mlx5e_dcbnl_dscp_app(priv, INIT);
1121 }
1122
mlx5e_dcbnl_delete_app(struct mlx5e_priv * priv)1123 void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv)
1124 {
1125 mlx5e_dcbnl_dscp_app(priv, DELETE);
1126 }
1127
mlx5e_params_calc_trust_tx_min_inline_mode(struct mlx5_core_dev * mdev,struct mlx5e_params * params,u8 trust_state)1128 static void mlx5e_params_calc_trust_tx_min_inline_mode(struct mlx5_core_dev *mdev,
1129 struct mlx5e_params *params,
1130 u8 trust_state)
1131 {
1132 mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode);
1133 if (trust_state == MLX5_QPTS_TRUST_DSCP &&
1134 params->tx_min_inline_mode == MLX5_INLINE_MODE_L2)
1135 params->tx_min_inline_mode = MLX5_INLINE_MODE_IP;
1136 }
1137
mlx5e_update_trust_state_hw(struct mlx5e_priv * priv,void * context)1138 static int mlx5e_update_trust_state_hw(struct mlx5e_priv *priv, void *context)
1139 {
1140 u8 *trust_state = context;
1141 int err;
1142
1143 err = mlx5_set_trust_state(priv->mdev, *trust_state);
1144 if (err)
1145 return err;
1146 WRITE_ONCE(priv->dcbx_dp.trust_state, *trust_state);
1147
1148 return 0;
1149 }
1150
mlx5e_set_trust_state(struct mlx5e_priv * priv,u8 trust_state)1151 static int mlx5e_set_trust_state(struct mlx5e_priv *priv, u8 trust_state)
1152 {
1153 struct mlx5e_params new_params;
1154 bool reset = true;
1155 int err;
1156
1157 netdev_lock(priv->netdev);
1158 mutex_lock(&priv->state_lock);
1159
1160 new_params = priv->channels.params;
1161 mlx5e_params_calc_trust_tx_min_inline_mode(priv->mdev, &new_params,
1162 trust_state);
1163
1164 /* Skip if tx_min_inline is the same */
1165 if (new_params.tx_min_inline_mode == priv->channels.params.tx_min_inline_mode)
1166 reset = false;
1167
1168 err = mlx5e_safe_switch_params(priv, &new_params,
1169 mlx5e_update_trust_state_hw,
1170 &trust_state, reset);
1171
1172 mutex_unlock(&priv->state_lock);
1173 netdev_unlock(priv->netdev);
1174
1175 return err;
1176 }
1177
mlx5e_set_dscp2prio(struct mlx5e_priv * priv,u8 dscp,u8 prio)1178 static int mlx5e_set_dscp2prio(struct mlx5e_priv *priv, u8 dscp, u8 prio)
1179 {
1180 int err;
1181
1182 err = mlx5_set_dscp2prio(priv->mdev, dscp, prio);
1183 if (err)
1184 return err;
1185
1186 priv->dcbx_dp.dscp2prio[dscp] = prio;
1187 return err;
1188 }
1189
mlx5e_trust_initialize(struct mlx5e_priv * priv)1190 static int mlx5e_trust_initialize(struct mlx5e_priv *priv)
1191 {
1192 struct mlx5_core_dev *mdev = priv->mdev;
1193 u8 trust_state;
1194 int err;
1195
1196 if (!MLX5_DSCP_SUPPORTED(mdev)) {
1197 WRITE_ONCE(priv->dcbx_dp.trust_state, MLX5_QPTS_TRUST_PCP);
1198 return 0;
1199 }
1200
1201 err = mlx5_query_trust_state(priv->mdev, &trust_state);
1202 if (err)
1203 return err;
1204 WRITE_ONCE(priv->dcbx_dp.trust_state, trust_state);
1205
1206 if (priv->dcbx_dp.trust_state == MLX5_QPTS_TRUST_PCP && priv->dcbx.dscp_app_cnt) {
1207 /*
1208 * Align the driver state with the register state.
1209 * Temporary state change is required to enable the app list reset.
1210 */
1211 priv->dcbx_dp.trust_state = MLX5_QPTS_TRUST_DSCP;
1212 mlx5e_dcbnl_delete_app(priv);
1213 priv->dcbx_dp.trust_state = MLX5_QPTS_TRUST_PCP;
1214 }
1215
1216 mlx5e_params_calc_trust_tx_min_inline_mode(priv->mdev, &priv->channels.params,
1217 priv->dcbx_dp.trust_state);
1218
1219 err = mlx5_query_dscp2prio(priv->mdev, priv->dcbx_dp.dscp2prio);
1220 if (err)
1221 return err;
1222
1223 return 0;
1224 }
1225
1226 #define MLX5E_BUFFER_CELL_SHIFT 7
1227
mlx5e_query_port_buffers_cell_size(struct mlx5e_priv * priv)1228 static u16 mlx5e_query_port_buffers_cell_size(struct mlx5e_priv *priv)
1229 {
1230 struct mlx5_core_dev *mdev = priv->mdev;
1231 u32 out[MLX5_ST_SZ_DW(sbcam_reg)] = {};
1232 u32 in[MLX5_ST_SZ_DW(sbcam_reg)] = {};
1233
1234 if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1235 return (1 << MLX5E_BUFFER_CELL_SHIFT);
1236
1237 if (mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out),
1238 MLX5_REG_SBCAM, 0, 0))
1239 return (1 << MLX5E_BUFFER_CELL_SHIFT);
1240
1241 return MLX5_GET(sbcam_reg, out, cap_cell_size);
1242 }
1243
mlx5e_dcbnl_initialize(struct mlx5e_priv * priv)1244 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv)
1245 {
1246 struct mlx5e_dcbx *dcbx = &priv->dcbx;
1247
1248 mlx5e_trust_initialize(priv);
1249
1250 if (!MLX5_CAP_GEN(priv->mdev, qos))
1251 return;
1252
1253 if (MLX5_CAP_GEN(priv->mdev, dcbx))
1254 mlx5e_dcbnl_query_dcbx_mode(priv, &dcbx->mode);
1255
1256 priv->dcbx.cap = DCB_CAP_DCBX_VER_CEE |
1257 DCB_CAP_DCBX_VER_IEEE;
1258 if (priv->dcbx.mode == MLX5E_DCBX_PARAM_VER_OPER_HOST)
1259 priv->dcbx.cap |= DCB_CAP_DCBX_HOST;
1260
1261 priv->dcbx.port_buff_cell_sz = mlx5e_query_port_buffers_cell_size(priv);
1262 priv->dcbx.cable_len = MLX5E_DEFAULT_CABLE_LEN;
1263
1264 mlx5e_ets_init(priv);
1265 }
1266