1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 4 * 5 * Derived from MIPS: 6 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle 7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 * Copyright (C) 2002, 2007 Maciej W. Rozycki 9 * Copyright (C) 2001, 2012 MIPS Technologies, Inc. All rights reserved. 10 */ 11#include <asm/asm.h> 12#include <asm/asmmacro.h> 13#include <asm/loongarch.h> 14#include <asm/regdef.h> 15#include <asm/fpregdef.h> 16#include <asm/stackframe.h> 17#include <asm/thread_info.h> 18 19 .align 5 20SYM_FUNC_START(__arch_cpu_idle) 21 /* start of idle interrupt region */ 22 ori t0, zero, CSR_CRMD_IE 23 /* idle instruction needs irq enabled */ 24 csrxchg t0, t0, LOONGARCH_CSR_CRMD 25 /* 26 * If an interrupt lands here; between enabling interrupts above and 27 * going idle on the next instruction, we must *NOT* go idle since the 28 * interrupt could have set TIF_NEED_RESCHED or caused an timer to need 29 * reprogramming. Fall through -- see handle_vint() below -- and have 30 * the idle loop take care of things. 31 */ 32 idle 0 33 /* end of idle interrupt region */ 341: jr ra 35SYM_FUNC_END(__arch_cpu_idle) 36 37SYM_CODE_START(handle_vint) 38 UNWIND_HINT_UNDEFINED 39 BACKUP_T0T1 40 SAVE_ALL 41 la_abs t1, 1b 42 LONG_L t0, sp, PT_ERA 43 /* 3 instructions idle interrupt region */ 44 ori t0, t0, 0b1100 45 bne t0, t1, 1f 46 LONG_S t0, sp, PT_ERA 471: move a0, sp 48 move a1, sp 49 la_abs t0, do_vint 50 jirl ra, t0, 0 51 RESTORE_ALL_AND_RET 52SYM_CODE_END(handle_vint) 53 54SYM_CODE_START(except_vec_cex) 55 UNWIND_HINT_UNDEFINED 56 b cache_parity_error 57SYM_CODE_END(except_vec_cex) 58 59 .macro build_prep_badv 60 csrrd t0, LOONGARCH_CSR_BADV 61 PTR_S t0, sp, PT_BVADDR 62 .endm 63 64 .macro build_prep_fcsr 65 movfcsr2gr a1, fcsr0 66 .endm 67 68 .macro build_prep_none 69 .endm 70 71 .macro BUILD_HANDLER exception handler prep 72 .align 5 73 SYM_CODE_START(handle_\exception) 74 UNWIND_HINT_UNDEFINED 75 666: 76 BACKUP_T0T1 77 SAVE_ALL 78 build_prep_\prep 79 move a0, sp 80 la_abs t0, do_\handler 81 jirl ra, t0, 0 82 668: 83 RESTORE_ALL_AND_RET 84 SYM_CODE_END(handle_\exception) 85 .pushsection ".data", "aw", %progbits 86 SYM_DATA(unwind_hint_\exception, .word 668b - 666b) 87 .popsection 88 .endm 89 90 BUILD_HANDLER ade ade badv 91 BUILD_HANDLER ale ale badv 92 BUILD_HANDLER bce bce none 93 BUILD_HANDLER bp bp none 94 BUILD_HANDLER fpe fpe fcsr 95 BUILD_HANDLER fpu fpu none 96 BUILD_HANDLER lsx lsx none 97 BUILD_HANDLER lasx lasx none 98 BUILD_HANDLER lbt lbt none 99 BUILD_HANDLER ri ri none 100 BUILD_HANDLER watch watch none 101 BUILD_HANDLER reserved reserved none /* others */ 102 103SYM_CODE_START(handle_sys) 104 UNWIND_HINT_UNDEFINED 105 la_abs t0, handle_syscall 106 jr t0 107SYM_CODE_END(handle_sys) 108