1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __DML2_INTERNAL_TYPES_H__ 28 #define __DML2_INTERNAL_TYPES_H__ 29 30 #include "dml2_dc_types.h" 31 #include "display_mode_core.h" 32 #include "dml2_wrapper.h" 33 #include "dml2_policy.h" 34 35 #include "dml_top.h" 36 #include "dml21_wrapper.h" 37 38 struct dml2_wrapper_optimize_configuration_params { 39 struct display_mode_lib_st *dml_core_ctx; 40 struct dml2_configuration_options *config; 41 struct ip_params_st *ip_params; 42 struct dml_display_cfg_st *cur_display_config; 43 struct dml_display_cfg_st *new_display_config; 44 const struct dml_mode_support_info_st *cur_mode_support_info; 45 struct dml_mode_eval_policy_st *cur_policy; 46 struct dml_mode_eval_policy_st *new_policy; 47 }; 48 49 struct dml2_calculate_lowest_supported_state_for_temp_read_scratch { 50 struct dml_mode_support_info_st evaluation_info; 51 dml_float_t uclk_change_latencies[__DML_MAX_STATE_ARRAY_SIZE__]; 52 struct dml_display_cfg_st cur_display_config; 53 struct dml_display_cfg_st new_display_config; 54 struct dml_mode_eval_policy_st new_policy; 55 struct dml_mode_eval_policy_st cur_policy; 56 }; 57 58 struct dml2_create_scratch { 59 struct dml2_policy_build_synthetic_soc_states_scratch build_synthetic_socbb_scratch; 60 struct soc_states_st in_states; 61 }; 62 63 struct dml2_calculate_rq_and_dlg_params_scratch { 64 struct _vcs_dpi_dml_display_rq_regs_st rq_regs; 65 struct _vcs_dpi_dml_display_dlg_regs_st disp_dlg_regs; 66 struct _vcs_dpi_dml_display_ttu_regs_st disp_ttu_regs; 67 }; 68 69 #define __DML2_WRAPPER_MAX_STREAMS_PLANES__ 6 70 71 struct dml2_dml_to_dc_pipe_mapping { 72 unsigned int disp_cfg_to_stream_id[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 73 bool disp_cfg_to_stream_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 74 unsigned int disp_cfg_to_plane_id[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 75 bool disp_cfg_to_plane_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 76 unsigned int dml_pipe_idx_to_stream_id[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 77 bool dml_pipe_idx_to_stream_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 78 unsigned int dml_pipe_idx_to_plane_id[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 79 bool dml_pipe_idx_to_plane_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 80 unsigned int dml_pipe_idx_to_plane_index[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 81 bool dml_pipe_idx_to_plane_index_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 82 }; 83 84 struct dml2_wrapper_scratch { 85 struct dml_display_cfg_st cur_display_config; 86 struct dml_display_cfg_st new_display_config; 87 struct dml_mode_eval_policy_st new_policy; 88 struct dml_mode_eval_policy_st cur_policy; 89 struct dml_mode_support_info_st mode_support_info; 90 struct dml_mode_support_ex_params_st mode_support_params; 91 92 struct dummy_pstate_entry dummy_pstate_table[4]; 93 94 struct dml2_create_scratch create_scratch; 95 struct dml2_calculate_lowest_supported_state_for_temp_read_scratch dml2_calculate_lowest_supported_state_for_temp_read_scratch; 96 struct dml2_calculate_rq_and_dlg_params_scratch calculate_rq_and_dlg_params_scratch; 97 98 struct dml2_wrapper_optimize_configuration_params optimize_configuration_params; 99 struct dml2_policy_build_synthetic_soc_states_params build_synthetic_socbb_params; 100 101 struct dml2_dml_to_dc_pipe_mapping dml_to_dc_pipe_mapping; 102 bool enable_flexible_pipe_mapping; 103 bool plane_duplicate_exists; 104 int hpo_stream_to_link_encoder_mapping[MAX_HPO_DP2_ENCODERS]; 105 }; 106 107 struct dml2_helper_det_policy_scratch { 108 int dpps_per_surface[MAX_PLANES]; 109 }; 110 111 enum dml2_architecture { 112 dml2_architecture_20, 113 dml2_architecture_21 114 }; 115 116 struct prepare_mcache_programming_locals { 117 struct dml2_build_mcache_programming_in_out build_mcache_programming_params; 118 }; 119 120 struct dml21_wrapper_scratch { 121 struct prepare_mcache_programming_locals prepare_mcache_locals; 122 struct pipe_ctx temp_pipe; 123 }; 124 125 struct dml2_pipe_combine_factor { 126 unsigned int source; 127 unsigned int target; 128 }; 129 130 struct dml2_pipe_combine_scratch { 131 struct dml2_pipe_combine_factor odm_factors[MAX_PIPES]; 132 struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES][MAX_PIPES]; 133 }; 134 135 struct dml2_context { 136 enum dml2_architecture architecture; 137 struct dml2_configuration_options config; 138 struct dml2_helper_det_policy_scratch det_helper_scratch; 139 struct dml2_pipe_combine_scratch pipe_combine_scratch; 140 union { 141 struct { 142 struct display_mode_lib_st dml_core_ctx; 143 struct dml2_wrapper_scratch scratch; 144 struct dcn_watermarks g6_temp_read_watermark_set; 145 } v20; 146 struct { 147 struct dml21_wrapper_scratch scratch; 148 struct dml2_initialize_instance_in_out dml_init; 149 struct dml2_display_cfg display_config; 150 struct dml2_check_mode_supported_in_out mode_support; 151 struct dml2_build_mode_programming_in_out mode_programming; 152 struct dml2_dml_to_dc_pipe_mapping dml_to_dc_pipe_mapping; 153 } v21; 154 }; 155 }; 156 157 #endif 158