1 // SPDX-License-Identifier: GPL-2.0 2 #define pr_fmt(fmt) "bcmasp_intf: " fmt 3 4 #include <asm/byteorder.h> 5 #include <linux/brcmphy.h> 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/etherdevice.h> 9 #include <linux/netdevice.h> 10 #include <linux/of_net.h> 11 #include <linux/of_mdio.h> 12 #include <linux/phy.h> 13 #include <linux/phy_fixed.h> 14 #include <linux/ptp_classify.h> 15 #include <linux/platform_device.h> 16 #include <net/ip.h> 17 #include <net/ipv6.h> 18 #include <net/netdev_queues.h> 19 #include <net/page_pool/helpers.h> 20 21 #include "bcmasp.h" 22 #include "bcmasp_intf_defs.h" 23 24 #define BCMASP_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 25 #define BCMASP_TX_START_THRS (2 * MAX_SKB_FRAGS) 26 27 static int incr_ring(int index, int ring_count) 28 { 29 index++; 30 if (index == ring_count) 31 return 0; 32 33 return index; 34 } 35 36 /* Points to last byte of descriptor */ 37 static dma_addr_t incr_last_byte(dma_addr_t addr, dma_addr_t beg, 38 int ring_count) 39 { 40 dma_addr_t end = beg + (ring_count * DESC_SIZE); 41 42 addr += DESC_SIZE; 43 if (addr > end) 44 return beg + DESC_SIZE - 1; 45 46 return addr; 47 } 48 49 /* Points to first byte of descriptor */ 50 static dma_addr_t incr_first_byte(dma_addr_t addr, dma_addr_t beg, 51 int ring_count) 52 { 53 dma_addr_t end = beg + (ring_count * DESC_SIZE); 54 55 addr += DESC_SIZE; 56 if (addr >= end) 57 return beg; 58 59 return addr; 60 } 61 62 static void bcmasp_enable_tx(struct bcmasp_intf *intf, int en) 63 { 64 if (en) { 65 tx_spb_ctrl_wl(intf, TX_SPB_CTRL_ENABLE_EN, TX_SPB_CTRL_ENABLE); 66 tx_epkt_core_wl(intf, (TX_EPKT_C_CFG_MISC_EN | 67 TX_EPKT_C_CFG_MISC_PT | 68 (intf->port << TX_EPKT_C_CFG_MISC_PS_SHIFT)), 69 TX_EPKT_C_CFG_MISC); 70 } else { 71 tx_spb_ctrl_wl(intf, 0x0, TX_SPB_CTRL_ENABLE); 72 tx_epkt_core_wl(intf, 0x0, TX_EPKT_C_CFG_MISC); 73 } 74 } 75 76 static void bcmasp_enable_rx(struct bcmasp_intf *intf, int en) 77 { 78 if (en) 79 rx_edpkt_cfg_wl(intf, RX_EDPKT_CFG_ENABLE_EN, 80 RX_EDPKT_CFG_ENABLE); 81 else 82 rx_edpkt_cfg_wl(intf, 0x0, RX_EDPKT_CFG_ENABLE); 83 } 84 85 static void bcmasp_set_rx_mode(struct net_device *dev) 86 { 87 unsigned char mask[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 88 struct bcmasp_intf *intf = netdev_priv(dev); 89 struct netdev_hw_addr *ha; 90 int ret; 91 92 spin_lock_bh(&intf->parent->mda_lock); 93 94 bcmasp_disable_all_filters(intf); 95 96 if (dev->flags & IFF_PROMISC) 97 goto set_promisc; 98 99 bcmasp_set_promisc(intf, 0); 100 101 bcmasp_set_broad(intf, 1); 102 103 bcmasp_set_oaddr(intf, dev->dev_addr, 1); 104 105 if (dev->flags & IFF_ALLMULTI) { 106 bcmasp_set_allmulti(intf, 1); 107 } else { 108 bcmasp_set_allmulti(intf, 0); 109 110 netdev_for_each_mc_addr(ha, dev) { 111 ret = bcmasp_set_en_mda_filter(intf, ha->addr, mask); 112 if (ret) { 113 intf->mib.mc_filters_full_cnt++; 114 goto set_promisc; 115 } 116 } 117 } 118 119 netdev_for_each_uc_addr(ha, dev) { 120 ret = bcmasp_set_en_mda_filter(intf, ha->addr, mask); 121 if (ret) { 122 intf->mib.uc_filters_full_cnt++; 123 goto set_promisc; 124 } 125 } 126 127 spin_unlock_bh(&intf->parent->mda_lock); 128 return; 129 130 set_promisc: 131 bcmasp_set_promisc(intf, 1); 132 intf->mib.promisc_filters_cnt++; 133 134 /* disable all filters used by this port */ 135 bcmasp_disable_all_filters(intf); 136 137 spin_unlock_bh(&intf->parent->mda_lock); 138 } 139 140 static void bcmasp_clean_txcb(struct bcmasp_intf *intf, int index) 141 { 142 struct bcmasp_tx_cb *txcb = &intf->tx_cbs[index]; 143 144 txcb->skb = NULL; 145 dma_unmap_addr_set(txcb, dma_addr, 0); 146 dma_unmap_len_set(txcb, dma_len, 0); 147 txcb->last = false; 148 } 149 150 static int bcmasp_tx_avail(struct bcmasp_intf *intf) 151 { 152 int used = (READ_ONCE(intf->tx_spb_index) - 153 READ_ONCE(intf->tx_spb_clean_index) + DESC_RING_COUNT) % 154 DESC_RING_COUNT; 155 156 return DESC_RING_COUNT - used - 1; 157 } 158 159 static struct sk_buff *bcmasp_csum_offload(struct net_device *dev, 160 struct sk_buff *skb, 161 bool *csum_hw) 162 { 163 struct bcmasp_intf *intf = netdev_priv(dev); 164 u32 header = 0, header2 = 0, epkt = 0; 165 struct bcmasp_pkt_offload *offload; 166 unsigned int header_cnt = 0; 167 u8 ip_proto; 168 int ret; 169 170 if (skb->ip_summed != CHECKSUM_PARTIAL) 171 return skb; 172 173 ret = skb_cow_head(skb, sizeof(*offload)); 174 if (ret < 0) { 175 intf->mib.tx_realloc_offload_failed++; 176 goto help; 177 } 178 179 switch (skb->protocol) { 180 case htons(ETH_P_IP): 181 header |= PKT_OFFLOAD_HDR_SIZE_2((ip_hdrlen(skb) >> 8) & 0xf); 182 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(ip_hdrlen(skb) & 0xff); 183 epkt |= PKT_OFFLOAD_EPKT_IP(0); 184 ip_proto = ip_hdr(skb)->protocol; 185 header_cnt += 2; 186 break; 187 case htons(ETH_P_IPV6): 188 header |= PKT_OFFLOAD_HDR_SIZE_2((IP6_HLEN >> 8) & 0xf); 189 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(IP6_HLEN & 0xff); 190 epkt |= PKT_OFFLOAD_EPKT_IP(1); 191 ip_proto = ipv6_hdr(skb)->nexthdr; 192 header_cnt += 2; 193 break; 194 default: 195 goto help; 196 } 197 198 switch (ip_proto) { 199 case IPPROTO_TCP: 200 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(tcp_hdrlen(skb)); 201 epkt |= PKT_OFFLOAD_EPKT_TP(0) | PKT_OFFLOAD_EPKT_CSUM_L4; 202 header_cnt++; 203 break; 204 case IPPROTO_UDP: 205 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(UDP_HLEN); 206 epkt |= PKT_OFFLOAD_EPKT_TP(1) | PKT_OFFLOAD_EPKT_CSUM_L4; 207 header_cnt++; 208 break; 209 default: 210 goto help; 211 } 212 213 offload = (struct bcmasp_pkt_offload *)skb_push(skb, sizeof(*offload)); 214 215 header |= PKT_OFFLOAD_HDR_OP | PKT_OFFLOAD_HDR_COUNT(header_cnt) | 216 PKT_OFFLOAD_HDR_SIZE_1(ETH_HLEN); 217 epkt |= PKT_OFFLOAD_EPKT_OP; 218 219 offload->nop = htonl(PKT_OFFLOAD_NOP); 220 offload->header = htonl(header); 221 offload->header2 = htonl(header2); 222 offload->epkt = htonl(epkt); 223 offload->end = htonl(PKT_OFFLOAD_END_OP); 224 *csum_hw = true; 225 226 return skb; 227 228 help: 229 skb_checksum_help(skb); 230 231 return skb; 232 } 233 234 static netdev_tx_t bcmasp_xmit(struct sk_buff *skb, struct net_device *dev) 235 { 236 struct bcmasp_intf *intf = netdev_priv(dev); 237 unsigned int total_bytes, size, min_size; 238 int spb_index, nr_frags, i, j; 239 struct bcmasp_tx_cb *txcb; 240 dma_addr_t mapping, valid; 241 struct bcmasp_desc *desc; 242 struct netdev_queue *txq; 243 bool csum_hw = false; 244 struct device *kdev; 245 skb_frag_t *frag; 246 247 kdev = &intf->parent->pdev->dev; 248 txq = netdev_get_tx_queue(dev, 0); 249 250 nr_frags = skb_shinfo(skb)->nr_frags; 251 252 if (unlikely(bcmasp_tx_avail(intf) < nr_frags + 1)) { 253 netif_txq_try_stop(txq, bcmasp_tx_avail(intf), 254 BCMASP_TX_START_THRS); 255 if (net_ratelimit()) 256 netdev_err(dev, "Tx Ring Full!\n"); 257 return NETDEV_TX_BUSY; 258 } 259 260 /* Save skb len before adding csum offload header */ 261 total_bytes = skb->len; 262 skb = bcmasp_csum_offload(dev, skb, &csum_hw); 263 if (!skb) 264 return NETDEV_TX_OK; 265 266 min_size = ETH_ZLEN + ETH_FCS_LEN; 267 if (csum_hw) 268 min_size += sizeof(struct bcmasp_pkt_offload); 269 270 if (skb->len < min_size) { 271 if (skb_put_padto(skb, min_size)) 272 return NETDEV_TX_OK; 273 nr_frags = skb_shinfo(skb)->nr_frags; 274 } 275 276 spb_index = intf->tx_spb_index; 277 valid = intf->tx_spb_dma_valid; 278 for (i = 0; i <= nr_frags; i++) { 279 if (!i) { 280 size = skb_headlen(skb); 281 mapping = dma_map_single(kdev, skb->data, size, 282 DMA_TO_DEVICE); 283 } else { 284 frag = &skb_shinfo(skb)->frags[i - 1]; 285 size = skb_frag_size(frag); 286 mapping = skb_frag_dma_map(kdev, frag, 0, size, 287 DMA_TO_DEVICE); 288 } 289 290 if (dma_mapping_error(kdev, mapping)) { 291 intf->mib.tx_dma_failed++; 292 spb_index = intf->tx_spb_index; 293 for (j = 0; j < i; j++) { 294 txcb = &intf->tx_cbs[spb_index]; 295 dma_unmap_single(kdev, 296 dma_unmap_addr(txcb, dma_addr), 297 dma_unmap_len(txcb, dma_len), 298 DMA_TO_DEVICE); 299 bcmasp_clean_txcb(intf, spb_index); 300 spb_index = incr_ring(spb_index, 301 DESC_RING_COUNT); 302 } 303 /* Rewind so we do not have a hole */ 304 spb_index = intf->tx_spb_index; 305 dev_kfree_skb(skb); 306 return NETDEV_TX_OK; 307 } 308 309 txcb = &intf->tx_cbs[spb_index]; 310 desc = &intf->tx_spb_cpu[spb_index]; 311 memset(desc, 0, sizeof(*desc)); 312 txcb->skb = skb; 313 txcb->bytes_sent = total_bytes; 314 dma_unmap_addr_set(txcb, dma_addr, mapping); 315 dma_unmap_len_set(txcb, dma_len, size); 316 txcb->last = false; 317 if (!i) { 318 desc->flags |= DESC_SOF; 319 if (csum_hw) 320 desc->flags |= DESC_EPKT_CMD; 321 } 322 323 if (i == nr_frags) { 324 desc->flags |= DESC_EOF; 325 txcb->last = true; 326 } 327 328 desc->buf = mapping; 329 desc->size = size; 330 desc->flags |= DESC_INT_EN; 331 332 netif_dbg(intf, tx_queued, dev, 333 "%s dma_buf=%pad dma_len=0x%x flags=0x%x index=0x%x\n", 334 __func__, &mapping, desc->size, desc->flags, 335 spb_index); 336 337 spb_index = incr_ring(spb_index, DESC_RING_COUNT); 338 valid = incr_last_byte(valid, intf->tx_spb_dma_addr, 339 DESC_RING_COUNT); 340 } 341 342 /* Ensure all descriptors have been written to DRAM for the 343 * hardware to see up-to-date contents. 344 */ 345 wmb(); 346 347 WRITE_ONCE(intf->tx_spb_index, spb_index); 348 intf->tx_spb_dma_valid = valid; 349 350 netdev_tx_sent_queue(txq, total_bytes); 351 352 skb_tx_timestamp(skb); 353 354 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_VALID); 355 356 netif_txq_maybe_stop(txq, bcmasp_tx_avail(intf), 357 BCMASP_TX_STOP_THRS, BCMASP_TX_START_THRS); 358 359 return NETDEV_TX_OK; 360 } 361 362 static void umac_reset_and_init(struct bcmasp_intf *intf, 363 const unsigned char *addr) 364 { 365 struct phy_device *phydev = intf->ndev->phydev; 366 u32 mac0, mac1; 367 368 umac_wl(intf, 0x0, UMC_CMD); 369 umac_wl(intf, UMC_CMD_SW_RESET, UMC_CMD); 370 usleep_range(10, 100); 371 /* We hold the umac in reset and bring it out of 372 * reset when phy link is up. 373 */ 374 375 umac_wl(intf, 0x800, UMC_FRM_LEN); 376 umac_wl(intf, 0xffff, UMC_PAUSE_CNTRL); 377 umac_wl(intf, 0x800, UMC_RX_MAX_PKT_SZ); 378 379 mac0 = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | 380 addr[3]; 381 mac1 = (addr[4] << 8) | addr[5]; 382 383 umac_wl(intf, mac0, UMC_MAC0); 384 umac_wl(intf, mac1, UMC_MAC1); 385 386 /* Reset shadow values since we reset the umac */ 387 intf->old_duplex = -1; 388 intf->old_link = -1; 389 intf->old_pause = -1; 390 phydev->eee_cfg.tx_lpi_timer = umac_rl(intf, UMC_EEE_LPI_TIMER); 391 } 392 393 static void umac_enable_set(struct bcmasp_intf *intf, u32 mask, 394 unsigned int enable) 395 { 396 u32 reg; 397 398 reg = umac_rl(intf, UMC_CMD); 399 if (reg & UMC_CMD_SW_RESET) 400 return; 401 if (enable) 402 reg |= mask; 403 else 404 reg &= ~mask; 405 umac_wl(intf, reg, UMC_CMD); 406 407 /* UniMAC stops on a packet boundary, wait for a full-sized packet 408 * to be processed (1 msec). 409 */ 410 if (enable == 0) 411 usleep_range(1000, 2000); 412 } 413 414 static int bcmasp_tx_reclaim(struct bcmasp_intf *intf, unsigned int *bytes_out) 415 { 416 struct bcmasp_intf_stats64 *stats = &intf->stats64; 417 struct device *kdev = &intf->parent->pdev->dev; 418 unsigned int bytes_compl = 0; 419 struct bcmasp_tx_cb *txcb; 420 struct bcmasp_desc *desc; 421 unsigned long read; 422 dma_addr_t mapping; 423 int packets = 0; 424 425 read = tx_spb_dma_rq(intf, TX_SPB_DMA_READ); 426 while (intf->tx_spb_dma_read != read) { 427 txcb = &intf->tx_cbs[intf->tx_spb_clean_index]; 428 mapping = dma_unmap_addr(txcb, dma_addr); 429 430 dma_unmap_single(kdev, mapping, 431 dma_unmap_len(txcb, dma_len), 432 DMA_TO_DEVICE); 433 434 if (txcb->last) { 435 dev_consume_skb_any(txcb->skb); 436 437 u64_stats_update_begin(&stats->syncp); 438 u64_stats_inc(&stats->tx_packets); 439 u64_stats_add(&stats->tx_bytes, txcb->bytes_sent); 440 u64_stats_update_end(&stats->syncp); 441 442 bytes_compl += txcb->bytes_sent; 443 packets++; 444 } 445 446 desc = &intf->tx_spb_cpu[intf->tx_spb_clean_index]; 447 448 netif_dbg(intf, tx_done, intf->ndev, 449 "%s dma_buf=%pad dma_len=0x%x flags=0x%x c_index=0x%x\n", 450 __func__, &mapping, desc->size, desc->flags, 451 intf->tx_spb_clean_index); 452 453 bcmasp_clean_txcb(intf, intf->tx_spb_clean_index); 454 455 WRITE_ONCE(intf->tx_spb_clean_index, 456 incr_ring(intf->tx_spb_clean_index, DESC_RING_COUNT)); 457 intf->tx_spb_dma_read = incr_first_byte(intf->tx_spb_dma_read, 458 intf->tx_spb_dma_addr, 459 DESC_RING_COUNT); 460 } 461 462 if (bytes_out) 463 *bytes_out = bytes_compl; 464 465 return packets; 466 } 467 468 static int bcmasp_tx_poll(struct napi_struct *napi, int budget) 469 { 470 struct bcmasp_intf *intf = 471 container_of(napi, struct bcmasp_intf, tx_napi); 472 struct netdev_queue *txq = netdev_get_tx_queue(intf->ndev, 0); 473 unsigned int bytes = 0; 474 int packets; 475 476 packets = bcmasp_tx_reclaim(intf, &bytes); 477 478 netif_txq_completed_wake(txq, packets, bytes, 479 bcmasp_tx_avail(intf), BCMASP_TX_START_THRS); 480 481 napi_complete(&intf->tx_napi); 482 483 bcmasp_enable_tx_irq(intf, 1); 484 485 return 0; 486 } 487 488 static int bcmasp_rx_poll(struct napi_struct *napi, int budget) 489 { 490 struct bcmasp_intf *intf = 491 container_of(napi, struct bcmasp_intf, rx_napi); 492 struct bcmasp_intf_stats64 *stats = &intf->stats64; 493 struct device *kdev = &intf->parent->pdev->dev; 494 unsigned long processed = 0; 495 struct bcmasp_desc *desc; 496 struct sk_buff *skb; 497 dma_addr_t valid; 498 struct page *page; 499 void *data; 500 u64 flags; 501 u32 len; 502 503 /* Hardware advances DMA_VALID as it writes each descriptor 504 * (RBUF_4K streaming mode); software chases with rx_edpkt_dma_read. 505 */ 506 valid = rx_edpkt_dma_rq(intf, RX_EDPKT_DMA_VALID) + 1; 507 if (valid == intf->rx_edpkt_dma_addr + DESC_RING_SIZE) 508 valid = intf->rx_edpkt_dma_addr; 509 510 while ((processed < budget) && (valid != intf->rx_edpkt_dma_read)) { 511 desc = &intf->rx_edpkt_cpu[intf->rx_edpkt_index]; 512 513 /* Ensure the descriptor has been fully written to DRAM by 514 * the hardware before the CPU reads it. 515 */ 516 rmb(); 517 518 /* Locate the packet data inside the streaming ring buffer. */ 519 data = intf->rx_ring_cpu + 520 (DESC_ADDR(desc->buf) - intf->rx_ring_dma); 521 522 flags = DESC_FLAGS(desc->buf); 523 if (unlikely(flags & (DESC_CRC_ERR | DESC_RX_SYM_ERR))) { 524 if (net_ratelimit()) { 525 netif_err(intf, rx_status, intf->ndev, 526 "flags=0x%llx\n", flags); 527 } 528 529 u64_stats_update_begin(&stats->syncp); 530 if (flags & DESC_CRC_ERR) 531 u64_stats_inc(&stats->rx_crc_errs); 532 if (flags & DESC_RX_SYM_ERR) 533 u64_stats_inc(&stats->rx_sym_errs); 534 u64_stats_update_end(&stats->syncp); 535 536 goto next; 537 } 538 539 dma_sync_single_for_cpu(kdev, DESC_ADDR(desc->buf), desc->size, 540 DMA_FROM_DEVICE); 541 542 len = desc->size; 543 if (unlikely(len < 2 + ETH_HLEN + (intf->crc_fwd ? ETH_FCS_LEN : 0))) { 544 u64_stats_update_begin(&stats->syncp); 545 u64_stats_inc(&stats->rx_dropped); 546 u64_stats_update_end(&stats->syncp); 547 goto next; 548 } 549 550 /* Allocate a page pool page as the SKB data area so the 551 * kernel can recycle it efficiently after the packet is 552 * consumed, avoiding repeated slab allocations. 553 */ 554 page = page_pool_dev_alloc_pages(intf->rx_page_pool); 555 if (!page) { 556 u64_stats_update_begin(&stats->syncp); 557 u64_stats_inc(&stats->rx_dropped); 558 u64_stats_update_end(&stats->syncp); 559 intf->mib.alloc_rx_skb_failed++; 560 goto next; 561 } 562 563 skb = napi_build_skb(page_address(page), PAGE_SIZE); 564 if (!skb) { 565 u64_stats_update_begin(&stats->syncp); 566 u64_stats_inc(&stats->rx_dropped); 567 u64_stats_update_end(&stats->syncp); 568 intf->mib.alloc_rx_skb_failed++; 569 page_pool_recycle_direct(intf->rx_page_pool, page); 570 goto next; 571 } 572 573 /* Reserve headroom then copy the full descriptor payload 574 * (hardware prepends a 2-byte alignment pad at the start). 575 */ 576 skb_reserve(skb, NET_SKB_PAD); 577 skb_put(skb, len); 578 memcpy(skb->data, data, len); 579 skb_mark_for_recycle(skb); 580 581 /* Skip the 2-byte hardware alignment pad. */ 582 skb_pull(skb, 2); 583 len -= 2; 584 if (likely(intf->crc_fwd)) { 585 skb_trim(skb, len - ETH_FCS_LEN); 586 len -= ETH_FCS_LEN; 587 } 588 589 if ((intf->ndev->features & NETIF_F_RXCSUM) && 590 (desc->buf & DESC_CHKSUM)) 591 skb->ip_summed = CHECKSUM_UNNECESSARY; 592 593 skb->protocol = eth_type_trans(skb, intf->ndev); 594 595 napi_gro_receive(napi, skb); 596 597 u64_stats_update_begin(&stats->syncp); 598 u64_stats_inc(&stats->rx_packets); 599 u64_stats_add(&stats->rx_bytes, len); 600 u64_stats_update_end(&stats->syncp); 601 602 next: 603 /* Return this portion of the streaming ring buffer to HW. */ 604 rx_edpkt_cfg_wq(intf, (DESC_ADDR(desc->buf) + desc->size), 605 RX_EDPKT_RING_BUFFER_READ); 606 607 processed++; 608 intf->rx_edpkt_dma_read = 609 incr_first_byte(intf->rx_edpkt_dma_read, 610 intf->rx_edpkt_dma_addr, 611 DESC_RING_COUNT); 612 intf->rx_edpkt_index = incr_ring(intf->rx_edpkt_index, 613 DESC_RING_COUNT); 614 } 615 616 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_read, RX_EDPKT_DMA_READ); 617 618 if (processed < budget && napi_complete_done(&intf->rx_napi, processed)) 619 bcmasp_enable_rx_irq(intf, 1); 620 621 return processed; 622 } 623 624 static void bcmasp_adj_link(struct net_device *dev) 625 { 626 struct bcmasp_intf *intf = netdev_priv(dev); 627 struct phy_device *phydev = dev->phydev; 628 u32 cmd_bits = 0, reg; 629 int changed = 0; 630 631 if (intf->old_link != phydev->link) { 632 changed = 1; 633 intf->old_link = phydev->link; 634 } 635 636 if (intf->old_duplex != phydev->duplex) { 637 changed = 1; 638 intf->old_duplex = phydev->duplex; 639 } 640 641 switch (phydev->speed) { 642 case SPEED_2500: 643 cmd_bits = UMC_CMD_SPEED_2500; 644 break; 645 case SPEED_1000: 646 cmd_bits = UMC_CMD_SPEED_1000; 647 break; 648 case SPEED_100: 649 cmd_bits = UMC_CMD_SPEED_100; 650 break; 651 case SPEED_10: 652 cmd_bits = UMC_CMD_SPEED_10; 653 break; 654 default: 655 break; 656 } 657 cmd_bits <<= UMC_CMD_SPEED_SHIFT; 658 659 if (phydev->duplex == DUPLEX_HALF) 660 cmd_bits |= UMC_CMD_HD_EN; 661 662 if (intf->old_pause != phydev->pause) { 663 changed = 1; 664 intf->old_pause = phydev->pause; 665 } 666 667 if (!phydev->pause) 668 cmd_bits |= UMC_CMD_RX_PAUSE_IGNORE | UMC_CMD_TX_PAUSE_IGNORE; 669 670 if (!changed) 671 return; 672 673 if (phydev->link) { 674 reg = umac_rl(intf, UMC_CMD); 675 reg &= ~((UMC_CMD_SPEED_MASK << UMC_CMD_SPEED_SHIFT) | 676 UMC_CMD_HD_EN | UMC_CMD_RX_PAUSE_IGNORE | 677 UMC_CMD_TX_PAUSE_IGNORE); 678 reg |= cmd_bits; 679 if (reg & UMC_CMD_SW_RESET) { 680 reg &= ~UMC_CMD_SW_RESET; 681 umac_wl(intf, reg, UMC_CMD); 682 udelay(2); 683 reg |= UMC_CMD_TX_EN | UMC_CMD_RX_EN | UMC_CMD_PROMISC; 684 } 685 umac_wl(intf, reg, UMC_CMD); 686 687 umac_wl(intf, phydev->eee_cfg.tx_lpi_timer, UMC_EEE_LPI_TIMER); 688 reg = umac_rl(intf, UMC_EEE_CTRL); 689 if (phydev->enable_tx_lpi) 690 reg |= EEE_EN; 691 else 692 reg &= ~EEE_EN; 693 umac_wl(intf, reg, UMC_EEE_CTRL); 694 } 695 696 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 697 if (phydev->link) 698 reg |= RGMII_LINK; 699 else 700 reg &= ~RGMII_LINK; 701 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 702 703 if (changed) 704 phy_print_status(phydev); 705 } 706 707 static struct page_pool * 708 bcmasp_rx_page_pool_create(struct bcmasp_intf *intf) 709 { 710 struct page_pool_params pp_params = { 711 .order = 0, 712 .flags = 0, 713 .pool_size = NUM_4K_BUFFERS, 714 .nid = NUMA_NO_NODE, 715 .dev = &intf->parent->pdev->dev, 716 .napi = &intf->rx_napi, 717 .netdev = intf->ndev, 718 .offset = 0, 719 .max_len = PAGE_SIZE, 720 }; 721 722 return page_pool_create(&pp_params); 723 } 724 725 static int bcmasp_alloc_rx_buffers(struct bcmasp_intf *intf) 726 { 727 struct device *kdev = &intf->parent->pdev->dev; 728 struct page *buffer_pg; 729 int ret; 730 731 /* Contiguous streaming ring that hardware writes packet data into. */ 732 intf->rx_buf_order = get_order(RING_BUFFER_SIZE); 733 buffer_pg = alloc_pages(GFP_KERNEL, intf->rx_buf_order); 734 if (!buffer_pg) 735 return -ENOMEM; 736 737 intf->rx_ring_cpu = page_to_virt(buffer_pg); 738 intf->rx_ring_dma = dma_map_page(kdev, buffer_pg, 0, RING_BUFFER_SIZE, 739 DMA_FROM_DEVICE); 740 if (dma_mapping_error(kdev, intf->rx_ring_dma)) { 741 ret = -ENOMEM; 742 goto free_ring_pages; 743 } 744 745 /* Page pool for SKB data areas (copy targets, not DMA buffers). */ 746 intf->rx_page_pool = bcmasp_rx_page_pool_create(intf); 747 if (IS_ERR(intf->rx_page_pool)) { 748 ret = PTR_ERR(intf->rx_page_pool); 749 intf->rx_page_pool = NULL; 750 goto free_ring_dma; 751 } 752 753 return 0; 754 755 free_ring_dma: 756 dma_unmap_page(kdev, intf->rx_ring_dma, RING_BUFFER_SIZE, 757 DMA_FROM_DEVICE); 758 free_ring_pages: 759 __free_pages(buffer_pg, intf->rx_buf_order); 760 return ret; 761 } 762 763 static void bcmasp_reclaim_rx_buffers(struct bcmasp_intf *intf) 764 { 765 struct device *kdev = &intf->parent->pdev->dev; 766 767 page_pool_destroy(intf->rx_page_pool); 768 intf->rx_page_pool = NULL; 769 dma_unmap_page(kdev, intf->rx_ring_dma, RING_BUFFER_SIZE, 770 DMA_FROM_DEVICE); 771 __free_pages(virt_to_page(intf->rx_ring_cpu), intf->rx_buf_order); 772 } 773 774 static int bcmasp_alloc_buffers(struct bcmasp_intf *intf) 775 { 776 struct device *kdev = &intf->parent->pdev->dev; 777 int ret; 778 779 /* Alloc RX */ 780 ret = bcmasp_alloc_rx_buffers(intf); 781 if (ret) 782 return ret; 783 784 intf->rx_edpkt_cpu = dma_alloc_coherent(kdev, DESC_RING_SIZE, 785 &intf->rx_edpkt_dma_addr, 786 GFP_KERNEL); 787 if (!intf->rx_edpkt_cpu) 788 goto free_rx_buffers; 789 790 /* Alloc TX */ 791 intf->tx_spb_cpu = dma_alloc_coherent(kdev, DESC_RING_SIZE, 792 &intf->tx_spb_dma_addr, GFP_KERNEL); 793 if (!intf->tx_spb_cpu) 794 goto free_rx_edpkt_dma; 795 796 intf->tx_cbs = kzalloc_objs(struct bcmasp_tx_cb, DESC_RING_COUNT); 797 if (!intf->tx_cbs) 798 goto free_tx_spb_dma; 799 800 return 0; 801 802 free_tx_spb_dma: 803 dma_free_coherent(kdev, DESC_RING_SIZE, intf->tx_spb_cpu, 804 intf->tx_spb_dma_addr); 805 free_rx_edpkt_dma: 806 dma_free_coherent(kdev, DESC_RING_SIZE, intf->rx_edpkt_cpu, 807 intf->rx_edpkt_dma_addr); 808 free_rx_buffers: 809 bcmasp_reclaim_rx_buffers(intf); 810 811 return -ENOMEM; 812 } 813 814 static void bcmasp_reclaim_free_buffers(struct bcmasp_intf *intf) 815 { 816 struct device *kdev = &intf->parent->pdev->dev; 817 818 /* RX buffers */ 819 dma_free_coherent(kdev, DESC_RING_SIZE, intf->rx_edpkt_cpu, 820 intf->rx_edpkt_dma_addr); 821 bcmasp_reclaim_rx_buffers(intf); 822 823 /* TX buffers */ 824 dma_free_coherent(kdev, DESC_RING_SIZE, intf->tx_spb_cpu, 825 intf->tx_spb_dma_addr); 826 kfree(intf->tx_cbs); 827 } 828 829 static void bcmasp_init_rx(struct bcmasp_intf *intf) 830 { 831 /* Restart from index 0 */ 832 intf->rx_ring_dma_valid = intf->rx_ring_dma + RING_BUFFER_SIZE - 1; 833 intf->rx_edpkt_dma_valid = intf->rx_edpkt_dma_addr + (DESC_RING_SIZE - 1); 834 intf->rx_edpkt_dma_read = intf->rx_edpkt_dma_addr; 835 intf->rx_edpkt_index = 0; 836 837 /* Make sure channels are disabled */ 838 rx_edpkt_cfg_wl(intf, 0x0, RX_EDPKT_CFG_ENABLE); 839 840 /* Streaming data ring: hardware writes raw packet bytes here. */ 841 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_READ); 842 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_WRITE); 843 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_BASE); 844 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma_valid, 845 RX_EDPKT_RING_BUFFER_END); 846 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma_valid, 847 RX_EDPKT_RING_BUFFER_VALID); 848 849 /* EDPKT descriptor ring: hardware fills descriptors pointing into 850 * the streaming ring buffer above (RBUF_4K mode). 851 */ 852 rx_edpkt_cfg_wl(intf, (RX_EDPKT_CFG_CFG0_RBUF_4K << 853 RX_EDPKT_CFG_CFG0_DBUF_SHIFT) | 854 (RX_EDPKT_CFG_CFG0_64_ALN << 855 RX_EDPKT_CFG_CFG0_BALN_SHIFT) | 856 (RX_EDPKT_CFG_CFG0_EFRM_STUF), 857 RX_EDPKT_CFG_CFG0); 858 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_WRITE); 859 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_READ); 860 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_BASE); 861 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_valid, RX_EDPKT_DMA_END); 862 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_valid, RX_EDPKT_DMA_VALID); 863 864 umac2fb_wl(intf, UMAC2FB_CFG_DEFAULT_EN | ((intf->channel + 11) << 865 UMAC2FB_CFG_CHID_SHIFT) | (0xd << UMAC2FB_CFG_OK_SEND_SHIFT), 866 UMAC2FB_CFG); 867 } 868 869 870 static void bcmasp_init_tx(struct bcmasp_intf *intf) 871 { 872 /* Restart from index 0 */ 873 intf->tx_spb_dma_valid = intf->tx_spb_dma_addr + DESC_RING_SIZE - 1; 874 intf->tx_spb_dma_read = intf->tx_spb_dma_addr; 875 intf->tx_spb_index = 0; 876 intf->tx_spb_clean_index = 0; 877 memset(intf->tx_cbs, 0, sizeof(struct bcmasp_tx_cb) * DESC_RING_COUNT); 878 netdev_tx_reset_queue(netdev_get_tx_queue(intf->ndev, 0)); 879 880 /* Make sure channels are disabled */ 881 tx_spb_ctrl_wl(intf, 0x0, TX_SPB_CTRL_ENABLE); 882 tx_epkt_core_wl(intf, 0x0, TX_EPKT_C_CFG_MISC); 883 884 /* Tx SPB */ 885 tx_spb_ctrl_wl(intf, ((intf->channel + 8) << TX_SPB_CTRL_XF_BID_SHIFT), 886 TX_SPB_CTRL_XF_CTRL2); 887 888 if (intf->parent->tx_chan_offset) 889 tx_pause_ctrl_wl(intf, (1 << (intf->channel + 8)), TX_PAUSE_MAP_VECTOR); 890 tx_spb_top_wl(intf, 0x1e, TX_SPB_TOP_BLKOUT); 891 892 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_READ); 893 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_BASE); 894 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_END); 895 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_VALID); 896 } 897 898 static void bcmasp_ephy_enable_set(struct bcmasp_intf *intf, bool enable) 899 { 900 u32 mask = RGMII_EPHY_CFG_IDDQ_BIAS | RGMII_EPHY_CFG_EXT_PWRDOWN | 901 RGMII_EPHY_CFG_IDDQ_GLOBAL; 902 u32 reg; 903 904 reg = rgmii_rl(intf, RGMII_EPHY_CNTRL); 905 if (enable) { 906 reg &= ~RGMII_EPHY_CK25_DIS; 907 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 908 mdelay(1); 909 910 reg &= ~mask; 911 reg |= RGMII_EPHY_RESET; 912 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 913 mdelay(1); 914 915 reg &= ~RGMII_EPHY_RESET; 916 } else { 917 reg |= mask | RGMII_EPHY_RESET; 918 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 919 mdelay(1); 920 reg |= RGMII_EPHY_CK25_DIS; 921 } 922 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 923 mdelay(1); 924 925 /* Set or clear the LED control override to avoid lighting up LEDs 926 * while the EPHY is powered off and drawing unnecessary current. 927 */ 928 reg = rgmii_rl(intf, RGMII_SYS_LED_CNTRL); 929 if (enable) 930 reg &= ~RGMII_SYS_LED_CNTRL_LINK_OVRD; 931 else 932 reg |= RGMII_SYS_LED_CNTRL_LINK_OVRD; 933 rgmii_wl(intf, reg, RGMII_SYS_LED_CNTRL); 934 } 935 936 static void bcmasp_rgmii_mode_en_set(struct bcmasp_intf *intf, bool enable) 937 { 938 u32 reg; 939 940 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 941 reg &= ~RGMII_OOB_DIS; 942 if (enable) 943 reg |= RGMII_MODE_EN; 944 else 945 reg &= ~RGMII_MODE_EN; 946 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 947 } 948 949 static void bcmasp_phy_hw_unprepare(struct bcmasp_intf *intf) 950 { 951 if (intf->internal_phy) 952 bcmasp_ephy_enable_set(intf, false); 953 else 954 bcmasp_rgmii_mode_en_set(intf, false); 955 } 956 957 static void bcmasp_netif_deinit(struct net_device *dev, bool stop_phy) 958 { 959 struct bcmasp_intf *intf = netdev_priv(dev); 960 u32 reg, timeout = 1000; 961 962 napi_disable(&intf->tx_napi); 963 964 bcmasp_enable_tx(intf, 0); 965 966 /* Flush any TX packets in the pipe */ 967 tx_spb_dma_wl(intf, TX_SPB_DMA_FIFO_FLUSH, TX_SPB_DMA_FIFO_CTRL); 968 do { 969 reg = tx_spb_dma_rl(intf, TX_SPB_DMA_FIFO_STATUS); 970 if (!(reg & TX_SPB_DMA_FIFO_FLUSH)) 971 break; 972 usleep_range(1000, 2000); 973 } while (timeout-- > 0); 974 tx_spb_dma_wl(intf, 0x0, TX_SPB_DMA_FIFO_CTRL); 975 976 bcmasp_tx_reclaim(intf, NULL); 977 978 umac_enable_set(intf, UMC_CMD_TX_EN, 0); 979 980 if (stop_phy) 981 phy_stop(dev->phydev); 982 983 umac_enable_set(intf, UMC_CMD_RX_EN, 0); 984 985 bcmasp_flush_rx_port(intf); 986 usleep_range(1000, 2000); 987 bcmasp_enable_rx(intf, 0); 988 989 napi_disable(&intf->rx_napi); 990 991 /* Disable interrupts */ 992 bcmasp_enable_tx_irq(intf, 0); 993 bcmasp_enable_rx_irq(intf, 0); 994 bcmasp_enable_phy_irq(intf, 0); 995 996 netif_napi_del(&intf->tx_napi); 997 netif_napi_del(&intf->rx_napi); 998 } 999 1000 static int bcmasp_stop(struct net_device *dev) 1001 { 1002 struct bcmasp_intf *intf = netdev_priv(dev); 1003 1004 netif_dbg(intf, ifdown, dev, "bcmasp stop\n"); 1005 1006 /* Stop tx from updating HW */ 1007 netif_tx_disable(dev); 1008 1009 bcmasp_netif_deinit(dev, true); 1010 1011 bcmasp_reclaim_free_buffers(intf); 1012 1013 phy_disconnect(dev->phydev); 1014 1015 bcmasp_phy_hw_unprepare(intf); 1016 1017 /* Disable the interface clocks */ 1018 bcmasp_core_clock_set_intf(intf, false); 1019 1020 clk_disable_unprepare(intf->parent->clk); 1021 1022 return 0; 1023 } 1024 1025 static void bcmasp_phy_hw_prepare(struct bcmasp_intf *intf) 1026 { 1027 u32 reg, id_mode_dis = 0; 1028 1029 if (intf->internal_phy) 1030 bcmasp_ephy_enable_set(intf, true); 1031 else 1032 bcmasp_rgmii_mode_en_set(intf, true); 1033 1034 reg = rgmii_rl(intf, RGMII_PORT_CNTRL); 1035 reg &= ~RGMII_PORT_MODE_MASK; 1036 1037 switch (intf->phy_interface) { 1038 case PHY_INTERFACE_MODE_RGMII: 1039 /* RGMII_NO_ID: TXC transitions at the same time as TXD 1040 * (requires PCB or receiver-side delay) 1041 * RGMII: Add 2ns delay on TXC (90 degree shift) 1042 * 1043 * ID is implicitly disabled for 100Mbps (RG)MII operation. 1044 */ 1045 id_mode_dis = RGMII_ID_MODE_DIS; 1046 fallthrough; 1047 case PHY_INTERFACE_MODE_RGMII_TXID: 1048 reg |= RGMII_PORT_MODE_EXT_GPHY; 1049 break; 1050 case PHY_INTERFACE_MODE_MII: 1051 reg |= RGMII_PORT_MODE_EXT_EPHY; 1052 break; 1053 default: 1054 break; 1055 } 1056 1057 if (intf->internal_phy) 1058 reg |= RGMII_PORT_MODE_EPHY; 1059 1060 rgmii_wl(intf, reg, RGMII_PORT_CNTRL); 1061 1062 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 1063 reg &= ~RGMII_ID_MODE_DIS; 1064 reg |= id_mode_dis; 1065 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 1066 } 1067 1068 static phy_interface_t bcmasp_phy_iface_for_connect(phy_interface_t mode) 1069 { 1070 /* This is an ugly quirk but we have not been correctly 1071 * interpreting the phy_interface values and we have done that 1072 * across different drivers, so at least we are consistent in 1073 * our mistakes. 1074 * 1075 * When the Generic PHY driver is in use either the PHY has 1076 * been strapped or programmed correctly by the boot loader so 1077 * we should stick to our incorrect interpretation since we 1078 * have validated it. 1079 * 1080 * Now when a dedicated PHY driver is in use, we need to 1081 * reverse the meaning of the phy_interface_mode values to 1082 * something that the PHY driver will interpret and act on such 1083 * that we have two mistakes canceling themselves so to speak. 1084 * We only do this for the two modes that GENET driver 1085 * officially supports on Broadcom STB chips: 1086 * PHY_INTERFACE_MODE_RGMII and PHY_INTERFACE_MODE_RGMII_TXID. 1087 * Other modes are not *officially* supported with the boot 1088 * loader and the scripted environment generating Device Tree 1089 * blobs for those platforms. 1090 * 1091 * Note that internal PHY and fixed-link configurations are not 1092 * affected because they use different phy_interface_t values 1093 * or the Generic PHY driver. 1094 */ 1095 switch (mode) { 1096 case PHY_INTERFACE_MODE_RGMII: 1097 return PHY_INTERFACE_MODE_RGMII_ID; 1098 case PHY_INTERFACE_MODE_RGMII_TXID: 1099 return PHY_INTERFACE_MODE_RGMII_RXID; 1100 default: 1101 return mode; 1102 } 1103 } 1104 1105 static int bcmasp_phy_attach(struct bcmasp_intf *intf) 1106 { 1107 u32 phy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE | 1108 PHY_BRCM_DIS_TXCRXC_NOENRGY | 1109 PHY_BRCM_IDDQ_SUSPEND; 1110 struct phy_device *phydev; 1111 phy_interface_t phy_iface; 1112 1113 phy_iface = bcmasp_phy_iface_for_connect(intf->phy_interface); 1114 phydev = of_phy_connect(intf->ndev, intf->phy_dn, 1115 bcmasp_adj_link, phy_flags, 1116 phy_iface); 1117 if (!phydev) { 1118 netdev_err(intf->ndev, "could not attach to PHY\n"); 1119 return -ENODEV; 1120 } 1121 if (intf->internal_phy) 1122 intf->ndev->phydev->irq = PHY_MAC_INTERRUPT; 1123 1124 phydev->mac_managed_pm = true; 1125 1126 return 0; 1127 } 1128 1129 static void bcmasp_netif_init(struct net_device *dev) 1130 { 1131 struct bcmasp_intf *intf = netdev_priv(dev); 1132 1133 bcmasp_init_tx(intf); 1134 netif_napi_add_tx(intf->ndev, &intf->tx_napi, bcmasp_tx_poll); 1135 bcmasp_enable_tx(intf, 1); 1136 1137 bcmasp_init_rx(intf); 1138 netif_napi_add(intf->ndev, &intf->rx_napi, bcmasp_rx_poll); 1139 bcmasp_enable_rx(intf, 1); 1140 1141 intf->crc_fwd = !!(umac_rl(intf, UMC_CMD) & UMC_CMD_CRC_FWD); 1142 1143 bcmasp_set_rx_mode(dev); 1144 napi_enable(&intf->tx_napi); 1145 napi_enable(&intf->rx_napi); 1146 1147 bcmasp_enable_rx_irq(intf, 1); 1148 bcmasp_enable_tx_irq(intf, 1); 1149 bcmasp_enable_phy_irq(intf, 1); 1150 } 1151 1152 static int bcmasp_open(struct net_device *dev) 1153 { 1154 struct bcmasp_intf *intf = netdev_priv(dev); 1155 int ret; 1156 1157 netif_dbg(intf, ifup, dev, "bcmasp open\n"); 1158 1159 ret = bcmasp_alloc_buffers(intf); 1160 if (ret) 1161 return ret; 1162 1163 ret = clk_prepare_enable(intf->parent->clk); 1164 if (ret) 1165 goto err_free_mem; 1166 1167 bcmasp_core_clock_set_intf(intf, true); 1168 1169 bcmasp_phy_hw_prepare(intf); 1170 1171 ret = bcmasp_phy_attach(intf); 1172 if (ret) 1173 goto err_phy_attach; 1174 1175 umac_reset_and_init(intf, dev->dev_addr); 1176 1177 dev->phydev->eee_cfg.tx_lpi_timer = umac_rl(intf, UMC_EEE_LPI_TIMER); 1178 1179 bcmasp_netif_init(dev); 1180 1181 phy_start(dev->phydev); 1182 1183 netif_start_queue(dev); 1184 1185 return ret; 1186 1187 err_phy_attach: 1188 bcmasp_phy_hw_unprepare(intf); 1189 bcmasp_core_clock_set_intf(intf, false); 1190 clk_disable_unprepare(intf->parent->clk); 1191 err_free_mem: 1192 bcmasp_reclaim_free_buffers(intf); 1193 1194 return ret; 1195 } 1196 1197 static void bcmasp_tx_timeout(struct net_device *dev, unsigned int txqueue) 1198 { 1199 struct bcmasp_intf *intf = netdev_priv(dev); 1200 1201 netif_dbg(intf, tx_err, dev, "transmit timeout!\n"); 1202 intf->mib.tx_timeout_cnt++; 1203 } 1204 1205 static int bcmasp_get_phys_port_name(struct net_device *dev, 1206 char *name, size_t len) 1207 { 1208 struct bcmasp_intf *intf = netdev_priv(dev); 1209 1210 if (snprintf(name, len, "p%d", intf->port) >= len) 1211 return -EINVAL; 1212 1213 return 0; 1214 } 1215 1216 static void bcmasp_get_stats64(struct net_device *dev, 1217 struct rtnl_link_stats64 *stats) 1218 { 1219 struct bcmasp_intf *intf = netdev_priv(dev); 1220 struct bcmasp_intf_stats64 *lstats; 1221 unsigned int start; 1222 1223 lstats = &intf->stats64; 1224 1225 do { 1226 start = u64_stats_fetch_begin(&lstats->syncp); 1227 stats->rx_packets = u64_stats_read(&lstats->rx_packets); 1228 stats->rx_bytes = u64_stats_read(&lstats->rx_bytes); 1229 stats->rx_dropped = u64_stats_read(&lstats->rx_dropped); 1230 stats->rx_crc_errors = u64_stats_read(&lstats->rx_crc_errs); 1231 stats->rx_frame_errors = u64_stats_read(&lstats->rx_sym_errs); 1232 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors; 1233 1234 stats->tx_packets = u64_stats_read(&lstats->tx_packets); 1235 stats->tx_bytes = u64_stats_read(&lstats->tx_bytes); 1236 } while (u64_stats_fetch_retry(&lstats->syncp, start)); 1237 } 1238 1239 static const struct net_device_ops bcmasp_netdev_ops = { 1240 .ndo_open = bcmasp_open, 1241 .ndo_stop = bcmasp_stop, 1242 .ndo_start_xmit = bcmasp_xmit, 1243 .ndo_tx_timeout = bcmasp_tx_timeout, 1244 .ndo_set_rx_mode = bcmasp_set_rx_mode, 1245 .ndo_get_phys_port_name = bcmasp_get_phys_port_name, 1246 .ndo_eth_ioctl = phy_do_ioctl_running, 1247 .ndo_set_mac_address = eth_mac_addr, 1248 .ndo_get_stats64 = bcmasp_get_stats64, 1249 }; 1250 1251 static void bcmasp_map_res(struct bcmasp_priv *priv, struct bcmasp_intf *intf) 1252 { 1253 /* Per port */ 1254 intf->res.umac = priv->base + UMC_OFFSET(intf); 1255 intf->res.umac2fb = priv->base + (UMAC2FB_OFFSET + priv->rx_ctrl_offset + 1256 (intf->port * 0x4)); 1257 intf->res.rgmii = priv->base + RGMII_OFFSET(intf); 1258 1259 /* Per ch */ 1260 intf->tx_spb_dma = priv->base + TX_SPB_DMA_OFFSET(intf); 1261 intf->res.tx_spb_ctrl = priv->base + TX_SPB_CTRL_OFFSET(intf); 1262 intf->res.tx_spb_top = priv->base + TX_SPB_TOP_OFFSET(intf); 1263 intf->res.tx_epkt_core = priv->base + TX_EPKT_C_OFFSET(intf); 1264 intf->res.tx_pause_ctrl = priv->base + TX_PAUSE_CTRL_OFFSET(intf); 1265 1266 intf->rx_edpkt_dma = priv->base + RX_EDPKT_DMA_OFFSET(intf); 1267 intf->rx_edpkt_cfg = priv->base + RX_EDPKT_CFG_OFFSET(intf); 1268 } 1269 1270 struct bcmasp_intf *bcmasp_interface_create(struct bcmasp_priv *priv, 1271 struct device_node *ndev_dn, int i) 1272 { 1273 struct device *dev = &priv->pdev->dev; 1274 struct bcmasp_intf *intf; 1275 struct net_device *ndev; 1276 int ch, port, ret; 1277 1278 if (of_property_read_u32(ndev_dn, "reg", &port)) { 1279 dev_warn(dev, "%s: invalid port number\n", ndev_dn->name); 1280 goto err; 1281 } 1282 1283 if (of_property_read_u32(ndev_dn, "brcm,channel", &ch)) { 1284 dev_warn(dev, "%s: invalid ch number\n", ndev_dn->name); 1285 goto err; 1286 } 1287 1288 ndev = alloc_etherdev(sizeof(struct bcmasp_intf)); 1289 if (!ndev) { 1290 dev_warn(dev, "%s: unable to alloc ndev\n", ndev_dn->name); 1291 goto err; 1292 } 1293 intf = netdev_priv(ndev); 1294 1295 intf->parent = priv; 1296 intf->ndev = ndev; 1297 intf->channel = ch; 1298 intf->port = port; 1299 intf->ndev_dn = ndev_dn; 1300 intf->index = i; 1301 1302 ret = of_get_phy_mode(ndev_dn, &intf->phy_interface); 1303 if (ret < 0) { 1304 dev_err(dev, "invalid PHY mode property\n"); 1305 goto err_free_netdev; 1306 } 1307 1308 if (intf->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 1309 intf->internal_phy = true; 1310 1311 intf->phy_dn = of_parse_phandle(ndev_dn, "phy-handle", 0); 1312 if (!intf->phy_dn && of_phy_is_fixed_link(ndev_dn)) { 1313 ret = of_phy_register_fixed_link(ndev_dn); 1314 if (ret) { 1315 dev_warn(dev, "%s: failed to register fixed PHY\n", 1316 ndev_dn->name); 1317 goto err_free_netdev; 1318 } 1319 intf->phy_dn = of_node_get(ndev_dn); 1320 } 1321 1322 /* Map resource */ 1323 bcmasp_map_res(priv, intf); 1324 1325 if ((!phy_interface_mode_is_rgmii(intf->phy_interface) && 1326 intf->phy_interface != PHY_INTERFACE_MODE_MII && 1327 intf->phy_interface != PHY_INTERFACE_MODE_INTERNAL) || 1328 (intf->port != 1 && intf->internal_phy)) { 1329 netdev_err(intf->ndev, "invalid PHY mode: %s for port %d\n", 1330 phy_modes(intf->phy_interface), intf->port); 1331 ret = -EINVAL; 1332 goto err_deregister_fixed_link; 1333 } 1334 1335 ret = of_get_ethdev_address(ndev_dn, ndev); 1336 if (ret) { 1337 netdev_warn(ndev, "using random Ethernet MAC\n"); 1338 eth_hw_addr_random(ndev); 1339 } 1340 1341 SET_NETDEV_DEV(ndev, dev); 1342 ndev->netdev_ops = &bcmasp_netdev_ops; 1343 ndev->ethtool_ops = &bcmasp_ethtool_ops; 1344 intf->msg_enable = netif_msg_init(-1, NETIF_MSG_DRV | 1345 NETIF_MSG_PROBE | 1346 NETIF_MSG_LINK); 1347 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 1348 NETIF_F_RXCSUM; 1349 ndev->hw_features |= ndev->features; 1350 ndev->needed_headroom += sizeof(struct bcmasp_pkt_offload); 1351 1352 netdev_sw_irq_coalesce_default_on(ndev); 1353 1354 return intf; 1355 1356 err_deregister_fixed_link: 1357 if (of_phy_is_fixed_link(ndev_dn)) 1358 of_phy_deregister_fixed_link(ndev_dn); 1359 of_node_put(intf->phy_dn); 1360 err_free_netdev: 1361 free_netdev(ndev); 1362 err: 1363 return NULL; 1364 } 1365 1366 void bcmasp_interface_destroy(struct bcmasp_intf *intf) 1367 { 1368 if (intf->ndev->reg_state == NETREG_REGISTERED) 1369 unregister_netdev(intf->ndev); 1370 if (of_phy_is_fixed_link(intf->ndev_dn)) 1371 of_phy_deregister_fixed_link(intf->ndev_dn); 1372 of_node_put(intf->phy_dn); 1373 free_netdev(intf->ndev); 1374 } 1375 1376 static void bcmasp_suspend_to_wol(struct bcmasp_intf *intf) 1377 { 1378 struct net_device *ndev = intf->ndev; 1379 u32 reg; 1380 1381 reg = umac_rl(intf, UMC_MPD_CTRL); 1382 if (intf->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) 1383 reg |= UMC_MPD_CTRL_MPD_EN; 1384 reg &= ~UMC_MPD_CTRL_PSW_EN; 1385 if (intf->wolopts & WAKE_MAGICSECURE) { 1386 /* Program the SecureOn password */ 1387 umac_wl(intf, get_unaligned_be16(&intf->sopass[0]), 1388 UMC_PSW_MS); 1389 umac_wl(intf, get_unaligned_be32(&intf->sopass[2]), 1390 UMC_PSW_LS); 1391 reg |= UMC_MPD_CTRL_PSW_EN; 1392 } 1393 umac_wl(intf, reg, UMC_MPD_CTRL); 1394 1395 if (intf->wolopts & WAKE_FILTER) 1396 bcmasp_netfilt_suspend(intf); 1397 1398 /* Bring UniMAC out of reset if needed and enable RX */ 1399 reg = umac_rl(intf, UMC_CMD); 1400 if (reg & UMC_CMD_SW_RESET) 1401 reg &= ~UMC_CMD_SW_RESET; 1402 1403 reg |= UMC_CMD_RX_EN | UMC_CMD_PROMISC; 1404 umac_wl(intf, reg, UMC_CMD); 1405 1406 umac_enable_set(intf, UMC_CMD_RX_EN, 1); 1407 1408 wakeup_intr2_core_wl(intf->parent, 0xffffffff, 1409 ASP_WAKEUP_INTR2_MASK_CLEAR); 1410 1411 if (ndev->phydev && ndev->phydev->eee_cfg.eee_enabled && 1412 intf->parent->eee_fixup) 1413 intf->parent->eee_fixup(intf, true); 1414 1415 netif_dbg(intf, wol, ndev, "entered WOL mode\n"); 1416 } 1417 1418 int bcmasp_interface_suspend(struct bcmasp_intf *intf) 1419 { 1420 struct device *kdev = &intf->parent->pdev->dev; 1421 struct net_device *dev = intf->ndev; 1422 bool wake; 1423 1424 if (!netif_running(dev)) 1425 return 0; 1426 1427 netif_device_detach(dev); 1428 1429 wake = device_may_wakeup(kdev) && intf->wolopts; 1430 1431 bcmasp_netif_deinit(dev, !wake); 1432 1433 if (wake) { 1434 /* Disable phy status updates while suspending */ 1435 mutex_lock(&dev->phydev->lock); 1436 dev->phydev->state = PHY_READY; 1437 mutex_unlock(&dev->phydev->lock); 1438 cancel_delayed_work_sync(&dev->phydev->state_queue); 1439 1440 bcmasp_suspend_to_wol(intf); 1441 } else { 1442 bcmasp_phy_hw_unprepare(intf); 1443 1444 /* If Wake-on-LAN is disabled, we can safely 1445 * disable the network interface clocks. 1446 */ 1447 bcmasp_core_clock_set_intf(intf, false); 1448 } 1449 1450 clk_disable_unprepare(intf->parent->clk); 1451 1452 return 0; 1453 } 1454 1455 static void bcmasp_resume_from_wol(struct bcmasp_intf *intf) 1456 { 1457 u32 reg; 1458 1459 if (intf->ndev->phydev && intf->ndev->phydev->eee_cfg.eee_enabled && 1460 intf->parent->eee_fixup) 1461 intf->parent->eee_fixup(intf, false); 1462 1463 reg = umac_rl(intf, UMC_MPD_CTRL); 1464 reg &= ~UMC_MPD_CTRL_MPD_EN; 1465 umac_wl(intf, reg, UMC_MPD_CTRL); 1466 1467 wakeup_intr2_core_wl(intf->parent, 0xffffffff, 1468 ASP_WAKEUP_INTR2_MASK_SET); 1469 } 1470 1471 int bcmasp_interface_resume(struct bcmasp_intf *intf) 1472 { 1473 struct device *kdev = &intf->parent->pdev->dev; 1474 struct net_device *dev = intf->ndev; 1475 bool wake; 1476 int ret; 1477 u32 reg; 1478 1479 if (!netif_running(dev)) 1480 return 0; 1481 1482 ret = clk_prepare_enable(intf->parent->clk); 1483 if (ret) 1484 return ret; 1485 1486 wake = device_may_wakeup(kdev) && intf->wolopts; 1487 1488 bcmasp_core_clock_set_intf(intf, true); 1489 1490 /* The interface might be HW reset in some suspend modes, so we may 1491 * need to restore the UNIMAC/PHY if that is the case. 1492 */ 1493 reg = umac_rl(intf, UMC_CMD); 1494 if (wake && (reg & UMC_CMD_RX_EN)) { 1495 umac_enable_set(intf, UMC_CMD_TX_EN, 1); 1496 bcmasp_resume_from_wol(intf); 1497 } else { 1498 bcmasp_phy_hw_prepare(intf); 1499 umac_reset_and_init(intf, dev->dev_addr); 1500 } 1501 1502 bcmasp_netif_init(dev); 1503 1504 if (wake) { 1505 /* If HW was reset, reprogram the unimac/PHY before resuming 1506 * link status tracking to avoid racing the state machine. 1507 */ 1508 if (!(reg & UMC_CMD_RX_EN)) 1509 bcmasp_adj_link(dev); 1510 1511 /* Resume link status tracking */ 1512 mutex_lock(&dev->phydev->lock); 1513 dev->phydev->state = dev->phydev->link ? PHY_RUNNING : PHY_NOLINK; 1514 mutex_unlock(&dev->phydev->lock); 1515 phy_trigger_machine(dev->phydev); 1516 } else { 1517 phy_start(dev->phydev); 1518 } 1519 1520 netif_device_attach(dev); 1521 1522 return 0; 1523 } 1524