1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AD7192 and similar SPI ADC driver
4 *
5 * Copyright 2011-2015 Analog Devices Inc.
6 */
7
8 #include <linux/interrupt.h>
9 #include <linux/bitfield.h>
10 #include <linux/cleanup.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/device.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/sysfs.h>
17 #include <linux/spi/spi.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/err.h>
20 #include <linux/sched.h>
21 #include <linux/delay.h>
22 #include <linux/module.h>
23 #include <linux/mod_devicetable.h>
24 #include <linux/property.h>
25 #include <linux/units.h>
26
27 #include <linux/iio/iio.h>
28 #include <linux/iio/sysfs.h>
29 #include <linux/iio/buffer.h>
30 #include <linux/iio/trigger.h>
31 #include <linux/iio/trigger_consumer.h>
32 #include <linux/iio/triggered_buffer.h>
33 #include <linux/iio/adc/ad_sigma_delta.h>
34
35 /* Registers */
36 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
37 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
38 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
39 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
40 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
41 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
42 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
43 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
44 /* (AD7792)/24-bit (AD7192)) */
45 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
46 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
47
48 /* Communications Register Bit Designations (AD7192_REG_COMM) */
49 #define AD7192_COMM_WEN BIT(7) /* Write Enable */
50 #define AD7192_COMM_WRITE 0 /* Write Operation */
51 #define AD7192_COMM_READ BIT(6) /* Read Operation */
52 #define AD7192_COMM_ADDR_MASK GENMASK(5, 3) /* Register Address Mask */
53 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */
54
55 /* Status Register Bit Designations (AD7192_REG_STAT) */
56 #define AD7192_STAT_RDY BIT(7) /* Ready */
57 #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */
58 #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */
59 #define AD7192_STAT_PARITY BIT(4) /* Parity */
60 #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */
61 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
62 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
63
64 /* Mode Register Bit Designations (AD7192_REG_MODE) */
65 #define AD7192_MODE_SEL_MASK GENMASK(23, 21) /* Operation Mode Select Mask */
66 #define AD7192_MODE_STA_MASK BIT(20) /* Status Register transmission Mask */
67 #define AD7192_MODE_CLKSRC_MASK GENMASK(19, 18) /* Clock Source Select Mask */
68 #define AD7192_MODE_AVG_MASK GENMASK(17, 16)
69 /* Fast Settling Filter Average Select Mask (AD7193 only) */
70 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
71 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
72 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
73 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
74 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */
75 /* Filter Update Rate Select Mask */
76 #define AD7192_MODE_RATE_MASK GENMASK(9, 0)
77
78 /* Mode Register: AD7192_MODE_SEL options */
79 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
80 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
81 #define AD7192_MODE_IDLE 2 /* Idle Mode */
82 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
83 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
84 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
85 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
86 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
87
88 /* Mode Register: AD7192_MODE_CLKSRC options */
89 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/
90 /* from MCLK1 to MCLK2 */
91 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
92 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */
93 /* available at the MCLK2 pin */
94 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/
95 /* at the MCLK2 pin */
96
97 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
98
99 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */
100 #define AD7192_CONF_ACX BIT(22) /* AC excitation enable(AD7195 only) */
101 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
102 #define AD7192_CONF_CHAN_MASK GENMASK(18, 8) /* Channel select mask */
103 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */
104 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */
105 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */
106 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */
107 #define AD7192_CONF_GAIN_MASK GENMASK(2, 0) /* Gain Select */
108
109 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */
110 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
111 #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */
112 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */
113 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */
114 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */
115 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */
116 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */
117
118 #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */
119 #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */
120 #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */
121 #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */
122 #define AD7193_CH_TEMP 0x100 /* Temp senseor */
123 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */
124 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */
125 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */
126 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */
127 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */
128 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */
129 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */
130 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */
131 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */
132 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */
133
134 #define AD7194_CH_POS(x) (((x) - 1) << 4)
135 #define AD7194_CH_NEG(x) ((x) - 1)
136
137 /* 10th bit corresponds to CON18(Pseudo) */
138 #define AD7194_CH(p) (BIT(10) | AD7194_CH_POS(p))
139
140 #define AD7194_DIFF_CH(p, n) (AD7194_CH_POS(p) | AD7194_CH_NEG(n))
141 #define AD7194_CH_TEMP 0x100
142 #define AD7194_CH_BASE_NR 2
143 #define AD7194_CH_AIN_START 1
144 #define AD7194_CH_AIN_NR 16
145 #define AD7194_CH_MAX_NR 272
146
147 /* ID Register Bit Designations (AD7192_REG_ID) */
148 #define CHIPID_AD7190 0x4
149 #define CHIPID_AD7192 0x0
150 #define CHIPID_AD7193 0x2
151 #define CHIPID_AD7194 0x3
152 #define CHIPID_AD7195 0x6
153 #define AD7192_ID_MASK GENMASK(3, 0)
154
155 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
156 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
157 #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */
158 #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */
159 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */
160 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */
161 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
162 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
163
164 #define AD7192_EXT_FREQ_MHZ_MIN 2457600
165 #define AD7192_EXT_FREQ_MHZ_MAX 5120000
166 #define AD7192_INT_FREQ_MHZ 4915200
167
168 #define AD7192_NO_SYNC_FILTER 1
169 #define AD7192_SYNC3_FILTER 3
170 #define AD7192_SYNC4_FILTER 4
171
172 /* NOTE:
173 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
174 * In order to avoid contentions on the SPI bus, it's therefore necessary
175 * to use spi bus locking.
176 *
177 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
178 */
179
180 enum {
181 AD7192_SYSCALIB_ZERO_SCALE,
182 AD7192_SYSCALIB_FULL_SCALE,
183 };
184
185 enum {
186 ID_AD7190,
187 ID_AD7192,
188 ID_AD7193,
189 ID_AD7194,
190 ID_AD7195,
191 };
192
193 struct ad7192_chip_info {
194 unsigned int chip_id;
195 const char *name;
196 const struct iio_chan_spec *channels;
197 u8 num_channels;
198 const struct ad_sigma_delta_info *sigma_delta_info;
199 const struct iio_info *info;
200 int (*parse_channels)(struct iio_dev *indio_dev);
201 };
202
203 struct ad7192_state {
204 const struct ad7192_chip_info *chip_info;
205 struct clk *mclk;
206 struct clk_hw int_clk_hw;
207 u16 int_vref_mv;
208 u32 aincom_mv;
209 u32 fclk;
210 u32 mode;
211 u32 conf;
212 u32 scale_avail[8][2];
213 u32 filter_freq_avail[4][2];
214 u32 oversampling_ratio_avail[4];
215 u8 gpocon;
216 u8 clock_sel;
217 struct mutex lock; /* protect sensor state */
218 u8 syscalib_mode[8];
219
220 struct ad_sigma_delta sd;
221 };
222
223 static const char * const ad7192_syscalib_modes[] = {
224 [AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale",
225 [AD7192_SYSCALIB_FULL_SCALE] = "full_scale",
226 };
227
ad7192_set_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)228 static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev,
229 const struct iio_chan_spec *chan,
230 unsigned int mode)
231 {
232 struct ad7192_state *st = iio_priv(indio_dev);
233
234 st->syscalib_mode[chan->channel] = mode;
235
236 return 0;
237 }
238
ad7192_get_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)239 static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev,
240 const struct iio_chan_spec *chan)
241 {
242 struct ad7192_state *st = iio_priv(indio_dev);
243
244 return st->syscalib_mode[chan->channel];
245 }
246
ad7192_write_syscalib(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)247 static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev,
248 uintptr_t private,
249 const struct iio_chan_spec *chan,
250 const char *buf, size_t len)
251 {
252 struct ad7192_state *st = iio_priv(indio_dev);
253 bool sys_calib;
254 int ret, temp;
255
256 ret = kstrtobool(buf, &sys_calib);
257 if (ret)
258 return ret;
259
260 if (!iio_device_claim_direct(indio_dev))
261 return -EBUSY;
262
263 temp = st->syscalib_mode[chan->channel];
264 if (sys_calib) {
265 if (temp == AD7192_SYSCALIB_ZERO_SCALE)
266 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO,
267 chan->address);
268 else
269 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL,
270 chan->address);
271 }
272
273 iio_device_release_direct(indio_dev);
274
275 return ret ? ret : len;
276 }
277
278 static const struct iio_enum ad7192_syscalib_mode_enum = {
279 .items = ad7192_syscalib_modes,
280 .num_items = ARRAY_SIZE(ad7192_syscalib_modes),
281 .set = ad7192_set_syscalib_mode,
282 .get = ad7192_get_syscalib_mode
283 };
284
285 static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = {
286 {
287 .name = "sys_calibration",
288 .write = ad7192_write_syscalib,
289 .shared = IIO_SEPARATE,
290 },
291 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,
292 &ad7192_syscalib_mode_enum),
293 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE,
294 &ad7192_syscalib_mode_enum),
295 { }
296 };
297
ad_sigma_delta_to_ad7192(struct ad_sigma_delta * sd)298 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
299 {
300 return container_of(sd, struct ad7192_state, sd);
301 }
302
ad7192_set_channel(struct ad_sigma_delta * sd,unsigned int channel)303 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
304 {
305 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
306
307 st->conf &= ~AD7192_CONF_CHAN_MASK;
308 st->conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, channel);
309
310 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
311 }
312
ad7192_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)313 static int ad7192_set_mode(struct ad_sigma_delta *sd,
314 enum ad_sigma_delta_mode mode)
315 {
316 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
317
318 st->mode &= ~AD7192_MODE_SEL_MASK;
319 st->mode |= FIELD_PREP(AD7192_MODE_SEL_MASK, mode);
320
321 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
322 }
323
ad7192_append_status(struct ad_sigma_delta * sd,bool append)324 static int ad7192_append_status(struct ad_sigma_delta *sd, bool append)
325 {
326 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
327 unsigned int mode = st->mode;
328 int ret;
329
330 mode &= ~AD7192_MODE_STA_MASK;
331 mode |= FIELD_PREP(AD7192_MODE_STA_MASK, append);
332
333 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode);
334 if (ret < 0)
335 return ret;
336
337 st->mode = mode;
338
339 return 0;
340 }
341
ad7192_disable_all(struct ad_sigma_delta * sd)342 static int ad7192_disable_all(struct ad_sigma_delta *sd)
343 {
344 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
345 u32 conf = st->conf;
346 int ret;
347
348 conf &= ~AD7192_CONF_CHAN_MASK;
349
350 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
351 if (ret < 0)
352 return ret;
353
354 st->conf = conf;
355
356 return 0;
357 }
358
359 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
360 .set_channel = ad7192_set_channel,
361 .append_status = ad7192_append_status,
362 .disable_all = ad7192_disable_all,
363 .set_mode = ad7192_set_mode,
364 .has_registers = true,
365 .addr_shift = 3,
366 .read_mask = BIT(6),
367 .status_ch_mask = GENMASK(3, 0),
368 .num_slots = 4,
369 .irq_flags = IRQF_TRIGGER_FALLING,
370 .num_resetclks = 40,
371 };
372
373 static const struct ad_sigma_delta_info ad7194_sigma_delta_info = {
374 .set_channel = ad7192_set_channel,
375 .append_status = ad7192_append_status,
376 .disable_all = ad7192_disable_all,
377 .set_mode = ad7192_set_mode,
378 .has_registers = true,
379 .addr_shift = 3,
380 .read_mask = BIT(6),
381 .status_ch_mask = GENMASK(3, 0),
382 .irq_flags = IRQF_TRIGGER_FALLING,
383 .num_resetclks = 40,
384 };
385
386 static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
387 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
388 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
389 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
390 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
391 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
392 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
393 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
394 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
395 };
396
ad7192_calibrate_all(struct ad7192_state * st)397 static int ad7192_calibrate_all(struct ad7192_state *st)
398 {
399 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
400 ARRAY_SIZE(ad7192_calib_arr));
401 }
402
ad7192_valid_external_frequency(u32 freq)403 static inline bool ad7192_valid_external_frequency(u32 freq)
404 {
405 return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
406 freq <= AD7192_EXT_FREQ_MHZ_MAX);
407 }
408
409 /*
410 * Position 0 of ad7192_clock_names, xtal, corresponds to clock source
411 * configuration AD7192_CLK_EXT_MCLK1_2 and position 1, mclk, corresponds to
412 * AD7192_CLK_EXT_MCLK2
413 */
414 static const char *const ad7192_clock_names[] = {
415 "xtal",
416 "mclk"
417 };
418
clk_hw_to_ad7192(struct clk_hw * hw)419 static struct ad7192_state *clk_hw_to_ad7192(struct clk_hw *hw)
420 {
421 return container_of(hw, struct ad7192_state, int_clk_hw);
422 }
423
ad7192_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)424 static unsigned long ad7192_clk_recalc_rate(struct clk_hw *hw,
425 unsigned long parent_rate)
426 {
427 return AD7192_INT_FREQ_MHZ;
428 }
429
ad7192_clk_output_is_enabled(struct clk_hw * hw)430 static int ad7192_clk_output_is_enabled(struct clk_hw *hw)
431 {
432 struct ad7192_state *st = clk_hw_to_ad7192(hw);
433
434 return st->clock_sel == AD7192_CLK_INT_CO;
435 }
436
ad7192_clk_prepare(struct clk_hw * hw)437 static int ad7192_clk_prepare(struct clk_hw *hw)
438 {
439 struct ad7192_state *st = clk_hw_to_ad7192(hw);
440 int ret;
441
442 st->mode &= ~AD7192_MODE_CLKSRC_MASK;
443 st->mode |= AD7192_CLK_INT_CO;
444
445 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
446 if (ret)
447 return ret;
448
449 st->clock_sel = AD7192_CLK_INT_CO;
450
451 return 0;
452 }
453
ad7192_clk_unprepare(struct clk_hw * hw)454 static void ad7192_clk_unprepare(struct clk_hw *hw)
455 {
456 struct ad7192_state *st = clk_hw_to_ad7192(hw);
457 int ret;
458
459 st->mode &= ~AD7192_MODE_CLKSRC_MASK;
460 st->mode |= AD7192_CLK_INT;
461
462 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
463 if (ret)
464 return;
465
466 st->clock_sel = AD7192_CLK_INT;
467 }
468
469 static const struct clk_ops ad7192_int_clk_ops = {
470 .recalc_rate = ad7192_clk_recalc_rate,
471 .is_enabled = ad7192_clk_output_is_enabled,
472 .prepare = ad7192_clk_prepare,
473 .unprepare = ad7192_clk_unprepare,
474 };
475
ad7192_register_clk_provider(struct ad7192_state * st)476 static int ad7192_register_clk_provider(struct ad7192_state *st)
477 {
478 struct device *dev = &st->sd.spi->dev;
479 struct clk_init_data init = {};
480 int ret;
481
482 if (!IS_ENABLED(CONFIG_COMMON_CLK))
483 return 0;
484
485 if (!device_property_present(dev, "#clock-cells"))
486 return 0;
487
488 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-clk",
489 fwnode_get_name(dev_fwnode(dev)));
490 if (!init.name)
491 return -ENOMEM;
492
493 init.ops = &ad7192_int_clk_ops;
494
495 st->int_clk_hw.init = &init;
496 ret = devm_clk_hw_register(dev, &st->int_clk_hw);
497 if (ret)
498 return ret;
499
500 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
501 &st->int_clk_hw);
502 }
503
ad7192_clock_setup(struct ad7192_state * st)504 static int ad7192_clock_setup(struct ad7192_state *st)
505 {
506 struct device *dev = &st->sd.spi->dev;
507 int ret;
508
509 /*
510 * The following two if branches are kept for backward compatibility but
511 * the use of the two devicetree properties is highly discouraged. Clock
512 * configuration should be done according to the bindings.
513 */
514
515 if (device_property_read_bool(dev, "adi,int-clock-output-enable")) {
516 st->clock_sel = AD7192_CLK_INT_CO;
517 st->fclk = AD7192_INT_FREQ_MHZ;
518 dev_warn(dev, "Property adi,int-clock-output-enable is deprecated! Check bindings!\n");
519 return 0;
520 }
521
522 if (device_property_read_bool(dev, "adi,clock-xtal")) {
523 st->clock_sel = AD7192_CLK_EXT_MCLK1_2;
524 st->mclk = devm_clk_get_enabled(dev, "mclk");
525 if (IS_ERR(st->mclk))
526 return dev_err_probe(dev, PTR_ERR(st->mclk),
527 "Failed to get mclk\n");
528
529 st->fclk = clk_get_rate(st->mclk);
530 if (!ad7192_valid_external_frequency(st->fclk))
531 return dev_err_probe(dev, -EINVAL,
532 "External clock frequency out of bounds\n");
533
534 dev_warn(dev, "Property adi,clock-xtal is deprecated! Check bindings!\n");
535 return 0;
536 }
537
538 ret = device_property_match_property_string(dev, "clock-names",
539 ad7192_clock_names,
540 ARRAY_SIZE(ad7192_clock_names));
541 if (ret < 0) {
542 st->clock_sel = AD7192_CLK_INT;
543 st->fclk = AD7192_INT_FREQ_MHZ;
544
545 ret = ad7192_register_clk_provider(st);
546 if (ret)
547 return dev_err_probe(dev, ret,
548 "Failed to register clock provider\n");
549 return 0;
550 }
551
552 st->clock_sel = AD7192_CLK_EXT_MCLK1_2 + ret;
553
554 st->mclk = devm_clk_get_enabled(dev, ad7192_clock_names[ret]);
555 if (IS_ERR(st->mclk))
556 return dev_err_probe(dev, PTR_ERR(st->mclk),
557 "Failed to get clock source\n");
558
559 st->fclk = clk_get_rate(st->mclk);
560 if (!ad7192_valid_external_frequency(st->fclk))
561 return dev_err_probe(dev, -EINVAL,
562 "External clock frequency out of bounds\n");
563
564 return 0;
565 }
566
ad7192_setup(struct iio_dev * indio_dev,struct device * dev)567 static int ad7192_setup(struct iio_dev *indio_dev, struct device *dev)
568 {
569 struct ad7192_state *st = iio_priv(indio_dev);
570 bool rej60_en, refin2_en;
571 bool buf_en, bipolar, burnout_curr_en;
572 unsigned long long scale_uv;
573 int i, ret, id;
574
575 /* reset the serial interface */
576 ret = ad_sd_reset(&st->sd);
577 if (ret < 0)
578 return ret;
579 usleep_range(500, 1000); /* Wait for at least 500us */
580
581 /* write/read test for device presence */
582 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
583 if (ret)
584 return ret;
585
586 id = FIELD_GET(AD7192_ID_MASK, id);
587
588 if (id != st->chip_info->chip_id)
589 dev_warn(dev, "device ID query failed (0x%X != 0x%X)\n",
590 id, st->chip_info->chip_id);
591
592 st->mode = FIELD_PREP(AD7192_MODE_SEL_MASK, AD7192_MODE_IDLE) |
593 FIELD_PREP(AD7192_MODE_CLKSRC_MASK, st->clock_sel) |
594 FIELD_PREP(AD7192_MODE_RATE_MASK, 480);
595
596 st->conf = FIELD_PREP(AD7192_CONF_GAIN_MASK, 0);
597
598 rej60_en = device_property_read_bool(dev, "adi,rejection-60-Hz-enable");
599 if (rej60_en)
600 st->mode |= AD7192_MODE_REJ60;
601
602 refin2_en = device_property_read_bool(dev, "adi,refin2-pins-enable");
603 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195)
604 st->conf |= AD7192_CONF_REFSEL;
605
606 st->conf &= ~AD7192_CONF_CHOP;
607
608 buf_en = device_property_read_bool(dev, "adi,buffer-enable");
609 if (buf_en)
610 st->conf |= AD7192_CONF_BUF;
611
612 bipolar = device_property_read_bool(dev, "bipolar");
613 if (!bipolar)
614 st->conf |= AD7192_CONF_UNIPOLAR;
615
616 burnout_curr_en = device_property_read_bool(dev,
617 "adi,burnout-currents-enable");
618 if (burnout_curr_en && buf_en) {
619 st->conf |= AD7192_CONF_BURN;
620 } else if (burnout_curr_en) {
621 dev_warn(dev,
622 "Can't enable burnout currents: see CHOP or buffer\n");
623 }
624
625 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
626 if (ret)
627 return ret;
628
629 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
630 if (ret)
631 return ret;
632
633 ret = ad7192_calibrate_all(st);
634 if (ret)
635 return ret;
636
637 /* Populate available ADC input ranges */
638 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
639 scale_uv = ((u64)st->int_vref_mv * 100000000)
640 >> (indio_dev->channels[0].scan_type.realbits -
641 !FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf));
642 scale_uv >>= i;
643
644 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
645 st->scale_avail[i][0] = scale_uv;
646 }
647
648 st->oversampling_ratio_avail[0] = 1;
649 st->oversampling_ratio_avail[1] = 2;
650 st->oversampling_ratio_avail[2] = 8;
651 st->oversampling_ratio_avail[3] = 16;
652
653 st->filter_freq_avail[0][0] = 600;
654 st->filter_freq_avail[1][0] = 800;
655 st->filter_freq_avail[2][0] = 2300;
656 st->filter_freq_avail[3][0] = 2720;
657
658 st->filter_freq_avail[0][1] = 1000;
659 st->filter_freq_avail[1][1] = 1000;
660 st->filter_freq_avail[2][1] = 1000;
661 st->filter_freq_avail[3][1] = 1000;
662
663 return 0;
664 }
665
ad7192_show_ac_excitation(struct device * dev,struct device_attribute * attr,char * buf)666 static ssize_t ad7192_show_ac_excitation(struct device *dev,
667 struct device_attribute *attr,
668 char *buf)
669 {
670 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
671 struct ad7192_state *st = iio_priv(indio_dev);
672
673 return sysfs_emit(buf, "%ld\n", FIELD_GET(AD7192_CONF_ACX, st->conf));
674 }
675
ad7192_show_bridge_switch(struct device * dev,struct device_attribute * attr,char * buf)676 static ssize_t ad7192_show_bridge_switch(struct device *dev,
677 struct device_attribute *attr,
678 char *buf)
679 {
680 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
681 struct ad7192_state *st = iio_priv(indio_dev);
682
683 return sysfs_emit(buf, "%ld\n",
684 FIELD_GET(AD7192_GPOCON_BPDSW, st->gpocon));
685 }
686
ad7192_set(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)687 static ssize_t ad7192_set(struct device *dev,
688 struct device_attribute *attr,
689 const char *buf,
690 size_t len)
691 {
692 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
693 struct ad7192_state *st = iio_priv(indio_dev);
694 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
695 int ret;
696 bool val;
697
698 ret = kstrtobool(buf, &val);
699 if (ret < 0)
700 return ret;
701
702 if (!iio_device_claim_direct(indio_dev))
703 return -EBUSY;
704
705 switch ((u32)this_attr->address) {
706 case AD7192_REG_GPOCON:
707 if (val)
708 st->gpocon |= AD7192_GPOCON_BPDSW;
709 else
710 st->gpocon &= ~AD7192_GPOCON_BPDSW;
711
712 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
713 break;
714 case AD7192_REG_CONF:
715 if (val)
716 st->conf |= AD7192_CONF_ACX;
717 else
718 st->conf &= ~AD7192_CONF_ACX;
719
720 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
721 break;
722 default:
723 ret = -EINVAL;
724 }
725
726 iio_device_release_direct(indio_dev);
727
728 return ret ? ret : len;
729 }
730
ad7192_compute_f_order(struct ad7192_state * st,bool sinc3_en,bool chop_en)731 static int ad7192_compute_f_order(struct ad7192_state *st, bool sinc3_en, bool chop_en)
732 {
733 u8 avg_factor_selected, oversampling_ratio;
734
735 avg_factor_selected = FIELD_GET(AD7192_MODE_AVG_MASK, st->mode);
736
737 if (!avg_factor_selected && !chop_en)
738 return 1;
739
740 oversampling_ratio = st->oversampling_ratio_avail[avg_factor_selected];
741
742 if (sinc3_en)
743 return AD7192_SYNC3_FILTER + oversampling_ratio - 1;
744
745 return AD7192_SYNC4_FILTER + oversampling_ratio - 1;
746 }
747
ad7192_get_f_order(struct ad7192_state * st)748 static int ad7192_get_f_order(struct ad7192_state *st)
749 {
750 bool sinc3_en, chop_en;
751
752 sinc3_en = FIELD_GET(AD7192_MODE_SINC3, st->mode);
753 chop_en = FIELD_GET(AD7192_CONF_CHOP, st->conf);
754
755 return ad7192_compute_f_order(st, sinc3_en, chop_en);
756 }
757
ad7192_compute_f_adc(struct ad7192_state * st,bool sinc3_en,bool chop_en)758 static int ad7192_compute_f_adc(struct ad7192_state *st, bool sinc3_en,
759 bool chop_en)
760 {
761 unsigned int f_order = ad7192_compute_f_order(st, sinc3_en, chop_en);
762
763 return DIV_ROUND_CLOSEST(st->fclk,
764 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode));
765 }
766
ad7192_get_f_adc(struct ad7192_state * st)767 static int ad7192_get_f_adc(struct ad7192_state *st)
768 {
769 unsigned int f_order = ad7192_get_f_order(st);
770
771 return DIV_ROUND_CLOSEST(st->fclk,
772 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode));
773 }
774
ad7192_update_filter_freq_avail(struct ad7192_state * st)775 static void ad7192_update_filter_freq_avail(struct ad7192_state *st)
776 {
777 unsigned int fadc;
778
779 /* Formulas for filter at page 25 of the datasheet */
780 fadc = ad7192_compute_f_adc(st, false, true);
781 st->filter_freq_avail[0][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
782
783 fadc = ad7192_compute_f_adc(st, true, true);
784 st->filter_freq_avail[1][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
785
786 fadc = ad7192_compute_f_adc(st, false, false);
787 st->filter_freq_avail[2][0] = DIV_ROUND_CLOSEST(fadc * 230, 1024);
788
789 fadc = ad7192_compute_f_adc(st, true, false);
790 st->filter_freq_avail[3][0] = DIV_ROUND_CLOSEST(fadc * 272, 1024);
791 }
792
793 static IIO_DEVICE_ATTR(bridge_switch_en, 0644,
794 ad7192_show_bridge_switch, ad7192_set,
795 AD7192_REG_GPOCON);
796
797 static IIO_DEVICE_ATTR(ac_excitation_en, 0644,
798 ad7192_show_ac_excitation, ad7192_set,
799 AD7192_REG_CONF);
800
801 static struct attribute *ad7192_attributes[] = {
802 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
803 NULL
804 };
805
806 static const struct attribute_group ad7192_attribute_group = {
807 .attrs = ad7192_attributes,
808 };
809
810 static struct attribute *ad7195_attributes[] = {
811 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
812 &iio_dev_attr_ac_excitation_en.dev_attr.attr,
813 NULL
814 };
815
816 static const struct attribute_group ad7195_attribute_group = {
817 .attrs = ad7195_attributes,
818 };
819
ad7192_get_temp_scale(bool unipolar)820 static unsigned int ad7192_get_temp_scale(bool unipolar)
821 {
822 return unipolar ? 2815 * 2 : 2815;
823 }
824
ad7192_set_3db_filter_freq(struct ad7192_state * st,int val,int val2)825 static int ad7192_set_3db_filter_freq(struct ad7192_state *st,
826 int val, int val2)
827 {
828 int i, ret, freq;
829 unsigned int diff_new, diff_old;
830 int idx = 0;
831
832 diff_old = U32_MAX;
833 freq = val * 1000 + val2;
834
835 for (i = 0; i < ARRAY_SIZE(st->filter_freq_avail); i++) {
836 diff_new = abs(freq - st->filter_freq_avail[i][0]);
837 if (diff_new < diff_old) {
838 diff_old = diff_new;
839 idx = i;
840 }
841 }
842
843 switch (idx) {
844 case 0:
845 st->mode &= ~AD7192_MODE_SINC3;
846
847 st->conf |= AD7192_CONF_CHOP;
848 break;
849 case 1:
850 st->mode |= AD7192_MODE_SINC3;
851
852 st->conf |= AD7192_CONF_CHOP;
853 break;
854 case 2:
855 st->mode &= ~AD7192_MODE_SINC3;
856
857 st->conf &= ~AD7192_CONF_CHOP;
858 break;
859 case 3:
860 st->mode |= AD7192_MODE_SINC3;
861
862 st->conf &= ~AD7192_CONF_CHOP;
863 break;
864 }
865
866 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
867 if (ret < 0)
868 return ret;
869
870 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
871 }
872
ad7192_get_3db_filter_freq(struct ad7192_state * st)873 static int ad7192_get_3db_filter_freq(struct ad7192_state *st)
874 {
875 unsigned int fadc;
876
877 fadc = ad7192_get_f_adc(st);
878
879 if (FIELD_GET(AD7192_CONF_CHOP, st->conf))
880 return DIV_ROUND_CLOSEST(fadc * 240, 1024);
881 if (FIELD_GET(AD7192_MODE_SINC3, st->mode))
882 return DIV_ROUND_CLOSEST(fadc * 272, 1024);
883 else
884 return DIV_ROUND_CLOSEST(fadc * 230, 1024);
885 }
886
ad7192_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)887 static int ad7192_read_raw(struct iio_dev *indio_dev,
888 struct iio_chan_spec const *chan,
889 int *val,
890 int *val2,
891 long m)
892 {
893 struct ad7192_state *st = iio_priv(indio_dev);
894 bool unipolar = FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf);
895 u8 gain = FIELD_GET(AD7192_CONF_GAIN_MASK, st->conf);
896
897 switch (m) {
898 case IIO_CHAN_INFO_RAW:
899 return ad_sigma_delta_single_conversion(indio_dev, chan, val);
900 case IIO_CHAN_INFO_SCALE:
901 switch (chan->type) {
902 case IIO_VOLTAGE:
903 mutex_lock(&st->lock);
904 *val = st->scale_avail[gain][0];
905 *val2 = st->scale_avail[gain][1];
906 mutex_unlock(&st->lock);
907 return IIO_VAL_INT_PLUS_NANO;
908 case IIO_TEMP:
909 *val = 0;
910 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
911 return IIO_VAL_INT_PLUS_NANO;
912 default:
913 return -EINVAL;
914 }
915 case IIO_CHAN_INFO_OFFSET:
916 if (!unipolar)
917 *val = -(1 << (chan->scan_type.realbits - 1));
918 else
919 *val = 0;
920
921 switch (chan->type) {
922 case IIO_VOLTAGE:
923 /*
924 * Only applies to pseudo-differential inputs.
925 * AINCOM voltage has to be converted to "raw" units.
926 */
927 if (st->aincom_mv && !chan->differential)
928 *val += DIV_ROUND_CLOSEST_ULL((u64)st->aincom_mv * NANO,
929 st->scale_avail[gain][1]);
930 return IIO_VAL_INT;
931 /* Kelvin to Celsius */
932 case IIO_TEMP:
933 *val -= 273 * ad7192_get_temp_scale(unipolar);
934 return IIO_VAL_INT;
935 default:
936 return -EINVAL;
937 }
938 case IIO_CHAN_INFO_SAMP_FREQ:
939 *val = DIV_ROUND_CLOSEST(ad7192_get_f_adc(st), 1024);
940 return IIO_VAL_INT;
941 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
942 *val = ad7192_get_3db_filter_freq(st);
943 *val2 = 1000;
944 return IIO_VAL_FRACTIONAL;
945 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
946 *val = st->oversampling_ratio_avail[FIELD_GET(AD7192_MODE_AVG_MASK, st->mode)];
947 return IIO_VAL_INT;
948 }
949
950 return -EINVAL;
951 }
952
__ad7192_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)953 static int __ad7192_write_raw(struct iio_dev *indio_dev,
954 struct iio_chan_spec const *chan,
955 int val,
956 int val2,
957 long mask)
958 {
959 struct ad7192_state *st = iio_priv(indio_dev);
960 int i, div;
961 unsigned int tmp;
962
963 guard(mutex)(&st->lock);
964
965 switch (mask) {
966 case IIO_CHAN_INFO_SCALE:
967 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
968 if (val2 != st->scale_avail[i][1])
969 continue;
970
971 tmp = st->conf;
972 st->conf &= ~AD7192_CONF_GAIN_MASK;
973 st->conf |= FIELD_PREP(AD7192_CONF_GAIN_MASK, i);
974 if (tmp == st->conf)
975 return 0;
976 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
977 ad7192_calibrate_all(st);
978 return 0;
979 }
980 return -EINVAL;
981 case IIO_CHAN_INFO_SAMP_FREQ:
982 if (!val)
983 return -EINVAL;
984
985 div = st->fclk / (val * ad7192_get_f_order(st) * 1024);
986 if (div < 1 || div > 1023)
987 return -EINVAL;
988
989 st->mode &= ~AD7192_MODE_RATE_MASK;
990 st->mode |= FIELD_PREP(AD7192_MODE_RATE_MASK, div);
991 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
992 ad7192_update_filter_freq_avail(st);
993 return 0;
994 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
995 return ad7192_set_3db_filter_freq(st, val, val2 / 1000);
996 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
997 for (i = 0; i < ARRAY_SIZE(st->oversampling_ratio_avail); i++) {
998 if (val != st->oversampling_ratio_avail[i])
999 continue;
1000
1001 tmp = st->mode;
1002 st->mode &= ~AD7192_MODE_AVG_MASK;
1003 st->mode |= FIELD_PREP(AD7192_MODE_AVG_MASK, i);
1004 if (tmp == st->mode)
1005 return 0;
1006 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
1007 ad7192_update_filter_freq_avail(st);
1008 return 0;
1009 }
1010 return -EINVAL;
1011 default:
1012 return -EINVAL;
1013 }
1014 }
1015
ad7192_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)1016 static int ad7192_write_raw(struct iio_dev *indio_dev,
1017 struct iio_chan_spec const *chan,
1018 int val,
1019 int val2,
1020 long mask)
1021 {
1022 int ret;
1023
1024 if (!iio_device_claim_direct(indio_dev))
1025 return -EBUSY;
1026
1027 ret = __ad7192_write_raw(indio_dev, chan, val, val2, mask);
1028
1029 iio_device_release_direct(indio_dev);
1030
1031 return ret;
1032 }
1033
ad7192_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)1034 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
1035 struct iio_chan_spec const *chan,
1036 long mask)
1037 {
1038 switch (mask) {
1039 case IIO_CHAN_INFO_SCALE:
1040 return IIO_VAL_INT_PLUS_NANO;
1041 case IIO_CHAN_INFO_SAMP_FREQ:
1042 return IIO_VAL_INT;
1043 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
1044 return IIO_VAL_INT_PLUS_MICRO;
1045 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1046 return IIO_VAL_INT;
1047 default:
1048 return -EINVAL;
1049 }
1050 }
1051
ad7192_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)1052 static int ad7192_read_avail(struct iio_dev *indio_dev,
1053 struct iio_chan_spec const *chan,
1054 const int **vals, int *type, int *length,
1055 long mask)
1056 {
1057 struct ad7192_state *st = iio_priv(indio_dev);
1058
1059 switch (mask) {
1060 case IIO_CHAN_INFO_SCALE:
1061 *vals = (int *)st->scale_avail;
1062 *type = IIO_VAL_INT_PLUS_NANO;
1063 /* Values are stored in a 2D matrix */
1064 *length = ARRAY_SIZE(st->scale_avail) * 2;
1065
1066 return IIO_AVAIL_LIST;
1067 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
1068 *vals = (int *)st->filter_freq_avail;
1069 *type = IIO_VAL_FRACTIONAL;
1070 *length = ARRAY_SIZE(st->filter_freq_avail) * 2;
1071
1072 return IIO_AVAIL_LIST;
1073 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1074 *vals = (int *)st->oversampling_ratio_avail;
1075 *type = IIO_VAL_INT;
1076 *length = ARRAY_SIZE(st->oversampling_ratio_avail);
1077
1078 return IIO_AVAIL_LIST;
1079 }
1080
1081 return -EINVAL;
1082 }
1083
ad7192_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)1084 static int ad7192_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask)
1085 {
1086 struct ad7192_state *st = iio_priv(indio_dev);
1087 u32 conf = st->conf;
1088 int ret;
1089 int i;
1090
1091 conf &= ~AD7192_CONF_CHAN_MASK;
1092 for_each_set_bit(i, scan_mask, 8)
1093 conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, BIT(i));
1094
1095 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
1096 if (ret < 0)
1097 return ret;
1098
1099 st->conf = conf;
1100
1101 return 0;
1102 }
1103
1104 static const struct iio_info ad7192_info = {
1105 .read_raw = ad7192_read_raw,
1106 .write_raw = ad7192_write_raw,
1107 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
1108 .read_avail = ad7192_read_avail,
1109 .attrs = &ad7192_attribute_group,
1110 .validate_trigger = ad_sd_validate_trigger,
1111 .update_scan_mode = ad7192_update_scan_mode,
1112 };
1113
1114 static const struct iio_info ad7194_info = {
1115 .read_raw = ad7192_read_raw,
1116 .write_raw = ad7192_write_raw,
1117 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
1118 .read_avail = ad7192_read_avail,
1119 .validate_trigger = ad_sd_validate_trigger,
1120 };
1121
1122 static const struct iio_info ad7195_info = {
1123 .read_raw = ad7192_read_raw,
1124 .write_raw = ad7192_write_raw,
1125 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
1126 .read_avail = ad7192_read_avail,
1127 .attrs = &ad7195_attribute_group,
1128 .validate_trigger = ad_sd_validate_trigger,
1129 .update_scan_mode = ad7192_update_scan_mode,
1130 };
1131
1132 #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _type, \
1133 _mask_all, _mask_type_av, _mask_all_av, _ext_info) \
1134 { \
1135 .type = (_type), \
1136 .differential = ((_channel2) == -1 ? 0 : 1), \
1137 .indexed = 1, \
1138 .channel = (_channel1), \
1139 .channel2 = (_channel2), \
1140 .address = (_address), \
1141 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1142 BIT(IIO_CHAN_INFO_OFFSET), \
1143 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
1144 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1145 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
1146 (_mask_all), \
1147 .info_mask_shared_by_type_available = (_mask_type_av), \
1148 .info_mask_shared_by_all_available = \
1149 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
1150 (_mask_all_av), \
1151 .ext_info = (_ext_info), \
1152 .scan_index = (_si), \
1153 .scan_type = { \
1154 .sign = 'u', \
1155 .realbits = 24, \
1156 .storagebits = 32, \
1157 .endianness = IIO_BE, \
1158 }, \
1159 }
1160
1161 #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \
1162 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, IIO_VOLTAGE, 0, \
1163 BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info)
1164
1165 #define AD719x_CHANNEL(_si, _channel1, _address) \
1166 __AD719x_CHANNEL(_si, _channel1, -1, _address, IIO_VOLTAGE, 0, \
1167 BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info)
1168
1169 #define AD719x_TEMP_CHANNEL(_si, _address) \
1170 __AD719x_CHANNEL(_si, 0, -1, _address, IIO_TEMP, 0, 0, 0, NULL)
1171
1172 #define AD7193_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \
1173 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, \
1174 IIO_VOLTAGE, \
1175 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1176 BIT(IIO_CHAN_INFO_SCALE), \
1177 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1178 ad7192_calibsys_ext_info)
1179
1180 #define AD7193_CHANNEL(_si, _channel1, _address) \
1181 AD7193_DIFF_CHANNEL(_si, _channel1, -1, _address)
1182
1183 static const struct iio_chan_spec ad7192_channels[] = {
1184 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M),
1185 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M),
1186 AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP),
1187 AD719x_DIFF_CHANNEL(3, 2, 2, AD7192_CH_AIN2P_AIN2M),
1188 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1),
1189 AD719x_CHANNEL(5, 2, AD7192_CH_AIN2),
1190 AD719x_CHANNEL(6, 3, AD7192_CH_AIN3),
1191 AD719x_CHANNEL(7, 4, AD7192_CH_AIN4),
1192 IIO_CHAN_SOFT_TIMESTAMP(8),
1193 };
1194
1195 static const struct iio_chan_spec ad7193_channels[] = {
1196 AD7193_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),
1197 AD7193_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),
1198 AD7193_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M),
1199 AD7193_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M),
1200 AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP),
1201 AD7193_DIFF_CHANNEL(5, 2, 2, AD7193_CH_AIN2P_AIN2M),
1202 AD7193_CHANNEL(6, 1, AD7193_CH_AIN1),
1203 AD7193_CHANNEL(7, 2, AD7193_CH_AIN2),
1204 AD7193_CHANNEL(8, 3, AD7193_CH_AIN3),
1205 AD7193_CHANNEL(9, 4, AD7193_CH_AIN4),
1206 AD7193_CHANNEL(10, 5, AD7193_CH_AIN5),
1207 AD7193_CHANNEL(11, 6, AD7193_CH_AIN6),
1208 AD7193_CHANNEL(12, 7, AD7193_CH_AIN7),
1209 AD7193_CHANNEL(13, 8, AD7193_CH_AIN8),
1210 IIO_CHAN_SOFT_TIMESTAMP(14),
1211 };
1212
ad7194_validate_ain_channel(struct device * dev,u32 ain)1213 static bool ad7194_validate_ain_channel(struct device *dev, u32 ain)
1214 {
1215 return in_range(ain, AD7194_CH_AIN_START, AD7194_CH_AIN_NR);
1216 }
1217
ad7194_parse_channels(struct iio_dev * indio_dev)1218 static int ad7194_parse_channels(struct iio_dev *indio_dev)
1219 {
1220 struct device *dev = indio_dev->dev.parent;
1221 struct iio_chan_spec *ad7194_channels;
1222 const struct iio_chan_spec ad7194_chan = AD7193_CHANNEL(0, 0, 0);
1223 const struct iio_chan_spec ad7194_chan_diff = AD7193_DIFF_CHANNEL(0, 0, 0, 0);
1224 const struct iio_chan_spec ad7194_chan_temp = AD719x_TEMP_CHANNEL(0, 0);
1225 const struct iio_chan_spec ad7194_chan_timestamp = IIO_CHAN_SOFT_TIMESTAMP(0);
1226 unsigned int num_channels, index = 0;
1227 u32 ain[2];
1228 int ret;
1229
1230 num_channels = device_get_child_node_count(dev);
1231 if (num_channels > AD7194_CH_MAX_NR)
1232 return dev_err_probe(dev, -EINVAL, "Too many channels: %u\n",
1233 num_channels);
1234
1235 num_channels += AD7194_CH_BASE_NR;
1236
1237 ad7194_channels = devm_kcalloc(dev, num_channels,
1238 sizeof(*ad7194_channels), GFP_KERNEL);
1239 if (!ad7194_channels)
1240 return -ENOMEM;
1241
1242 indio_dev->channels = ad7194_channels;
1243 indio_dev->num_channels = num_channels;
1244
1245 device_for_each_child_node_scoped(dev, child) {
1246 ret = fwnode_property_read_u32_array(child, "diff-channels",
1247 ain, ARRAY_SIZE(ain));
1248 if (ret == 0) {
1249 if (!ad7194_validate_ain_channel(dev, ain[0]))
1250 return dev_err_probe(dev, -EINVAL,
1251 "Invalid AIN channel: %u\n",
1252 ain[0]);
1253
1254 if (!ad7194_validate_ain_channel(dev, ain[1]))
1255 return dev_err_probe(dev, -EINVAL,
1256 "Invalid AIN channel: %u\n",
1257 ain[1]);
1258
1259 *ad7194_channels = ad7194_chan_diff;
1260 ad7194_channels->scan_index = index++;
1261 ad7194_channels->channel = ain[0];
1262 ad7194_channels->channel2 = ain[1];
1263 ad7194_channels->address = AD7194_DIFF_CH(ain[0], ain[1]);
1264 } else {
1265 ret = fwnode_property_read_u32(child, "single-channel",
1266 &ain[0]);
1267 if (ret)
1268 return dev_err_probe(dev, ret,
1269 "Missing channel property\n");
1270
1271 if (!ad7194_validate_ain_channel(dev, ain[0]))
1272 return dev_err_probe(dev, -EINVAL,
1273 "Invalid AIN channel: %u\n",
1274 ain[0]);
1275
1276 *ad7194_channels = ad7194_chan;
1277 ad7194_channels->scan_index = index++;
1278 ad7194_channels->channel = ain[0];
1279 ad7194_channels->address = AD7194_CH(ain[0]);
1280 }
1281 ad7194_channels++;
1282 }
1283
1284 *ad7194_channels = ad7194_chan_temp;
1285 ad7194_channels->scan_index = index++;
1286 ad7194_channels->address = AD7194_CH_TEMP;
1287 ad7194_channels++;
1288
1289 *ad7194_channels = ad7194_chan_timestamp;
1290 ad7194_channels->scan_index = index;
1291
1292 return 0;
1293 }
1294
1295 static const struct ad7192_chip_info ad7192_chip_info_tbl[] = {
1296 [ID_AD7190] = {
1297 .chip_id = CHIPID_AD7190,
1298 .name = "ad7190",
1299 .channels = ad7192_channels,
1300 .num_channels = ARRAY_SIZE(ad7192_channels),
1301 .sigma_delta_info = &ad7192_sigma_delta_info,
1302 .info = &ad7192_info,
1303 },
1304 [ID_AD7192] = {
1305 .chip_id = CHIPID_AD7192,
1306 .name = "ad7192",
1307 .channels = ad7192_channels,
1308 .num_channels = ARRAY_SIZE(ad7192_channels),
1309 .sigma_delta_info = &ad7192_sigma_delta_info,
1310 .info = &ad7192_info,
1311 },
1312 [ID_AD7193] = {
1313 .chip_id = CHIPID_AD7193,
1314 .name = "ad7193",
1315 .channels = ad7193_channels,
1316 .num_channels = ARRAY_SIZE(ad7193_channels),
1317 .sigma_delta_info = &ad7192_sigma_delta_info,
1318 .info = &ad7192_info,
1319 },
1320 [ID_AD7194] = {
1321 .chip_id = CHIPID_AD7194,
1322 .name = "ad7194",
1323 .info = &ad7194_info,
1324 .sigma_delta_info = &ad7194_sigma_delta_info,
1325 .parse_channels = ad7194_parse_channels,
1326 },
1327 [ID_AD7195] = {
1328 .chip_id = CHIPID_AD7195,
1329 .name = "ad7195",
1330 .channels = ad7192_channels,
1331 .num_channels = ARRAY_SIZE(ad7192_channels),
1332 .sigma_delta_info = &ad7192_sigma_delta_info,
1333 .info = &ad7195_info,
1334 },
1335 };
1336
ad7192_probe(struct spi_device * spi)1337 static int ad7192_probe(struct spi_device *spi)
1338 {
1339 struct device *dev = &spi->dev;
1340 struct ad7192_state *st;
1341 struct iio_dev *indio_dev;
1342 int ret, avdd_mv;
1343
1344 if (!spi->irq)
1345 return dev_err_probe(dev, -ENODEV, "Failed to get IRQ\n");
1346
1347 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1348 if (!indio_dev)
1349 return -ENOMEM;
1350
1351 st = iio_priv(indio_dev);
1352
1353 mutex_init(&st->lock);
1354
1355 /*
1356 * Regulator aincom is optional to maintain compatibility with older DT.
1357 * Newer firmware should provide a zero volt fixed supply if wired to
1358 * ground.
1359 */
1360 ret = devm_regulator_get_enable_read_voltage(dev, "aincom");
1361 if (ret < 0 && ret != -ENODEV)
1362 return dev_err_probe(dev, ret, "Failed to get AINCOM voltage\n");
1363
1364 st->aincom_mv = ret == -ENODEV ? 0 : ret / MILLI;
1365
1366 /* AVDD can optionally be used as reference voltage */
1367 ret = devm_regulator_get_enable_read_voltage(dev, "avdd");
1368 if (ret == -ENODEV || ret == -EINVAL) {
1369 int ret2;
1370
1371 /*
1372 * We get -EINVAL if avdd is a supply with unknown voltage. We
1373 * still need to enable it since it is also a power supply.
1374 */
1375 ret2 = devm_regulator_get_enable(dev, "avdd");
1376 if (ret2)
1377 return dev_err_probe(dev, ret2,
1378 "Failed to enable AVDD supply\n");
1379 } else if (ret < 0) {
1380 return dev_err_probe(dev, ret, "Failed to get AVDD voltage\n");
1381 }
1382
1383 avdd_mv = ret == -ENODEV || ret == -EINVAL ? 0 : ret / MILLI;
1384
1385 ret = devm_regulator_get_enable(dev, "dvdd");
1386 if (ret)
1387 return dev_err_probe(dev, ret, "Failed to enable specified DVdd supply\n");
1388
1389 /*
1390 * This is either REFIN1 or REFIN2 depending on adi,refin2-pins-enable.
1391 * If this supply is not present, fall back to AVDD as reference.
1392 */
1393 ret = devm_regulator_get_enable_read_voltage(dev, "vref");
1394 if (ret == -ENODEV) {
1395 if (avdd_mv == 0)
1396 return dev_err_probe(dev, -ENODEV,
1397 "No reference voltage available\n");
1398 } else if (ret < 0) {
1399 return ret;
1400 }
1401
1402 st->int_vref_mv = ret == -ENODEV ? avdd_mv : ret / MILLI;
1403
1404 st->chip_info = spi_get_device_match_data(spi);
1405 if (!st->chip_info)
1406 return -ENODEV;
1407
1408 indio_dev->name = st->chip_info->name;
1409 indio_dev->modes = INDIO_DIRECT_MODE;
1410 indio_dev->info = st->chip_info->info;
1411 if (st->chip_info->parse_channels) {
1412 ret = st->chip_info->parse_channels(indio_dev);
1413 if (ret)
1414 return ret;
1415 } else {
1416 indio_dev->channels = st->chip_info->channels;
1417 indio_dev->num_channels = st->chip_info->num_channels;
1418 }
1419
1420 ret = ad_sd_init(&st->sd, indio_dev, spi, st->chip_info->sigma_delta_info);
1421 if (ret)
1422 return ret;
1423
1424 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev);
1425 if (ret)
1426 return ret;
1427
1428 ret = ad7192_clock_setup(st);
1429 if (ret)
1430 return ret;
1431
1432 ret = ad7192_setup(indio_dev, dev);
1433 if (ret)
1434 return ret;
1435
1436 return devm_iio_device_register(dev, indio_dev);
1437 }
1438
1439 static const struct of_device_id ad7192_of_match[] = {
1440 { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] },
1441 { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] },
1442 { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] },
1443 { .compatible = "adi,ad7194", .data = &ad7192_chip_info_tbl[ID_AD7194] },
1444 { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] },
1445 { }
1446 };
1447 MODULE_DEVICE_TABLE(of, ad7192_of_match);
1448
1449 static const struct spi_device_id ad7192_ids[] = {
1450 { "ad7190", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7190] },
1451 { "ad7192", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7192] },
1452 { "ad7193", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7193] },
1453 { "ad7194", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7194] },
1454 { "ad7195", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7195] },
1455 { }
1456 };
1457 MODULE_DEVICE_TABLE(spi, ad7192_ids);
1458
1459 static struct spi_driver ad7192_driver = {
1460 .driver = {
1461 .name = "ad7192",
1462 .of_match_table = ad7192_of_match,
1463 },
1464 .probe = ad7192_probe,
1465 .id_table = ad7192_ids,
1466 };
1467 module_spi_driver(ad7192_driver);
1468
1469 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
1470 MODULE_DESCRIPTION("Analog Devices AD7192 and similar ADC");
1471 MODULE_LICENSE("GPL v2");
1472 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA");
1473