1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/bitops.h>
3 #include <linux/types.h>
4 #include <linux/slab.h>
5 #include <linux/sched/clock.h>
6
7 #include <asm/cpu_entry_area.h>
8 #include <asm/debugreg.h>
9 #include <asm/perf_event.h>
10 #include <asm/tlbflush.h>
11 #include <asm/insn.h>
12 #include <asm/io.h>
13 #include <asm/timer.h>
14
15 #include "../perf_event.h"
16
17 /* Waste a full page so it can be mapped into the cpu_entry_area */
18 DEFINE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store);
19
20 /* The size of a BTS record in bytes: */
21 #define BTS_RECORD_SIZE 24
22
23 #define PEBS_FIXUP_SIZE PAGE_SIZE
24
25 /*
26 * pebs_record_32 for p4 and core not supported
27
28 struct pebs_record_32 {
29 u32 flags, ip;
30 u32 ax, bc, cx, dx;
31 u32 si, di, bp, sp;
32 };
33
34 */
35
36 union intel_x86_pebs_dse {
37 u64 val;
38 struct {
39 unsigned int ld_dse:4;
40 unsigned int ld_stlb_miss:1;
41 unsigned int ld_locked:1;
42 unsigned int ld_data_blk:1;
43 unsigned int ld_addr_blk:1;
44 unsigned int ld_reserved:24;
45 };
46 struct {
47 unsigned int st_l1d_hit:1;
48 unsigned int st_reserved1:3;
49 unsigned int st_stlb_miss:1;
50 unsigned int st_locked:1;
51 unsigned int st_reserved2:26;
52 };
53 struct {
54 unsigned int st_lat_dse:4;
55 unsigned int st_lat_stlb_miss:1;
56 unsigned int st_lat_locked:1;
57 unsigned int ld_reserved3:26;
58 };
59 struct {
60 unsigned int mtl_dse:5;
61 unsigned int mtl_locked:1;
62 unsigned int mtl_stlb_miss:1;
63 unsigned int mtl_fwd_blk:1;
64 unsigned int ld_reserved4:24;
65 };
66 struct {
67 unsigned int lnc_dse:8;
68 unsigned int ld_reserved5:2;
69 unsigned int lnc_stlb_miss:1;
70 unsigned int lnc_locked:1;
71 unsigned int lnc_data_blk:1;
72 unsigned int lnc_addr_blk:1;
73 unsigned int ld_reserved6:18;
74 };
75 };
76
77
78 /*
79 * Map PEBS Load Latency Data Source encodings to generic
80 * memory data source information
81 */
82 #define P(a, b) PERF_MEM_S(a, b)
83 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
84 #define LEVEL(x) P(LVLNUM, x)
85 #define REM P(REMOTE, REMOTE)
86 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
87
88 /* Version for Sandy Bridge and later */
89 static u64 pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX] = {
90 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
91 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 local */
92 OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
93 OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
94 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
95 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
96 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
97 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
98 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
99 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
100 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
101 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
102 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | SNOOP_NONE_MISS, /* 0x0c: L3 miss, excl */
103 OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */
104 OP_LH | P(LVL, IO) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */
105 OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */
106 };
107
108 /* Patch up minor differences in the bits */
intel_pmu_pebs_data_source_nhm(void)109 void __init intel_pmu_pebs_data_source_nhm(void)
110 {
111 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
112 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
113 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
114 }
115
__intel_pmu_pebs_data_source_skl(bool pmem,u64 * data_source)116 static void __init __intel_pmu_pebs_data_source_skl(bool pmem, u64 *data_source)
117 {
118 u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4);
119
120 data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT);
121 data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT);
122 data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE);
123 data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD);
124 data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM);
125 }
126
intel_pmu_pebs_data_source_skl(bool pmem)127 void __init intel_pmu_pebs_data_source_skl(bool pmem)
128 {
129 __intel_pmu_pebs_data_source_skl(pmem, pebs_data_source);
130 }
131
__intel_pmu_pebs_data_source_grt(u64 * data_source)132 static void __init __intel_pmu_pebs_data_source_grt(u64 *data_source)
133 {
134 data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
135 data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
136 data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD);
137 }
138
intel_pmu_pebs_data_source_grt(void)139 void __init intel_pmu_pebs_data_source_grt(void)
140 {
141 __intel_pmu_pebs_data_source_grt(pebs_data_source);
142 }
143
intel_pmu_pebs_data_source_adl(void)144 void __init intel_pmu_pebs_data_source_adl(void)
145 {
146 u64 *data_source;
147
148 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source;
149 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
150 __intel_pmu_pebs_data_source_skl(false, data_source);
151
152 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source;
153 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
154 __intel_pmu_pebs_data_source_grt(data_source);
155 }
156
__intel_pmu_pebs_data_source_cmt(u64 * data_source)157 static void __init __intel_pmu_pebs_data_source_cmt(u64 *data_source)
158 {
159 data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD);
160 data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
161 data_source[0x0a] = OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, NONE);
162 data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE);
163 data_source[0x0c] = OP_LH | LEVEL(RAM) | REM | P(SNOOPX, FWD);
164 data_source[0x0d] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, HITM);
165 }
166
intel_pmu_pebs_data_source_mtl(void)167 void __init intel_pmu_pebs_data_source_mtl(void)
168 {
169 u64 *data_source;
170
171 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source;
172 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
173 __intel_pmu_pebs_data_source_skl(false, data_source);
174
175 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source;
176 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
177 __intel_pmu_pebs_data_source_cmt(data_source);
178 }
179
intel_pmu_pebs_data_source_arl_h(void)180 void __init intel_pmu_pebs_data_source_arl_h(void)
181 {
182 u64 *data_source;
183
184 intel_pmu_pebs_data_source_lnl();
185
186 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX].pebs_data_source;
187 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
188 __intel_pmu_pebs_data_source_cmt(data_source);
189 }
190
intel_pmu_pebs_data_source_cmt(void)191 void __init intel_pmu_pebs_data_source_cmt(void)
192 {
193 __intel_pmu_pebs_data_source_cmt(pebs_data_source);
194 }
195
196 /* Version for Lion Cove and later */
197 static u64 lnc_pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX] = {
198 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA), /* 0x00: ukn L3 */
199 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 hit */
200 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x02: L1 hit */
201 OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x03: LFB/L1 Miss Handling Buffer hit */
202 0, /* 0x04: Reserved */
203 OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x05: L2 Hit */
204 OP_LH | LEVEL(L2_MHB) | P(SNOOP, NONE), /* 0x06: L2 Miss Handling Buffer Hit */
205 0, /* 0x07: Reserved */
206 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x08: L3 Hit */
207 0, /* 0x09: Reserved */
208 0, /* 0x0a: Reserved */
209 0, /* 0x0b: Reserved */
210 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD), /* 0x0c: L3 Hit Snoop Fwd */
211 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x0d: L3 Hit Snoop HitM */
212 0, /* 0x0e: Reserved */
213 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x0f: L3 Miss Snoop HitM */
214 OP_LH | LEVEL(MSC) | P(SNOOP, NONE), /* 0x10: Memory-side Cache Hit */
215 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, NONE), /* 0x11: Local Memory Hit */
216 };
217
intel_pmu_pebs_data_source_lnl(void)218 void __init intel_pmu_pebs_data_source_lnl(void)
219 {
220 u64 *data_source;
221
222 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source;
223 memcpy(data_source, lnc_pebs_data_source, sizeof(lnc_pebs_data_source));
224
225 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source;
226 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
227 __intel_pmu_pebs_data_source_cmt(data_source);
228 }
229
precise_store_data(u64 status)230 static u64 precise_store_data(u64 status)
231 {
232 union intel_x86_pebs_dse dse;
233 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
234
235 dse.val = status;
236
237 /*
238 * bit 4: TLB access
239 * 1 = stored missed 2nd level TLB
240 *
241 * so it either hit the walker or the OS
242 * otherwise hit 2nd level TLB
243 */
244 if (dse.st_stlb_miss)
245 val |= P(TLB, MISS);
246 else
247 val |= P(TLB, HIT);
248
249 /*
250 * bit 0: hit L1 data cache
251 * if not set, then all we know is that
252 * it missed L1D
253 */
254 if (dse.st_l1d_hit)
255 val |= P(LVL, HIT);
256 else
257 val |= P(LVL, MISS);
258
259 /*
260 * bit 5: Locked prefix
261 */
262 if (dse.st_locked)
263 val |= P(LOCK, LOCKED);
264
265 return val;
266 }
267
precise_datala_hsw(struct perf_event * event,u64 status)268 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
269 {
270 union perf_mem_data_src dse;
271
272 dse.val = PERF_MEM_NA;
273
274 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
275 dse.mem_op = PERF_MEM_OP_STORE;
276 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
277 dse.mem_op = PERF_MEM_OP_LOAD;
278
279 /*
280 * L1 info only valid for following events:
281 *
282 * MEM_UOPS_RETIRED.STLB_MISS_STORES
283 * MEM_UOPS_RETIRED.LOCK_STORES
284 * MEM_UOPS_RETIRED.SPLIT_STORES
285 * MEM_UOPS_RETIRED.ALL_STORES
286 */
287 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
288 if (status & 1)
289 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
290 else
291 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
292 }
293 return dse.val;
294 }
295
pebs_set_tlb_lock(u64 * val,bool tlb,bool lock)296 static inline void pebs_set_tlb_lock(u64 *val, bool tlb, bool lock)
297 {
298 /*
299 * TLB access
300 * 0 = did not miss 2nd level TLB
301 * 1 = missed 2nd level TLB
302 */
303 if (tlb)
304 *val |= P(TLB, MISS) | P(TLB, L2);
305 else
306 *val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
307
308 /* locked prefix */
309 if (lock)
310 *val |= P(LOCK, LOCKED);
311 }
312
313 /* Retrieve the latency data for e-core of ADL */
__grt_latency_data(struct perf_event * event,u64 status,u8 dse,bool tlb,bool lock,bool blk)314 static u64 __grt_latency_data(struct perf_event *event, u64 status,
315 u8 dse, bool tlb, bool lock, bool blk)
316 {
317 u64 val;
318
319 WARN_ON_ONCE(hybrid_pmu(event->pmu)->pmu_type == hybrid_big);
320
321 dse &= PERF_PEBS_DATA_SOURCE_GRT_MASK;
322 val = hybrid_var(event->pmu, pebs_data_source)[dse];
323
324 pebs_set_tlb_lock(&val, tlb, lock);
325
326 if (blk)
327 val |= P(BLK, DATA);
328 else
329 val |= P(BLK, NA);
330
331 return val;
332 }
333
grt_latency_data(struct perf_event * event,u64 status)334 u64 grt_latency_data(struct perf_event *event, u64 status)
335 {
336 union intel_x86_pebs_dse dse;
337
338 dse.val = status;
339
340 return __grt_latency_data(event, status, dse.ld_dse,
341 dse.ld_locked, dse.ld_stlb_miss,
342 dse.ld_data_blk);
343 }
344
345 /* Retrieve the latency data for e-core of MTL */
cmt_latency_data(struct perf_event * event,u64 status)346 u64 cmt_latency_data(struct perf_event *event, u64 status)
347 {
348 union intel_x86_pebs_dse dse;
349
350 dse.val = status;
351
352 return __grt_latency_data(event, status, dse.mtl_dse,
353 dse.mtl_stlb_miss, dse.mtl_locked,
354 dse.mtl_fwd_blk);
355 }
356
lnc_latency_data(struct perf_event * event,u64 status)357 static u64 lnc_latency_data(struct perf_event *event, u64 status)
358 {
359 union intel_x86_pebs_dse dse;
360 union perf_mem_data_src src;
361 u64 val;
362
363 dse.val = status;
364
365 /* LNC core latency data */
366 val = hybrid_var(event->pmu, pebs_data_source)[status & PERF_PEBS_DATA_SOURCE_MASK];
367 if (!val)
368 val = P(OP, LOAD) | LEVEL(NA) | P(SNOOP, NA);
369
370 if (dse.lnc_stlb_miss)
371 val |= P(TLB, MISS) | P(TLB, L2);
372 else
373 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
374
375 if (dse.lnc_locked)
376 val |= P(LOCK, LOCKED);
377
378 if (dse.lnc_data_blk)
379 val |= P(BLK, DATA);
380 if (dse.lnc_addr_blk)
381 val |= P(BLK, ADDR);
382 if (!dse.lnc_data_blk && !dse.lnc_addr_blk)
383 val |= P(BLK, NA);
384
385 src.val = val;
386 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
387 src.mem_op = P(OP, STORE);
388
389 return src.val;
390 }
391
lnl_latency_data(struct perf_event * event,u64 status)392 u64 lnl_latency_data(struct perf_event *event, u64 status)
393 {
394 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
395
396 if (pmu->pmu_type == hybrid_small)
397 return cmt_latency_data(event, status);
398
399 return lnc_latency_data(event, status);
400 }
401
arl_h_latency_data(struct perf_event * event,u64 status)402 u64 arl_h_latency_data(struct perf_event *event, u64 status)
403 {
404 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
405
406 if (pmu->pmu_type == hybrid_tiny)
407 return cmt_latency_data(event, status);
408
409 return lnl_latency_data(event, status);
410 }
411
load_latency_data(struct perf_event * event,u64 status)412 static u64 load_latency_data(struct perf_event *event, u64 status)
413 {
414 union intel_x86_pebs_dse dse;
415 u64 val;
416
417 dse.val = status;
418
419 /*
420 * use the mapping table for bit 0-3
421 */
422 val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse];
423
424 /*
425 * Nehalem models do not support TLB, Lock infos
426 */
427 if (x86_pmu.pebs_no_tlb) {
428 val |= P(TLB, NA) | P(LOCK, NA);
429 return val;
430 }
431
432 pebs_set_tlb_lock(&val, dse.ld_stlb_miss, dse.ld_locked);
433
434 /*
435 * Ice Lake and earlier models do not support block infos.
436 */
437 if (!x86_pmu.pebs_block) {
438 val |= P(BLK, NA);
439 return val;
440 }
441 /*
442 * bit 6: load was blocked since its data could not be forwarded
443 * from a preceding store
444 */
445 if (dse.ld_data_blk)
446 val |= P(BLK, DATA);
447
448 /*
449 * bit 7: load was blocked due to potential address conflict with
450 * a preceding store
451 */
452 if (dse.ld_addr_blk)
453 val |= P(BLK, ADDR);
454
455 if (!dse.ld_data_blk && !dse.ld_addr_blk)
456 val |= P(BLK, NA);
457
458 return val;
459 }
460
store_latency_data(struct perf_event * event,u64 status)461 static u64 store_latency_data(struct perf_event *event, u64 status)
462 {
463 union intel_x86_pebs_dse dse;
464 union perf_mem_data_src src;
465 u64 val;
466
467 dse.val = status;
468
469 /*
470 * use the mapping table for bit 0-3
471 */
472 val = hybrid_var(event->pmu, pebs_data_source)[dse.st_lat_dse];
473
474 pebs_set_tlb_lock(&val, dse.st_lat_stlb_miss, dse.st_lat_locked);
475
476 val |= P(BLK, NA);
477
478 /*
479 * the pebs_data_source table is only for loads
480 * so override the mem_op to say STORE instead
481 */
482 src.val = val;
483 src.mem_op = P(OP,STORE);
484
485 return src.val;
486 }
487
488 struct pebs_record_core {
489 u64 flags, ip;
490 u64 ax, bx, cx, dx;
491 u64 si, di, bp, sp;
492 u64 r8, r9, r10, r11;
493 u64 r12, r13, r14, r15;
494 };
495
496 struct pebs_record_nhm {
497 u64 flags, ip;
498 u64 ax, bx, cx, dx;
499 u64 si, di, bp, sp;
500 u64 r8, r9, r10, r11;
501 u64 r12, r13, r14, r15;
502 u64 status, dla, dse, lat;
503 };
504
505 /*
506 * Same as pebs_record_nhm, with two additional fields.
507 */
508 struct pebs_record_hsw {
509 u64 flags, ip;
510 u64 ax, bx, cx, dx;
511 u64 si, di, bp, sp;
512 u64 r8, r9, r10, r11;
513 u64 r12, r13, r14, r15;
514 u64 status, dla, dse, lat;
515 u64 real_ip, tsx_tuning;
516 };
517
518 union hsw_tsx_tuning {
519 struct {
520 u32 cycles_last_block : 32,
521 hle_abort : 1,
522 rtm_abort : 1,
523 instruction_abort : 1,
524 non_instruction_abort : 1,
525 retry : 1,
526 data_conflict : 1,
527 capacity_writes : 1,
528 capacity_reads : 1;
529 };
530 u64 value;
531 };
532
533 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
534
535 /* Same as HSW, plus TSC */
536
537 struct pebs_record_skl {
538 u64 flags, ip;
539 u64 ax, bx, cx, dx;
540 u64 si, di, bp, sp;
541 u64 r8, r9, r10, r11;
542 u64 r12, r13, r14, r15;
543 u64 status, dla, dse, lat;
544 u64 real_ip, tsx_tuning;
545 u64 tsc;
546 };
547
init_debug_store_on_cpu(int cpu)548 void init_debug_store_on_cpu(int cpu)
549 {
550 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
551
552 if (!ds)
553 return;
554
555 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
556 (u32)((u64)(unsigned long)ds),
557 (u32)((u64)(unsigned long)ds >> 32));
558 }
559
fini_debug_store_on_cpu(int cpu)560 void fini_debug_store_on_cpu(int cpu)
561 {
562 if (!per_cpu(cpu_hw_events, cpu).ds)
563 return;
564
565 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
566 }
567
568 static DEFINE_PER_CPU(void *, insn_buffer);
569
ds_update_cea(void * cea,void * addr,size_t size,pgprot_t prot)570 static void ds_update_cea(void *cea, void *addr, size_t size, pgprot_t prot)
571 {
572 unsigned long start = (unsigned long)cea;
573 phys_addr_t pa;
574 size_t msz = 0;
575
576 pa = virt_to_phys(addr);
577
578 preempt_disable();
579 for (; msz < size; msz += PAGE_SIZE, pa += PAGE_SIZE, cea += PAGE_SIZE)
580 cea_set_pte(cea, pa, prot);
581
582 /*
583 * This is a cross-CPU update of the cpu_entry_area, we must shoot down
584 * all TLB entries for it.
585 */
586 flush_tlb_kernel_range(start, start + size);
587 preempt_enable();
588 }
589
ds_clear_cea(void * cea,size_t size)590 static void ds_clear_cea(void *cea, size_t size)
591 {
592 unsigned long start = (unsigned long)cea;
593 size_t msz = 0;
594
595 preempt_disable();
596 for (; msz < size; msz += PAGE_SIZE, cea += PAGE_SIZE)
597 cea_set_pte(cea, 0, PAGE_NONE);
598
599 flush_tlb_kernel_range(start, start + size);
600 preempt_enable();
601 }
602
dsalloc_pages(size_t size,gfp_t flags,int cpu)603 static void *dsalloc_pages(size_t size, gfp_t flags, int cpu)
604 {
605 unsigned int order = get_order(size);
606 int node = cpu_to_node(cpu);
607 struct page *page;
608
609 page = __alloc_pages_node(node, flags | __GFP_ZERO, order);
610 return page ? page_address(page) : NULL;
611 }
612
dsfree_pages(const void * buffer,size_t size)613 static void dsfree_pages(const void *buffer, size_t size)
614 {
615 if (buffer)
616 free_pages((unsigned long)buffer, get_order(size));
617 }
618
alloc_pebs_buffer(int cpu)619 static int alloc_pebs_buffer(int cpu)
620 {
621 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
622 struct debug_store *ds = hwev->ds;
623 size_t bsiz = x86_pmu.pebs_buffer_size;
624 int max, node = cpu_to_node(cpu);
625 void *buffer, *insn_buff, *cea;
626
627 if (!x86_pmu.pebs)
628 return 0;
629
630 buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu);
631 if (unlikely(!buffer))
632 return -ENOMEM;
633
634 /*
635 * HSW+ already provides us the eventing ip; no need to allocate this
636 * buffer then.
637 */
638 if (x86_pmu.intel_cap.pebs_format < 2) {
639 insn_buff = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
640 if (!insn_buff) {
641 dsfree_pages(buffer, bsiz);
642 return -ENOMEM;
643 }
644 per_cpu(insn_buffer, cpu) = insn_buff;
645 }
646 hwev->ds_pebs_vaddr = buffer;
647 /* Update the cpu entry area mapping */
648 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
649 ds->pebs_buffer_base = (unsigned long) cea;
650 ds_update_cea(cea, buffer, bsiz, PAGE_KERNEL);
651 ds->pebs_index = ds->pebs_buffer_base;
652 max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size);
653 ds->pebs_absolute_maximum = ds->pebs_buffer_base + max;
654 return 0;
655 }
656
release_pebs_buffer(int cpu)657 static void release_pebs_buffer(int cpu)
658 {
659 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
660 void *cea;
661
662 if (!x86_pmu.pebs)
663 return;
664
665 kfree(per_cpu(insn_buffer, cpu));
666 per_cpu(insn_buffer, cpu) = NULL;
667
668 /* Clear the fixmap */
669 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
670 ds_clear_cea(cea, x86_pmu.pebs_buffer_size);
671 dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size);
672 hwev->ds_pebs_vaddr = NULL;
673 }
674
alloc_bts_buffer(int cpu)675 static int alloc_bts_buffer(int cpu)
676 {
677 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
678 struct debug_store *ds = hwev->ds;
679 void *buffer, *cea;
680 int max;
681
682 if (!x86_pmu.bts)
683 return 0;
684
685 buffer = dsalloc_pages(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, cpu);
686 if (unlikely(!buffer)) {
687 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
688 return -ENOMEM;
689 }
690 hwev->ds_bts_vaddr = buffer;
691 /* Update the fixmap */
692 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
693 ds->bts_buffer_base = (unsigned long) cea;
694 ds_update_cea(cea, buffer, BTS_BUFFER_SIZE, PAGE_KERNEL);
695 ds->bts_index = ds->bts_buffer_base;
696 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
697 ds->bts_absolute_maximum = ds->bts_buffer_base +
698 max * BTS_RECORD_SIZE;
699 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
700 (max / 16) * BTS_RECORD_SIZE;
701 return 0;
702 }
703
release_bts_buffer(int cpu)704 static void release_bts_buffer(int cpu)
705 {
706 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
707 void *cea;
708
709 if (!x86_pmu.bts)
710 return;
711
712 /* Clear the fixmap */
713 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
714 ds_clear_cea(cea, BTS_BUFFER_SIZE);
715 dsfree_pages(hwev->ds_bts_vaddr, BTS_BUFFER_SIZE);
716 hwev->ds_bts_vaddr = NULL;
717 }
718
alloc_ds_buffer(int cpu)719 static int alloc_ds_buffer(int cpu)
720 {
721 struct debug_store *ds = &get_cpu_entry_area(cpu)->cpu_debug_store;
722
723 memset(ds, 0, sizeof(*ds));
724 per_cpu(cpu_hw_events, cpu).ds = ds;
725 return 0;
726 }
727
release_ds_buffer(int cpu)728 static void release_ds_buffer(int cpu)
729 {
730 per_cpu(cpu_hw_events, cpu).ds = NULL;
731 }
732
release_ds_buffers(void)733 void release_ds_buffers(void)
734 {
735 int cpu;
736
737 if (!x86_pmu.bts && !x86_pmu.pebs)
738 return;
739
740 for_each_possible_cpu(cpu)
741 release_ds_buffer(cpu);
742
743 for_each_possible_cpu(cpu) {
744 /*
745 * Again, ignore errors from offline CPUs, they will no longer
746 * observe cpu_hw_events.ds and not program the DS_AREA when
747 * they come up.
748 */
749 fini_debug_store_on_cpu(cpu);
750 }
751
752 for_each_possible_cpu(cpu) {
753 release_pebs_buffer(cpu);
754 release_bts_buffer(cpu);
755 }
756 }
757
reserve_ds_buffers(void)758 void reserve_ds_buffers(void)
759 {
760 int bts_err = 0, pebs_err = 0;
761 int cpu;
762
763 x86_pmu.bts_active = 0;
764 x86_pmu.pebs_active = 0;
765
766 if (!x86_pmu.bts && !x86_pmu.pebs)
767 return;
768
769 if (!x86_pmu.bts)
770 bts_err = 1;
771
772 if (!x86_pmu.pebs)
773 pebs_err = 1;
774
775 for_each_possible_cpu(cpu) {
776 if (alloc_ds_buffer(cpu)) {
777 bts_err = 1;
778 pebs_err = 1;
779 }
780
781 if (!bts_err && alloc_bts_buffer(cpu))
782 bts_err = 1;
783
784 if (!pebs_err && alloc_pebs_buffer(cpu))
785 pebs_err = 1;
786
787 if (bts_err && pebs_err)
788 break;
789 }
790
791 if (bts_err) {
792 for_each_possible_cpu(cpu)
793 release_bts_buffer(cpu);
794 }
795
796 if (pebs_err) {
797 for_each_possible_cpu(cpu)
798 release_pebs_buffer(cpu);
799 }
800
801 if (bts_err && pebs_err) {
802 for_each_possible_cpu(cpu)
803 release_ds_buffer(cpu);
804 } else {
805 if (x86_pmu.bts && !bts_err)
806 x86_pmu.bts_active = 1;
807
808 if (x86_pmu.pebs && !pebs_err)
809 x86_pmu.pebs_active = 1;
810
811 for_each_possible_cpu(cpu) {
812 /*
813 * Ignores wrmsr_on_cpu() errors for offline CPUs they
814 * will get this call through intel_pmu_cpu_starting().
815 */
816 init_debug_store_on_cpu(cpu);
817 }
818 }
819 }
820
821 /*
822 * BTS
823 */
824
825 struct event_constraint bts_constraint =
826 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
827
intel_pmu_enable_bts(u64 config)828 void intel_pmu_enable_bts(u64 config)
829 {
830 unsigned long debugctlmsr;
831
832 debugctlmsr = get_debugctlmsr();
833
834 debugctlmsr |= DEBUGCTLMSR_TR;
835 debugctlmsr |= DEBUGCTLMSR_BTS;
836 if (config & ARCH_PERFMON_EVENTSEL_INT)
837 debugctlmsr |= DEBUGCTLMSR_BTINT;
838
839 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
840 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
841
842 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
843 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
844
845 update_debugctlmsr(debugctlmsr);
846 }
847
intel_pmu_disable_bts(void)848 void intel_pmu_disable_bts(void)
849 {
850 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
851 unsigned long debugctlmsr;
852
853 if (!cpuc->ds)
854 return;
855
856 debugctlmsr = get_debugctlmsr();
857
858 debugctlmsr &=
859 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
860 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
861
862 update_debugctlmsr(debugctlmsr);
863 }
864
intel_pmu_drain_bts_buffer(void)865 int intel_pmu_drain_bts_buffer(void)
866 {
867 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
868 struct debug_store *ds = cpuc->ds;
869 struct bts_record {
870 u64 from;
871 u64 to;
872 u64 flags;
873 };
874 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
875 struct bts_record *at, *base, *top;
876 struct perf_output_handle handle;
877 struct perf_event_header header;
878 struct perf_sample_data data;
879 unsigned long skip = 0;
880 struct pt_regs regs;
881
882 if (!event)
883 return 0;
884
885 if (!x86_pmu.bts_active)
886 return 0;
887
888 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
889 top = (struct bts_record *)(unsigned long)ds->bts_index;
890
891 if (top <= base)
892 return 0;
893
894 memset(®s, 0, sizeof(regs));
895
896 ds->bts_index = ds->bts_buffer_base;
897
898 perf_sample_data_init(&data, 0, event->hw.last_period);
899
900 /*
901 * BTS leaks kernel addresses in branches across the cpl boundary,
902 * such as traps or system calls, so unless the user is asking for
903 * kernel tracing (and right now it's not possible), we'd need to
904 * filter them out. But first we need to count how many of those we
905 * have in the current batch. This is an extra O(n) pass, however,
906 * it's much faster than the other one especially considering that
907 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
908 * alloc_bts_buffer()).
909 */
910 for (at = base; at < top; at++) {
911 /*
912 * Note that right now *this* BTS code only works if
913 * attr::exclude_kernel is set, but let's keep this extra
914 * check here in case that changes.
915 */
916 if (event->attr.exclude_kernel &&
917 (kernel_ip(at->from) || kernel_ip(at->to)))
918 skip++;
919 }
920
921 /*
922 * Prepare a generic sample, i.e. fill in the invariant fields.
923 * We will overwrite the from and to address before we output
924 * the sample.
925 */
926 rcu_read_lock();
927 perf_prepare_sample(&data, event, ®s);
928 perf_prepare_header(&header, &data, event, ®s);
929
930 if (perf_output_begin(&handle, &data, event,
931 header.size * (top - base - skip)))
932 goto unlock;
933
934 for (at = base; at < top; at++) {
935 /* Filter out any records that contain kernel addresses. */
936 if (event->attr.exclude_kernel &&
937 (kernel_ip(at->from) || kernel_ip(at->to)))
938 continue;
939
940 data.ip = at->from;
941 data.addr = at->to;
942
943 perf_output_sample(&handle, &header, &data, event);
944 }
945
946 perf_output_end(&handle);
947
948 /* There's new data available. */
949 event->hw.interrupts++;
950 event->pending_kill = POLL_IN;
951 unlock:
952 rcu_read_unlock();
953 return 1;
954 }
955
intel_pmu_drain_pebs_buffer(void)956 static inline void intel_pmu_drain_pebs_buffer(void)
957 {
958 struct perf_sample_data data;
959
960 x86_pmu.drain_pebs(NULL, &data);
961 }
962
963 /*
964 * PEBS
965 */
966 struct event_constraint intel_core2_pebs_event_constraints[] = {
967 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
968 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
969 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
970 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
971 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
972 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
973 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
974 EVENT_CONSTRAINT_END
975 };
976
977 struct event_constraint intel_atom_pebs_event_constraints[] = {
978 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
979 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
980 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
981 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
982 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
983 /* Allow all events as PEBS with no flags */
984 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
985 EVENT_CONSTRAINT_END
986 };
987
988 struct event_constraint intel_slm_pebs_event_constraints[] = {
989 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
990 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x1),
991 /* Allow all events as PEBS with no flags */
992 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
993 EVENT_CONSTRAINT_END
994 };
995
996 struct event_constraint intel_glm_pebs_event_constraints[] = {
997 /* Allow all events as PEBS with no flags */
998 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
999 EVENT_CONSTRAINT_END
1000 };
1001
1002 struct event_constraint intel_grt_pebs_event_constraints[] = {
1003 /* Allow all events as PEBS with no flags */
1004 INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3),
1005 INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xf),
1006 EVENT_CONSTRAINT_END
1007 };
1008
1009 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
1010 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
1011 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
1012 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
1013 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
1014 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
1015 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
1016 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
1017 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
1018 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
1019 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
1020 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
1021 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
1022 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
1023 EVENT_CONSTRAINT_END
1024 };
1025
1026 struct event_constraint intel_westmere_pebs_event_constraints[] = {
1027 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
1028 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
1029 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
1030 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
1031 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
1032 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
1033 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
1034 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
1035 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
1036 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
1037 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
1038 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
1039 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
1040 EVENT_CONSTRAINT_END
1041 };
1042
1043 struct event_constraint intel_snb_pebs_event_constraints[] = {
1044 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
1045 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
1046 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
1047 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
1048 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
1049 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
1050 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
1051 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
1052 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
1053 /* Allow all events as PEBS with no flags */
1054 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
1055 EVENT_CONSTRAINT_END
1056 };
1057
1058 struct event_constraint intel_ivb_pebs_event_constraints[] = {
1059 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
1060 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
1061 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
1062 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
1063 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
1064 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
1065 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
1066 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
1067 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
1068 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
1069 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
1070 /* Allow all events as PEBS with no flags */
1071 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
1072 EVENT_CONSTRAINT_END
1073 };
1074
1075 struct event_constraint intel_hsw_pebs_event_constraints[] = {
1076 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
1077 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
1078 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
1079 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
1080 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
1081 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
1082 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
1083 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
1084 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
1085 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
1086 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
1087 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
1088 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
1089 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
1090 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
1091 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
1092 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
1093 /* Allow all events as PEBS with no flags */
1094 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
1095 EVENT_CONSTRAINT_END
1096 };
1097
1098 struct event_constraint intel_bdw_pebs_event_constraints[] = {
1099 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
1100 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
1101 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
1102 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
1103 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
1104 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
1105 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
1106 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
1107 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
1108 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
1109 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
1110 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
1111 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
1112 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
1113 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
1114 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
1115 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
1116 /* Allow all events as PEBS with no flags */
1117 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
1118 EVENT_CONSTRAINT_END
1119 };
1120
1121
1122 struct event_constraint intel_skl_pebs_event_constraints[] = {
1123 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
1124 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
1125 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
1126 /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
1127 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
1128 INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */
1129 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
1130 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
1131 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
1132 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
1133 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
1134 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
1135 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
1136 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
1137 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
1138 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
1139 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */
1140 /* Allow all events as PEBS with no flags */
1141 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
1142 EVENT_CONSTRAINT_END
1143 };
1144
1145 struct event_constraint intel_icl_pebs_event_constraints[] = {
1146 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x100000000ULL), /* old INST_RETIRED.PREC_DIST */
1147 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
1148 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), /* SLOTS */
1149
1150 INTEL_PLD_CONSTRAINT(0x1cd, 0xff), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
1151 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
1152 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
1153 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
1154 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
1155 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
1156 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
1157 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
1158
1159 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), /* MEM_LOAD_*_RETIRED.* */
1160
1161 INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
1162
1163 /*
1164 * Everything else is handled by PMU_FL_PEBS_ALL, because we
1165 * need the full constraints from the main table.
1166 */
1167
1168 EVENT_CONSTRAINT_END
1169 };
1170
1171 struct event_constraint intel_glc_pebs_event_constraints[] = {
1172 INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
1173 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
1174
1175 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xfe),
1176 INTEL_PLD_CONSTRAINT(0x1cd, 0xfe),
1177 INTEL_PSD_CONSTRAINT(0x2cd, 0x1),
1178 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
1179 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
1180 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
1181 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
1182 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
1183 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
1184 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
1185
1186 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),
1187
1188 INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf),
1189
1190 /*
1191 * Everything else is handled by PMU_FL_PEBS_ALL, because we
1192 * need the full constraints from the main table.
1193 */
1194
1195 EVENT_CONSTRAINT_END
1196 };
1197
1198 struct event_constraint intel_lnc_pebs_event_constraints[] = {
1199 INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
1200 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
1201
1202 INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0x3fc),
1203 INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3),
1204 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
1205 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
1206 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
1207 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
1208 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
1209 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
1210 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
1211
1212 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),
1213
1214 INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf),
1215
1216 /*
1217 * Everything else is handled by PMU_FL_PEBS_ALL, because we
1218 * need the full constraints from the main table.
1219 */
1220
1221 EVENT_CONSTRAINT_END
1222 };
1223
intel_pebs_constraints(struct perf_event * event)1224 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
1225 {
1226 struct event_constraint *pebs_constraints = hybrid(event->pmu, pebs_constraints);
1227 struct event_constraint *c;
1228
1229 if (!event->attr.precise_ip)
1230 return NULL;
1231
1232 if (pebs_constraints) {
1233 for_each_event_constraint(c, pebs_constraints) {
1234 if (constraint_match(c, event->hw.config)) {
1235 event->hw.flags |= c->flags;
1236 return c;
1237 }
1238 }
1239 }
1240
1241 /*
1242 * Extended PEBS support
1243 * Makes the PEBS code search the normal constraints.
1244 */
1245 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
1246 return NULL;
1247
1248 return &emptyconstraint;
1249 }
1250
1251 /*
1252 * We need the sched_task callback even for per-cpu events when we use
1253 * the large interrupt threshold, such that we can provide PID and TID
1254 * to PEBS samples.
1255 */
pebs_needs_sched_cb(struct cpu_hw_events * cpuc)1256 static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc)
1257 {
1258 if (cpuc->n_pebs == cpuc->n_pebs_via_pt)
1259 return false;
1260
1261 return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs);
1262 }
1263
intel_pmu_pebs_sched_task(struct perf_event_pmu_context * pmu_ctx,bool sched_in)1264 void intel_pmu_pebs_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in)
1265 {
1266 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1267
1268 if (!sched_in && pebs_needs_sched_cb(cpuc))
1269 intel_pmu_drain_pebs_buffer();
1270 }
1271
pebs_update_threshold(struct cpu_hw_events * cpuc)1272 static inline void pebs_update_threshold(struct cpu_hw_events *cpuc)
1273 {
1274 struct debug_store *ds = cpuc->ds;
1275 int max_pebs_events = intel_pmu_max_num_pebs(cpuc->pmu);
1276 u64 threshold;
1277 int reserved;
1278
1279 if (cpuc->n_pebs_via_pt)
1280 return;
1281
1282 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
1283 reserved = max_pebs_events + x86_pmu_max_num_counters_fixed(cpuc->pmu);
1284 else
1285 reserved = max_pebs_events;
1286
1287 if (cpuc->n_pebs == cpuc->n_large_pebs) {
1288 threshold = ds->pebs_absolute_maximum -
1289 reserved * cpuc->pebs_record_size;
1290 } else {
1291 threshold = ds->pebs_buffer_base + cpuc->pebs_record_size;
1292 }
1293
1294 ds->pebs_interrupt_threshold = threshold;
1295 }
1296
adaptive_pebs_record_size_update(void)1297 static void adaptive_pebs_record_size_update(void)
1298 {
1299 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1300 u64 pebs_data_cfg = cpuc->pebs_data_cfg;
1301 int sz = sizeof(struct pebs_basic);
1302
1303 if (pebs_data_cfg & PEBS_DATACFG_MEMINFO)
1304 sz += sizeof(struct pebs_meminfo);
1305 if (pebs_data_cfg & PEBS_DATACFG_GP)
1306 sz += sizeof(struct pebs_gprs);
1307 if (pebs_data_cfg & PEBS_DATACFG_XMMS)
1308 sz += sizeof(struct pebs_xmm);
1309 if (pebs_data_cfg & PEBS_DATACFG_LBRS)
1310 sz += x86_pmu.lbr_nr * sizeof(struct lbr_entry);
1311
1312 cpuc->pebs_record_size = sz;
1313 }
1314
1315 #define PERF_PEBS_MEMINFO_TYPE (PERF_SAMPLE_ADDR | PERF_SAMPLE_DATA_SRC | \
1316 PERF_SAMPLE_PHYS_ADDR | \
1317 PERF_SAMPLE_WEIGHT_TYPE | \
1318 PERF_SAMPLE_TRANSACTION | \
1319 PERF_SAMPLE_DATA_PAGE_SIZE)
1320
pebs_update_adaptive_cfg(struct perf_event * event)1321 static u64 pebs_update_adaptive_cfg(struct perf_event *event)
1322 {
1323 struct perf_event_attr *attr = &event->attr;
1324 u64 sample_type = attr->sample_type;
1325 u64 pebs_data_cfg = 0;
1326 bool gprs, tsx_weight;
1327
1328 if (!(sample_type & ~(PERF_SAMPLE_IP|PERF_SAMPLE_TIME)) &&
1329 attr->precise_ip > 1)
1330 return pebs_data_cfg;
1331
1332 if (sample_type & PERF_PEBS_MEMINFO_TYPE)
1333 pebs_data_cfg |= PEBS_DATACFG_MEMINFO;
1334
1335 /*
1336 * We need GPRs when:
1337 * + user requested them
1338 * + precise_ip < 2 for the non event IP
1339 * + For RTM TSX weight we need GPRs for the abort code.
1340 */
1341 gprs = (sample_type & PERF_SAMPLE_REGS_INTR) &&
1342 (attr->sample_regs_intr & PEBS_GP_REGS);
1343
1344 tsx_weight = (sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&
1345 ((attr->config & INTEL_ARCH_EVENT_MASK) ==
1346 x86_pmu.rtm_abort_event);
1347
1348 if (gprs || (attr->precise_ip < 2) || tsx_weight)
1349 pebs_data_cfg |= PEBS_DATACFG_GP;
1350
1351 if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
1352 (attr->sample_regs_intr & PERF_REG_EXTENDED_MASK))
1353 pebs_data_cfg |= PEBS_DATACFG_XMMS;
1354
1355 if (sample_type & PERF_SAMPLE_BRANCH_STACK) {
1356 /*
1357 * For now always log all LBRs. Could configure this
1358 * later.
1359 */
1360 pebs_data_cfg |= PEBS_DATACFG_LBRS |
1361 ((x86_pmu.lbr_nr-1) << PEBS_DATACFG_LBR_SHIFT);
1362 }
1363
1364 return pebs_data_cfg;
1365 }
1366
1367 static void
pebs_update_state(bool needed_cb,struct cpu_hw_events * cpuc,struct perf_event * event,bool add)1368 pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc,
1369 struct perf_event *event, bool add)
1370 {
1371 struct pmu *pmu = event->pmu;
1372
1373 /*
1374 * Make sure we get updated with the first PEBS event.
1375 * During removal, ->pebs_data_cfg is still valid for
1376 * the last PEBS event. Don't clear it.
1377 */
1378 if ((cpuc->n_pebs == 1) && add)
1379 cpuc->pebs_data_cfg = PEBS_UPDATE_DS_SW;
1380
1381 if (needed_cb != pebs_needs_sched_cb(cpuc)) {
1382 if (!needed_cb)
1383 perf_sched_cb_inc(pmu);
1384 else
1385 perf_sched_cb_dec(pmu);
1386
1387 cpuc->pebs_data_cfg |= PEBS_UPDATE_DS_SW;
1388 }
1389
1390 /*
1391 * The PEBS record doesn't shrink on pmu::del(). Doing so would require
1392 * iterating all remaining PEBS events to reconstruct the config.
1393 */
1394 if (x86_pmu.intel_cap.pebs_baseline && add) {
1395 u64 pebs_data_cfg;
1396
1397 pebs_data_cfg = pebs_update_adaptive_cfg(event);
1398 /*
1399 * Be sure to update the thresholds when we change the record.
1400 */
1401 if (pebs_data_cfg & ~cpuc->pebs_data_cfg)
1402 cpuc->pebs_data_cfg |= pebs_data_cfg | PEBS_UPDATE_DS_SW;
1403 }
1404 }
1405
intel_pmu_pebs_add(struct perf_event * event)1406 void intel_pmu_pebs_add(struct perf_event *event)
1407 {
1408 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1409 struct hw_perf_event *hwc = &event->hw;
1410 bool needed_cb = pebs_needs_sched_cb(cpuc);
1411
1412 cpuc->n_pebs++;
1413 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
1414 cpuc->n_large_pebs++;
1415 if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT)
1416 cpuc->n_pebs_via_pt++;
1417
1418 pebs_update_state(needed_cb, cpuc, event, true);
1419 }
1420
intel_pmu_pebs_via_pt_disable(struct perf_event * event)1421 static void intel_pmu_pebs_via_pt_disable(struct perf_event *event)
1422 {
1423 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1424
1425 if (!is_pebs_pt(event))
1426 return;
1427
1428 if (!(cpuc->pebs_enabled & ~PEBS_VIA_PT_MASK))
1429 cpuc->pebs_enabled &= ~PEBS_VIA_PT_MASK;
1430 }
1431
intel_pmu_pebs_via_pt_enable(struct perf_event * event)1432 static void intel_pmu_pebs_via_pt_enable(struct perf_event *event)
1433 {
1434 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1435 struct hw_perf_event *hwc = &event->hw;
1436 struct debug_store *ds = cpuc->ds;
1437 u64 value = ds->pebs_event_reset[hwc->idx];
1438 u32 base = MSR_RELOAD_PMC0;
1439 unsigned int idx = hwc->idx;
1440
1441 if (!is_pebs_pt(event))
1442 return;
1443
1444 if (!(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
1445 cpuc->pebs_enabled |= PEBS_PMI_AFTER_EACH_RECORD;
1446
1447 cpuc->pebs_enabled |= PEBS_OUTPUT_PT;
1448
1449 if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
1450 base = MSR_RELOAD_FIXED_CTR0;
1451 idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1452 if (x86_pmu.intel_cap.pebs_format < 5)
1453 value = ds->pebs_event_reset[MAX_PEBS_EVENTS_FMT4 + idx];
1454 else
1455 value = ds->pebs_event_reset[MAX_PEBS_EVENTS + idx];
1456 }
1457 wrmsrl(base + idx, value);
1458 }
1459
intel_pmu_drain_large_pebs(struct cpu_hw_events * cpuc)1460 static inline void intel_pmu_drain_large_pebs(struct cpu_hw_events *cpuc)
1461 {
1462 if (cpuc->n_pebs == cpuc->n_large_pebs &&
1463 cpuc->n_pebs != cpuc->n_pebs_via_pt)
1464 intel_pmu_drain_pebs_buffer();
1465 }
1466
intel_pmu_pebs_enable(struct perf_event * event)1467 void intel_pmu_pebs_enable(struct perf_event *event)
1468 {
1469 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1470 u64 pebs_data_cfg = cpuc->pebs_data_cfg & ~PEBS_UPDATE_DS_SW;
1471 struct hw_perf_event *hwc = &event->hw;
1472 struct debug_store *ds = cpuc->ds;
1473 unsigned int idx = hwc->idx;
1474
1475 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
1476
1477 cpuc->pebs_enabled |= 1ULL << hwc->idx;
1478
1479 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && (x86_pmu.version < 5))
1480 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
1481 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
1482 cpuc->pebs_enabled |= 1ULL << 63;
1483
1484 if (x86_pmu.intel_cap.pebs_baseline) {
1485 hwc->config |= ICL_EVENTSEL_ADAPTIVE;
1486 if (pebs_data_cfg != cpuc->active_pebs_data_cfg) {
1487 /*
1488 * drain_pebs() assumes uniform record size;
1489 * hence we need to drain when changing said
1490 * size.
1491 */
1492 intel_pmu_drain_pebs_buffer();
1493 adaptive_pebs_record_size_update();
1494 wrmsrl(MSR_PEBS_DATA_CFG, pebs_data_cfg);
1495 cpuc->active_pebs_data_cfg = pebs_data_cfg;
1496 }
1497 }
1498 if (cpuc->pebs_data_cfg & PEBS_UPDATE_DS_SW) {
1499 cpuc->pebs_data_cfg = pebs_data_cfg;
1500 pebs_update_threshold(cpuc);
1501 }
1502
1503 if (idx >= INTEL_PMC_IDX_FIXED) {
1504 if (x86_pmu.intel_cap.pebs_format < 5)
1505 idx = MAX_PEBS_EVENTS_FMT4 + (idx - INTEL_PMC_IDX_FIXED);
1506 else
1507 idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED);
1508 }
1509
1510 /*
1511 * Use auto-reload if possible to save a MSR write in the PMI.
1512 * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD.
1513 */
1514 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
1515 ds->pebs_event_reset[idx] =
1516 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
1517 } else {
1518 ds->pebs_event_reset[idx] = 0;
1519 }
1520
1521 intel_pmu_pebs_via_pt_enable(event);
1522 }
1523
intel_pmu_pebs_del(struct perf_event * event)1524 void intel_pmu_pebs_del(struct perf_event *event)
1525 {
1526 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1527 struct hw_perf_event *hwc = &event->hw;
1528 bool needed_cb = pebs_needs_sched_cb(cpuc);
1529
1530 cpuc->n_pebs--;
1531 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
1532 cpuc->n_large_pebs--;
1533 if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT)
1534 cpuc->n_pebs_via_pt--;
1535
1536 pebs_update_state(needed_cb, cpuc, event, false);
1537 }
1538
intel_pmu_pebs_disable(struct perf_event * event)1539 void intel_pmu_pebs_disable(struct perf_event *event)
1540 {
1541 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1542 struct hw_perf_event *hwc = &event->hw;
1543
1544 intel_pmu_drain_large_pebs(cpuc);
1545
1546 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
1547
1548 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) &&
1549 (x86_pmu.version < 5))
1550 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
1551 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
1552 cpuc->pebs_enabled &= ~(1ULL << 63);
1553
1554 intel_pmu_pebs_via_pt_disable(event);
1555
1556 if (cpuc->enabled)
1557 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
1558
1559 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
1560 }
1561
intel_pmu_pebs_enable_all(void)1562 void intel_pmu_pebs_enable_all(void)
1563 {
1564 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1565
1566 if (cpuc->pebs_enabled)
1567 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
1568 }
1569
intel_pmu_pebs_disable_all(void)1570 void intel_pmu_pebs_disable_all(void)
1571 {
1572 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1573
1574 if (cpuc->pebs_enabled)
1575 __intel_pmu_pebs_disable_all();
1576 }
1577
intel_pmu_pebs_fixup_ip(struct pt_regs * regs)1578 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
1579 {
1580 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1581 unsigned long from = cpuc->lbr_entries[0].from;
1582 unsigned long old_to, to = cpuc->lbr_entries[0].to;
1583 unsigned long ip = regs->ip;
1584 int is_64bit = 0;
1585 void *kaddr;
1586 int size;
1587
1588 /*
1589 * We don't need to fixup if the PEBS assist is fault like
1590 */
1591 if (!x86_pmu.intel_cap.pebs_trap)
1592 return 1;
1593
1594 /*
1595 * No LBR entry, no basic block, no rewinding
1596 */
1597 if (!cpuc->lbr_stack.nr || !from || !to)
1598 return 0;
1599
1600 /*
1601 * Basic blocks should never cross user/kernel boundaries
1602 */
1603 if (kernel_ip(ip) != kernel_ip(to))
1604 return 0;
1605
1606 /*
1607 * unsigned math, either ip is before the start (impossible) or
1608 * the basic block is larger than 1 page (sanity)
1609 */
1610 if ((ip - to) > PEBS_FIXUP_SIZE)
1611 return 0;
1612
1613 /*
1614 * We sampled a branch insn, rewind using the LBR stack
1615 */
1616 if (ip == to) {
1617 set_linear_ip(regs, from);
1618 return 1;
1619 }
1620
1621 size = ip - to;
1622 if (!kernel_ip(ip)) {
1623 int bytes;
1624 u8 *buf = this_cpu_read(insn_buffer);
1625
1626 /* 'size' must fit our buffer, see above */
1627 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
1628 if (bytes != 0)
1629 return 0;
1630
1631 kaddr = buf;
1632 } else {
1633 kaddr = (void *)to;
1634 }
1635
1636 do {
1637 struct insn insn;
1638
1639 old_to = to;
1640
1641 #ifdef CONFIG_X86_64
1642 is_64bit = kernel_ip(to) || any_64bit_mode(regs);
1643 #endif
1644 insn_init(&insn, kaddr, size, is_64bit);
1645
1646 /*
1647 * Make sure there was not a problem decoding the instruction.
1648 * This is doubly important because we have an infinite loop if
1649 * insn.length=0.
1650 */
1651 if (insn_get_length(&insn))
1652 break;
1653
1654 to += insn.length;
1655 kaddr += insn.length;
1656 size -= insn.length;
1657 } while (to < ip);
1658
1659 if (to == ip) {
1660 set_linear_ip(regs, old_to);
1661 return 1;
1662 }
1663
1664 /*
1665 * Even though we decoded the basic block, the instruction stream
1666 * never matched the given IP, either the TO or the IP got corrupted.
1667 */
1668 return 0;
1669 }
1670
intel_get_tsx_weight(u64 tsx_tuning)1671 static inline u64 intel_get_tsx_weight(u64 tsx_tuning)
1672 {
1673 if (tsx_tuning) {
1674 union hsw_tsx_tuning tsx = { .value = tsx_tuning };
1675 return tsx.cycles_last_block;
1676 }
1677 return 0;
1678 }
1679
intel_get_tsx_transaction(u64 tsx_tuning,u64 ax)1680 static inline u64 intel_get_tsx_transaction(u64 tsx_tuning, u64 ax)
1681 {
1682 u64 txn = (tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
1683
1684 /* For RTM XABORTs also log the abort code from AX */
1685 if ((txn & PERF_TXN_TRANSACTION) && (ax & 1))
1686 txn |= ((ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
1687 return txn;
1688 }
1689
get_pebs_status(void * n)1690 static inline u64 get_pebs_status(void *n)
1691 {
1692 if (x86_pmu.intel_cap.pebs_format < 4)
1693 return ((struct pebs_record_nhm *)n)->status;
1694 return ((struct pebs_basic *)n)->applicable_counters;
1695 }
1696
1697 #define PERF_X86_EVENT_PEBS_HSW_PREC \
1698 (PERF_X86_EVENT_PEBS_ST_HSW | \
1699 PERF_X86_EVENT_PEBS_LD_HSW | \
1700 PERF_X86_EVENT_PEBS_NA_HSW)
1701
get_data_src(struct perf_event * event,u64 aux)1702 static u64 get_data_src(struct perf_event *event, u64 aux)
1703 {
1704 u64 val = PERF_MEM_NA;
1705 int fl = event->hw.flags;
1706 bool fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
1707
1708 if (fl & PERF_X86_EVENT_PEBS_LDLAT)
1709 val = load_latency_data(event, aux);
1710 else if (fl & PERF_X86_EVENT_PEBS_STLAT)
1711 val = store_latency_data(event, aux);
1712 else if (fl & PERF_X86_EVENT_PEBS_LAT_HYBRID)
1713 val = x86_pmu.pebs_latency_data(event, aux);
1714 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
1715 val = precise_datala_hsw(event, aux);
1716 else if (fst)
1717 val = precise_store_data(aux);
1718 return val;
1719 }
1720
setup_pebs_time(struct perf_event * event,struct perf_sample_data * data,u64 tsc)1721 static void setup_pebs_time(struct perf_event *event,
1722 struct perf_sample_data *data,
1723 u64 tsc)
1724 {
1725 /* Converting to a user-defined clock is not supported yet. */
1726 if (event->attr.use_clockid != 0)
1727 return;
1728
1729 /*
1730 * Doesn't support the conversion when the TSC is unstable.
1731 * The TSC unstable case is a corner case and very unlikely to
1732 * happen. If it happens, the TSC in a PEBS record will be
1733 * dropped and fall back to perf_event_clock().
1734 */
1735 if (!using_native_sched_clock() || !sched_clock_stable())
1736 return;
1737
1738 data->time = native_sched_clock_from_tsc(tsc) + __sched_clock_offset;
1739 data->sample_flags |= PERF_SAMPLE_TIME;
1740 }
1741
1742 #define PERF_SAMPLE_ADDR_TYPE (PERF_SAMPLE_ADDR | \
1743 PERF_SAMPLE_PHYS_ADDR | \
1744 PERF_SAMPLE_DATA_PAGE_SIZE)
1745
setup_pebs_fixed_sample_data(struct perf_event * event,struct pt_regs * iregs,void * __pebs,struct perf_sample_data * data,struct pt_regs * regs)1746 static void setup_pebs_fixed_sample_data(struct perf_event *event,
1747 struct pt_regs *iregs, void *__pebs,
1748 struct perf_sample_data *data,
1749 struct pt_regs *regs)
1750 {
1751 /*
1752 * We cast to the biggest pebs_record but are careful not to
1753 * unconditionally access the 'extra' entries.
1754 */
1755 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1756 struct pebs_record_skl *pebs = __pebs;
1757 u64 sample_type;
1758 int fll;
1759
1760 if (pebs == NULL)
1761 return;
1762
1763 sample_type = event->attr.sample_type;
1764 fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
1765
1766 perf_sample_data_init(data, 0, event->hw.last_period);
1767
1768 data->period = event->hw.last_period;
1769
1770 /*
1771 * Use latency for weight (only avail with PEBS-LL)
1772 */
1773 if (fll && (sample_type & PERF_SAMPLE_WEIGHT_TYPE)) {
1774 data->weight.full = pebs->lat;
1775 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
1776 }
1777
1778 /*
1779 * data.data_src encodes the data source
1780 */
1781 if (sample_type & PERF_SAMPLE_DATA_SRC) {
1782 data->data_src.val = get_data_src(event, pebs->dse);
1783 data->sample_flags |= PERF_SAMPLE_DATA_SRC;
1784 }
1785
1786 /*
1787 * We must however always use iregs for the unwinder to stay sane; the
1788 * record BP,SP,IP can point into thin air when the record is from a
1789 * previous PMI context or an (I)RET happened between the record and
1790 * PMI.
1791 */
1792 perf_sample_save_callchain(data, event, iregs);
1793
1794 /*
1795 * We use the interrupt regs as a base because the PEBS record does not
1796 * contain a full regs set, specifically it seems to lack segment
1797 * descriptors, which get used by things like user_mode().
1798 *
1799 * In the simple case fix up only the IP for PERF_SAMPLE_IP.
1800 */
1801 *regs = *iregs;
1802
1803 /*
1804 * Initialize regs_>flags from PEBS,
1805 * Clear exact bit (which uses x86 EFLAGS Reserved bit 3),
1806 * i.e., do not rely on it being zero:
1807 */
1808 regs->flags = pebs->flags & ~PERF_EFLAGS_EXACT;
1809
1810 if (sample_type & PERF_SAMPLE_REGS_INTR) {
1811 regs->ax = pebs->ax;
1812 regs->bx = pebs->bx;
1813 regs->cx = pebs->cx;
1814 regs->dx = pebs->dx;
1815 regs->si = pebs->si;
1816 regs->di = pebs->di;
1817
1818 regs->bp = pebs->bp;
1819 regs->sp = pebs->sp;
1820
1821 #ifndef CONFIG_X86_32
1822 regs->r8 = pebs->r8;
1823 regs->r9 = pebs->r9;
1824 regs->r10 = pebs->r10;
1825 regs->r11 = pebs->r11;
1826 regs->r12 = pebs->r12;
1827 regs->r13 = pebs->r13;
1828 regs->r14 = pebs->r14;
1829 regs->r15 = pebs->r15;
1830 #endif
1831 }
1832
1833 if (event->attr.precise_ip > 1) {
1834 /*
1835 * Haswell and later processors have an 'eventing IP'
1836 * (real IP) which fixes the off-by-1 skid in hardware.
1837 * Use it when precise_ip >= 2 :
1838 */
1839 if (x86_pmu.intel_cap.pebs_format >= 2) {
1840 set_linear_ip(regs, pebs->real_ip);
1841 regs->flags |= PERF_EFLAGS_EXACT;
1842 } else {
1843 /* Otherwise, use PEBS off-by-1 IP: */
1844 set_linear_ip(regs, pebs->ip);
1845
1846 /*
1847 * With precise_ip >= 2, try to fix up the off-by-1 IP
1848 * using the LBR. If successful, the fixup function
1849 * corrects regs->ip and calls set_linear_ip() on regs:
1850 */
1851 if (intel_pmu_pebs_fixup_ip(regs))
1852 regs->flags |= PERF_EFLAGS_EXACT;
1853 }
1854 } else {
1855 /*
1856 * When precise_ip == 1, return the PEBS off-by-1 IP,
1857 * no fixup attempted:
1858 */
1859 set_linear_ip(regs, pebs->ip);
1860 }
1861
1862
1863 if ((sample_type & PERF_SAMPLE_ADDR_TYPE) &&
1864 x86_pmu.intel_cap.pebs_format >= 1) {
1865 data->addr = pebs->dla;
1866 data->sample_flags |= PERF_SAMPLE_ADDR;
1867 }
1868
1869 if (x86_pmu.intel_cap.pebs_format >= 2) {
1870 /* Only set the TSX weight when no memory weight. */
1871 if ((sample_type & PERF_SAMPLE_WEIGHT_TYPE) && !fll) {
1872 data->weight.full = intel_get_tsx_weight(pebs->tsx_tuning);
1873 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
1874 }
1875 if (sample_type & PERF_SAMPLE_TRANSACTION) {
1876 data->txn = intel_get_tsx_transaction(pebs->tsx_tuning,
1877 pebs->ax);
1878 data->sample_flags |= PERF_SAMPLE_TRANSACTION;
1879 }
1880 }
1881
1882 /*
1883 * v3 supplies an accurate time stamp, so we use that
1884 * for the time stamp.
1885 *
1886 * We can only do this for the default trace clock.
1887 */
1888 if (x86_pmu.intel_cap.pebs_format >= 3)
1889 setup_pebs_time(event, data, pebs->tsc);
1890
1891 perf_sample_save_brstack(data, event, &cpuc->lbr_stack, NULL);
1892 }
1893
adaptive_pebs_save_regs(struct pt_regs * regs,struct pebs_gprs * gprs)1894 static void adaptive_pebs_save_regs(struct pt_regs *regs,
1895 struct pebs_gprs *gprs)
1896 {
1897 regs->ax = gprs->ax;
1898 regs->bx = gprs->bx;
1899 regs->cx = gprs->cx;
1900 regs->dx = gprs->dx;
1901 regs->si = gprs->si;
1902 regs->di = gprs->di;
1903 regs->bp = gprs->bp;
1904 regs->sp = gprs->sp;
1905 #ifndef CONFIG_X86_32
1906 regs->r8 = gprs->r8;
1907 regs->r9 = gprs->r9;
1908 regs->r10 = gprs->r10;
1909 regs->r11 = gprs->r11;
1910 regs->r12 = gprs->r12;
1911 regs->r13 = gprs->r13;
1912 regs->r14 = gprs->r14;
1913 regs->r15 = gprs->r15;
1914 #endif
1915 }
1916
1917 #define PEBS_LATENCY_MASK 0xffff
1918
1919 /*
1920 * With adaptive PEBS the layout depends on what fields are configured.
1921 */
1922
setup_pebs_adaptive_sample_data(struct perf_event * event,struct pt_regs * iregs,void * __pebs,struct perf_sample_data * data,struct pt_regs * regs)1923 static void setup_pebs_adaptive_sample_data(struct perf_event *event,
1924 struct pt_regs *iregs, void *__pebs,
1925 struct perf_sample_data *data,
1926 struct pt_regs *regs)
1927 {
1928 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1929 struct pebs_basic *basic = __pebs;
1930 void *next_record = basic + 1;
1931 u64 sample_type, format_group;
1932 struct pebs_meminfo *meminfo = NULL;
1933 struct pebs_gprs *gprs = NULL;
1934 struct x86_perf_regs *perf_regs;
1935
1936 if (basic == NULL)
1937 return;
1938
1939 perf_regs = container_of(regs, struct x86_perf_regs, regs);
1940 perf_regs->xmm_regs = NULL;
1941
1942 sample_type = event->attr.sample_type;
1943 format_group = basic->format_group;
1944 perf_sample_data_init(data, 0, event->hw.last_period);
1945 data->period = event->hw.last_period;
1946
1947 setup_pebs_time(event, data, basic->tsc);
1948
1949 /*
1950 * We must however always use iregs for the unwinder to stay sane; the
1951 * record BP,SP,IP can point into thin air when the record is from a
1952 * previous PMI context or an (I)RET happened between the record and
1953 * PMI.
1954 */
1955 perf_sample_save_callchain(data, event, iregs);
1956
1957 *regs = *iregs;
1958 /* The ip in basic is EventingIP */
1959 set_linear_ip(regs, basic->ip);
1960 regs->flags = PERF_EFLAGS_EXACT;
1961
1962 if (sample_type & PERF_SAMPLE_WEIGHT_STRUCT) {
1963 if (x86_pmu.flags & PMU_FL_RETIRE_LATENCY)
1964 data->weight.var3_w = basic->retire_latency;
1965 else
1966 data->weight.var3_w = 0;
1967 }
1968
1969 /*
1970 * The record for MEMINFO is in front of GP
1971 * But PERF_SAMPLE_TRANSACTION needs gprs->ax.
1972 * Save the pointer here but process later.
1973 */
1974 if (format_group & PEBS_DATACFG_MEMINFO) {
1975 meminfo = next_record;
1976 next_record = meminfo + 1;
1977 }
1978
1979 if (format_group & PEBS_DATACFG_GP) {
1980 gprs = next_record;
1981 next_record = gprs + 1;
1982
1983 if (event->attr.precise_ip < 2) {
1984 set_linear_ip(regs, gprs->ip);
1985 regs->flags &= ~PERF_EFLAGS_EXACT;
1986 }
1987
1988 if (sample_type & PERF_SAMPLE_REGS_INTR)
1989 adaptive_pebs_save_regs(regs, gprs);
1990 }
1991
1992 if (format_group & PEBS_DATACFG_MEMINFO) {
1993 if (sample_type & PERF_SAMPLE_WEIGHT_TYPE) {
1994 u64 latency = x86_pmu.flags & PMU_FL_INSTR_LATENCY ?
1995 meminfo->cache_latency : meminfo->mem_latency;
1996
1997 if (x86_pmu.flags & PMU_FL_INSTR_LATENCY)
1998 data->weight.var2_w = meminfo->instr_latency;
1999
2000 /*
2001 * Although meminfo::latency is defined as a u64,
2002 * only the lower 32 bits include the valid data
2003 * in practice on Ice Lake and earlier platforms.
2004 */
2005 if (sample_type & PERF_SAMPLE_WEIGHT) {
2006 data->weight.full = latency ?:
2007 intel_get_tsx_weight(meminfo->tsx_tuning);
2008 } else {
2009 data->weight.var1_dw = (u32)latency ?:
2010 intel_get_tsx_weight(meminfo->tsx_tuning);
2011 }
2012
2013 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
2014 }
2015
2016 if (sample_type & PERF_SAMPLE_DATA_SRC) {
2017 data->data_src.val = get_data_src(event, meminfo->aux);
2018 data->sample_flags |= PERF_SAMPLE_DATA_SRC;
2019 }
2020
2021 if (sample_type & PERF_SAMPLE_ADDR_TYPE) {
2022 data->addr = meminfo->address;
2023 data->sample_flags |= PERF_SAMPLE_ADDR;
2024 }
2025
2026 if (sample_type & PERF_SAMPLE_TRANSACTION) {
2027 data->txn = intel_get_tsx_transaction(meminfo->tsx_tuning,
2028 gprs ? gprs->ax : 0);
2029 data->sample_flags |= PERF_SAMPLE_TRANSACTION;
2030 }
2031 }
2032
2033 if (format_group & PEBS_DATACFG_XMMS) {
2034 struct pebs_xmm *xmm = next_record;
2035
2036 next_record = xmm + 1;
2037 perf_regs->xmm_regs = xmm->xmm;
2038 }
2039
2040 if (format_group & PEBS_DATACFG_LBRS) {
2041 struct lbr_entry *lbr = next_record;
2042 int num_lbr = ((format_group >> PEBS_DATACFG_LBR_SHIFT)
2043 & 0xff) + 1;
2044 next_record = next_record + num_lbr * sizeof(struct lbr_entry);
2045
2046 if (has_branch_stack(event)) {
2047 intel_pmu_store_pebs_lbrs(lbr);
2048 intel_pmu_lbr_save_brstack(data, cpuc, event);
2049 }
2050 }
2051
2052 WARN_ONCE(next_record != __pebs + basic->format_size,
2053 "PEBS record size %u, expected %llu, config %llx\n",
2054 basic->format_size,
2055 (u64)(next_record - __pebs),
2056 format_group);
2057 }
2058
2059 static inline void *
get_next_pebs_record_by_bit(void * base,void * top,int bit)2060 get_next_pebs_record_by_bit(void *base, void *top, int bit)
2061 {
2062 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2063 void *at;
2064 u64 pebs_status;
2065
2066 /*
2067 * fmt0 does not have a status bitfield (does not use
2068 * perf_record_nhm format)
2069 */
2070 if (x86_pmu.intel_cap.pebs_format < 1)
2071 return base;
2072
2073 if (base == NULL)
2074 return NULL;
2075
2076 for (at = base; at < top; at += cpuc->pebs_record_size) {
2077 unsigned long status = get_pebs_status(at);
2078
2079 if (test_bit(bit, (unsigned long *)&status)) {
2080 /* PEBS v3 has accurate status bits */
2081 if (x86_pmu.intel_cap.pebs_format >= 3)
2082 return at;
2083
2084 if (status == (1 << bit))
2085 return at;
2086
2087 /* clear non-PEBS bit and re-check */
2088 pebs_status = status & cpuc->pebs_enabled;
2089 pebs_status &= PEBS_COUNTER_MASK;
2090 if (pebs_status == (1 << bit))
2091 return at;
2092 }
2093 }
2094 return NULL;
2095 }
2096
intel_pmu_auto_reload_read(struct perf_event * event)2097 void intel_pmu_auto_reload_read(struct perf_event *event)
2098 {
2099 WARN_ON(!(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD));
2100
2101 perf_pmu_disable(event->pmu);
2102 intel_pmu_drain_pebs_buffer();
2103 perf_pmu_enable(event->pmu);
2104 }
2105
2106 /*
2107 * Special variant of intel_pmu_save_and_restart() for auto-reload.
2108 */
2109 static int
intel_pmu_save_and_restart_reload(struct perf_event * event,int count)2110 intel_pmu_save_and_restart_reload(struct perf_event *event, int count)
2111 {
2112 struct hw_perf_event *hwc = &event->hw;
2113 int shift = 64 - x86_pmu.cntval_bits;
2114 u64 period = hwc->sample_period;
2115 u64 prev_raw_count, new_raw_count;
2116 s64 new, old;
2117
2118 WARN_ON(!period);
2119
2120 /*
2121 * drain_pebs() only happens when the PMU is disabled.
2122 */
2123 WARN_ON(this_cpu_read(cpu_hw_events.enabled));
2124
2125 prev_raw_count = local64_read(&hwc->prev_count);
2126 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
2127 local64_set(&hwc->prev_count, new_raw_count);
2128
2129 /*
2130 * Since the counter increments a negative counter value and
2131 * overflows on the sign switch, giving the interval:
2132 *
2133 * [-period, 0]
2134 *
2135 * the difference between two consecutive reads is:
2136 *
2137 * A) value2 - value1;
2138 * when no overflows have happened in between,
2139 *
2140 * B) (0 - value1) + (value2 - (-period));
2141 * when one overflow happened in between,
2142 *
2143 * C) (0 - value1) + (n - 1) * (period) + (value2 - (-period));
2144 * when @n overflows happened in between.
2145 *
2146 * Here A) is the obvious difference, B) is the extension to the
2147 * discrete interval, where the first term is to the top of the
2148 * interval and the second term is from the bottom of the next
2149 * interval and C) the extension to multiple intervals, where the
2150 * middle term is the whole intervals covered.
2151 *
2152 * An equivalent of C, by reduction, is:
2153 *
2154 * value2 - value1 + n * period
2155 */
2156 new = ((s64)(new_raw_count << shift) >> shift);
2157 old = ((s64)(prev_raw_count << shift) >> shift);
2158 local64_add(new - old + count * period, &event->count);
2159
2160 local64_set(&hwc->period_left, -new);
2161
2162 perf_event_update_userpage(event);
2163
2164 return 0;
2165 }
2166
2167 typedef void (*setup_fn)(struct perf_event *, struct pt_regs *, void *,
2168 struct perf_sample_data *, struct pt_regs *);
2169
2170 static struct pt_regs dummy_iregs;
2171
2172 static __always_inline void
__intel_pmu_pebs_event(struct perf_event * event,struct pt_regs * iregs,struct pt_regs * regs,struct perf_sample_data * data,void * at,setup_fn setup_sample)2173 __intel_pmu_pebs_event(struct perf_event *event,
2174 struct pt_regs *iregs,
2175 struct pt_regs *regs,
2176 struct perf_sample_data *data,
2177 void *at,
2178 setup_fn setup_sample)
2179 {
2180 setup_sample(event, iregs, at, data, regs);
2181 perf_event_output(event, data, regs);
2182 }
2183
2184 static __always_inline void
__intel_pmu_pebs_last_event(struct perf_event * event,struct pt_regs * iregs,struct pt_regs * regs,struct perf_sample_data * data,void * at,int count,setup_fn setup_sample)2185 __intel_pmu_pebs_last_event(struct perf_event *event,
2186 struct pt_regs *iregs,
2187 struct pt_regs *regs,
2188 struct perf_sample_data *data,
2189 void *at,
2190 int count,
2191 setup_fn setup_sample)
2192 {
2193 struct hw_perf_event *hwc = &event->hw;
2194
2195 setup_sample(event, iregs, at, data, regs);
2196 if (iregs == &dummy_iregs) {
2197 /*
2198 * The PEBS records may be drained in the non-overflow context,
2199 * e.g., large PEBS + context switch. Perf should treat the
2200 * last record the same as other PEBS records, and doesn't
2201 * invoke the generic overflow handler.
2202 */
2203 perf_event_output(event, data, regs);
2204 } else {
2205 /*
2206 * All but the last records are processed.
2207 * The last one is left to be able to call the overflow handler.
2208 */
2209 if (perf_event_overflow(event, data, regs))
2210 x86_pmu_stop(event, 0);
2211 }
2212
2213 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
2214 /*
2215 * Now, auto-reload is only enabled in fixed period mode.
2216 * The reload value is always hwc->sample_period.
2217 * May need to change it, if auto-reload is enabled in
2218 * freq mode later.
2219 */
2220 intel_pmu_save_and_restart_reload(event, count);
2221 } else
2222 intel_pmu_save_and_restart(event);
2223 }
2224
2225 static __always_inline void
__intel_pmu_pebs_events(struct perf_event * event,struct pt_regs * iregs,struct perf_sample_data * data,void * base,void * top,int bit,int count,setup_fn setup_sample)2226 __intel_pmu_pebs_events(struct perf_event *event,
2227 struct pt_regs *iregs,
2228 struct perf_sample_data *data,
2229 void *base, void *top,
2230 int bit, int count,
2231 setup_fn setup_sample)
2232 {
2233 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2234 struct x86_perf_regs perf_regs;
2235 struct pt_regs *regs = &perf_regs.regs;
2236 void *at = get_next_pebs_record_by_bit(base, top, bit);
2237 int cnt = count;
2238
2239 if (!iregs)
2240 iregs = &dummy_iregs;
2241
2242 while (cnt > 1) {
2243 __intel_pmu_pebs_event(event, iregs, regs, data, at, setup_sample);
2244 at += cpuc->pebs_record_size;
2245 at = get_next_pebs_record_by_bit(at, top, bit);
2246 cnt--;
2247 }
2248
2249 __intel_pmu_pebs_last_event(event, iregs, regs, data, at, count, setup_sample);
2250 }
2251
intel_pmu_drain_pebs_core(struct pt_regs * iregs,struct perf_sample_data * data)2252 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs, struct perf_sample_data *data)
2253 {
2254 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2255 struct debug_store *ds = cpuc->ds;
2256 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
2257 struct pebs_record_core *at, *top;
2258 int n;
2259
2260 if (!x86_pmu.pebs_active)
2261 return;
2262
2263 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
2264 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
2265
2266 /*
2267 * Whatever else happens, drain the thing
2268 */
2269 ds->pebs_index = ds->pebs_buffer_base;
2270
2271 if (!test_bit(0, cpuc->active_mask))
2272 return;
2273
2274 WARN_ON_ONCE(!event);
2275
2276 if (!event->attr.precise_ip)
2277 return;
2278
2279 n = top - at;
2280 if (n <= 0) {
2281 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2282 intel_pmu_save_and_restart_reload(event, 0);
2283 return;
2284 }
2285
2286 __intel_pmu_pebs_events(event, iregs, data, at, top, 0, n,
2287 setup_pebs_fixed_sample_data);
2288 }
2289
intel_pmu_pebs_event_update_no_drain(struct cpu_hw_events * cpuc,int size)2290 static void intel_pmu_pebs_event_update_no_drain(struct cpu_hw_events *cpuc, int size)
2291 {
2292 struct perf_event *event;
2293 int bit;
2294
2295 /*
2296 * The drain_pebs() could be called twice in a short period
2297 * for auto-reload event in pmu::read(). There are no
2298 * overflows have happened in between.
2299 * It needs to call intel_pmu_save_and_restart_reload() to
2300 * update the event->count for this case.
2301 */
2302 for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled, size) {
2303 event = cpuc->events[bit];
2304 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2305 intel_pmu_save_and_restart_reload(event, 0);
2306 }
2307 }
2308
intel_pmu_drain_pebs_nhm(struct pt_regs * iregs,struct perf_sample_data * data)2309 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_data *data)
2310 {
2311 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2312 struct debug_store *ds = cpuc->ds;
2313 struct perf_event *event;
2314 void *base, *at, *top;
2315 short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
2316 short error[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
2317 int max_pebs_events = intel_pmu_max_num_pebs(NULL);
2318 int bit, i, size;
2319 u64 mask;
2320
2321 if (!x86_pmu.pebs_active)
2322 return;
2323
2324 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
2325 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
2326
2327 ds->pebs_index = ds->pebs_buffer_base;
2328
2329 mask = x86_pmu.pebs_events_mask;
2330 size = max_pebs_events;
2331 if (x86_pmu.flags & PMU_FL_PEBS_ALL) {
2332 mask |= x86_pmu.fixed_cntr_mask64 << INTEL_PMC_IDX_FIXED;
2333 size = INTEL_PMC_IDX_FIXED + x86_pmu_max_num_counters_fixed(NULL);
2334 }
2335
2336 if (unlikely(base >= top)) {
2337 intel_pmu_pebs_event_update_no_drain(cpuc, size);
2338 return;
2339 }
2340
2341 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
2342 struct pebs_record_nhm *p = at;
2343 u64 pebs_status;
2344
2345 pebs_status = p->status & cpuc->pebs_enabled;
2346 pebs_status &= mask;
2347
2348 /* PEBS v3 has more accurate status bits */
2349 if (x86_pmu.intel_cap.pebs_format >= 3) {
2350 for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
2351 counts[bit]++;
2352
2353 continue;
2354 }
2355
2356 /*
2357 * On some CPUs the PEBS status can be zero when PEBS is
2358 * racing with clearing of GLOBAL_STATUS.
2359 *
2360 * Normally we would drop that record, but in the
2361 * case when there is only a single active PEBS event
2362 * we can assume it's for that event.
2363 */
2364 if (!pebs_status && cpuc->pebs_enabled &&
2365 !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))
2366 pebs_status = p->status = cpuc->pebs_enabled;
2367
2368 bit = find_first_bit((unsigned long *)&pebs_status,
2369 max_pebs_events);
2370
2371 if (!(x86_pmu.pebs_events_mask & (1 << bit)))
2372 continue;
2373
2374 /*
2375 * The PEBS hardware does not deal well with the situation
2376 * when events happen near to each other and multiple bits
2377 * are set. But it should happen rarely.
2378 *
2379 * If these events include one PEBS and multiple non-PEBS
2380 * events, it doesn't impact PEBS record. The record will
2381 * be handled normally. (slow path)
2382 *
2383 * If these events include two or more PEBS events, the
2384 * records for the events can be collapsed into a single
2385 * one, and it's not possible to reconstruct all events
2386 * that caused the PEBS record. It's called collision.
2387 * If collision happened, the record will be dropped.
2388 */
2389 if (pebs_status != (1ULL << bit)) {
2390 for_each_set_bit(i, (unsigned long *)&pebs_status, size)
2391 error[i]++;
2392 continue;
2393 }
2394
2395 counts[bit]++;
2396 }
2397
2398 for_each_set_bit(bit, (unsigned long *)&mask, size) {
2399 if ((counts[bit] == 0) && (error[bit] == 0))
2400 continue;
2401
2402 event = cpuc->events[bit];
2403 if (WARN_ON_ONCE(!event))
2404 continue;
2405
2406 if (WARN_ON_ONCE(!event->attr.precise_ip))
2407 continue;
2408
2409 /* log dropped samples number */
2410 if (error[bit]) {
2411 perf_log_lost_samples(event, error[bit]);
2412
2413 if (iregs && perf_event_account_interrupt(event))
2414 x86_pmu_stop(event, 0);
2415 }
2416
2417 if (counts[bit]) {
2418 __intel_pmu_pebs_events(event, iregs, data, base,
2419 top, bit, counts[bit],
2420 setup_pebs_fixed_sample_data);
2421 }
2422 }
2423 }
2424
intel_pmu_drain_pebs_icl(struct pt_regs * iregs,struct perf_sample_data * data)2425 static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_data *data)
2426 {
2427 short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
2428 void *last[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS];
2429 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2430 struct debug_store *ds = cpuc->ds;
2431 struct x86_perf_regs perf_regs;
2432 struct pt_regs *regs = &perf_regs.regs;
2433 struct pebs_basic *basic;
2434 struct perf_event *event;
2435 void *base, *at, *top;
2436 int bit;
2437 u64 mask;
2438
2439 if (!x86_pmu.pebs_active)
2440 return;
2441
2442 base = (struct pebs_basic *)(unsigned long)ds->pebs_buffer_base;
2443 top = (struct pebs_basic *)(unsigned long)ds->pebs_index;
2444
2445 ds->pebs_index = ds->pebs_buffer_base;
2446
2447 mask = hybrid(cpuc->pmu, pebs_events_mask) |
2448 (hybrid(cpuc->pmu, fixed_cntr_mask64) << INTEL_PMC_IDX_FIXED);
2449
2450 if (unlikely(base >= top)) {
2451 intel_pmu_pebs_event_update_no_drain(cpuc, X86_PMC_IDX_MAX);
2452 return;
2453 }
2454
2455 if (!iregs)
2456 iregs = &dummy_iregs;
2457
2458 /* Process all but the last event for each counter. */
2459 for (at = base; at < top; at += basic->format_size) {
2460 u64 pebs_status;
2461
2462 basic = at;
2463 if (basic->format_size != cpuc->pebs_record_size)
2464 continue;
2465
2466 pebs_status = basic->applicable_counters & cpuc->pebs_enabled & mask;
2467 for_each_set_bit(bit, (unsigned long *)&pebs_status, X86_PMC_IDX_MAX) {
2468 event = cpuc->events[bit];
2469
2470 if (WARN_ON_ONCE(!event) ||
2471 WARN_ON_ONCE(!event->attr.precise_ip))
2472 continue;
2473
2474 if (counts[bit]++) {
2475 __intel_pmu_pebs_event(event, iregs, regs, data, last[bit],
2476 setup_pebs_adaptive_sample_data);
2477 }
2478 last[bit] = at;
2479 }
2480 }
2481
2482 for_each_set_bit(bit, (unsigned long *)&mask, X86_PMC_IDX_MAX) {
2483 if (!counts[bit])
2484 continue;
2485
2486 event = cpuc->events[bit];
2487
2488 __intel_pmu_pebs_last_event(event, iregs, regs, data, last[bit],
2489 counts[bit], setup_pebs_adaptive_sample_data);
2490 }
2491 }
2492
2493 /*
2494 * BTS, PEBS probe and setup
2495 */
2496
intel_ds_init(void)2497 void __init intel_ds_init(void)
2498 {
2499 /*
2500 * No support for 32bit formats
2501 */
2502 if (!boot_cpu_has(X86_FEATURE_DTES64))
2503 return;
2504
2505 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
2506 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
2507 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
2508 if (x86_pmu.version <= 4)
2509 x86_pmu.pebs_no_isolation = 1;
2510
2511 if (x86_pmu.pebs) {
2512 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
2513 char *pebs_qual = "";
2514 int format = x86_pmu.intel_cap.pebs_format;
2515
2516 if (format < 4)
2517 x86_pmu.intel_cap.pebs_baseline = 0;
2518
2519 switch (format) {
2520 case 0:
2521 pr_cont("PEBS fmt0%c, ", pebs_type);
2522 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
2523 /*
2524 * Using >PAGE_SIZE buffers makes the WRMSR to
2525 * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
2526 * mysteriously hang on Core2.
2527 *
2528 * As a workaround, we don't do this.
2529 */
2530 x86_pmu.pebs_buffer_size = PAGE_SIZE;
2531 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
2532 break;
2533
2534 case 1:
2535 pr_cont("PEBS fmt1%c, ", pebs_type);
2536 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
2537 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2538 break;
2539
2540 case 2:
2541 pr_cont("PEBS fmt2%c, ", pebs_type);
2542 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
2543 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2544 break;
2545
2546 case 3:
2547 pr_cont("PEBS fmt3%c, ", pebs_type);
2548 x86_pmu.pebs_record_size =
2549 sizeof(struct pebs_record_skl);
2550 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2551 x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
2552 break;
2553
2554 case 6:
2555 case 5:
2556 x86_pmu.pebs_ept = 1;
2557 fallthrough;
2558 case 4:
2559 x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl;
2560 x86_pmu.pebs_record_size = sizeof(struct pebs_basic);
2561 if (x86_pmu.intel_cap.pebs_baseline) {
2562 x86_pmu.large_pebs_flags |=
2563 PERF_SAMPLE_BRANCH_STACK |
2564 PERF_SAMPLE_TIME;
2565 x86_pmu.flags |= PMU_FL_PEBS_ALL;
2566 x86_pmu.pebs_capable = ~0ULL;
2567 pebs_qual = "-baseline";
2568 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
2569 } else {
2570 /* Only basic record supported */
2571 x86_pmu.large_pebs_flags &=
2572 ~(PERF_SAMPLE_ADDR |
2573 PERF_SAMPLE_TIME |
2574 PERF_SAMPLE_DATA_SRC |
2575 PERF_SAMPLE_TRANSACTION |
2576 PERF_SAMPLE_REGS_USER |
2577 PERF_SAMPLE_REGS_INTR);
2578 }
2579 pr_cont("PEBS fmt4%c%s, ", pebs_type, pebs_qual);
2580
2581 /*
2582 * The PEBS-via-PT is not supported on hybrid platforms,
2583 * because not all CPUs of a hybrid machine support it.
2584 * The global x86_pmu.intel_cap, which only contains the
2585 * common capabilities, is used to check the availability
2586 * of the feature. The per-PMU pebs_output_pt_available
2587 * in a hybrid machine should be ignored.
2588 */
2589 if (x86_pmu.intel_cap.pebs_output_pt_available) {
2590 pr_cont("PEBS-via-PT, ");
2591 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_AUX_OUTPUT;
2592 }
2593
2594 break;
2595
2596 default:
2597 pr_cont("no PEBS fmt%d%c, ", format, pebs_type);
2598 x86_pmu.pebs = 0;
2599 }
2600 }
2601 }
2602
perf_restore_debug_store(void)2603 void perf_restore_debug_store(void)
2604 {
2605 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2606
2607 if (!x86_pmu.bts && !x86_pmu.pebs)
2608 return;
2609
2610 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
2611 }
2612