1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * rt5645.c -- RT5645 ALSA SoC audio codec driver
4 *
5 * Copyright 2013 Realtek Semiconductor Corp.
6 * Author: Bard Liao <bardliao@realtek.com>
7 */
8
9 #include <linux/cleanup.h>
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
14 #include <linux/pm.h>
15 #include <linux/i2c.h>
16 #include <linux/platform_device.h>
17 #include <linux/spi/spi.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/acpi.h>
20 #include <linux/dmi.h>
21 #include <linux/regulator/consumer.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/jack.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30
31 #include "rl6231.h"
32 #include "rt5645.h"
33
34 #define QUIRK_INV_JD1_1(q) ((q) & 1)
35 #define QUIRK_LEVEL_IRQ(q) (((q) >> 1) & 1)
36 #define QUIRK_IN2_DIFF(q) (((q) >> 2) & 1)
37 #define QUIRK_INV_HP_POL(q) (((q) >> 3) & 1)
38 #define QUIRK_JD_MODE(q) (((q) >> 4) & 7)
39 #define QUIRK_DMIC1_DATA_PIN(q) (((q) >> 8) & 3)
40 #define QUIRK_DMIC2_DATA_PIN(q) (((q) >> 12) & 3)
41
42 static unsigned int quirk = -1;
43 module_param(quirk, uint, 0444);
44 MODULE_PARM_DESC(quirk, "RT5645 pdata quirk override");
45
46 static const struct acpi_gpio_mapping *cht_rt5645_gpios;
47
48 #define RT5645_DEVICE_ID 0x6308
49 #define RT5650_DEVICE_ID 0x6419
50
51 #define RT5645_PR_RANGE_BASE (0xff + 1)
52 #define RT5645_PR_SPACING 0x100
53
54 #define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
55
56 #define RT5645_HWEQ_NUM 57
57
58 #define TIME_TO_POWER_MS 400
59
60 static const struct regmap_range_cfg rt5645_ranges[] = {
61 {
62 .name = "PR",
63 .range_min = RT5645_PR_BASE,
64 .range_max = RT5645_PR_BASE + 0xf8,
65 .selector_reg = RT5645_PRIV_INDEX,
66 .selector_mask = 0xff,
67 .selector_shift = 0x0,
68 .window_start = RT5645_PRIV_DATA,
69 .window_len = 0x1,
70 },
71 };
72
73 static const struct reg_sequence init_list[] = {
74 {RT5645_PR_BASE + 0x3d, 0x3600},
75 {RT5645_PR_BASE + 0x1c, 0xfd70},
76 {RT5645_PR_BASE + 0x20, 0x611f},
77 {RT5645_PR_BASE + 0x21, 0x4040},
78 {RT5645_PR_BASE + 0x23, 0x0004},
79 {RT5645_ASRC_4, 0x0120},
80 };
81
82 static const struct reg_sequence rt5650_init_list[] = {
83 {0xf6, 0x0100},
84 {RT5645_PWR_ANLG1, 0x02},
85 {RT5645_IL_CMD3, 0x6728},
86 {RT5645_PR_BASE + 0x3a, 0x0000},
87 {RT5645_CLSD_OUT_CTRL1, 0x4059},
88 {RT5645_GEN_CTRL3, 0x0200},
89 };
90
91 static const struct reg_default rt5645_reg[] = {
92 { 0x00, 0x0000 },
93 { 0x01, 0xc8c8 },
94 { 0x02, 0xc8c8 },
95 { 0x03, 0xc8c8 },
96 { 0x0a, 0x0002 },
97 { 0x0b, 0x2827 },
98 { 0x0c, 0xe000 },
99 { 0x0d, 0x0000 },
100 { 0x0e, 0x0000 },
101 { 0x0f, 0x0808 },
102 { 0x14, 0x3333 },
103 { 0x16, 0x4b00 },
104 { 0x18, 0x018b },
105 { 0x19, 0xafaf },
106 { 0x1a, 0xafaf },
107 { 0x1b, 0x0001 },
108 { 0x1c, 0x2f2f },
109 { 0x1d, 0x2f2f },
110 { 0x1e, 0x0000 },
111 { 0x20, 0x0000 },
112 { 0x27, 0x7060 },
113 { 0x28, 0x7070 },
114 { 0x29, 0x8080 },
115 { 0x2a, 0x5656 },
116 { 0x2b, 0x5454 },
117 { 0x2c, 0xaaa0 },
118 { 0x2d, 0x0000 },
119 { 0x2f, 0x1002 },
120 { 0x31, 0x5000 },
121 { 0x32, 0x0000 },
122 { 0x33, 0x0000 },
123 { 0x34, 0x0000 },
124 { 0x35, 0x0000 },
125 { 0x3b, 0x0000 },
126 { 0x3c, 0x007f },
127 { 0x3d, 0x0000 },
128 { 0x3e, 0x007f },
129 { 0x3f, 0x0000 },
130 { 0x40, 0x001f },
131 { 0x41, 0x0000 },
132 { 0x42, 0x001f },
133 { 0x45, 0x6000 },
134 { 0x46, 0x003e },
135 { 0x47, 0x003e },
136 { 0x48, 0xf807 },
137 { 0x4a, 0x0004 },
138 { 0x4d, 0x0000 },
139 { 0x4e, 0x0000 },
140 { 0x4f, 0x01ff },
141 { 0x50, 0x0000 },
142 { 0x51, 0x0000 },
143 { 0x52, 0x01ff },
144 { 0x53, 0xf000 },
145 { 0x56, 0x0111 },
146 { 0x57, 0x0064 },
147 { 0x58, 0xef0e },
148 { 0x59, 0xf0f0 },
149 { 0x5a, 0xef0e },
150 { 0x5b, 0xf0f0 },
151 { 0x5c, 0xef0e },
152 { 0x5d, 0xf0f0 },
153 { 0x5e, 0xf000 },
154 { 0x5f, 0x0000 },
155 { 0x61, 0x0300 },
156 { 0x62, 0x0000 },
157 { 0x63, 0x00c2 },
158 { 0x64, 0x0000 },
159 { 0x65, 0x0000 },
160 { 0x66, 0x0000 },
161 { 0x6a, 0x0000 },
162 { 0x6c, 0x0aaa },
163 { 0x70, 0x8000 },
164 { 0x71, 0x8000 },
165 { 0x72, 0x8000 },
166 { 0x73, 0x7770 },
167 { 0x74, 0x3e00 },
168 { 0x75, 0x2409 },
169 { 0x76, 0x000a },
170 { 0x77, 0x0c00 },
171 { 0x78, 0x0000 },
172 { 0x79, 0x0123 },
173 { 0x80, 0x0000 },
174 { 0x81, 0x0000 },
175 { 0x82, 0x0000 },
176 { 0x83, 0x0000 },
177 { 0x84, 0x0000 },
178 { 0x85, 0x0000 },
179 { 0x8a, 0x0120 },
180 { 0x8e, 0x0004 },
181 { 0x8f, 0x1100 },
182 { 0x90, 0x0646 },
183 { 0x91, 0x0c06 },
184 { 0x93, 0x0000 },
185 { 0x94, 0x0200 },
186 { 0x95, 0x0000 },
187 { 0x9a, 0x2184 },
188 { 0x9b, 0x010a },
189 { 0x9c, 0x0aea },
190 { 0x9d, 0x000c },
191 { 0x9e, 0x0400 },
192 { 0xa0, 0xa0a8 },
193 { 0xa1, 0x0059 },
194 { 0xa2, 0x0001 },
195 { 0xae, 0x6000 },
196 { 0xaf, 0x0000 },
197 { 0xb0, 0x6000 },
198 { 0xb1, 0x0000 },
199 { 0xb2, 0x0000 },
200 { 0xb3, 0x001f },
201 { 0xb4, 0x020c },
202 { 0xb5, 0x1f00 },
203 { 0xb6, 0x0000 },
204 { 0xbb, 0x0000 },
205 { 0xbc, 0x0000 },
206 { 0xbd, 0x0000 },
207 { 0xbe, 0x0000 },
208 { 0xbf, 0x3100 },
209 { 0xc0, 0x0000 },
210 { 0xc1, 0x0000 },
211 { 0xc2, 0x0000 },
212 { 0xc3, 0x2000 },
213 { 0xcd, 0x0000 },
214 { 0xce, 0x0000 },
215 { 0xcf, 0x1813 },
216 { 0xd0, 0x0690 },
217 { 0xd1, 0x1c17 },
218 { 0xd3, 0xb320 },
219 { 0xd4, 0x0000 },
220 { 0xd6, 0x0400 },
221 { 0xd9, 0x0809 },
222 { 0xda, 0x0000 },
223 { 0xdb, 0x0003 },
224 { 0xdc, 0x0049 },
225 { 0xdd, 0x001b },
226 { 0xdf, 0x0008 },
227 { 0xe0, 0x4000 },
228 { 0xe6, 0x8000 },
229 { 0xe7, 0x0200 },
230 { 0xec, 0xb300 },
231 { 0xed, 0x0000 },
232 { 0xf0, 0x001f },
233 { 0xf1, 0x020c },
234 { 0xf2, 0x1f00 },
235 { 0xf3, 0x0000 },
236 { 0xf4, 0x4000 },
237 { 0xf8, 0x0000 },
238 { 0xf9, 0x0000 },
239 { 0xfa, 0x2060 },
240 { 0xfb, 0x4040 },
241 { 0xfc, 0x0000 },
242 { 0xfd, 0x0002 },
243 { 0xfe, 0x10ec },
244 { 0xff, 0x6308 },
245 };
246
247 static const struct reg_default rt5650_reg[] = {
248 { 0x00, 0x0000 },
249 { 0x01, 0xc8c8 },
250 { 0x02, 0xc8c8 },
251 { 0x03, 0xc8c8 },
252 { 0x0a, 0x0002 },
253 { 0x0b, 0x2827 },
254 { 0x0c, 0xe000 },
255 { 0x0d, 0x0000 },
256 { 0x0e, 0x0000 },
257 { 0x0f, 0x0808 },
258 { 0x14, 0x3333 },
259 { 0x16, 0x4b00 },
260 { 0x18, 0x018b },
261 { 0x19, 0xafaf },
262 { 0x1a, 0xafaf },
263 { 0x1b, 0x0001 },
264 { 0x1c, 0x2f2f },
265 { 0x1d, 0x2f2f },
266 { 0x1e, 0x0000 },
267 { 0x20, 0x0000 },
268 { 0x27, 0x7060 },
269 { 0x28, 0x7070 },
270 { 0x29, 0x8080 },
271 { 0x2a, 0x5656 },
272 { 0x2b, 0x5454 },
273 { 0x2c, 0xaaa0 },
274 { 0x2d, 0x0000 },
275 { 0x2f, 0x5002 },
276 { 0x31, 0x5000 },
277 { 0x32, 0x0000 },
278 { 0x33, 0x0000 },
279 { 0x34, 0x0000 },
280 { 0x35, 0x0000 },
281 { 0x3b, 0x0000 },
282 { 0x3c, 0x007f },
283 { 0x3d, 0x0000 },
284 { 0x3e, 0x007f },
285 { 0x3f, 0x0000 },
286 { 0x40, 0x001f },
287 { 0x41, 0x0000 },
288 { 0x42, 0x001f },
289 { 0x45, 0x6000 },
290 { 0x46, 0x003e },
291 { 0x47, 0x003e },
292 { 0x48, 0xf807 },
293 { 0x4a, 0x0004 },
294 { 0x4d, 0x0000 },
295 { 0x4e, 0x0000 },
296 { 0x4f, 0x01ff },
297 { 0x50, 0x0000 },
298 { 0x51, 0x0000 },
299 { 0x52, 0x01ff },
300 { 0x53, 0xf000 },
301 { 0x56, 0x0111 },
302 { 0x57, 0x0064 },
303 { 0x58, 0xef0e },
304 { 0x59, 0xf0f0 },
305 { 0x5a, 0xef0e },
306 { 0x5b, 0xf0f0 },
307 { 0x5c, 0xef0e },
308 { 0x5d, 0xf0f0 },
309 { 0x5e, 0xf000 },
310 { 0x5f, 0x0000 },
311 { 0x61, 0x0300 },
312 { 0x62, 0x0000 },
313 { 0x63, 0x00c2 },
314 { 0x64, 0x0000 },
315 { 0x65, 0x0000 },
316 { 0x66, 0x0000 },
317 { 0x6a, 0x0000 },
318 { 0x6c, 0x0aaa },
319 { 0x70, 0x8000 },
320 { 0x71, 0x8000 },
321 { 0x72, 0x8000 },
322 { 0x73, 0x7770 },
323 { 0x74, 0x3e00 },
324 { 0x75, 0x2409 },
325 { 0x76, 0x000a },
326 { 0x77, 0x0c00 },
327 { 0x78, 0x0000 },
328 { 0x79, 0x0123 },
329 { 0x7a, 0x0123 },
330 { 0x80, 0x0000 },
331 { 0x81, 0x0000 },
332 { 0x82, 0x0000 },
333 { 0x83, 0x0000 },
334 { 0x84, 0x0000 },
335 { 0x85, 0x0000 },
336 { 0x8a, 0x0120 },
337 { 0x8e, 0x0004 },
338 { 0x8f, 0x1100 },
339 { 0x90, 0x0646 },
340 { 0x91, 0x0c06 },
341 { 0x93, 0x0000 },
342 { 0x94, 0x0200 },
343 { 0x95, 0x0000 },
344 { 0x9a, 0x2184 },
345 { 0x9b, 0x010a },
346 { 0x9c, 0x0aea },
347 { 0x9d, 0x000c },
348 { 0x9e, 0x0400 },
349 { 0xa0, 0xa0a8 },
350 { 0xa1, 0x0059 },
351 { 0xa2, 0x0001 },
352 { 0xae, 0x6000 },
353 { 0xaf, 0x0000 },
354 { 0xb0, 0x6000 },
355 { 0xb1, 0x0000 },
356 { 0xb2, 0x0000 },
357 { 0xb3, 0x001f },
358 { 0xb4, 0x020c },
359 { 0xb5, 0x1f00 },
360 { 0xb6, 0x0000 },
361 { 0xbb, 0x0000 },
362 { 0xbc, 0x0000 },
363 { 0xbd, 0x0000 },
364 { 0xbe, 0x0000 },
365 { 0xbf, 0x3100 },
366 { 0xc0, 0x0000 },
367 { 0xc1, 0x0000 },
368 { 0xc2, 0x0000 },
369 { 0xc3, 0x2000 },
370 { 0xcd, 0x0000 },
371 { 0xce, 0x0000 },
372 { 0xcf, 0x1813 },
373 { 0xd0, 0x0690 },
374 { 0xd1, 0x1c17 },
375 { 0xd3, 0xb320 },
376 { 0xd4, 0x0000 },
377 { 0xd6, 0x0400 },
378 { 0xd9, 0x0809 },
379 { 0xda, 0x0000 },
380 { 0xdb, 0x0003 },
381 { 0xdc, 0x0049 },
382 { 0xdd, 0x001b },
383 { 0xdf, 0x0008 },
384 { 0xe0, 0x4000 },
385 { 0xe6, 0x8000 },
386 { 0xe7, 0x0200 },
387 { 0xec, 0xb300 },
388 { 0xed, 0x0000 },
389 { 0xf0, 0x001f },
390 { 0xf1, 0x020c },
391 { 0xf2, 0x1f00 },
392 { 0xf3, 0x0000 },
393 { 0xf4, 0x4000 },
394 { 0xf8, 0x0000 },
395 { 0xf9, 0x0000 },
396 { 0xfa, 0x2060 },
397 { 0xfb, 0x4040 },
398 { 0xfc, 0x0000 },
399 { 0xfd, 0x0002 },
400 { 0xfe, 0x10ec },
401 { 0xff, 0x6308 },
402 };
403
404 struct rt5645_eq_param_s {
405 unsigned short reg;
406 unsigned short val;
407 };
408
409 struct rt5645_eq_param_s_be16 {
410 __be16 reg;
411 __be16 val;
412 };
413
414 static const char *const rt5645_supply_names[] = {
415 "avdd",
416 "cpvdd",
417 };
418
419 struct rt5645_platform_data {
420 /* IN2 can optionally be differential */
421 bool in2_diff;
422
423 unsigned int dmic1_data_pin;
424 /* 0 = IN2N; 1 = GPIO5; 2 = GPIO11 */
425 unsigned int dmic2_data_pin;
426 /* 0 = IN2P; 1 = GPIO6; 2 = GPIO10; 3 = GPIO12 */
427
428 unsigned int jd_mode;
429 /* Use level triggered irq */
430 bool level_trigger_irq;
431 /* Invert JD1_1 status polarity */
432 bool inv_jd1_1;
433 /* Invert HP detect status polarity */
434 bool inv_hp_pol;
435
436 /* Only 1 speaker connected */
437 bool mono_speaker;
438
439 /* Value to assign to snd_soc_card.long_name */
440 const char *long_name;
441
442 /* Some (package) variants have the headset-mic pin not-connected */
443 bool no_headset_mic;
444 };
445
446 struct rt5645_priv {
447 struct snd_soc_component *component;
448 struct rt5645_platform_data pdata;
449 struct regmap *regmap;
450 struct i2c_client *i2c;
451 struct gpio_desc *gpiod_hp_det;
452 struct gpio_desc *gpiod_cbj_sleeve;
453 struct snd_soc_jack *hp_jack;
454 struct snd_soc_jack *mic_jack;
455 struct snd_soc_jack *btn_jack;
456 struct delayed_work jack_detect_work, rcclock_work;
457 struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)];
458 struct rt5645_eq_param_s *eq_param;
459 struct timer_list btn_check_timer;
460 struct mutex jd_mutex;
461
462 int codec_type;
463 int sysclk;
464 int sysclk_src;
465 int lrck[RT5645_AIFS];
466 int bclk[RT5645_AIFS];
467 int master[RT5645_AIFS];
468
469 int pll_src;
470 int pll_in;
471 int pll_out;
472
473 int jack_type;
474 bool en_button_func;
475 int v_id;
476 };
477
rt5645_reset(struct snd_soc_component * component)478 static int rt5645_reset(struct snd_soc_component *component)
479 {
480 return snd_soc_component_write(component, RT5645_RESET, 0);
481 }
482
rt5645_volatile_register(struct device * dev,unsigned int reg)483 static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
484 {
485 int i;
486
487 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
488 if (reg >= rt5645_ranges[i].range_min &&
489 reg <= rt5645_ranges[i].range_max) {
490 return true;
491 }
492 }
493
494 switch (reg) {
495 case RT5645_RESET:
496 case RT5645_PRIV_INDEX:
497 case RT5645_PRIV_DATA:
498 case RT5645_IN1_CTRL1:
499 case RT5645_IN1_CTRL2:
500 case RT5645_IN1_CTRL3:
501 case RT5645_A_JD_CTRL1:
502 case RT5645_ADC_EQ_CTRL1:
503 case RT5645_EQ_CTRL1:
504 case RT5645_ALC_CTRL_1:
505 case RT5645_IRQ_CTRL2:
506 case RT5645_IRQ_CTRL3:
507 case RT5645_INT_IRQ_ST:
508 case RT5645_IL_CMD:
509 case RT5650_4BTN_IL_CMD1:
510 case RT5645_VENDOR_ID:
511 case RT5645_VENDOR_ID1:
512 case RT5645_VENDOR_ID2:
513 return true;
514 default:
515 return false;
516 }
517 }
518
rt5645_readable_register(struct device * dev,unsigned int reg)519 static bool rt5645_readable_register(struct device *dev, unsigned int reg)
520 {
521 int i;
522
523 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
524 if (reg >= rt5645_ranges[i].range_min &&
525 reg <= rt5645_ranges[i].range_max) {
526 return true;
527 }
528 }
529
530 switch (reg) {
531 case RT5645_RESET:
532 case RT5645_SPK_VOL:
533 case RT5645_HP_VOL:
534 case RT5645_LOUT1:
535 case RT5645_IN1_CTRL1:
536 case RT5645_IN1_CTRL2:
537 case RT5645_IN1_CTRL3:
538 case RT5645_IN2_CTRL:
539 case RT5645_INL1_INR1_VOL:
540 case RT5645_SPK_FUNC_LIM:
541 case RT5645_ADJ_HPF_CTRL:
542 case RT5645_DAC1_DIG_VOL:
543 case RT5645_DAC2_DIG_VOL:
544 case RT5645_DAC_CTRL:
545 case RT5645_STO1_ADC_DIG_VOL:
546 case RT5645_MONO_ADC_DIG_VOL:
547 case RT5645_ADC_BST_VOL1:
548 case RT5645_ADC_BST_VOL2:
549 case RT5645_STO1_ADC_MIXER:
550 case RT5645_MONO_ADC_MIXER:
551 case RT5645_AD_DA_MIXER:
552 case RT5645_STO_DAC_MIXER:
553 case RT5645_MONO_DAC_MIXER:
554 case RT5645_DIG_MIXER:
555 case RT5650_A_DAC_SOUR:
556 case RT5645_DIG_INF1_DATA:
557 case RT5645_PDM_OUT_CTRL:
558 case RT5645_REC_L1_MIXER:
559 case RT5645_REC_L2_MIXER:
560 case RT5645_REC_R1_MIXER:
561 case RT5645_REC_R2_MIXER:
562 case RT5645_HPMIXL_CTRL:
563 case RT5645_HPOMIXL_CTRL:
564 case RT5645_HPMIXR_CTRL:
565 case RT5645_HPOMIXR_CTRL:
566 case RT5645_HPO_MIXER:
567 case RT5645_SPK_L_MIXER:
568 case RT5645_SPK_R_MIXER:
569 case RT5645_SPO_MIXER:
570 case RT5645_SPO_CLSD_RATIO:
571 case RT5645_OUT_L1_MIXER:
572 case RT5645_OUT_R1_MIXER:
573 case RT5645_OUT_L_GAIN1:
574 case RT5645_OUT_L_GAIN2:
575 case RT5645_OUT_R_GAIN1:
576 case RT5645_OUT_R_GAIN2:
577 case RT5645_LOUT_MIXER:
578 case RT5645_HAPTIC_CTRL1:
579 case RT5645_HAPTIC_CTRL2:
580 case RT5645_HAPTIC_CTRL3:
581 case RT5645_HAPTIC_CTRL4:
582 case RT5645_HAPTIC_CTRL5:
583 case RT5645_HAPTIC_CTRL6:
584 case RT5645_HAPTIC_CTRL7:
585 case RT5645_HAPTIC_CTRL8:
586 case RT5645_HAPTIC_CTRL9:
587 case RT5645_HAPTIC_CTRL10:
588 case RT5645_PWR_DIG1:
589 case RT5645_PWR_DIG2:
590 case RT5645_PWR_ANLG1:
591 case RT5645_PWR_ANLG2:
592 case RT5645_PWR_MIXER:
593 case RT5645_PWR_VOL:
594 case RT5645_PRIV_INDEX:
595 case RT5645_PRIV_DATA:
596 case RT5645_I2S1_SDP:
597 case RT5645_I2S2_SDP:
598 case RT5645_ADDA_CLK1:
599 case RT5645_ADDA_CLK2:
600 case RT5645_DMIC_CTRL1:
601 case RT5645_DMIC_CTRL2:
602 case RT5645_TDM_CTRL_1:
603 case RT5645_TDM_CTRL_2:
604 case RT5645_TDM_CTRL_3:
605 case RT5650_TDM_CTRL_4:
606 case RT5645_GLB_CLK:
607 case RT5645_PLL_CTRL1:
608 case RT5645_PLL_CTRL2:
609 case RT5645_ASRC_1:
610 case RT5645_ASRC_2:
611 case RT5645_ASRC_3:
612 case RT5645_ASRC_4:
613 case RT5645_DEPOP_M1:
614 case RT5645_DEPOP_M2:
615 case RT5645_DEPOP_M3:
616 case RT5645_CHARGE_PUMP:
617 case RT5645_MICBIAS:
618 case RT5645_A_JD_CTRL1:
619 case RT5645_VAD_CTRL4:
620 case RT5645_CLSD_OUT_CTRL:
621 case RT5645_ADC_EQ_CTRL1:
622 case RT5645_ADC_EQ_CTRL2:
623 case RT5645_EQ_CTRL1:
624 case RT5645_EQ_CTRL2:
625 case RT5645_ALC_CTRL_1:
626 case RT5645_ALC_CTRL_2:
627 case RT5645_ALC_CTRL_3:
628 case RT5645_ALC_CTRL_4:
629 case RT5645_ALC_CTRL_5:
630 case RT5645_JD_CTRL:
631 case RT5645_IRQ_CTRL1:
632 case RT5645_IRQ_CTRL2:
633 case RT5645_IRQ_CTRL3:
634 case RT5645_INT_IRQ_ST:
635 case RT5645_GPIO_CTRL1:
636 case RT5645_GPIO_CTRL2:
637 case RT5645_GPIO_CTRL3:
638 case RT5645_BASS_BACK:
639 case RT5645_MP3_PLUS1:
640 case RT5645_MP3_PLUS2:
641 case RT5645_ADJ_HPF1:
642 case RT5645_ADJ_HPF2:
643 case RT5645_HP_CALIB_AMP_DET:
644 case RT5645_SV_ZCD1:
645 case RT5645_SV_ZCD2:
646 case RT5645_IL_CMD:
647 case RT5645_IL_CMD2:
648 case RT5645_IL_CMD3:
649 case RT5650_4BTN_IL_CMD1:
650 case RT5650_4BTN_IL_CMD2:
651 case RT5645_DRC1_HL_CTRL1:
652 case RT5645_DRC2_HL_CTRL1:
653 case RT5645_ADC_MONO_HP_CTRL1:
654 case RT5645_ADC_MONO_HP_CTRL2:
655 case RT5645_DRC2_CTRL1:
656 case RT5645_DRC2_CTRL2:
657 case RT5645_DRC2_CTRL3:
658 case RT5645_DRC2_CTRL4:
659 case RT5645_DRC2_CTRL5:
660 case RT5645_JD_CTRL3:
661 case RT5645_JD_CTRL4:
662 case RT5645_GEN_CTRL1:
663 case RT5645_GEN_CTRL2:
664 case RT5645_GEN_CTRL3:
665 case RT5645_VENDOR_ID:
666 case RT5645_VENDOR_ID1:
667 case RT5645_VENDOR_ID2:
668 return true;
669 default:
670 return false;
671 }
672 }
673
674 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
675 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
676 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
677 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
678 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
679
680 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
681 static const DECLARE_TLV_DB_RANGE(bst_tlv,
682 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
683 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
684 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
685 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
686 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
687 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
688 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
689 );
690
691 /* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */
692 static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv,
693 0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0),
694 5, 5, TLV_DB_SCALE_ITEM(82, 0, 0),
695 6, 6, TLV_DB_SCALE_ITEM(158, 0, 0),
696 7, 7, TLV_DB_SCALE_ITEM(228, 0, 0)
697 );
698
rt5645_hweq_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)699 static int rt5645_hweq_info(struct snd_kcontrol *kcontrol,
700 struct snd_ctl_elem_info *uinfo)
701 {
702 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
703 uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s);
704
705 return 0;
706 }
707
rt5645_hweq_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)708 static int rt5645_hweq_get(struct snd_kcontrol *kcontrol,
709 struct snd_ctl_elem_value *ucontrol)
710 {
711 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
712 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
713 struct rt5645_eq_param_s_be16 *eq_param =
714 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data;
715 int i;
716
717 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
718 eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg);
719 eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val);
720 }
721
722 return 0;
723 }
724
rt5645_validate_hweq(unsigned short reg)725 static bool rt5645_validate_hweq(unsigned short reg)
726 {
727 if ((reg >= 0x1a4 && reg <= 0x1cd) || (reg >= 0x1e5 && reg <= 0x1f8) ||
728 (reg == RT5645_EQ_CTRL2))
729 return true;
730
731 return false;
732 }
733
rt5645_hweq_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)734 static int rt5645_hweq_put(struct snd_kcontrol *kcontrol,
735 struct snd_ctl_elem_value *ucontrol)
736 {
737 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
738 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
739 struct rt5645_eq_param_s_be16 *eq_param =
740 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data;
741 int i;
742
743 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
744 rt5645->eq_param[i].reg = be16_to_cpu(eq_param[i].reg);
745 rt5645->eq_param[i].val = be16_to_cpu(eq_param[i].val);
746 }
747
748 /* The final setting of the table should be RT5645_EQ_CTRL2 */
749 for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) {
750 if (rt5645->eq_param[i].reg == 0)
751 continue;
752 else if (rt5645->eq_param[i].reg != RT5645_EQ_CTRL2)
753 return 0;
754 else
755 break;
756 }
757
758 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
759 if (!rt5645_validate_hweq(rt5645->eq_param[i].reg) &&
760 rt5645->eq_param[i].reg != 0)
761 return 0;
762 else if (rt5645->eq_param[i].reg == 0)
763 break;
764 }
765
766 return 0;
767 }
768
769 #define RT5645_HWEQ(xname) \
770 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
771 .info = rt5645_hweq_info, \
772 .get = rt5645_hweq_get, \
773 .put = rt5645_hweq_put \
774 }
775
rt5645_spk_put_volsw(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)776 static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol,
777 struct snd_ctl_elem_value *ucontrol)
778 {
779 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
780 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
781 int ret;
782
783 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
784 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU);
785
786 ret = snd_soc_put_volsw(kcontrol, ucontrol);
787
788 mod_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work,
789 msecs_to_jiffies(200));
790
791 return ret;
792 }
793
794 static const char * const rt5645_dac1_vol_ctrl_mode_text[] = {
795 "immediately", "zero crossing", "soft ramp"
796 };
797
798 static SOC_ENUM_SINGLE_DECL(
799 rt5645_dac1_vol_ctrl_mode, RT5645_PR_BASE,
800 RT5645_DA1_ZDET_SFT, rt5645_dac1_vol_ctrl_mode_text);
801
802 static const struct snd_kcontrol_new rt5645_snd_controls[] = {
803 /* Speaker Output Volume */
804 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
805 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
806 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
807 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw,
808 rt5645_spk_put_volsw, out_vol_tlv),
809
810 /* ClassD modulator Speaker Gain Ratio */
811 SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO,
812 RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv),
813
814 /* Headphone Output Volume */
815 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL,
816 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
817 SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL,
818 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
819
820 /* OUTPUT Control */
821 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
822 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
823 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
824 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
825 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
826 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
827
828 /* DAC Digital Volume */
829 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
830 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
831 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
832 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
833 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
834 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
835
836 /* IN1/IN2 Control */
837 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
838 RT5645_BST_SFT1, 12, 0, bst_tlv),
839 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
840 RT5645_BST_SFT2, 8, 0, bst_tlv),
841
842 /* INL/INR Volume Control */
843 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
844 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
845
846 /* ADC Digital Volume Control */
847 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
848 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
849 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
850 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
851 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
852 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
853 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
854 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
855
856 /* ADC Boost Volume Control */
857 SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1,
858 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
859 adc_bst_tlv),
860 SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2,
861 RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0,
862 adc_bst_tlv),
863
864 /* I2S2 function select */
865 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
866 1, 1),
867 RT5645_HWEQ("Speaker HWEQ"),
868
869 /* Digital Soft Volume Control */
870 SOC_ENUM("DAC1 Digital Volume Control Func", rt5645_dac1_vol_ctrl_mode),
871 };
872
873 /**
874 * set_dmic_clk - Set parameter of dmic.
875 *
876 * @w: DAPM widget.
877 * @kcontrol: The kcontrol of this widget.
878 * @event: Event id.
879 *
880 */
set_dmic_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)881 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
882 struct snd_kcontrol *kcontrol, int event)
883 {
884 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
885 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
886 int idx, rate;
887
888 rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap,
889 RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT);
890 idx = rl6231_calc_dmic_clk(rate);
891 if (idx < 0)
892 dev_err(component->dev, "Failed to set DMIC clock\n");
893 else
894 snd_soc_component_update_bits(component, RT5645_DMIC_CTRL1,
895 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
896 return idx;
897 }
898
is_sys_clk_from_pll(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)899 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
900 struct snd_soc_dapm_widget *sink)
901 {
902 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
903 unsigned int val;
904
905 val = snd_soc_component_read(component, RT5645_GLB_CLK);
906 val &= RT5645_SCLK_SRC_MASK;
907 if (val == RT5645_SCLK_SRC_PLL1)
908 return 1;
909 else
910 return 0;
911 }
912
is_using_asrc(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)913 static int is_using_asrc(struct snd_soc_dapm_widget *source,
914 struct snd_soc_dapm_widget *sink)
915 {
916 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
917 unsigned int reg, shift, val;
918
919 switch (source->shift) {
920 case 0:
921 reg = RT5645_ASRC_3;
922 shift = 0;
923 break;
924 case 1:
925 reg = RT5645_ASRC_3;
926 shift = 4;
927 break;
928 case 3:
929 reg = RT5645_ASRC_2;
930 shift = 0;
931 break;
932 case 8:
933 reg = RT5645_ASRC_2;
934 shift = 4;
935 break;
936 case 9:
937 reg = RT5645_ASRC_2;
938 shift = 8;
939 break;
940 case 10:
941 reg = RT5645_ASRC_2;
942 shift = 12;
943 break;
944 default:
945 return 0;
946 }
947
948 val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
949 switch (val) {
950 case 1:
951 case 2:
952 case 3:
953 case 4:
954 return 1;
955 default:
956 return 0;
957 }
958
959 }
960
rt5645_enable_hweq(struct snd_soc_component * component)961 static int rt5645_enable_hweq(struct snd_soc_component *component)
962 {
963 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
964 int i;
965
966 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
967 if (rt5645_validate_hweq(rt5645->eq_param[i].reg))
968 regmap_write(rt5645->regmap, rt5645->eq_param[i].reg,
969 rt5645->eq_param[i].val);
970 else
971 break;
972 }
973
974 return 0;
975 }
976
977 /**
978 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
979 * @component: SoC audio component device.
980 * @filter_mask: mask of filters.
981 * @clk_src: clock source
982 *
983 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
984 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
985 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
986 * ASRC function will track i2s clock and generate a corresponding system clock
987 * for codec. This function provides an API to select the clock source for a
988 * set of filters specified by the mask. And the codec driver will turn on ASRC
989 * for these filters if ASRC is selected as their clock source.
990 */
rt5645_sel_asrc_clk_src(struct snd_soc_component * component,unsigned int filter_mask,unsigned int clk_src)991 int rt5645_sel_asrc_clk_src(struct snd_soc_component *component,
992 unsigned int filter_mask, unsigned int clk_src)
993 {
994 unsigned int asrc2_mask = 0;
995 unsigned int asrc2_value = 0;
996 unsigned int asrc3_mask = 0;
997 unsigned int asrc3_value = 0;
998
999 switch (clk_src) {
1000 case RT5645_CLK_SEL_SYS:
1001 case RT5645_CLK_SEL_I2S1_ASRC:
1002 case RT5645_CLK_SEL_I2S2_ASRC:
1003 case RT5645_CLK_SEL_SYS2:
1004 break;
1005
1006 default:
1007 return -EINVAL;
1008 }
1009
1010 if (filter_mask & RT5645_DA_STEREO_FILTER) {
1011 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
1012 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
1013 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
1014 }
1015
1016 if (filter_mask & RT5645_DA_MONO_L_FILTER) {
1017 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
1018 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
1019 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
1020 }
1021
1022 if (filter_mask & RT5645_DA_MONO_R_FILTER) {
1023 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
1024 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
1025 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
1026 }
1027
1028 if (filter_mask & RT5645_AD_STEREO_FILTER) {
1029 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
1030 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
1031 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
1032 }
1033
1034 if (filter_mask & RT5645_AD_MONO_L_FILTER) {
1035 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
1036 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
1037 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
1038 }
1039
1040 if (filter_mask & RT5645_AD_MONO_R_FILTER) {
1041 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
1042 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
1043 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
1044 }
1045
1046 if (asrc2_mask)
1047 snd_soc_component_update_bits(component, RT5645_ASRC_2,
1048 asrc2_mask, asrc2_value);
1049
1050 if (asrc3_mask)
1051 snd_soc_component_update_bits(component, RT5645_ASRC_3,
1052 asrc3_mask, asrc3_value);
1053
1054 return 0;
1055 }
1056 EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
1057
1058 /* Digital Mixer */
1059 static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
1060 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
1061 RT5645_M_ADC_L1_SFT, 1, 1),
1062 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
1063 RT5645_M_ADC_L2_SFT, 1, 1),
1064 };
1065
1066 static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
1067 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
1068 RT5645_M_ADC_R1_SFT, 1, 1),
1069 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
1070 RT5645_M_ADC_R2_SFT, 1, 1),
1071 };
1072
1073 static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
1074 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
1075 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
1076 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
1077 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
1078 };
1079
1080 static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
1081 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
1082 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
1083 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
1084 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
1085 };
1086
1087 static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
1088 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
1089 RT5645_M_ADCMIX_L_SFT, 1, 1),
1090 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1091 RT5645_M_DAC1_L_SFT, 1, 1),
1092 };
1093
1094 static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
1095 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
1096 RT5645_M_ADCMIX_R_SFT, 1, 1),
1097 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1098 RT5645_M_DAC1_R_SFT, 1, 1),
1099 };
1100
1101 static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
1102 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
1103 RT5645_M_DAC_L1_SFT, 1, 1),
1104 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
1105 RT5645_M_DAC_L2_SFT, 1, 1),
1106 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
1107 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
1108 };
1109
1110 static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
1111 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
1112 RT5645_M_DAC_R1_SFT, 1, 1),
1113 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
1114 RT5645_M_DAC_R2_SFT, 1, 1),
1115 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
1116 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
1117 };
1118
1119 static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
1120 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
1121 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
1122 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
1123 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
1124 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
1125 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
1126 };
1127
1128 static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
1129 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
1130 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
1131 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
1132 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
1133 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
1134 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
1135 };
1136
1137 static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
1138 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
1139 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
1140 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
1141 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
1142 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
1143 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
1144 };
1145
1146 static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
1147 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
1148 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
1149 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
1150 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
1151 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
1152 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
1153 };
1154
1155 /* Analog Input Mixer */
1156 static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
1157 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
1158 RT5645_M_HP_L_RM_L_SFT, 1, 1),
1159 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
1160 RT5645_M_IN_L_RM_L_SFT, 1, 1),
1161 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
1162 RT5645_M_BST2_RM_L_SFT, 1, 1),
1163 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
1164 RT5645_M_BST1_RM_L_SFT, 1, 1),
1165 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
1166 RT5645_M_OM_L_RM_L_SFT, 1, 1),
1167 };
1168
1169 static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
1170 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
1171 RT5645_M_HP_R_RM_R_SFT, 1, 1),
1172 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
1173 RT5645_M_IN_R_RM_R_SFT, 1, 1),
1174 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
1175 RT5645_M_BST2_RM_R_SFT, 1, 1),
1176 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
1177 RT5645_M_BST1_RM_R_SFT, 1, 1),
1178 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
1179 RT5645_M_OM_R_RM_R_SFT, 1, 1),
1180 };
1181
1182 static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
1183 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
1184 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
1185 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
1186 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
1187 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
1188 RT5645_M_IN_L_SM_L_SFT, 1, 1),
1189 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
1190 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
1191 };
1192
1193 static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
1194 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
1195 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
1196 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
1197 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
1198 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
1199 RT5645_M_IN_R_SM_R_SFT, 1, 1),
1200 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
1201 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
1202 };
1203
1204 static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
1205 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
1206 RT5645_M_BST1_OM_L_SFT, 1, 1),
1207 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
1208 RT5645_M_IN_L_OM_L_SFT, 1, 1),
1209 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
1210 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
1211 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
1212 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
1213 };
1214
1215 static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
1216 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
1217 RT5645_M_BST2_OM_R_SFT, 1, 1),
1218 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
1219 RT5645_M_IN_R_OM_R_SFT, 1, 1),
1220 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
1221 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
1222 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
1223 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
1224 };
1225
1226 static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
1227 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1228 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
1229 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
1230 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
1231 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1232 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
1233 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
1234 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
1235 };
1236
1237 static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
1238 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1239 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
1240 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1241 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
1242 };
1243
1244 static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
1245 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
1246 RT5645_M_DAC1_HM_SFT, 1, 1),
1247 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
1248 RT5645_M_HPVOL_HM_SFT, 1, 1),
1249 };
1250
1251 static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
1252 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
1253 RT5645_M_DAC1_HV_SFT, 1, 1),
1254 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
1255 RT5645_M_DAC2_HV_SFT, 1, 1),
1256 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
1257 RT5645_M_IN_HV_SFT, 1, 1),
1258 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
1259 RT5645_M_BST1_HV_SFT, 1, 1),
1260 };
1261
1262 static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
1263 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
1264 RT5645_M_DAC1_HV_SFT, 1, 1),
1265 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
1266 RT5645_M_DAC2_HV_SFT, 1, 1),
1267 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
1268 RT5645_M_IN_HV_SFT, 1, 1),
1269 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
1270 RT5645_M_BST2_HV_SFT, 1, 1),
1271 };
1272
1273 static const struct snd_kcontrol_new rt5645_lout_mix[] = {
1274 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
1275 RT5645_M_DAC_L1_LM_SFT, 1, 1),
1276 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
1277 RT5645_M_DAC_R1_LM_SFT, 1, 1),
1278 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
1279 RT5645_M_OV_L_LM_SFT, 1, 1),
1280 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
1281 RT5645_M_OV_R_LM_SFT, 1, 1),
1282 };
1283
1284 /*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
1285 static const char * const rt5645_dac1_src[] = {
1286 "IF1 DAC", "IF2 DAC", "IF3 DAC"
1287 };
1288
1289 static SOC_ENUM_SINGLE_DECL(
1290 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
1291 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
1292
1293 static const struct snd_kcontrol_new rt5645_dac1l_mux =
1294 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
1295
1296 static SOC_ENUM_SINGLE_DECL(
1297 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
1298 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
1299
1300 static const struct snd_kcontrol_new rt5645_dac1r_mux =
1301 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
1302
1303 /*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
1304 static const char * const rt5645_dac12_src[] = {
1305 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
1306 };
1307
1308 static SOC_ENUM_SINGLE_DECL(
1309 rt5645_dac2l_enum, RT5645_DAC_CTRL,
1310 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
1311
1312 static const struct snd_kcontrol_new rt5645_dac_l2_mux =
1313 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
1314
1315 static const char * const rt5645_dacr2_src[] = {
1316 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
1317 };
1318
1319 static SOC_ENUM_SINGLE_DECL(
1320 rt5645_dac2r_enum, RT5645_DAC_CTRL,
1321 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
1322
1323 static const struct snd_kcontrol_new rt5645_dac_r2_mux =
1324 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
1325
1326 /* Stereo1 ADC source */
1327 /* MX-27 [12] */
1328 static const char * const rt5645_stereo_adc1_src[] = {
1329 "DAC MIX", "ADC"
1330 };
1331
1332 static SOC_ENUM_SINGLE_DECL(
1333 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
1334 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
1335
1336 static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
1337 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
1338
1339 /* MX-27 [11] */
1340 static const char * const rt5645_stereo_adc2_src[] = {
1341 "DAC MIX", "DMIC"
1342 };
1343
1344 static SOC_ENUM_SINGLE_DECL(
1345 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
1346 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
1347
1348 static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
1349 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
1350
1351 /* MX-27 [8] */
1352 static const char * const rt5645_stereo_dmic_src[] = {
1353 "DMIC1", "DMIC2"
1354 };
1355
1356 static SOC_ENUM_SINGLE_DECL(
1357 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
1358 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
1359
1360 static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
1361 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
1362
1363 /* Mono ADC source */
1364 /* MX-28 [12] */
1365 static const char * const rt5645_mono_adc_l1_src[] = {
1366 "Mono DAC MIXL", "ADC"
1367 };
1368
1369 static SOC_ENUM_SINGLE_DECL(
1370 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
1371 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
1372
1373 static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
1374 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
1375 /* MX-28 [11] */
1376 static const char * const rt5645_mono_adc_l2_src[] = {
1377 "Mono DAC MIXL", "DMIC"
1378 };
1379
1380 static SOC_ENUM_SINGLE_DECL(
1381 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
1382 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
1383
1384 static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
1385 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
1386
1387 /* MX-28 [8] */
1388 static const char * const rt5645_mono_dmic_src[] = {
1389 "DMIC1", "DMIC2"
1390 };
1391
1392 static SOC_ENUM_SINGLE_DECL(
1393 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
1394 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
1395
1396 static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
1397 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
1398 /* MX-28 [1:0] */
1399 static SOC_ENUM_SINGLE_DECL(
1400 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
1401 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
1402
1403 static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
1404 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
1405 /* MX-28 [4] */
1406 static const char * const rt5645_mono_adc_r1_src[] = {
1407 "Mono DAC MIXR", "ADC"
1408 };
1409
1410 static SOC_ENUM_SINGLE_DECL(
1411 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
1412 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
1413
1414 static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
1415 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
1416 /* MX-28 [3] */
1417 static const char * const rt5645_mono_adc_r2_src[] = {
1418 "Mono DAC MIXR", "DMIC"
1419 };
1420
1421 static SOC_ENUM_SINGLE_DECL(
1422 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
1423 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
1424
1425 static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1426 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
1427
1428 /* MX-77 [9:8] */
1429 static const char * const rt5645_if1_adc_in_src[] = {
1430 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC",
1431 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1"
1432 };
1433
1434 static SOC_ENUM_SINGLE_DECL(
1435 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1436 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1437
1438 static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1439 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1440
1441 /* MX-78 [4:0] */
1442 static const char * const rt5650_if1_adc_in_src[] = {
1443 "IF_ADC1/IF_ADC2/DAC_REF/Null",
1444 "IF_ADC1/IF_ADC2/Null/DAC_REF",
1445 "IF_ADC1/DAC_REF/IF_ADC2/Null",
1446 "IF_ADC1/DAC_REF/Null/IF_ADC2",
1447 "IF_ADC1/Null/DAC_REF/IF_ADC2",
1448 "IF_ADC1/Null/IF_ADC2/DAC_REF",
1449
1450 "IF_ADC2/IF_ADC1/DAC_REF/Null",
1451 "IF_ADC2/IF_ADC1/Null/DAC_REF",
1452 "IF_ADC2/DAC_REF/IF_ADC1/Null",
1453 "IF_ADC2/DAC_REF/Null/IF_ADC1",
1454 "IF_ADC2/Null/DAC_REF/IF_ADC1",
1455 "IF_ADC2/Null/IF_ADC1/DAC_REF",
1456
1457 "DAC_REF/IF_ADC1/IF_ADC2/Null",
1458 "DAC_REF/IF_ADC1/Null/IF_ADC2",
1459 "DAC_REF/IF_ADC2/IF_ADC1/Null",
1460 "DAC_REF/IF_ADC2/Null/IF_ADC1",
1461 "DAC_REF/Null/IF_ADC1/IF_ADC2",
1462 "DAC_REF/Null/IF_ADC2/IF_ADC1",
1463
1464 "Null/IF_ADC1/IF_ADC2/DAC_REF",
1465 "Null/IF_ADC1/DAC_REF/IF_ADC2",
1466 "Null/IF_ADC2/IF_ADC1/DAC_REF",
1467 "Null/IF_ADC2/DAC_REF/IF_ADC1",
1468 "Null/DAC_REF/IF_ADC1/IF_ADC2",
1469 "Null/DAC_REF/IF_ADC2/IF_ADC1",
1470 };
1471
1472 static SOC_ENUM_SINGLE_DECL(
1473 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2,
1474 0, rt5650_if1_adc_in_src);
1475
1476 static const struct snd_kcontrol_new rt5650_if1_adc_in_mux =
1477 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum);
1478
1479 /* MX-78 [15:14][13:12][11:10] */
1480 static const char * const rt5645_tdm_adc_swap_select[] = {
1481 "L/R", "R/L", "L/L", "R/R"
1482 };
1483
1484 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum,
1485 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select);
1486
1487 static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux =
1488 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum);
1489
1490 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum,
1491 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select);
1492
1493 static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux =
1494 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum);
1495
1496 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum,
1497 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select);
1498
1499 static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux =
1500 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum);
1501
1502 /* MX-77 [7:6][5:4][3:2] */
1503 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
1504 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select);
1505
1506 static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux =
1507 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum);
1508
1509 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
1510 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select);
1511
1512 static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux =
1513 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum);
1514
1515 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
1516 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select);
1517
1518 static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux =
1519 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum);
1520
1521 /* MX-79 [14:12][10:8][6:4][2:0] */
1522 static const char * const rt5645_tdm_dac_swap_select[] = {
1523 "Slot0", "Slot1", "Slot2", "Slot3"
1524 };
1525
1526 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum,
1527 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select);
1528
1529 static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux =
1530 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum);
1531
1532 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum,
1533 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select);
1534
1535 static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux =
1536 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum);
1537
1538 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum,
1539 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select);
1540
1541 static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux =
1542 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum);
1543
1544 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum,
1545 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select);
1546
1547 static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux =
1548 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum);
1549
1550 /* MX-7a [14:12][10:8][6:4][2:0] */
1551 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum,
1552 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select);
1553
1554 static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux =
1555 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum);
1556
1557 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum,
1558 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select);
1559
1560 static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux =
1561 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum);
1562
1563 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum,
1564 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select);
1565
1566 static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux =
1567 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum);
1568
1569 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum,
1570 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select);
1571
1572 static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux =
1573 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum);
1574
1575 /* MX-2d [3] [2] */
1576 static const char * const rt5650_a_dac1_src[] = {
1577 "DAC1", "Stereo DAC Mixer"
1578 };
1579
1580 static SOC_ENUM_SINGLE_DECL(
1581 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
1582 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
1583
1584 static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
1585 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
1586
1587 static SOC_ENUM_SINGLE_DECL(
1588 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
1589 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
1590
1591 static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
1592 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
1593
1594 /* MX-2d [1] [0] */
1595 static const char * const rt5650_a_dac2_src[] = {
1596 "Stereo DAC Mixer", "Mono DAC Mixer"
1597 };
1598
1599 static SOC_ENUM_SINGLE_DECL(
1600 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
1601 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
1602
1603 static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
1604 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
1605
1606 static SOC_ENUM_SINGLE_DECL(
1607 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
1608 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
1609
1610 static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
1611 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
1612
1613 /* MX-2F [13:12] */
1614 static const char * const rt5645_if2_adc_in_src[] = {
1615 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1616 };
1617
1618 static SOC_ENUM_SINGLE_DECL(
1619 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1620 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1621
1622 static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1623 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1624
1625 /* MX-31 [15] [13] [11] [9] */
1626 static const char * const rt5645_pdm_src[] = {
1627 "Mono DAC", "Stereo DAC"
1628 };
1629
1630 static SOC_ENUM_SINGLE_DECL(
1631 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1632 RT5645_PDM1_L_SFT, rt5645_pdm_src);
1633
1634 static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1635 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1636
1637 static SOC_ENUM_SINGLE_DECL(
1638 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1639 RT5645_PDM1_R_SFT, rt5645_pdm_src);
1640
1641 static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1642 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1643
1644 /* MX-9D [9:8] */
1645 static const char * const rt5645_vad_adc_src[] = {
1646 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1647 };
1648
1649 static SOC_ENUM_SINGLE_DECL(
1650 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1651 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1652
1653 static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1654 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1655
1656 static const struct snd_kcontrol_new spk_l_vol_control =
1657 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1658 RT5645_L_MUTE_SFT, 1, 1);
1659
1660 static const struct snd_kcontrol_new spk_r_vol_control =
1661 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1662 RT5645_R_MUTE_SFT, 1, 1);
1663
1664 static const struct snd_kcontrol_new hp_l_vol_control =
1665 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1666 RT5645_L_MUTE_SFT, 1, 1);
1667
1668 static const struct snd_kcontrol_new hp_r_vol_control =
1669 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1670 RT5645_R_MUTE_SFT, 1, 1);
1671
1672 static const struct snd_kcontrol_new pdm1_l_vol_control =
1673 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1674 RT5645_M_PDM1_L, 1, 1);
1675
1676 static const struct snd_kcontrol_new pdm1_r_vol_control =
1677 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1678 RT5645_M_PDM1_R, 1, 1);
1679
hp_amp_power(struct snd_soc_component * component,int on)1680 static void hp_amp_power(struct snd_soc_component *component, int on)
1681 {
1682 static int hp_amp_power_count;
1683 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
1684 int i, val;
1685
1686 if (on) {
1687 if (hp_amp_power_count <= 0) {
1688 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1689 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x3100);
1690 snd_soc_component_write(component, RT5645_CHARGE_PUMP,
1691 0x0e06);
1692 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d);
1693 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1694 RT5645_HP_DCC_INT1, 0x9f01);
1695 for (i = 0; i < 20; i++) {
1696 usleep_range(1000, 1500);
1697 regmap_read(rt5645->regmap, RT5645_PR_BASE +
1698 RT5645_HP_DCC_INT1, &val);
1699 if (!(val & 0x8000))
1700 break;
1701 }
1702 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1703 RT5645_HP_CO_MASK, RT5645_HP_CO_EN);
1704 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1705 0x3e, 0x7400);
1706 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737);
1707 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1708 RT5645_MAMP_INT_REG2, 0xfc00);
1709 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
1710 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1711 RT5645_PWR_HP_L | RT5645_PWR_HP_R,
1712 RT5645_PWR_HP_L | RT5645_PWR_HP_R);
1713 msleep(90);
1714 } else {
1715 /* depop parameters */
1716 snd_soc_component_update_bits(component, RT5645_DEPOP_M2,
1717 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1718 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d);
1719 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1720 RT5645_HP_DCC_INT1, 0x9f01);
1721 mdelay(150);
1722 /* headphone amp power on */
1723 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1724 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0);
1725 snd_soc_component_update_bits(component, RT5645_PWR_VOL,
1726 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1727 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1728 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1729 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1730 RT5645_PWR_HA,
1731 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1732 RT5645_PWR_HA);
1733 mdelay(5);
1734 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1735 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1736 RT5645_PWR_FV1 | RT5645_PWR_FV2);
1737
1738 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1739 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1740 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1741 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1742 0x14, 0x1aaa);
1743 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1744 0x24, 0x0430);
1745 }
1746 }
1747 hp_amp_power_count++;
1748 } else {
1749 hp_amp_power_count--;
1750 if (hp_amp_power_count <= 0) {
1751 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1752 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1753 0x3e, 0x7400);
1754 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737);
1755 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1756 RT5645_MAMP_INT_REG2, 0xfc00);
1757 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
1758 msleep(100);
1759 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0001);
1760 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1761 RT5645_PWR_HP_L | RT5645_PWR_HP_R, 0);
1762 } else {
1763 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1764 RT5645_HP_SG_MASK |
1765 RT5645_HP_L_SMT_MASK |
1766 RT5645_HP_R_SMT_MASK,
1767 RT5645_HP_SG_DIS |
1768 RT5645_HP_L_SMT_DIS |
1769 RT5645_HP_R_SMT_DIS);
1770 /* headphone amp power down */
1771 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0000);
1772 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1773 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1774 RT5645_PWR_HA, 0);
1775 snd_soc_component_update_bits(component, RT5645_DEPOP_M2,
1776 RT5645_DEPOP_MASK, 0);
1777 }
1778 }
1779 }
1780 }
1781
rt5645_hp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1782 static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1783 struct snd_kcontrol *kcontrol, int event)
1784 {
1785 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1786 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
1787
1788 switch (event) {
1789 case SND_SOC_DAPM_POST_PMU:
1790 hp_amp_power(component, 1);
1791 /* headphone unmute sequence */
1792 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
1793 snd_soc_component_update_bits(component, RT5645_DEPOP_M3,
1794 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1795 RT5645_CP_FQ3_MASK,
1796 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1797 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1798 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
1799 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1800 RT5645_MAMP_INT_REG2, 0xfc00);
1801 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1802 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1803 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1804 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1805 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1806 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1807 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1808 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1809 msleep(40);
1810 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1811 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1812 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1813 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1814 }
1815 break;
1816
1817 case SND_SOC_DAPM_PRE_PMD:
1818 /* headphone mute sequence */
1819 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
1820 snd_soc_component_update_bits(component, RT5645_DEPOP_M3,
1821 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1822 RT5645_CP_FQ3_MASK,
1823 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1824 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1825 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
1826 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1827 RT5645_MAMP_INT_REG2, 0xfc00);
1828 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1829 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1830 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1831 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1832 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1833 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1834 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1835 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1836 msleep(30);
1837 }
1838 hp_amp_power(component, 0);
1839 break;
1840
1841 default:
1842 return 0;
1843 }
1844
1845 return 0;
1846 }
1847
rt5645_spk_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1848 static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1849 struct snd_kcontrol *kcontrol, int event)
1850 {
1851 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1852
1853 switch (event) {
1854 case SND_SOC_DAPM_POST_PMU:
1855 rt5645_enable_hweq(component);
1856 snd_soc_component_update_bits(component, RT5645_PWR_DIG1,
1857 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1858 RT5645_PWR_CLS_D_L,
1859 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1860 RT5645_PWR_CLS_D_L);
1861 break;
1862
1863 case SND_SOC_DAPM_PRE_PMD:
1864 snd_soc_component_write(component, RT5645_EQ_CTRL2, 0);
1865 snd_soc_component_update_bits(component, RT5645_PWR_DIG1,
1866 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1867 RT5645_PWR_CLS_D_L, 0);
1868 break;
1869
1870 default:
1871 return 0;
1872 }
1873
1874 return 0;
1875 }
1876
rt5645_lout_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1877 static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1878 struct snd_kcontrol *kcontrol, int event)
1879 {
1880 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1881
1882 switch (event) {
1883 case SND_SOC_DAPM_POST_PMU:
1884 hp_amp_power(component, 1);
1885 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1886 RT5645_PWR_LM, RT5645_PWR_LM);
1887 snd_soc_component_update_bits(component, RT5645_LOUT1,
1888 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1889 break;
1890
1891 case SND_SOC_DAPM_PRE_PMD:
1892 snd_soc_component_update_bits(component, RT5645_LOUT1,
1893 RT5645_L_MUTE | RT5645_R_MUTE,
1894 RT5645_L_MUTE | RT5645_R_MUTE);
1895 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1896 RT5645_PWR_LM, 0);
1897 hp_amp_power(component, 0);
1898 break;
1899
1900 default:
1901 return 0;
1902 }
1903
1904 return 0;
1905 }
1906
rt5645_bst2_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1907 static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1908 struct snd_kcontrol *kcontrol, int event)
1909 {
1910 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1911
1912 switch (event) {
1913 case SND_SOC_DAPM_POST_PMU:
1914 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2,
1915 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1916 break;
1917
1918 case SND_SOC_DAPM_PRE_PMD:
1919 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2,
1920 RT5645_PWR_BST2_P, 0);
1921 break;
1922
1923 default:
1924 return 0;
1925 }
1926
1927 return 0;
1928 }
1929
rt5645_set_micbias1_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)1930 static int rt5645_set_micbias1_event(struct snd_soc_dapm_widget *w,
1931 struct snd_kcontrol *k, int event)
1932 {
1933 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1934
1935 switch (event) {
1936 case SND_SOC_DAPM_PRE_PMU:
1937 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1938 RT5645_MICBIAS1_POW_CTRL_SEL_MASK,
1939 RT5645_MICBIAS1_POW_CTRL_SEL_M);
1940 break;
1941
1942 case SND_SOC_DAPM_POST_PMD:
1943 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1944 RT5645_MICBIAS1_POW_CTRL_SEL_MASK,
1945 RT5645_MICBIAS1_POW_CTRL_SEL_A);
1946 break;
1947
1948 default:
1949 return 0;
1950 }
1951
1952 return 0;
1953 }
1954
rt5645_set_micbias2_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)1955 static int rt5645_set_micbias2_event(struct snd_soc_dapm_widget *w,
1956 struct snd_kcontrol *k, int event)
1957 {
1958 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1959
1960 switch (event) {
1961 case SND_SOC_DAPM_PRE_PMU:
1962 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1963 RT5645_MICBIAS2_POW_CTRL_SEL_MASK,
1964 RT5645_MICBIAS2_POW_CTRL_SEL_M);
1965 break;
1966
1967 case SND_SOC_DAPM_POST_PMD:
1968 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1969 RT5645_MICBIAS2_POW_CTRL_SEL_MASK,
1970 RT5645_MICBIAS2_POW_CTRL_SEL_A);
1971 break;
1972
1973 default:
1974 return 0;
1975 }
1976
1977 return 0;
1978 }
1979
1980 static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1981 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1982 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1983 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1984 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1985
1986 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1987 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1988 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1989 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1990
1991 /* ASRC */
1992 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1993 11, 0, NULL, 0),
1994 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1995 12, 0, NULL, 0),
1996 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1997 10, 0, NULL, 0),
1998 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
1999 9, 0, NULL, 0),
2000 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
2001 8, 0, NULL, 0),
2002 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
2003 7, 0, NULL, 0),
2004 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
2005 5, 0, NULL, 0),
2006 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
2007 4, 0, NULL, 0),
2008 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
2009 3, 0, NULL, 0),
2010 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
2011 1, 0, NULL, 0),
2012 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
2013 0, 0, NULL, 0),
2014
2015 /* Input Side */
2016 /* micbias */
2017 SND_SOC_DAPM_SUPPLY("micbias1", RT5645_PWR_ANLG2,
2018 RT5645_PWR_MB1_BIT, 0, rt5645_set_micbias1_event,
2019 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2020 SND_SOC_DAPM_SUPPLY("micbias2", RT5645_PWR_ANLG2,
2021 RT5645_PWR_MB2_BIT, 0, rt5645_set_micbias2_event,
2022 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2023 /* Input Lines */
2024 SND_SOC_DAPM_INPUT("DMIC L1"),
2025 SND_SOC_DAPM_INPUT("DMIC R1"),
2026 SND_SOC_DAPM_INPUT("DMIC L2"),
2027 SND_SOC_DAPM_INPUT("DMIC R2"),
2028
2029 SND_SOC_DAPM_INPUT("IN1P"),
2030 SND_SOC_DAPM_INPUT("IN1N"),
2031 SND_SOC_DAPM_INPUT("IN2P"),
2032 SND_SOC_DAPM_INPUT("IN2N"),
2033
2034 SND_SOC_DAPM_INPUT("Haptic Generator"),
2035
2036 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2037 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2038 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2039 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2040 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
2041 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
2042 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
2043 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
2044 /* Boost */
2045 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
2046 RT5645_PWR_BST1_BIT, 0, NULL, 0),
2047 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
2048 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
2049 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2050 /* Input Volume */
2051 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
2052 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
2053 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
2054 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
2055 /* REC Mixer */
2056 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
2057 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
2058 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
2059 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
2060 /* ADCs */
2061 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2062 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2063
2064 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
2065 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
2066 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
2067 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
2068
2069 /* ADC Mux */
2070 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2071 &rt5645_sto1_dmic_mux),
2072 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2073 &rt5645_sto_adc2_mux),
2074 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2075 &rt5645_sto_adc2_mux),
2076 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2077 &rt5645_sto_adc1_mux),
2078 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2079 &rt5645_sto_adc1_mux),
2080 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2081 &rt5645_mono_dmic_l_mux),
2082 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2083 &rt5645_mono_dmic_r_mux),
2084 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2085 &rt5645_mono_adc_l2_mux),
2086 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2087 &rt5645_mono_adc_l1_mux),
2088 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2089 &rt5645_mono_adc_r1_mux),
2090 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2091 &rt5645_mono_adc_r2_mux),
2092 /* ADC Mixer */
2093
2094 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
2095 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
2096 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2097 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
2098 NULL, 0),
2099 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2100 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
2101 NULL, 0),
2102 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
2103 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2104 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2105 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
2106 NULL, 0),
2107 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
2108 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2109 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2110 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
2111 NULL, 0),
2112
2113 /* ADC PGA */
2114 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2115 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2116 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2117 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2118 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2119 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2120 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2121 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2122 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2123 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2124
2125 /* IF1 2 Mux */
2126 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
2127 0, 0, &rt5645_if2_adc_in_mux),
2128
2129 /* Digital Interface */
2130 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
2131 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
2132 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2133 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2134 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2135 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2136 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2137 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2138 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2139 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
2140 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
2141 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2142 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2143 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2144 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2145
2146 /* Digital Interface Select */
2147 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
2148 0, 0, &rt5645_vad_adc_mux),
2149
2150 /* Audio Interface */
2151 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2152 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2153 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2154 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2155
2156 /* Output Side */
2157 /* DAC mixer before sound effect */
2158 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2159 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
2160 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2161 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
2162
2163 /* DAC2 channel Mux */
2164 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
2165 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
2166 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
2167 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
2168 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
2169 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
2170
2171 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
2172 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
2173
2174 /* DAC Mixer */
2175 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
2176 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
2177 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
2178 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
2179 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
2180 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
2181 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2182 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
2183 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2184 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
2185 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2186 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
2187 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2188 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
2189 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
2190 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
2191 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
2192 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
2193
2194 /* DACs */
2195 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
2196 0),
2197 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
2198 0),
2199 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
2200 0),
2201 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
2202 0),
2203 /* OUT Mixer */
2204 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
2205 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
2206 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
2207 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
2208 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
2209 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
2210 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
2211 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
2212 /* Ouput Volume */
2213 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
2214 &spk_l_vol_control),
2215 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
2216 &spk_r_vol_control),
2217 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
2218 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
2219 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
2220 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
2221 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
2222 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
2223 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
2224 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
2225 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
2226 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
2227 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
2228 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
2229 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
2230
2231 /* HPO/LOUT/Mono Mixer */
2232 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
2233 ARRAY_SIZE(rt5645_spo_l_mix)),
2234 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
2235 ARRAY_SIZE(rt5645_spo_r_mix)),
2236 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
2237 ARRAY_SIZE(rt5645_hpo_mix)),
2238 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
2239 ARRAY_SIZE(rt5645_lout_mix)),
2240
2241 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
2242 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2243 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
2244 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2245 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
2246 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2247
2248 /* PDM */
2249 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
2250 0, NULL, 0),
2251 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
2252 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
2253
2254 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
2255 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
2256
2257 /* Output Lines */
2258 SND_SOC_DAPM_OUTPUT("HPOL"),
2259 SND_SOC_DAPM_OUTPUT("HPOR"),
2260 SND_SOC_DAPM_OUTPUT("LOUTL"),
2261 SND_SOC_DAPM_OUTPUT("LOUTR"),
2262 SND_SOC_DAPM_OUTPUT("PDM1L"),
2263 SND_SOC_DAPM_OUTPUT("PDM1R"),
2264 SND_SOC_DAPM_OUTPUT("SPOL"),
2265 SND_SOC_DAPM_OUTPUT("SPOR"),
2266 };
2267
2268 static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = {
2269 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2270 &rt5645_if1_dac0_tdm_sel_mux),
2271 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2272 &rt5645_if1_dac1_tdm_sel_mux),
2273 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2274 &rt5645_if1_dac2_tdm_sel_mux),
2275 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2276 &rt5645_if1_dac3_tdm_sel_mux),
2277 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM,
2278 0, 0, &rt5645_if1_adc_in_mux),
2279 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2280 0, 0, &rt5645_if1_adc1_in_mux),
2281 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2282 0, 0, &rt5645_if1_adc2_in_mux),
2283 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2284 0, 0, &rt5645_if1_adc3_in_mux),
2285 };
2286
2287 static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
2288 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
2289 0, 0, &rt5650_a_dac1_l_mux),
2290 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
2291 0, 0, &rt5650_a_dac1_r_mux),
2292 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
2293 0, 0, &rt5650_a_dac2_l_mux),
2294 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
2295 0, 0, &rt5650_a_dac2_r_mux),
2296
2297 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2298 0, 0, &rt5650_if1_adc1_in_mux),
2299 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2300 0, 0, &rt5650_if1_adc2_in_mux),
2301 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2302 0, 0, &rt5650_if1_adc3_in_mux),
2303 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM,
2304 0, 0, &rt5650_if1_adc_in_mux),
2305
2306 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2307 &rt5650_if1_dac0_tdm_sel_mux),
2308 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2309 &rt5650_if1_dac1_tdm_sel_mux),
2310 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2311 &rt5650_if1_dac2_tdm_sel_mux),
2312 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2313 &rt5650_if1_dac3_tdm_sel_mux),
2314 };
2315
2316 static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
2317 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
2318 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
2319 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
2320 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
2321 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
2322 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
2323
2324 { "I2S1", NULL, "I2S1 ASRC" },
2325 { "I2S2", NULL, "I2S2 ASRC" },
2326
2327 { "IN1P", NULL, "LDO2" },
2328 { "IN2P", NULL, "LDO2" },
2329
2330 { "DMIC1", NULL, "DMIC L1" },
2331 { "DMIC1", NULL, "DMIC R1" },
2332 { "DMIC2", NULL, "DMIC L2" },
2333 { "DMIC2", NULL, "DMIC R2" },
2334
2335 { "BST1", NULL, "IN1P" },
2336 { "BST1", NULL, "IN1N" },
2337 { "BST1", NULL, "JD Power" },
2338 { "BST1", NULL, "Mic Det Power" },
2339 { "BST2", NULL, "IN2P" },
2340 { "BST2", NULL, "IN2N" },
2341
2342 { "INL VOL", NULL, "IN2P" },
2343 { "INR VOL", NULL, "IN2N" },
2344
2345 { "RECMIXL", "HPOL Switch", "HPOL" },
2346 { "RECMIXL", "INL Switch", "INL VOL" },
2347 { "RECMIXL", "BST2 Switch", "BST2" },
2348 { "RECMIXL", "BST1 Switch", "BST1" },
2349 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
2350
2351 { "RECMIXR", "HPOR Switch", "HPOR" },
2352 { "RECMIXR", "INR Switch", "INR VOL" },
2353 { "RECMIXR", "BST2 Switch", "BST2" },
2354 { "RECMIXR", "BST1 Switch", "BST1" },
2355 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
2356
2357 { "ADC L", NULL, "RECMIXL" },
2358 { "ADC L", NULL, "ADC L power" },
2359 { "ADC R", NULL, "RECMIXR" },
2360 { "ADC R", NULL, "ADC R power" },
2361
2362 {"DMIC L1", NULL, "DMIC CLK"},
2363 {"DMIC L1", NULL, "DMIC1 Power"},
2364 {"DMIC R1", NULL, "DMIC CLK"},
2365 {"DMIC R1", NULL, "DMIC1 Power"},
2366 {"DMIC L2", NULL, "DMIC CLK"},
2367 {"DMIC L2", NULL, "DMIC2 Power"},
2368 {"DMIC R2", NULL, "DMIC CLK"},
2369 {"DMIC R2", NULL, "DMIC2 Power"},
2370
2371 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2372 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2373 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
2374
2375 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
2376 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
2377 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
2378
2379 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
2380 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
2381 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
2382
2383 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2384 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2385 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
2386 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
2387
2388 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
2389 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2390 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2391 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2392
2393 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2394 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2395 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2396 { "Mono ADC L1 Mux", "ADC", "ADC L" },
2397
2398 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2399 { "Mono ADC R1 Mux", "ADC", "ADC R" },
2400 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2401 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2402
2403 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
2404 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2405 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
2406 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
2407
2408 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2409 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2410 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2411
2412 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2413 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2414 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2415
2416 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
2417 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
2418 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2419 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2420
2421 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
2422 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
2423 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2424 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2425
2426 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
2427 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
2428 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
2429
2430 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
2431 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
2432 { "IF_ADC2", NULL, "Mono ADC MIXL" },
2433 { "IF_ADC2", NULL, "Mono ADC MIXR" },
2434 { "VAD_ADC", NULL, "VAD ADC Mux" },
2435
2436 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
2437 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
2438 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
2439
2440 { "IF1 ADC", NULL, "I2S1" },
2441 { "IF2 ADC", NULL, "I2S2" },
2442 { "IF2 ADC", NULL, "IF2 ADC Mux" },
2443
2444 { "AIF2TX", NULL, "IF2 ADC" },
2445
2446 { "IF1 DAC0", NULL, "AIF1RX" },
2447 { "IF1 DAC1", NULL, "AIF1RX" },
2448 { "IF1 DAC2", NULL, "AIF1RX" },
2449 { "IF1 DAC3", NULL, "AIF1RX" },
2450 { "IF2 DAC", NULL, "AIF2RX" },
2451
2452 { "IF1 DAC0", NULL, "I2S1" },
2453 { "IF1 DAC1", NULL, "I2S1" },
2454 { "IF1 DAC2", NULL, "I2S1" },
2455 { "IF1 DAC3", NULL, "I2S1" },
2456 { "IF2 DAC", NULL, "I2S2" },
2457
2458 { "IF2 DAC L", NULL, "IF2 DAC" },
2459 { "IF2 DAC R", NULL, "IF2 DAC" },
2460
2461 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
2462 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
2463
2464 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
2465 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
2466 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2467 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
2468 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
2469 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2470
2471 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
2472 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
2473 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
2474 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
2475 { "DAC L2 Volume", NULL, "dac mono left filter" },
2476
2477 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
2478 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
2479 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
2480 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
2481 { "DAC R2 Volume", NULL, "dac mono right filter" },
2482
2483 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2484 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
2485 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2486 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2487 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2488 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
2489 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2490 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2491
2492 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2493 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2494 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2495 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2496 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2497 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2498 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2499 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2500
2501 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2502 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2503 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2504 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2505 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2506 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2507
2508 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
2509 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
2510 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
2511 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
2512
2513 { "SPK MIXL", "BST1 Switch", "BST1" },
2514 { "SPK MIXL", "INL Switch", "INL VOL" },
2515 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
2516 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
2517 { "SPK MIXR", "BST2 Switch", "BST2" },
2518 { "SPK MIXR", "INR Switch", "INR VOL" },
2519 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
2520 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
2521
2522 { "OUT MIXL", "BST1 Switch", "BST1" },
2523 { "OUT MIXL", "INL Switch", "INL VOL" },
2524 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
2525 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
2526
2527 { "OUT MIXR", "BST2 Switch", "BST2" },
2528 { "OUT MIXR", "INR Switch", "INR VOL" },
2529 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
2530 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
2531
2532 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
2533 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
2534 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
2535 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
2536 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
2537 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
2538 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
2539 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
2540 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
2541 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
2542
2543 { "DAC 2", NULL, "DAC L2" },
2544 { "DAC 2", NULL, "DAC R2" },
2545 { "DAC 1", NULL, "DAC L1" },
2546 { "DAC 1", NULL, "DAC R1" },
2547 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
2548 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
2549 { "HPOVOL", NULL, "HPOVOL L" },
2550 { "HPOVOL", NULL, "HPOVOL R" },
2551 { "HPO MIX", "DAC1 Switch", "DAC 1" },
2552 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
2553
2554 { "SPKVOL L", "Switch", "SPK MIXL" },
2555 { "SPKVOL R", "Switch", "SPK MIXR" },
2556
2557 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
2558 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
2559 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
2560 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
2561
2562 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
2563 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
2564 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
2565 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
2566
2567 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2568 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
2569 { "PDM1 L Mux", NULL, "PDM1 Power" },
2570 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2571 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2572 { "PDM1 R Mux", NULL, "PDM1 Power" },
2573
2574 { "HP amp", NULL, "HPO MIX" },
2575 { "HP amp", NULL, "JD Power" },
2576 { "HP amp", NULL, "Mic Det Power" },
2577 { "HP amp", NULL, "LDO2" },
2578 { "HPOL", NULL, "HP amp" },
2579 { "HPOR", NULL, "HP amp" },
2580
2581 { "LOUT amp", NULL, "LOUT MIX" },
2582 { "LOUTL", NULL, "LOUT amp" },
2583 { "LOUTR", NULL, "LOUT amp" },
2584
2585 { "PDM1 L", "Switch", "PDM1 L Mux" },
2586 { "PDM1 R", "Switch", "PDM1 R Mux" },
2587
2588 { "PDM1L", NULL, "PDM1 L" },
2589 { "PDM1R", NULL, "PDM1 R" },
2590
2591 { "SPK amp", NULL, "SPOL MIX" },
2592 { "SPK amp", NULL, "SPOR MIX" },
2593 { "SPOL", NULL, "SPK amp" },
2594 { "SPOR", NULL, "SPK amp" },
2595 };
2596
2597 static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
2598 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"},
2599 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2600 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"},
2601 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2602
2603 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2604 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
2605 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2606 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
2607
2608 { "DAC L1", NULL, "A DAC1 L Mux" },
2609 { "DAC R1", NULL, "A DAC1 R Mux" },
2610 { "DAC L2", NULL, "A DAC2 L Mux" },
2611 { "DAC R2", NULL, "A DAC2 R Mux" },
2612
2613 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2614 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2615 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2616 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2617
2618 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2619 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2620 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2621 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2622
2623 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2624 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2625 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2626 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2627
2628 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" },
2629 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" },
2630 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" },
2631
2632 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" },
2633 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" },
2634 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" },
2635 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" },
2636 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" },
2637 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" },
2638
2639 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" },
2640 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" },
2641 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" },
2642 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" },
2643 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" },
2644 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" },
2645
2646 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" },
2647 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" },
2648 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" },
2649 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" },
2650 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" },
2651 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" },
2652
2653 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" },
2654 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" },
2655 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" },
2656 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" },
2657 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" },
2658 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" },
2659 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" },
2660
2661 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2662 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2663 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2664 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2665
2666 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2667 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2668 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2669 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2670
2671 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2672 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2673 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2674 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2675
2676 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2677 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2678 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2679 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2680
2681 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" },
2682 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" },
2683
2684 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },
2685 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },
2686 };
2687
2688 static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
2689 { "DAC L1", NULL, "Stereo DAC MIXL" },
2690 { "DAC R1", NULL, "Stereo DAC MIXR" },
2691 { "DAC L2", NULL, "Mono DAC MIXL" },
2692 { "DAC R2", NULL, "Mono DAC MIXR" },
2693
2694 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2695 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2696 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2697 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2698
2699 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2700 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2701 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2702 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2703
2704 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2705 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2706 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2707 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2708
2709 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" },
2710 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" },
2711 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" },
2712
2713 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" },
2714 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" },
2715 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" },
2716 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" },
2717 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" },
2718
2719 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2720 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2721 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2722 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2723
2724 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2725 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2726 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2727 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2728
2729 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2730 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2731 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2732 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2733
2734 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2735 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2736 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2737 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2738
2739 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" },
2740 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" },
2741
2742 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },
2743 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },
2744 };
2745
2746 static const struct snd_soc_dapm_route rt5645_old_dapm_routes[] = {
2747 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
2748 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
2749 };
2750
rt5645_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)2751 static int rt5645_hw_params(struct snd_pcm_substream *substream,
2752 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2753 {
2754 struct snd_soc_component *component = dai->component;
2755 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2756 unsigned int val_len = 0, val_clk, mask_clk, dl_sft;
2757 int pre_div, bclk_ms, frame_size;
2758
2759 rt5645->lrck[dai->id] = params_rate(params);
2760 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
2761 if (pre_div < 0) {
2762 dev_err(component->dev, "Unsupported clock setting\n");
2763 return -EINVAL;
2764 }
2765 frame_size = snd_soc_params_to_frame_size(params);
2766 if (frame_size < 0) {
2767 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
2768 return -EINVAL;
2769 }
2770
2771 switch (rt5645->codec_type) {
2772 case CODEC_TYPE_RT5650:
2773 dl_sft = 4;
2774 break;
2775 default:
2776 dl_sft = 2;
2777 break;
2778 }
2779
2780 bclk_ms = frame_size > 32;
2781 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
2782
2783 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2784 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
2785 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2786 bclk_ms, pre_div, dai->id);
2787
2788 switch (params_width(params)) {
2789 case 16:
2790 break;
2791 case 20:
2792 val_len = 0x1;
2793 break;
2794 case 24:
2795 val_len = 0x2;
2796 break;
2797 case 8:
2798 val_len = 0x3;
2799 break;
2800 default:
2801 return -EINVAL;
2802 }
2803
2804 switch (dai->id) {
2805 case RT5645_AIF1:
2806 mask_clk = RT5645_I2S_PD1_MASK;
2807 val_clk = pre_div << RT5645_I2S_PD1_SFT;
2808 snd_soc_component_update_bits(component, RT5645_I2S1_SDP,
2809 (0x3 << dl_sft), (val_len << dl_sft));
2810 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk);
2811 break;
2812 case RT5645_AIF2:
2813 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
2814 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
2815 pre_div << RT5645_I2S_PD2_SFT;
2816 snd_soc_component_update_bits(component, RT5645_I2S2_SDP,
2817 (0x3 << dl_sft), (val_len << dl_sft));
2818 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk);
2819 break;
2820 default:
2821 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2822 return -EINVAL;
2823 }
2824
2825 return 0;
2826 }
2827
rt5645_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)2828 static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2829 {
2830 struct snd_soc_component *component = dai->component;
2831 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2832 unsigned int reg_val = 0, pol_sft;
2833
2834 switch (rt5645->codec_type) {
2835 case CODEC_TYPE_RT5650:
2836 pol_sft = 8;
2837 break;
2838 default:
2839 pol_sft = 7;
2840 break;
2841 }
2842
2843 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2844 case SND_SOC_DAIFMT_CBP_CFP:
2845 rt5645->master[dai->id] = 1;
2846 break;
2847 case SND_SOC_DAIFMT_CBC_CFC:
2848 reg_val |= RT5645_I2S_MS_S;
2849 rt5645->master[dai->id] = 0;
2850 break;
2851 default:
2852 return -EINVAL;
2853 }
2854
2855 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2856 case SND_SOC_DAIFMT_NB_NF:
2857 break;
2858 case SND_SOC_DAIFMT_IB_NF:
2859 reg_val |= (1 << pol_sft);
2860 break;
2861 default:
2862 return -EINVAL;
2863 }
2864
2865 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2866 case SND_SOC_DAIFMT_I2S:
2867 break;
2868 case SND_SOC_DAIFMT_LEFT_J:
2869 reg_val |= RT5645_I2S_DF_LEFT;
2870 break;
2871 case SND_SOC_DAIFMT_DSP_A:
2872 reg_val |= RT5645_I2S_DF_PCM_A;
2873 break;
2874 case SND_SOC_DAIFMT_DSP_B:
2875 reg_val |= RT5645_I2S_DF_PCM_B;
2876 break;
2877 default:
2878 return -EINVAL;
2879 }
2880 switch (dai->id) {
2881 case RT5645_AIF1:
2882 snd_soc_component_update_bits(component, RT5645_I2S1_SDP,
2883 RT5645_I2S_MS_MASK | (1 << pol_sft) |
2884 RT5645_I2S_DF_MASK, reg_val);
2885 break;
2886 case RT5645_AIF2:
2887 snd_soc_component_update_bits(component, RT5645_I2S2_SDP,
2888 RT5645_I2S_MS_MASK | (1 << pol_sft) |
2889 RT5645_I2S_DF_MASK, reg_val);
2890 break;
2891 default:
2892 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2893 return -EINVAL;
2894 }
2895 return 0;
2896 }
2897
rt5645_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)2898 static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2899 int clk_id, unsigned int freq, int dir)
2900 {
2901 struct snd_soc_component *component = dai->component;
2902 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2903 unsigned int reg_val = 0;
2904
2905 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2906 return 0;
2907
2908 switch (clk_id) {
2909 case RT5645_SCLK_S_MCLK:
2910 reg_val |= RT5645_SCLK_SRC_MCLK;
2911 break;
2912 case RT5645_SCLK_S_PLL1:
2913 reg_val |= RT5645_SCLK_SRC_PLL1;
2914 break;
2915 case RT5645_SCLK_S_RCCLK:
2916 reg_val |= RT5645_SCLK_SRC_RCCLK;
2917 break;
2918 default:
2919 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2920 return -EINVAL;
2921 }
2922 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2923 RT5645_SCLK_SRC_MASK, reg_val);
2924 rt5645->sysclk = freq;
2925 rt5645->sysclk_src = clk_id;
2926
2927 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2928
2929 return 0;
2930 }
2931
rt5645_set_dai_pll(struct snd_soc_dai * dai,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)2932 static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2933 unsigned int freq_in, unsigned int freq_out)
2934 {
2935 struct snd_soc_component *component = dai->component;
2936 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2937 struct rl6231_pll_code pll_code;
2938 int ret;
2939
2940 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2941 freq_out == rt5645->pll_out)
2942 return 0;
2943
2944 if (!freq_in || !freq_out) {
2945 dev_dbg(component->dev, "PLL disabled\n");
2946
2947 rt5645->pll_in = 0;
2948 rt5645->pll_out = 0;
2949 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2950 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2951 return 0;
2952 }
2953
2954 switch (source) {
2955 case RT5645_PLL1_S_MCLK:
2956 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2957 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2958 break;
2959 case RT5645_PLL1_S_BCLK1:
2960 case RT5645_PLL1_S_BCLK2:
2961 switch (dai->id) {
2962 case RT5645_AIF1:
2963 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2964 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2965 break;
2966 case RT5645_AIF2:
2967 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2968 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2969 break;
2970 default:
2971 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2972 return -EINVAL;
2973 }
2974 break;
2975 default:
2976 dev_err(component->dev, "Unknown PLL source %d\n", source);
2977 return -EINVAL;
2978 }
2979
2980 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2981 if (ret < 0) {
2982 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
2983 return ret;
2984 }
2985
2986 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2987 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2988 pll_code.n_code, pll_code.k_code);
2989
2990 snd_soc_component_write(component, RT5645_PLL_CTRL1,
2991 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2992 snd_soc_component_write(component, RT5645_PLL_CTRL2,
2993 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT) |
2994 (pll_code.m_bp << RT5645_PLL_M_BP_SFT));
2995
2996 rt5645->pll_in = freq_in;
2997 rt5645->pll_out = freq_out;
2998 rt5645->pll_src = source;
2999
3000 return 0;
3001 }
3002
rt5645_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)3003 static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
3004 unsigned int rx_mask, int slots, int slot_width)
3005 {
3006 struct snd_soc_component *component = dai->component;
3007 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3008 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft;
3009 unsigned int mask, val = 0;
3010
3011 switch (rt5645->codec_type) {
3012 case CODEC_TYPE_RT5650:
3013 en_sft = 15;
3014 i_slot_sft = 10;
3015 o_slot_sft = 8;
3016 i_width_sht = 6;
3017 o_width_sht = 4;
3018 mask = 0x8ff0;
3019 break;
3020 default:
3021 en_sft = 14;
3022 i_slot_sft = o_slot_sft = 12;
3023 i_width_sht = o_width_sht = 10;
3024 mask = 0x7c00;
3025 break;
3026 }
3027 if (rx_mask || tx_mask) {
3028 val |= (1 << en_sft);
3029 if (rt5645->codec_type == CODEC_TYPE_RT5645)
3030 snd_soc_component_update_bits(component, RT5645_BASS_BACK,
3031 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
3032 }
3033
3034 switch (slots) {
3035 case 4:
3036 val |= (1 << i_slot_sft) | (1 << o_slot_sft);
3037 break;
3038 case 6:
3039 val |= (2 << i_slot_sft) | (2 << o_slot_sft);
3040 break;
3041 case 8:
3042 val |= (3 << i_slot_sft) | (3 << o_slot_sft);
3043 break;
3044 case 2:
3045 default:
3046 break;
3047 }
3048
3049 switch (slot_width) {
3050 case 20:
3051 val |= (1 << i_width_sht) | (1 << o_width_sht);
3052 break;
3053 case 24:
3054 val |= (2 << i_width_sht) | (2 << o_width_sht);
3055 break;
3056 case 32:
3057 val |= (3 << i_width_sht) | (3 << o_width_sht);
3058 break;
3059 case 16:
3060 default:
3061 break;
3062 }
3063
3064 snd_soc_component_update_bits(component, RT5645_TDM_CTRL_1, mask, val);
3065
3066 return 0;
3067 }
3068
rt5645_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)3069 static int rt5645_set_bias_level(struct snd_soc_component *component,
3070 enum snd_soc_bias_level level)
3071 {
3072 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3073 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
3074
3075 switch (level) {
3076 case SND_SOC_BIAS_PREPARE:
3077 if (SND_SOC_BIAS_STANDBY == snd_soc_dapm_get_bias_level(dapm)) {
3078 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3079 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3080 RT5645_PWR_BG | RT5645_PWR_VREF2,
3081 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3082 RT5645_PWR_BG | RT5645_PWR_VREF2);
3083 mdelay(10);
3084 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3085 RT5645_PWR_FV1 | RT5645_PWR_FV2,
3086 RT5645_PWR_FV1 | RT5645_PWR_FV2);
3087 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1,
3088 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
3089 }
3090 break;
3091
3092 case SND_SOC_BIAS_STANDBY:
3093 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3094 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3095 RT5645_PWR_BG | RT5645_PWR_VREF2,
3096 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3097 RT5645_PWR_BG | RT5645_PWR_VREF2);
3098 mdelay(10);
3099 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3100 RT5645_PWR_FV1 | RT5645_PWR_FV2,
3101 RT5645_PWR_FV1 | RT5645_PWR_FV2);
3102 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) {
3103 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
3104 msleep(40);
3105 if (rt5645->en_button_func)
3106 queue_delayed_work(system_power_efficient_wq,
3107 &rt5645->jack_detect_work,
3108 msecs_to_jiffies(0));
3109 }
3110 break;
3111
3112 case SND_SOC_BIAS_OFF:
3113 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1100);
3114 if (!rt5645->en_button_func)
3115 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1,
3116 RT5645_DIG_GATE_CTRL, 0);
3117 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3118 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3119 RT5645_PWR_BG | RT5645_PWR_VREF2 |
3120 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
3121 break;
3122
3123 default:
3124 break;
3125 }
3126
3127 return 0;
3128 }
3129
rt5645_enable_push_button_irq(struct snd_soc_component * component,bool enable)3130 static void rt5645_enable_push_button_irq(struct snd_soc_component *component,
3131 bool enable)
3132 {
3133 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
3134 int ret;
3135
3136 if (enable) {
3137 snd_soc_dapm_force_enable_pin(dapm, "ADC L power");
3138 snd_soc_dapm_force_enable_pin(dapm, "ADC R power");
3139 snd_soc_dapm_sync(dapm);
3140
3141 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2,
3142 RT5645_EN_4BTN_IL_MASK | RT5645_RST_4BTN_IL_MASK,
3143 RT5645_EN_4BTN_IL_EN | RT5645_RST_4BTN_IL_RST);
3144 usleep_range(10000, 15000);
3145 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2,
3146 RT5645_EN_4BTN_IL_MASK | RT5645_RST_4BTN_IL_MASK,
3147 RT5645_EN_4BTN_IL_EN | RT5645_RST_4BTN_IL_NORM);
3148 msleep(50);
3149 ret = snd_soc_component_read(component, RT5645_INT_IRQ_ST);
3150 pr_debug("%s read %x = %x\n", __func__, RT5645_INT_IRQ_ST,
3151 snd_soc_component_read(component, RT5645_INT_IRQ_ST));
3152 snd_soc_component_write(component, RT5645_INT_IRQ_ST, ret);
3153 ret = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1);
3154 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1,
3155 snd_soc_component_read(component, RT5650_4BTN_IL_CMD1));
3156 snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, ret);
3157 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD1, 0x3, 0x3);
3158 snd_soc_component_update_bits(component,
3159 RT5645_INT_IRQ_ST, 0x8, 0x8);
3160 } else {
3161 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 0x8000, 0x0);
3162 snd_soc_component_update_bits(component, RT5645_INT_IRQ_ST, 0x8, 0x0);
3163
3164 snd_soc_dapm_disable_pin(dapm, "ADC L power");
3165 snd_soc_dapm_disable_pin(dapm, "ADC R power");
3166 snd_soc_dapm_sync(dapm);
3167 }
3168 }
3169
rt5645_jack_detect(struct snd_soc_component * component,int jack_insert)3170 static int rt5645_jack_detect(struct snd_soc_component *component, int jack_insert)
3171 {
3172 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
3173 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3174 unsigned int val;
3175
3176 if (jack_insert) {
3177 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0206);
3178
3179 /* for jack type detect */
3180 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3181 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
3182 snd_soc_dapm_sync(dapm);
3183 if (!snd_soc_card_is_instantiated(component->card)) {
3184 /* Power up necessary bits for JD if dapm is
3185 not ready yet */
3186 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1,
3187 RT5645_PWR_MB | RT5645_PWR_VREF2,
3188 RT5645_PWR_MB | RT5645_PWR_VREF2);
3189 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER,
3190 RT5645_PWR_LDO2, RT5645_PWR_LDO2);
3191 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL,
3192 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET);
3193 }
3194
3195 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
3196 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3197 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
3198 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3199 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
3200 msleep(100);
3201 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3202 RT5645_CBJ_MN_JD, 0);
3203
3204 if (rt5645->gpiod_cbj_sleeve)
3205 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 1);
3206
3207 msleep(600);
3208 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val);
3209 val &= 0x7;
3210 dev_dbg(component->dev, "val = %d\n", val);
3211
3212 if ((val == 1 || val == 2) && !rt5645->pdata.no_headset_mic) {
3213 rt5645->jack_type = SND_JACK_HEADSET;
3214 if (rt5645->en_button_func) {
3215 rt5645_enable_push_button_irq(component, true);
3216 }
3217 } else {
3218 if (rt5645->en_button_func)
3219 rt5645_enable_push_button_irq(component, false);
3220 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
3221 snd_soc_dapm_sync(dapm);
3222 rt5645->jack_type = SND_JACK_HEADPHONE;
3223 if (rt5645->gpiod_cbj_sleeve)
3224 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);
3225 }
3226 if (rt5645->pdata.level_trigger_irq)
3227 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3228 RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR);
3229
3230 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06);
3231 } else { /* jack out */
3232 rt5645->jack_type = 0;
3233
3234 regmap_update_bits(rt5645->regmap, RT5645_HP_VOL,
3235 RT5645_L_MUTE | RT5645_R_MUTE,
3236 RT5645_L_MUTE | RT5645_R_MUTE);
3237 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3238 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
3239 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3240 RT5645_CBJ_BST1_EN, 0);
3241
3242 if (rt5645->en_button_func)
3243 rt5645_enable_push_button_irq(component, false);
3244
3245 if (rt5645->pdata.jd_mode == 0)
3246 snd_soc_dapm_disable_pin(dapm, "LDO2");
3247 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
3248 snd_soc_dapm_sync(dapm);
3249 if (rt5645->pdata.level_trigger_irq)
3250 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3251 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
3252
3253 if (rt5645->gpiod_cbj_sleeve)
3254 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);
3255 }
3256
3257 return rt5645->jack_type;
3258 }
3259
rt5645_button_detect(struct snd_soc_component * component)3260 static int rt5645_button_detect(struct snd_soc_component *component)
3261 {
3262 int btn_type, val;
3263
3264 val = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1);
3265 pr_debug("val=0x%x\n", val);
3266 btn_type = val & 0xfff0;
3267 snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, val);
3268
3269 return btn_type;
3270 }
3271
3272 static irqreturn_t rt5645_irq(int irq, void *data);
3273
rt5645_set_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * hp_jack,struct snd_soc_jack * mic_jack,struct snd_soc_jack * btn_jack)3274 int rt5645_set_jack_detect(struct snd_soc_component *component,
3275 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
3276 struct snd_soc_jack *btn_jack)
3277 {
3278 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3279
3280 rt5645->hp_jack = hp_jack;
3281 rt5645->mic_jack = mic_jack;
3282 rt5645->btn_jack = btn_jack;
3283 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) {
3284 rt5645->en_button_func = true;
3285 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3286 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
3287 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1,
3288 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
3289 regmap_update_bits(rt5645->regmap, RT5645_DEPOP_M1,
3290 RT5645_HP_CB_MASK, RT5645_HP_CB_PU);
3291 }
3292 rt5645_irq(0, rt5645);
3293
3294 return 0;
3295 }
3296 EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
3297
rt5645_component_set_jack(struct snd_soc_component * component,struct snd_soc_jack * hs_jack,void * data)3298 static int rt5645_component_set_jack(struct snd_soc_component *component,
3299 struct snd_soc_jack *hs_jack, void *data)
3300 {
3301 struct snd_soc_jack *mic_jack = NULL;
3302 struct snd_soc_jack *btn_jack = NULL;
3303 int type;
3304
3305 if (hs_jack) {
3306 type = *(int *)data;
3307
3308 if (type & SND_JACK_MICROPHONE)
3309 mic_jack = hs_jack;
3310 if (type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3311 SND_JACK_BTN_2 | SND_JACK_BTN_3))
3312 btn_jack = hs_jack;
3313 }
3314
3315 return rt5645_set_jack_detect(component, hs_jack, mic_jack, btn_jack);
3316 }
3317
rt5645_jack_detect_work(struct work_struct * work)3318 static void rt5645_jack_detect_work(struct work_struct *work)
3319 {
3320 struct rt5645_priv *rt5645 =
3321 container_of(work, struct rt5645_priv, jack_detect_work.work);
3322 int val, btn_type, gpio_state = 0, report = 0;
3323
3324 if (!rt5645->component)
3325 return;
3326
3327 scoped_guard(mutex, &rt5645->jd_mutex) {
3328 switch (rt5645->pdata.jd_mode) {
3329 case 0: /* Not using rt5645 JD */
3330 if (rt5645->gpiod_hp_det) {
3331 gpio_state = gpiod_get_value(rt5645->gpiod_hp_det);
3332 if (rt5645->pdata.inv_hp_pol)
3333 gpio_state ^= 1;
3334 dev_dbg(rt5645->component->dev, "gpio_state = %d\n",
3335 gpio_state);
3336 report = rt5645_jack_detect(rt5645->component, gpio_state);
3337 }
3338 snd_soc_jack_report(rt5645->hp_jack,
3339 report, SND_JACK_HEADPHONE);
3340 snd_soc_jack_report(rt5645->mic_jack,
3341 report, SND_JACK_MICROPHONE);
3342 return;
3343 case 4:
3344 val = snd_soc_component_read(rt5645->component, RT5645_A_JD_CTRL1) & 0x0020;
3345 break;
3346 default: /* read rt5645 jd1_1 status */
3347 val = snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x1000;
3348 break;
3349 }
3350
3351 if (!val && rt5645->jack_type == 0) { /* jack in */
3352 report = rt5645_jack_detect(rt5645->component, 1);
3353 } else if (!val && rt5645->jack_type == SND_JACK_HEADSET) {
3354 /* for push button and jack out */
3355 btn_type = 0;
3356 if (snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x4) {
3357 /* button pressed */
3358 report = SND_JACK_HEADSET;
3359 btn_type = rt5645_button_detect(rt5645->component);
3360 /*
3361 * rt5650 can report three kinds of button behavior,
3362 * one click, double click and hold. However,
3363 * currently we will report button pressed/released
3364 * event. So all the three button behaviors are
3365 * treated as button pressed.
3366 */
3367 switch (btn_type) {
3368 case 0x8000:
3369 case 0x4000:
3370 case 0x2000:
3371 report |= SND_JACK_BTN_0;
3372 break;
3373 case 0x1000:
3374 case 0x0800:
3375 case 0x0400:
3376 report |= SND_JACK_BTN_1;
3377 break;
3378 case 0x0200:
3379 case 0x0100:
3380 case 0x0080:
3381 report |= SND_JACK_BTN_2;
3382 break;
3383 case 0x0040:
3384 case 0x0020:
3385 case 0x0010:
3386 report |= SND_JACK_BTN_3;
3387 break;
3388 case 0x0000: /* unpressed */
3389 break;
3390 default:
3391 dev_err(rt5645->component->dev,
3392 "Unexpected button code 0x%04x\n",
3393 btn_type);
3394 break;
3395 }
3396 }
3397 if (btn_type == 0)/* button release */
3398 report = rt5645->jack_type;
3399 else
3400 mod_timer(&rt5645->btn_check_timer,
3401 msecs_to_jiffies(100));
3402 } else {
3403 /* jack out */
3404 report = 0;
3405 snd_soc_component_update_bits(rt5645->component,
3406 RT5645_INT_IRQ_ST, 0x1, 0x0);
3407 rt5645_jack_detect(rt5645->component, 0);
3408 }
3409 }
3410
3411 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE);
3412 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE);
3413 if (rt5645->en_button_func)
3414 snd_soc_jack_report(rt5645->btn_jack,
3415 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3416 SND_JACK_BTN_2 | SND_JACK_BTN_3);
3417 }
3418
rt5645_rcclock_work(struct work_struct * work)3419 static void rt5645_rcclock_work(struct work_struct *work)
3420 {
3421 struct rt5645_priv *rt5645 =
3422 container_of(work, struct rt5645_priv, rcclock_work.work);
3423
3424 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3425 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD);
3426 }
3427
rt5645_irq(int irq,void * data)3428 static irqreturn_t rt5645_irq(int irq, void *data)
3429 {
3430 struct rt5645_priv *rt5645 = data;
3431
3432 queue_delayed_work(system_power_efficient_wq,
3433 &rt5645->jack_detect_work, msecs_to_jiffies(250));
3434
3435 return IRQ_HANDLED;
3436 }
3437
rt5645_btn_check_callback(struct timer_list * t)3438 static void rt5645_btn_check_callback(struct timer_list *t)
3439 {
3440 struct rt5645_priv *rt5645 = timer_container_of(rt5645, t,
3441 btn_check_timer);
3442
3443 queue_delayed_work(system_power_efficient_wq,
3444 &rt5645->jack_detect_work, msecs_to_jiffies(5));
3445 }
3446
rt5645_probe(struct snd_soc_component * component)3447 static int rt5645_probe(struct snd_soc_component *component)
3448 {
3449 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
3450 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3451
3452 rt5645->component = component;
3453
3454 switch (rt5645->codec_type) {
3455 case CODEC_TYPE_RT5645:
3456 snd_soc_dapm_new_controls(dapm,
3457 rt5645_specific_dapm_widgets,
3458 ARRAY_SIZE(rt5645_specific_dapm_widgets));
3459 snd_soc_dapm_add_routes(dapm,
3460 rt5645_specific_dapm_routes,
3461 ARRAY_SIZE(rt5645_specific_dapm_routes));
3462 if (rt5645->v_id < 3) {
3463 snd_soc_dapm_add_routes(dapm,
3464 rt5645_old_dapm_routes,
3465 ARRAY_SIZE(rt5645_old_dapm_routes));
3466 }
3467 break;
3468 case CODEC_TYPE_RT5650:
3469 snd_soc_dapm_new_controls(dapm,
3470 rt5650_specific_dapm_widgets,
3471 ARRAY_SIZE(rt5650_specific_dapm_widgets));
3472 snd_soc_dapm_add_routes(dapm,
3473 rt5650_specific_dapm_routes,
3474 ARRAY_SIZE(rt5650_specific_dapm_routes));
3475 break;
3476 }
3477
3478 snd_soc_dapm_force_bias_level(dapm, SND_SOC_BIAS_OFF);
3479
3480 /* for JD function */
3481 if (rt5645->pdata.jd_mode) {
3482 snd_soc_dapm_force_enable_pin(dapm, "JD Power");
3483 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3484 snd_soc_dapm_sync(dapm);
3485 }
3486
3487 if (rt5645->pdata.long_name)
3488 component->card->long_name = rt5645->pdata.long_name;
3489
3490 rt5645->eq_param = devm_kcalloc(component->dev,
3491 RT5645_HWEQ_NUM, sizeof(struct rt5645_eq_param_s),
3492 GFP_KERNEL);
3493
3494 if (!rt5645->eq_param)
3495 return -ENOMEM;
3496
3497 /* no machine driver to call rt5645_set_jack_detect(), so detect here */
3498 if (!rt5645->pdata.jd_mode && rt5645->gpiod_hp_det)
3499 rt5645_irq(0, rt5645);
3500
3501 return 0;
3502 }
3503
rt5645_remove(struct snd_soc_component * component)3504 static void rt5645_remove(struct snd_soc_component *component)
3505 {
3506 rt5645_reset(component);
3507 }
3508
3509 #ifdef CONFIG_PM
rt5645_suspend(struct snd_soc_component * component)3510 static int rt5645_suspend(struct snd_soc_component *component)
3511 {
3512 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3513
3514 regcache_cache_only(rt5645->regmap, true);
3515 regcache_mark_dirty(rt5645->regmap);
3516
3517 return 0;
3518 }
3519
rt5645_resume(struct snd_soc_component * component)3520 static int rt5645_resume(struct snd_soc_component *component)
3521 {
3522 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3523 int ret;
3524
3525 regcache_cache_only(rt5645->regmap, false);
3526 ret = regcache_sync(rt5645->regmap);
3527 if (ret) {
3528 regcache_cache_only(rt5645->regmap, true);
3529 regcache_mark_dirty(rt5645->regmap);
3530 return ret;
3531 }
3532
3533 return 0;
3534 }
3535 #else
3536 #define rt5645_suspend NULL
3537 #define rt5645_resume NULL
3538 #endif
3539
3540 #define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3541 #define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3542 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3543
3544 static const struct snd_soc_dai_ops rt5645_aif_dai_ops = {
3545 .hw_params = rt5645_hw_params,
3546 .set_fmt = rt5645_set_dai_fmt,
3547 .set_sysclk = rt5645_set_dai_sysclk,
3548 .set_tdm_slot = rt5645_set_tdm_slot,
3549 .set_pll = rt5645_set_dai_pll,
3550 };
3551
3552 static struct snd_soc_dai_driver rt5645_dai[] = {
3553 {
3554 .name = "rt5645-aif1",
3555 .id = RT5645_AIF1,
3556 .playback = {
3557 .stream_name = "AIF1 Playback",
3558 .channels_min = 1,
3559 .channels_max = 2,
3560 .rates = RT5645_STEREO_RATES,
3561 .formats = RT5645_FORMATS,
3562 },
3563 .capture = {
3564 .stream_name = "AIF1 Capture",
3565 .channels_min = 1,
3566 .channels_max = 4,
3567 .rates = RT5645_STEREO_RATES,
3568 .formats = RT5645_FORMATS,
3569 },
3570 .ops = &rt5645_aif_dai_ops,
3571 },
3572 {
3573 .name = "rt5645-aif2",
3574 .id = RT5645_AIF2,
3575 .playback = {
3576 .stream_name = "AIF2 Playback",
3577 .channels_min = 1,
3578 .channels_max = 2,
3579 .rates = RT5645_STEREO_RATES,
3580 .formats = RT5645_FORMATS,
3581 },
3582 .capture = {
3583 .stream_name = "AIF2 Capture",
3584 .channels_min = 1,
3585 .channels_max = 2,
3586 .rates = RT5645_STEREO_RATES,
3587 .formats = RT5645_FORMATS,
3588 },
3589 .ops = &rt5645_aif_dai_ops,
3590 },
3591 };
3592
3593 static const struct snd_soc_component_driver soc_component_dev_rt5645 = {
3594 .probe = rt5645_probe,
3595 .remove = rt5645_remove,
3596 .suspend = rt5645_suspend,
3597 .resume = rt5645_resume,
3598 .set_bias_level = rt5645_set_bias_level,
3599 .controls = rt5645_snd_controls,
3600 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
3601 .dapm_widgets = rt5645_dapm_widgets,
3602 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
3603 .dapm_routes = rt5645_dapm_routes,
3604 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
3605 .set_jack = rt5645_component_set_jack,
3606 .use_pmdown_time = 1,
3607 .endianness = 1,
3608 };
3609
3610 static const struct regmap_config rt5645_regmap = {
3611 .reg_bits = 8,
3612 .val_bits = 16,
3613 .use_single_read = true,
3614 .use_single_write = true,
3615 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3616 RT5645_PR_SPACING),
3617 .volatile_reg = rt5645_volatile_register,
3618 .readable_reg = rt5645_readable_register,
3619
3620 .cache_type = REGCACHE_MAPLE,
3621 .reg_defaults = rt5645_reg,
3622 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
3623 .ranges = rt5645_ranges,
3624 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3625 };
3626
3627 static const struct regmap_config rt5650_regmap = {
3628 .reg_bits = 8,
3629 .val_bits = 16,
3630 .use_single_read = true,
3631 .use_single_write = true,
3632 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3633 RT5645_PR_SPACING),
3634 .volatile_reg = rt5645_volatile_register,
3635 .readable_reg = rt5645_readable_register,
3636
3637 .cache_type = REGCACHE_MAPLE,
3638 .reg_defaults = rt5650_reg,
3639 .num_reg_defaults = ARRAY_SIZE(rt5650_reg),
3640 .ranges = rt5645_ranges,
3641 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3642 };
3643
3644 static const struct regmap_config temp_regmap = {
3645 .name="nocache",
3646 .reg_bits = 8,
3647 .val_bits = 16,
3648 .use_single_read = true,
3649 .use_single_write = true,
3650 .max_register = RT5645_VENDOR_ID2 + 1,
3651 .cache_type = REGCACHE_NONE,
3652 };
3653
3654 static const struct i2c_device_id rt5645_i2c_id[] = {
3655 { .name = "rt5645" },
3656 { .name = "rt5650" },
3657 { }
3658 };
3659 MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
3660
3661 #ifdef CONFIG_OF
3662 static const struct of_device_id rt5645_of_match[] = {
3663 { .compatible = "realtek,rt5645", },
3664 { .compatible = "realtek,rt5650", },
3665 { }
3666 };
3667 MODULE_DEVICE_TABLE(of, rt5645_of_match);
3668 #endif
3669
3670 #ifdef CONFIG_ACPI
3671 static const struct acpi_device_id rt5645_acpi_match[] = {
3672 { "10EC3270" },
3673 { "10EC5640" },
3674 { "10EC5645" },
3675 { "10EC5648" },
3676 { "10EC5650" },
3677 { }
3678 };
3679 MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
3680 #endif
3681
3682 static const struct rt5645_platform_data intel_braswell_platform_data = {
3683 .dmic1_data_pin = RT5645_DMIC1_DISABLE,
3684 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3685 .jd_mode = 3,
3686 };
3687
3688 static const struct rt5645_platform_data buddy_platform_data = {
3689 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
3690 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3691 .jd_mode = 4,
3692 .level_trigger_irq = true,
3693 };
3694
3695 static const struct rt5645_platform_data gpd_win_platform_data = {
3696 .jd_mode = 3,
3697 .inv_jd1_1 = true,
3698 .mono_speaker = true,
3699 .long_name = "gpd-win-pocket-rt5645",
3700 /* The GPD pocket has a diff. mic, for the win this does not matter. */
3701 .in2_diff = true,
3702 };
3703
3704 static const struct rt5645_platform_data asus_t100ha_platform_data = {
3705 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N,
3706 .dmic2_data_pin = RT5645_DMIC2_DISABLE,
3707 .jd_mode = 3,
3708 .inv_jd1_1 = true,
3709 };
3710
3711 static const struct rt5645_platform_data asus_t101ha_platform_data = {
3712 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N,
3713 .dmic2_data_pin = RT5645_DMIC2_DISABLE,
3714 .jd_mode = 3,
3715 };
3716
3717 static const struct rt5645_platform_data lenovo_ideapad_miix_310_pdata = {
3718 .jd_mode = 3,
3719 .in2_diff = true,
3720 };
3721
3722 static const struct rt5645_platform_data jd_mode3_monospk_platform_data = {
3723 .jd_mode = 3,
3724 .mono_speaker = true,
3725 };
3726
3727 static const struct rt5645_platform_data jd_mode3_inv_data = {
3728 .jd_mode = 3,
3729 .inv_jd1_1 = true,
3730 };
3731
3732 static const struct rt5645_platform_data jd_mode3_platform_data = {
3733 .jd_mode = 3,
3734 };
3735
3736 static const struct rt5645_platform_data lattepanda_board_platform_data = {
3737 .jd_mode = 2,
3738 .inv_jd1_1 = true
3739 };
3740
3741 static const struct rt5645_platform_data kahlee_platform_data = {
3742 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
3743 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3744 .jd_mode = 3,
3745 };
3746
3747 static const struct rt5645_platform_data ecs_ef20_platform_data = {
3748 .dmic1_data_pin = RT5645_DMIC1_DISABLE,
3749 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3750 .inv_hp_pol = 1,
3751 };
3752
3753 static const struct acpi_gpio_params ef20_hp_detect = { 1, 0, false };
3754
3755 static const struct acpi_gpio_mapping cht_rt5645_ef20_gpios[] = {
3756 { "hp-detect-gpios", &ef20_hp_detect, 1 },
3757 { },
3758 };
3759
cht_rt5645_ef20_quirk_cb(const struct dmi_system_id * id)3760 static int cht_rt5645_ef20_quirk_cb(const struct dmi_system_id *id)
3761 {
3762 cht_rt5645_gpios = cht_rt5645_ef20_gpios;
3763 return 1;
3764 }
3765
3766 static const struct dmi_system_id dmi_platform_data[] = {
3767 {
3768 .ident = "Chrome Buddy",
3769 .matches = {
3770 DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"),
3771 },
3772 .driver_data = (void *)&buddy_platform_data,
3773 },
3774 {
3775 .ident = "Intel Strago",
3776 .matches = {
3777 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"),
3778 },
3779 .driver_data = (void *)&intel_braswell_platform_data,
3780 },
3781 {
3782 .ident = "Google Chrome",
3783 .matches = {
3784 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
3785 },
3786 .driver_data = (void *)&intel_braswell_platform_data,
3787 },
3788 {
3789 .ident = "Google Setzer",
3790 .matches = {
3791 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
3792 },
3793 .driver_data = (void *)&intel_braswell_platform_data,
3794 },
3795 {
3796 .ident = "Microsoft Surface 3",
3797 .matches = {
3798 DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"),
3799 },
3800 .driver_data = (void *)&intel_braswell_platform_data,
3801 },
3802 {
3803 /*
3804 * Match for the GPDwin which unfortunately uses somewhat
3805 * generic dmi strings, which is why we test for 4 strings.
3806 * Comparing against 23 other byt/cht boards, board_vendor
3807 * and board_name are unique to the GPDwin, where as only one
3808 * other board has the same board_serial and 3 others have
3809 * the same default product_name. Also the GPDwin is the
3810 * only device to have both board_ and product_name not set.
3811 */
3812 .ident = "GPD Win / Pocket",
3813 .matches = {
3814 DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
3815 DMI_MATCH(DMI_BOARD_NAME, "Default string"),
3816 DMI_MATCH(DMI_BOARD_SERIAL, "Default string"),
3817 DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
3818 },
3819 .driver_data = (void *)&gpd_win_platform_data,
3820 },
3821 {
3822 .ident = "ASUS T100HAN",
3823 .matches = {
3824 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
3825 DMI_MATCH(DMI_PRODUCT_NAME, "T100HAN"),
3826 },
3827 .driver_data = (void *)&asus_t100ha_platform_data,
3828 },
3829 {
3830 .ident = "ASUS T101HA",
3831 .matches = {
3832 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
3833 DMI_MATCH(DMI_PRODUCT_NAME, "T101HA"),
3834 },
3835 .driver_data = (void *)&asus_t101ha_platform_data,
3836 },
3837 {
3838 .ident = "MINIX Z83-4",
3839 .matches = {
3840 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MINIX"),
3841 DMI_MATCH(DMI_PRODUCT_NAME, "Z83-4"),
3842 },
3843 .driver_data = (void *)&jd_mode3_platform_data,
3844 },
3845 {
3846 .ident = "Teclast X80 Pro",
3847 .matches = {
3848 DMI_MATCH(DMI_SYS_VENDOR, "TECLAST"),
3849 DMI_MATCH(DMI_PRODUCT_NAME, "X80 Pro"),
3850 },
3851 .driver_data = (void *)&jd_mode3_monospk_platform_data,
3852 },
3853 {
3854 .ident = "Lenovo Ideapad Miix 310",
3855 .matches = {
3856 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"),
3857 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80SG"),
3858 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "MIIX 310-10ICR"),
3859 },
3860 .driver_data = (void *)&lenovo_ideapad_miix_310_pdata,
3861 },
3862 {
3863 .ident = "Lenovo Ideapad Miix 320",
3864 .matches = {
3865 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"),
3866 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80XF"),
3867 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
3868 },
3869 .driver_data = (void *)&intel_braswell_platform_data,
3870 },
3871 {
3872 .ident = "LattePanda board",
3873 .matches = {
3874 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
3875 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
3876 DMI_EXACT_MATCH(DMI_BOARD_VERSION, "Default string"),
3877 /*
3878 * Above strings are too generic, LattePanda BIOS versions for
3879 * all 4 hw revisions are:
3880 * DF-BI-7-S70CR100-*
3881 * DF-BI-7-S70CR110-*
3882 * DF-BI-7-S70CR200-*
3883 * LP-BS-7-S70CR700-*
3884 * Do a partial match for S70CR to avoid false positive matches.
3885 */
3886 DMI_MATCH(DMI_BIOS_VERSION, "S70CR"),
3887 },
3888 .driver_data = (void *)&lattepanda_board_platform_data,
3889 },
3890 {
3891 .ident = "Chrome Kahlee",
3892 .matches = {
3893 DMI_MATCH(DMI_PRODUCT_NAME, "Kahlee"),
3894 },
3895 .driver_data = (void *)&kahlee_platform_data,
3896 },
3897 {
3898 .ident = "Medion E1239T",
3899 .matches = {
3900 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MEDION"),
3901 DMI_MATCH(DMI_PRODUCT_NAME, "E1239T MD60568"),
3902 },
3903 .driver_data = (void *)&intel_braswell_platform_data,
3904 },
3905 {
3906 .ident = "EF20",
3907 .callback = cht_rt5645_ef20_quirk_cb,
3908 .matches = {
3909 DMI_MATCH(DMI_PRODUCT_NAME, "EF20"),
3910 },
3911 .driver_data = (void *)&ecs_ef20_platform_data,
3912 },
3913 {
3914 .ident = "Acer Switch V 10 (SW5-017)",
3915 .matches = {
3916 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Acer"),
3917 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "SW5-017"),
3918 },
3919 .driver_data = (void *)&intel_braswell_platform_data,
3920 },
3921 {
3922 .ident = "Meegopad T08",
3923 .matches = {
3924 DMI_MATCH(DMI_SYS_VENDOR, "Default string"),
3925 DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
3926 DMI_MATCH(DMI_BOARD_NAME, "T3 MRD"),
3927 DMI_MATCH(DMI_BOARD_VERSION, "V1.1"),
3928 },
3929 .driver_data = (void *)&jd_mode3_inv_data,
3930 },
3931 { }
3932 };
3933
rt5645_check_dp(struct device * dev)3934 static bool rt5645_check_dp(struct device *dev)
3935 {
3936 if (device_property_present(dev, "realtek,in2-differential") ||
3937 device_property_present(dev, "realtek,dmic1-data-pin") ||
3938 device_property_present(dev, "realtek,dmic2-data-pin") ||
3939 device_property_present(dev, "realtek,jd-mode"))
3940 return true;
3941
3942 return false;
3943 }
3944
rt5645_parse_dt(struct device * dev,struct rt5645_platform_data * pdata)3945 static void rt5645_parse_dt(struct device *dev, struct rt5645_platform_data *pdata)
3946 {
3947 pdata->in2_diff = device_property_read_bool(dev, "realtek,in2-differential");
3948 device_property_read_u32(dev, "realtek,dmic1-data-pin", &pdata->dmic1_data_pin);
3949 device_property_read_u32(dev, "realtek,dmic2-data-pin", &pdata->dmic2_data_pin);
3950 device_property_read_u32(dev, "realtek,jd-mode", &pdata->jd_mode);
3951 }
3952
rt5645_get_pdata(struct device * codec_dev,struct rt5645_platform_data * pdata)3953 static void rt5645_get_pdata(struct device *codec_dev, struct rt5645_platform_data *pdata)
3954 {
3955 const struct dmi_system_id *dmi_data;
3956
3957 dmi_data = dmi_first_match(dmi_platform_data);
3958 if (dmi_data) {
3959 dev_info(codec_dev, "Detected %s platform\n", dmi_data->ident);
3960 *pdata = *((struct rt5645_platform_data *)dmi_data->driver_data);
3961 } else if (rt5645_check_dp(codec_dev)) {
3962 rt5645_parse_dt(codec_dev, pdata);
3963 } else {
3964 *pdata = jd_mode3_platform_data;
3965 }
3966
3967 if (quirk != -1) {
3968 pdata->in2_diff = QUIRK_IN2_DIFF(quirk);
3969 pdata->level_trigger_irq = QUIRK_LEVEL_IRQ(quirk);
3970 pdata->inv_jd1_1 = QUIRK_INV_JD1_1(quirk);
3971 pdata->inv_hp_pol = QUIRK_INV_HP_POL(quirk);
3972 pdata->jd_mode = QUIRK_JD_MODE(quirk);
3973 pdata->dmic1_data_pin = QUIRK_DMIC1_DATA_PIN(quirk);
3974 pdata->dmic2_data_pin = QUIRK_DMIC2_DATA_PIN(quirk);
3975 }
3976 }
3977
rt5645_components(struct device * codec_dev)3978 const char *rt5645_components(struct device *codec_dev)
3979 {
3980 struct rt5645_platform_data pdata = { };
3981 static char buf[32];
3982 const char *mic;
3983 int spk = 2;
3984
3985 rt5645_get_pdata(codec_dev, &pdata);
3986
3987 if (pdata.mono_speaker)
3988 spk = 1;
3989
3990 if (pdata.dmic1_data_pin && pdata.dmic2_data_pin)
3991 mic = "dmics12";
3992 else if (pdata.dmic1_data_pin)
3993 mic = "dmic1";
3994 else if (pdata.dmic2_data_pin)
3995 mic = "dmic2";
3996 else
3997 mic = "in2";
3998
3999 snprintf(buf, sizeof(buf), "cfg-spk:%d cfg-mic:%s", spk, mic);
4000
4001 return buf;
4002 }
4003 EXPORT_SYMBOL_GPL(rt5645_components);
4004
rt5645_i2c_probe(struct i2c_client * i2c)4005 static int rt5645_i2c_probe(struct i2c_client *i2c)
4006 {
4007 struct rt5645_priv *rt5645;
4008 int ret, i;
4009 unsigned int val;
4010 struct regmap *regmap;
4011
4012 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
4013 GFP_KERNEL);
4014 if (rt5645 == NULL)
4015 return -ENOMEM;
4016
4017 rt5645->i2c = i2c;
4018 i2c_set_clientdata(i2c, rt5645);
4019 rt5645_get_pdata(&i2c->dev, &rt5645->pdata);
4020
4021 if (has_acpi_companion(&i2c->dev)) {
4022 if (cht_rt5645_gpios) {
4023 if (devm_acpi_dev_add_driver_gpios(&i2c->dev, cht_rt5645_gpios))
4024 dev_dbg(&i2c->dev, "Failed to add driver gpios\n");
4025 }
4026
4027 /* The ALC3270 package has the headset-mic pin not-connected */
4028 if (acpi_dev_hid_uid_match(ACPI_COMPANION(&i2c->dev), "10EC3270", NULL))
4029 rt5645->pdata.no_headset_mic = true;
4030 }
4031
4032 rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect",
4033 GPIOD_IN);
4034
4035 if (IS_ERR(rt5645->gpiod_hp_det)) {
4036 dev_info(&i2c->dev, "failed to initialize gpiod\n");
4037 ret = PTR_ERR(rt5645->gpiod_hp_det);
4038 /*
4039 * Continue if optional gpiod is missing, bail for all other
4040 * errors, including -EPROBE_DEFER
4041 */
4042 if (ret != -ENOENT)
4043 return ret;
4044 }
4045
4046 rt5645->gpiod_cbj_sleeve = devm_gpiod_get_optional(&i2c->dev, "cbj-sleeve",
4047 GPIOD_OUT_LOW);
4048
4049 if (IS_ERR(rt5645->gpiod_cbj_sleeve)) {
4050 ret = PTR_ERR(rt5645->gpiod_cbj_sleeve);
4051 dev_info(&i2c->dev, "failed to initialize gpiod, ret=%d\n", ret);
4052 if (ret != -ENOENT)
4053 return ret;
4054 }
4055
4056 for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++)
4057 rt5645->supplies[i].supply = rt5645_supply_names[i];
4058
4059 ret = devm_regulator_bulk_get(&i2c->dev,
4060 ARRAY_SIZE(rt5645->supplies),
4061 rt5645->supplies);
4062 if (ret) {
4063 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
4064 return ret;
4065 }
4066
4067 ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies),
4068 rt5645->supplies);
4069 if (ret) {
4070 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
4071 return ret;
4072 }
4073
4074 regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
4075 if (IS_ERR(regmap)) {
4076 ret = PTR_ERR(regmap);
4077 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
4078 ret);
4079 goto err_enable;
4080 }
4081
4082 /*
4083 * Read after 400msec, as it is the interval required between
4084 * read and power On.
4085 */
4086 msleep(TIME_TO_POWER_MS);
4087 ret = regmap_read(regmap, RT5645_VENDOR_ID2, &val);
4088 if (ret < 0) {
4089 dev_err(&i2c->dev, "Failed to read: 0x%02X\n, ret = %d", RT5645_VENDOR_ID2, ret);
4090 goto err_enable;
4091 }
4092
4093 switch (val) {
4094 case RT5645_DEVICE_ID:
4095 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
4096 rt5645->codec_type = CODEC_TYPE_RT5645;
4097 break;
4098 case RT5650_DEVICE_ID:
4099 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5650_regmap);
4100 rt5645->codec_type = CODEC_TYPE_RT5650;
4101 break;
4102 default:
4103 dev_err(&i2c->dev,
4104 "Device with ID register %#x is not rt5645 or rt5650\n",
4105 val);
4106 ret = -ENODEV;
4107 goto err_enable;
4108 }
4109
4110 if (IS_ERR(rt5645->regmap)) {
4111 ret = PTR_ERR(rt5645->regmap);
4112 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4113 ret);
4114 goto err_enable;
4115 }
4116
4117 regmap_write(rt5645->regmap, RT5645_RESET, 0);
4118
4119 regmap_read(regmap, RT5645_VENDOR_ID, &val);
4120 rt5645->v_id = val & 0xff;
4121
4122 regmap_write(rt5645->regmap, RT5645_AD_DA_MIXER, 0x8080);
4123
4124 ret = regmap_multi_reg_write(rt5645->regmap, init_list,
4125 ARRAY_SIZE(init_list));
4126 if (ret != 0)
4127 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
4128
4129 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
4130 ret = regmap_multi_reg_write(rt5645->regmap, rt5650_init_list,
4131 ARRAY_SIZE(rt5650_init_list));
4132 if (ret != 0)
4133 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
4134 ret);
4135 }
4136
4137 regmap_update_bits(rt5645->regmap, RT5645_CLSD_OUT_CTRL, 0xc0, 0xc0);
4138
4139 if (rt5645->pdata.in2_diff)
4140 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
4141 RT5645_IN_DF2, RT5645_IN_DF2);
4142
4143 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {
4144 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4145 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
4146 }
4147 switch (rt5645->pdata.dmic1_data_pin) {
4148 case RT5645_DMIC_DATA_IN2N:
4149 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4150 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
4151 break;
4152
4153 case RT5645_DMIC_DATA_GPIO5:
4154 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4155 RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO);
4156 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4157 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
4158 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4159 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
4160 break;
4161
4162 case RT5645_DMIC_DATA_GPIO11:
4163 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4164 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
4165 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4166 RT5645_GP11_PIN_MASK,
4167 RT5645_GP11_PIN_DMIC1_SDA);
4168 break;
4169
4170 default:
4171 break;
4172 }
4173
4174 switch (rt5645->pdata.dmic2_data_pin) {
4175 case RT5645_DMIC_DATA_IN2P:
4176 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4177 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
4178 break;
4179
4180 case RT5645_DMIC_DATA_GPIO6:
4181 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4182 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
4183 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4184 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
4185 break;
4186
4187 case RT5645_DMIC_DATA_GPIO10:
4188 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4189 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
4190 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4191 RT5645_GP10_PIN_MASK,
4192 RT5645_GP10_PIN_DMIC2_SDA);
4193 break;
4194
4195 case RT5645_DMIC_DATA_GPIO12:
4196 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4197 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
4198 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4199 RT5645_GP12_PIN_MASK,
4200 RT5645_GP12_PIN_DMIC2_SDA);
4201 break;
4202
4203 default:
4204 break;
4205 }
4206
4207 if (rt5645->pdata.jd_mode) {
4208 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
4209 RT5645_IRQ_CLK_GATE_CTRL,
4210 RT5645_IRQ_CLK_GATE_CTRL);
4211 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
4212 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
4213 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
4214 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
4215 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
4216 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
4217 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
4218 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
4219 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
4220 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
4221 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4222 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
4223 switch (rt5645->pdata.jd_mode) {
4224 case 1:
4225 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
4226 RT5645_JD1_MODE_MASK,
4227 RT5645_JD1_MODE_0);
4228 break;
4229 case 2:
4230 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
4231 RT5645_JD1_MODE_MASK,
4232 RT5645_JD1_MODE_1);
4233 break;
4234 case 3:
4235 case 4:
4236 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
4237 RT5645_JD1_MODE_MASK,
4238 RT5645_JD1_MODE_2);
4239 break;
4240 default:
4241 break;
4242 }
4243 if (rt5645->pdata.inv_jd1_1) {
4244 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
4245 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
4246 }
4247 }
4248
4249 regmap_update_bits(rt5645->regmap, RT5645_ADDA_CLK1,
4250 RT5645_I2S_PD1_MASK, RT5645_I2S_PD1_2);
4251
4252 if (rt5645->pdata.level_trigger_irq) {
4253 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
4254 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
4255 }
4256 timer_setup(&rt5645->btn_check_timer, rt5645_btn_check_callback, 0);
4257
4258 mutex_init(&rt5645->jd_mutex);
4259 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
4260 INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work);
4261
4262 if (rt5645->i2c->irq) {
4263 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
4264 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4265 | IRQF_ONESHOT, "rt5645", rt5645);
4266 if (ret) {
4267 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret);
4268 goto err_enable;
4269 }
4270 }
4271
4272 ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5645,
4273 rt5645_dai, ARRAY_SIZE(rt5645_dai));
4274 if (ret)
4275 goto err_irq;
4276
4277 return 0;
4278
4279 err_irq:
4280 if (rt5645->i2c->irq)
4281 free_irq(rt5645->i2c->irq, rt5645);
4282 err_enable:
4283 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
4284 return ret;
4285 }
4286
rt5645_i2c_remove(struct i2c_client * i2c)4287 static void rt5645_i2c_remove(struct i2c_client *i2c)
4288 {
4289 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
4290
4291 if (i2c->irq)
4292 free_irq(i2c->irq, rt5645);
4293
4294 /*
4295 * Since the rt5645_btn_check_callback() can queue jack_detect_work,
4296 * the timer need to be delted first
4297 */
4298 timer_delete_sync(&rt5645->btn_check_timer);
4299
4300 cancel_delayed_work_sync(&rt5645->jack_detect_work);
4301 cancel_delayed_work_sync(&rt5645->rcclock_work);
4302
4303 if (rt5645->gpiod_cbj_sleeve)
4304 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);
4305
4306 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
4307 }
4308
rt5645_i2c_shutdown(struct i2c_client * i2c)4309 static void rt5645_i2c_shutdown(struct i2c_client *i2c)
4310 {
4311 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
4312
4313 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
4314 RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND);
4315 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD,
4316 RT5645_CBJ_MN_JD);
4317 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN,
4318 0);
4319 msleep(20);
4320 regmap_write(rt5645->regmap, RT5645_RESET, 0);
4321
4322 if (rt5645->gpiod_cbj_sleeve)
4323 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);
4324 }
4325
rt5645_sys_suspend(struct device * dev)4326 static int rt5645_sys_suspend(struct device *dev)
4327 {
4328 struct rt5645_priv *rt5645 = dev_get_drvdata(dev);
4329
4330 timer_delete_sync(&rt5645->btn_check_timer);
4331 cancel_delayed_work_sync(&rt5645->jack_detect_work);
4332 cancel_delayed_work_sync(&rt5645->rcclock_work);
4333
4334 regcache_cache_only(rt5645->regmap, true);
4335 regcache_mark_dirty(rt5645->regmap);
4336 return 0;
4337 }
4338
rt5645_sys_resume(struct device * dev)4339 static int rt5645_sys_resume(struct device *dev)
4340 {
4341 struct rt5645_priv *rt5645 = dev_get_drvdata(dev);
4342 int ret;
4343
4344 regcache_cache_only(rt5645->regmap, false);
4345 ret = regcache_sync(rt5645->regmap);
4346 if (ret) {
4347 regcache_cache_only(rt5645->regmap, true);
4348 regcache_mark_dirty(rt5645->regmap);
4349 return ret;
4350 }
4351
4352 if (rt5645->hp_jack) {
4353 rt5645->jack_type = 0;
4354 rt5645_jack_detect_work(&rt5645->jack_detect_work.work);
4355 }
4356 return 0;
4357 }
4358
4359 static const struct dev_pm_ops rt5645_pm = {
4360 SYSTEM_SLEEP_PM_OPS(rt5645_sys_suspend, rt5645_sys_resume)
4361 };
4362
4363 static struct i2c_driver rt5645_i2c_driver = {
4364 .driver = {
4365 .name = "rt5645",
4366 .of_match_table = of_match_ptr(rt5645_of_match),
4367 .acpi_match_table = ACPI_PTR(rt5645_acpi_match),
4368 .pm = pm_ptr(&rt5645_pm),
4369 },
4370 .probe = rt5645_i2c_probe,
4371 .remove = rt5645_i2c_remove,
4372 .shutdown = rt5645_i2c_shutdown,
4373 .id_table = rt5645_i2c_id,
4374 };
4375 module_i2c_driver(rt5645_i2c_driver);
4376
4377 MODULE_DESCRIPTION("ASoC RT5645 driver");
4378 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4379 MODULE_LICENSE("GPL v2");
4380