1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Common device tree for components shared between the BCM21664 and BCM23550 4 * SoCs. 5 * 6 * Copyright (C) 2016 Broadcom 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/clock/bcm21664.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14 15/ { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 /* Hub bus */ 20 hub: hub-bus@34000000 { 21 compatible = "simple-bus"; 22 ranges = <0 0x34000000 0x102f83ac>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 26 smc: smc@4e000 { 27 /* Compatible filled by SoC DTSI */ 28 reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */ 29 }; 30 31 resetmgr: reset-controller@1001f00 { 32 compatible = "brcm,bcm21664-resetmgr"; 33 reg = <0x01001f00 0x24>; 34 }; 35 36 gpio: gpio@1003000 { 37 /* Compatible filled by SoC DTSI */ 38 reg = <0x01003000 0x524>; 39 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 43 #gpio-cells = <2>; 44 #interrupt-cells = <2>; 45 gpio-controller; 46 interrupt-controller; 47 }; 48 49 pinctrl: pinctrl@1004800 { 50 compatible = "brcm,bcm21664-pinctrl"; 51 reg = <0x01004800 0x7f4>; 52 }; 53 54 timer@1006000 { 55 compatible = "brcm,kona-timer"; 56 reg = <0x01006000 0x1c>; 57 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 58 clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; 59 }; 60 }; 61 62 /* Slaves bus */ 63 slaves: slaves-bus@3e000000 { 64 compatible = "simple-bus"; 65 ranges = <0 0x3e000000 0x0001c070>; 66 #address-cells = <1>; 67 #size-cells = <1>; 68 69 uartb: serial@0 { 70 compatible = "snps,dw-apb-uart"; 71 reg = <0x00000000 0x118>; 72 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; 73 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 74 reg-shift = <2>; 75 reg-io-width = <4>; 76 status = "disabled"; 77 }; 78 79 uartb2: serial@1000 { 80 compatible = "snps,dw-apb-uart"; 81 reg = <0x00001000 0x118>; 82 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; 83 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 84 reg-shift = <2>; 85 reg-io-width = <4>; 86 status = "disabled"; 87 }; 88 89 uartb3: serial@2000 { 90 compatible = "snps,dw-apb-uart"; 91 reg = <0x00002000 0x118>; 92 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; 93 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 94 reg-shift = <2>; 95 reg-io-width = <4>; 96 status = "disabled"; 97 }; 98 99 bsc1: i2c@16000 { 100 /* Compatible filled by SoC DTSI */ 101 reg = <0x00016000 0x70>; 102 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 103 #address-cells = <1>; 104 #size-cells = <0>; 105 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; 106 status = "disabled"; 107 }; 108 109 bsc2: i2c@17000 { 110 /* Compatible filled by SoC DTSI */ 111 reg = <0x00017000 0x70>; 112 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 113 #address-cells = <1>; 114 #size-cells = <0>; 115 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; 116 status = "disabled"; 117 }; 118 119 bsc3: i2c@18000 { 120 /* Compatible filled by SoC DTSI */ 121 reg = <0x00018000 0x70>; 122 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 123 #address-cells = <1>; 124 #size-cells = <0>; 125 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; 126 status = "disabled"; 127 }; 128 129 bsc4: i2c@1c000 { 130 /* Compatible filled by SoC DTSI */ 131 reg = <0x0001c000 0x70>; 132 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 133 #address-cells = <1>; 134 #size-cells = <0>; 135 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; 136 status = "disabled"; 137 }; 138 }; 139 140 /* Apps bus */ 141 apps: apps-bus@3e300000 { 142 compatible = "simple-bus"; 143 ranges = <0 0x3e300000 0x01c02000>; 144 #address-cells = <1>; 145 #size-cells = <1>; 146 147 usbotg: usb@e20000 { 148 compatible = "snps,dwc2"; 149 reg = <0x00e20000 0x10000>; 150 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 151 clocks = <&usb_otg_ahb_clk>; 152 clock-names = "otg"; 153 phys = <&usbphy>; 154 phy-names = "usb2-phy"; 155 status = "disabled"; 156 }; 157 158 usbphy: usb-phy@e30000 { 159 compatible = "brcm,kona-usb2-phy"; 160 reg = <0x00e30000 0x28>; 161 #phy-cells = <0>; 162 status = "disabled"; 163 }; 164 165 sdio1: mmc@e80000 { 166 compatible = "brcm,kona-sdhci"; 167 reg = <0x00e80000 0x801c>; 168 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; 170 status = "disabled"; 171 }; 172 173 sdio2: mmc@e90000 { 174 compatible = "brcm,kona-sdhci"; 175 reg = <0x00e90000 0x801c>; 176 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 177 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; 178 status = "disabled"; 179 }; 180 181 sdio3: mmc@ea0000 { 182 compatible = "brcm,kona-sdhci"; 183 reg = <0x00ea0000 0x801c>; 184 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; 186 status = "disabled"; 187 }; 188 189 sdio4: mmc@eb0000 { 190 compatible = "brcm,kona-sdhci"; 191 reg = <0x00eb0000 0x801c>; 192 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; 194 status = "disabled"; 195 }; 196 }; 197 198 clocks { 199 #address-cells = <1>; 200 #size-cells = <1>; 201 ranges; 202 203 /* 204 * Fixed clocks are defined before CCUs whose 205 * clocks may depend on them. 206 */ 207 208 ref_32k_clk: ref_32k { 209 #clock-cells = <0>; 210 compatible = "fixed-clock"; 211 clock-frequency = <32768>; 212 }; 213 214 bbl_32k_clk: bbl_32k { 215 #clock-cells = <0>; 216 compatible = "fixed-clock"; 217 clock-frequency = <32768>; 218 }; 219 220 ref_13m_clk: ref_13m { 221 #clock-cells = <0>; 222 compatible = "fixed-clock"; 223 clock-frequency = <13000000>; 224 }; 225 226 var_13m_clk: var_13m { 227 #clock-cells = <0>; 228 compatible = "fixed-clock"; 229 clock-frequency = <13000000>; 230 }; 231 232 dft_19_5m_clk: dft_19_5m { 233 #clock-cells = <0>; 234 compatible = "fixed-clock"; 235 clock-frequency = <19500000>; 236 }; 237 238 ref_crystal_clk: ref_crystal { 239 #clock-cells = <0>; 240 compatible = "fixed-clock"; 241 clock-frequency = <26000000>; 242 }; 243 244 ref_52m_clk: ref_52m { 245 #clock-cells = <0>; 246 compatible = "fixed-clock"; 247 clock-frequency = <52000000>; 248 }; 249 250 var_52m_clk: var_52m { 251 #clock-cells = <0>; 252 compatible = "fixed-clock"; 253 clock-frequency = <52000000>; 254 }; 255 256 usb_otg_ahb_clk: usb_otg_ahb { 257 #clock-cells = <0>; 258 compatible = "fixed-clock"; 259 clock-frequency = <52000000>; 260 }; 261 262 ref_96m_clk: ref_96m { 263 #clock-cells = <0>; 264 compatible = "fixed-clock"; 265 clock-frequency = <96000000>; 266 }; 267 268 var_96m_clk: var_96m { 269 #clock-cells = <0>; 270 compatible = "fixed-clock"; 271 clock-frequency = <96000000>; 272 }; 273 274 ref_104m_clk: ref_104m { 275 #clock-cells = <0>; 276 compatible = "fixed-clock"; 277 clock-frequency = <104000000>; 278 }; 279 280 var_104m_clk: var_104m { 281 #clock-cells = <0>; 282 compatible = "fixed-clock"; 283 clock-frequency = <104000000>; 284 }; 285 286 ref_156m_clk: ref_156m { 287 #clock-cells = <0>; 288 compatible = "fixed-clock"; 289 clock-frequency = <156000000>; 290 }; 291 292 var_156m_clk: var_156m { 293 #clock-cells = <0>; 294 compatible = "fixed-clock"; 295 clock-frequency = <156000000>; 296 }; 297 298 root_ccu: root_ccu@35001000 { 299 compatible = "brcm,bcm21664-root-ccu"; 300 reg = <0x35001000 0x0f00>; 301 #clock-cells = <1>; 302 clock-output-names = "frac_1m"; 303 }; 304 305 aon_ccu: aon_ccu@35002000 { 306 compatible = "brcm,bcm21664-aon-ccu"; 307 reg = <0x35002000 0x0f00>; 308 #clock-cells = <1>; 309 clock-output-names = "hub_timer"; 310 }; 311 312 slave_ccu: slave_ccu@3e011000 { 313 compatible = "brcm,bcm21664-slave-ccu"; 314 reg = <0x3e011000 0x0f00>; 315 #clock-cells = <1>; 316 clock-output-names = "uartb", 317 "uartb2", 318 "uartb3", 319 "bsc1", 320 "bsc2", 321 "bsc3", 322 "bsc4"; 323 }; 324 325 master_ccu: master_ccu@3f001000 { 326 compatible = "brcm,bcm21664-master-ccu"; 327 reg = <0x3f001000 0x0f00>; 328 #clock-cells = <1>; 329 clock-output-names = "sdio1", 330 "sdio2", 331 "sdio3", 332 "sdio4", 333 "sdio1_sleep", 334 "sdio2_sleep", 335 "sdio3_sleep", 336 "sdio4_sleep"; 337 }; 338 }; 339}; 340 341#include "bcm2166x-pinctrl.dtsi" 342