1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU specific errata definitions 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 8 #include <linux/arm-smccc.h> 9 #include <linux/types.h> 10 #include <linux/cpu.h> 11 #include <asm/cpu.h> 12 #include <asm/cputype.h> 13 #include <asm/cpufeature.h> 14 #include <asm/fpsimd.h> 15 #include <asm/kvm_asm.h> 16 #include <asm/smp_plat.h> 17 18 static u64 target_impl_cpu_num; 19 static struct target_impl_cpu *target_impl_cpus; 20 21 bool cpu_errata_set_target_impl(u64 num, void *impl_cpus) 22 { 23 if (target_impl_cpu_num || !num || !impl_cpus) 24 return false; 25 26 target_impl_cpu_num = num; 27 target_impl_cpus = impl_cpus; 28 return true; 29 } 30 31 static inline bool __is_midr_in_range(u32 midr, struct midr_range const *range) 32 { 33 return midr_is_cpu_model_range(midr, range->model, 34 range->rv_min, range->rv_max); 35 } 36 37 static inline bool is_midr_in_range(struct midr_range const *range) 38 { 39 int i; 40 41 if (!target_impl_cpu_num) 42 return __is_midr_in_range(read_cpuid_id(), range); 43 44 for (i = 0; i < target_impl_cpu_num; i++) { 45 if (__is_midr_in_range(target_impl_cpus[i].midr, range)) 46 return true; 47 } 48 return false; 49 } 50 51 bool is_midr_in_range_list(struct midr_range const *ranges) 52 { 53 while (ranges->model) 54 if (is_midr_in_range(ranges++)) 55 return true; 56 return false; 57 } 58 EXPORT_SYMBOL_GPL(is_midr_in_range_list); 59 60 static bool __maybe_unused 61 __is_affected_midr_range(const struct arm64_cpu_capabilities *entry, 62 u32 midr, u32 revidr) 63 { 64 const struct arm64_midr_revidr *fix; 65 if (!__is_midr_in_range(midr, &entry->midr_range)) 66 return false; 67 68 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK; 69 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) 70 if (midr == fix->midr_rv && (revidr & fix->revidr_mask)) 71 return false; 72 return true; 73 } 74 75 static bool __maybe_unused 76 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) 77 { 78 int i; 79 80 if (!target_impl_cpu_num) { 81 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 82 return __is_affected_midr_range(entry, read_cpuid_id(), 83 read_cpuid(REVIDR_EL1)); 84 } 85 86 for (i = 0; i < target_impl_cpu_num; i++) { 87 if (__is_affected_midr_range(entry, target_impl_cpus[i].midr, 88 target_impl_cpus[i].revidr)) 89 return true; 90 } 91 return false; 92 } 93 94 static bool __maybe_unused 95 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry, 96 int scope) 97 { 98 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 99 return is_midr_in_range_list(entry->midr_range_list); 100 } 101 102 static bool __maybe_unused 103 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope) 104 { 105 u32 model; 106 107 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 108 109 model = read_cpuid_id(); 110 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) | 111 MIDR_ARCHITECTURE_MASK; 112 113 return model == entry->midr_range.model; 114 } 115 116 static bool 117 has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry, 118 int scope) 119 { 120 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 121 u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask; 122 u64 ctr_raw, ctr_real; 123 124 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 125 126 /* 127 * We want to make sure that all the CPUs in the system expose 128 * a consistent CTR_EL0 to make sure that applications behaves 129 * correctly with migration. 130 * 131 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 : 132 * 133 * 1) It is safe if the system doesn't support IDC, as CPU anyway 134 * reports IDC = 0, consistent with the rest. 135 * 136 * 2) If the system has IDC, it is still safe as we trap CTR_EL0 137 * access on this CPU via the ARM64_HAS_CACHE_IDC capability. 138 * 139 * So, we need to make sure either the raw CTR_EL0 or the effective 140 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot. 141 */ 142 ctr_raw = read_cpuid_cachetype() & mask; 143 ctr_real = read_cpuid_effective_cachetype() & mask; 144 145 return (ctr_real != sys) && (ctr_raw != sys); 146 } 147 148 #ifdef CONFIG_ARM64_ERRATUM_4311569 149 static DEFINE_STATIC_KEY_FALSE(arm_si_l1_workaround_4311569); 150 static int __init early_arm_si_l1_workaround_4311569_cfg(char *arg) 151 { 152 static_branch_enable(&arm_si_l1_workaround_4311569); 153 pr_info("Enabling cache maintenance workaround for ARM SI-L1 erratum 4311569\n"); 154 155 return 0; 156 } 157 early_param("arm_si_l1_workaround_4311569", early_arm_si_l1_workaround_4311569_cfg); 158 159 /* 160 * We have some earlier use cases to call cache maintenance operation functions, for example, 161 * dcache_inval_poc() and dcache_clean_poc() in head.S, before making decision to turn on this 162 * workaround. Since the scope of this workaround is limited to non-coherent DMA agents, its 163 * safe to have the workaround off by default. 164 */ 165 static bool 166 need_arm_si_l1_workaround_4311569(const struct arm64_cpu_capabilities *entry, int scope) 167 { 168 return static_branch_unlikely(&arm_si_l1_workaround_4311569); 169 } 170 #endif 171 172 static void 173 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap) 174 { 175 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 176 bool enable_uct_trap = false; 177 178 /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */ 179 if ((read_cpuid_cachetype() & mask) != 180 (arm64_ftr_reg_ctrel0.sys_val & mask)) 181 enable_uct_trap = true; 182 183 /* ... or if the system is affected by an erratum */ 184 if (cap->capability == ARM64_WORKAROUND_1542419) 185 enable_uct_trap = true; 186 187 if (enable_uct_trap) 188 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 189 } 190 191 #ifdef CONFIG_ARM64_ERRATUM_1463225 192 static bool 193 has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry, 194 int scope) 195 { 196 return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode(); 197 } 198 #endif 199 200 static void __maybe_unused 201 cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) 202 { 203 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0); 204 } 205 206 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 207 .matches = is_affected_midr_range, \ 208 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max) 209 210 #define CAP_MIDR_ALL_VERSIONS(model) \ 211 .matches = is_affected_midr_range, \ 212 .midr_range = MIDR_ALL_VERSIONS(model) 213 214 #define MIDR_FIXED(rev, revidr_mask) \ 215 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}} 216 217 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 218 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 219 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) 220 221 #define CAP_MIDR_RANGE_LIST(list) \ 222 .matches = is_affected_midr_range_list, \ 223 .midr_range_list = list 224 225 /* Errata affecting a range of revisions of given model variant */ 226 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \ 227 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max) 228 229 /* Errata affecting a single variant/revision of a model */ 230 #define ERRATA_MIDR_REV(model, var, rev) \ 231 ERRATA_MIDR_RANGE(model, var, rev, var, rev) 232 233 /* Errata affecting all variants/revisions of a given a model */ 234 #define ERRATA_MIDR_ALL_VERSIONS(model) \ 235 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 236 CAP_MIDR_ALL_VERSIONS(model) 237 238 /* Errata affecting a list of midr ranges, with same work around */ 239 #define ERRATA_MIDR_RANGE_LIST(midr_list) \ 240 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 241 CAP_MIDR_RANGE_LIST(midr_list) 242 243 static const __maybe_unused struct midr_range tx2_family_cpus[] = { 244 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 245 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 246 {}, 247 }; 248 249 static bool __maybe_unused 250 needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry, 251 int scope) 252 { 253 int i; 254 255 if (!is_affected_midr_range_list(entry, scope) || 256 !is_hyp_mode_available()) 257 return false; 258 259 for_each_possible_cpu(i) { 260 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0) 261 return true; 262 } 263 264 return false; 265 } 266 267 static bool __maybe_unused 268 has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry, 269 int scope) 270 { 271 bool has_dic = read_cpuid_cachetype() & BIT(CTR_EL0_DIC_SHIFT); 272 const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1); 273 274 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 275 return is_midr_in_range(&range) && has_dic; 276 } 277 278 static const struct midr_range apple_cpus[] = { 279 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM), 280 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM), 281 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO), 282 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO), 283 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX), 284 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX), 285 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 286 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 287 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 288 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 289 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 290 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 291 {}, 292 }; 293 294 static bool has_impdef_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) 295 { 296 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 297 unsigned int pmuver; 298 299 if (!is_kernel_in_hyp_mode()) 300 return false; 301 302 pmuver = cpuid_feature_extract_unsigned_field(dfr0, 303 ID_AA64DFR0_EL1_PMUVer_SHIFT); 304 if (pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 305 return false; 306 307 return is_midr_in_range_list(apple_cpus); 308 } 309 310 static bool has_broken_gic_v3_seis(const struct arm64_cpu_capabilities *entry, int scope) 311 { 312 return (is_kernel_in_hyp_mode() && 313 is_midr_in_range_list(apple_cpus) && 314 (read_sysreg_s(SYS_ICH_VTR_EL2) & ICH_VTR_EL2_SEIS)); 315 } 316 317 static void cpu_enable_impdef_pmuv3_traps(const struct arm64_cpu_capabilities *__unused) 318 { 319 sysreg_clear_set_s(SYS_HACR_EL2, 0, BIT(56)); 320 } 321 322 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI_SYNC 323 static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { 324 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 325 { 326 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0) 327 }, 328 { 329 .midr_range.model = MIDR_QCOM_KRYO, 330 .matches = is_kryo_midr, 331 }, 332 #endif 333 #ifdef CONFIG_ARM64_ERRATUM_1286807 334 { 335 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0), 336 }, 337 { 338 /* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */ 339 ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe), 340 }, 341 #endif 342 #ifdef CONFIG_ARM64_ERRATUM_2441007 343 { 344 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 345 }, 346 #endif 347 #ifdef CONFIG_ARM64_ERRATUM_2441009 348 { 349 /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */ 350 ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), 351 }, 352 #endif 353 #ifdef CONFIG_ARM64_ERRATUM_4118414 354 { 355 ERRATA_MIDR_RANGE_LIST(((const struct midr_range[]) { 356 MIDR_ALL_VERSIONS(MIDR_C1_PREMIUM), 357 MIDR_ALL_VERSIONS(MIDR_C1_ULTRA), 358 MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), 359 MIDR_ALL_VERSIONS(MIDR_CORTEX_A76AE), 360 MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), 361 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), 362 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78AE), 363 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), 364 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 365 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), 366 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C), 367 MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), 368 MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), 369 MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), 370 MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), 371 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), 372 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 373 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), 374 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), 375 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), 376 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE), 377 MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), 378 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 379 {} 380 })), 381 }, 382 #endif 383 {} 384 }; 385 #endif 386 387 #ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT 388 static const struct midr_range workaround_amu_constcnt_list[] = { 389 #ifdef CONFIG_ARM64_ERRATUM_2457168 390 /* Cortex-A510 r0p0-r1p1 */ 391 MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), 392 #endif 393 #ifdef CONFIG_ARM64_ERRATUM_3821522 394 /* Cortex-A725 r0p0 - r0p2 */ 395 MIDR_RANGE(MIDR_CORTEX_A725, 0, 0, 0, 2), 396 #endif 397 {} 398 }; 399 #endif /* CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT */ 400 401 #ifdef CONFIG_CAVIUM_ERRATUM_23154 402 static const struct midr_range cavium_erratum_23154_cpus[] = { 403 MIDR_ALL_VERSIONS(MIDR_THUNDERX), 404 MIDR_ALL_VERSIONS(MIDR_THUNDERX_81XX), 405 MIDR_ALL_VERSIONS(MIDR_THUNDERX_83XX), 406 MIDR_ALL_VERSIONS(MIDR_OCTX2_98XX), 407 MIDR_ALL_VERSIONS(MIDR_OCTX2_96XX), 408 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XX), 409 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXN), 410 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXMM), 411 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXO), 412 {}, 413 }; 414 #endif 415 416 #ifdef CONFIG_CAVIUM_ERRATUM_27456 417 static const struct midr_range cavium_erratum_27456_cpus[] = { 418 /* Cavium ThunderX, T88 pass 1.x - 2.1 */ 419 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1), 420 /* Cavium ThunderX, T81 pass 1.0 */ 421 MIDR_REV(MIDR_THUNDERX_81XX, 0, 0), 422 {}, 423 }; 424 #endif 425 426 #ifdef CONFIG_CAVIUM_ERRATUM_30115 427 static const struct midr_range cavium_erratum_30115_cpus[] = { 428 /* Cavium ThunderX, T88 pass 1.x - 2.2 */ 429 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2), 430 /* Cavium ThunderX, T81 pass 1.0 - 1.2 */ 431 MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2), 432 /* Cavium ThunderX, T83 pass 1.0 */ 433 MIDR_REV(MIDR_THUNDERX_83XX, 0, 0), 434 {}, 435 }; 436 #endif 437 438 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 439 static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = { 440 { 441 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0), 442 }, 443 { 444 .midr_range.model = MIDR_QCOM_KRYO, 445 .matches = is_kryo_midr, 446 }, 447 {}, 448 }; 449 #endif 450 451 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 452 static const struct midr_range workaround_clean_cache[] = { 453 #if defined(CONFIG_ARM64_ERRATUM_826319) || \ 454 defined(CONFIG_ARM64_ERRATUM_827319) || \ 455 defined(CONFIG_ARM64_ERRATUM_824069) 456 /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */ 457 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2), 458 #endif 459 #ifdef CONFIG_ARM64_ERRATUM_819472 460 /* Cortex-A53 r0p[01] : ARM errata 819472 */ 461 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1), 462 #endif 463 {}, 464 }; 465 #endif 466 467 #ifdef CONFIG_ARM64_ERRATUM_1418040 468 /* 469 * - 1188873 affects r0p0 to r2p0 470 * - 1418040 affects r0p0 to r3p1 471 */ 472 static const struct midr_range erratum_1418040_list[] = { 473 /* Cortex-A76 r0p0 to r3p1 */ 474 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 475 /* Neoverse-N1 r0p0 to r3p1 */ 476 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1), 477 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 478 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 479 {}, 480 }; 481 #endif 482 483 #ifdef CONFIG_ARM64_ERRATUM_845719 484 static const struct midr_range erratum_845719_list[] = { 485 /* Cortex-A53 r0p[01234] */ 486 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 487 /* Brahma-B53 r0p[0] */ 488 MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 489 /* Kryo2XX Silver rAp4 */ 490 MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4), 491 {}, 492 }; 493 #endif 494 495 #ifdef CONFIG_ARM64_ERRATUM_843419 496 static const struct arm64_cpu_capabilities erratum_843419_list[] = { 497 { 498 /* Cortex-A53 r0p[01234] */ 499 .matches = is_affected_midr_range, 500 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 501 MIDR_FIXED(0x4, BIT(8)), 502 }, 503 { 504 /* Brahma-B53 r0p[0] */ 505 .matches = is_affected_midr_range, 506 ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 507 }, 508 {}, 509 }; 510 #endif 511 512 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 513 static const struct midr_range erratum_speculative_at_list[] = { 514 #ifdef CONFIG_ARM64_ERRATUM_1165522 515 /* Cortex A76 r0p0 to r2p0 */ 516 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0), 517 #endif 518 #ifdef CONFIG_ARM64_ERRATUM_1319367 519 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 520 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 521 #endif 522 #ifdef CONFIG_ARM64_ERRATUM_1530923 523 /* Cortex A55 r0p0 to r2p0 */ 524 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0), 525 /* Kryo4xx Silver (rdpe => r1p0) */ 526 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 527 #endif 528 {}, 529 }; 530 #endif 531 532 #ifdef CONFIG_ARM64_ERRATUM_1463225 533 static const struct midr_range erratum_1463225[] = { 534 /* Cortex-A76 r0p0 - r3p1 */ 535 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 536 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 537 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 538 {}, 539 }; 540 #endif 541 542 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 543 static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { 544 #ifdef CONFIG_ARM64_ERRATUM_2139208 545 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 546 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 547 #endif 548 #ifdef CONFIG_ARM64_ERRATUM_2119858 549 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 550 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0), 551 #endif 552 {}, 553 }; 554 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */ 555 556 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE 557 static const struct midr_range tsb_flush_fail_cpus[] = { 558 #ifdef CONFIG_ARM64_ERRATUM_2067961 559 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 560 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 561 #endif 562 #ifdef CONFIG_ARM64_ERRATUM_2054223 563 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 564 #endif 565 {}, 566 }; 567 #endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ 568 569 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 570 static struct midr_range trbe_write_out_of_range_cpus[] = { 571 #ifdef CONFIG_ARM64_ERRATUM_2253138 572 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 573 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 574 #endif 575 #ifdef CONFIG_ARM64_ERRATUM_2224489 576 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 577 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0), 578 #endif 579 {}, 580 }; 581 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ 582 583 #ifdef CONFIG_ARM64_ERRATUM_1742098 584 static struct midr_range broken_aarch32_aes[] = { 585 MIDR_RANGE(MIDR_CORTEX_A57, 0, 1, 0xf, 0xf), 586 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 587 {}, 588 }; 589 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ 590 591 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 592 static const struct midr_range erratum_spec_unpriv_load_list[] = { 593 #ifdef CONFIG_ARM64_ERRATUM_3117295 594 MIDR_ALL_VERSIONS(MIDR_CORTEX_A510), 595 #endif 596 #ifdef CONFIG_ARM64_ERRATUM_2966298 597 /* Cortex-A520 r0p0 to r0p1 */ 598 MIDR_REV_RANGE(MIDR_CORTEX_A520, 0, 0, 1), 599 #endif 600 {}, 601 }; 602 #endif 603 604 #ifdef CONFIG_ARM64_ERRATUM_3194386 605 static const struct midr_range erratum_spec_ssbs_list[] = { 606 MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), 607 MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), 608 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), 609 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), 610 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 611 MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), 612 MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), 613 MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), 614 MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), 615 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), 616 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C), 617 MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), 618 MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), 619 MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), 620 MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), 621 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 622 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), 623 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 624 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), 625 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), 626 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), 627 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), 628 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE), 629 {} 630 }; 631 #endif 632 633 #ifdef CONFIG_ARM64_ERRATUM_4193714 634 static bool has_sme_dvmsync_erratum(const struct arm64_cpu_capabilities *entry, 635 int scope) 636 { 637 if (!id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) 638 return false; 639 640 return is_affected_midr_range(entry, scope); 641 } 642 643 static void cpu_enable_sme_dvmsync(const struct arm64_cpu_capabilities *__unused) 644 { 645 if (this_cpu_has_cap(ARM64_WORKAROUND_4193714)) 646 sme_enable_dvmsync(); 647 } 648 #endif 649 650 #ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38 651 static const struct midr_range erratum_ac03_cpu_38_list[] = { 652 MIDR_ALL_VERSIONS(MIDR_AMPERE1), 653 MIDR_ALL_VERSIONS(MIDR_AMPERE1A), 654 {}, 655 }; 656 #endif 657 658 #ifdef CONFIG_AMPERE_ERRATUM_AC04_CPU_23 659 static const struct midr_range erratum_ac04_cpu_23_list[] = { 660 MIDR_ALL_VERSIONS(MIDR_AMPERE1A), 661 {}, 662 }; 663 #endif 664 665 #ifdef CONFIG_ARM64_WORKAROUND_DISABLE_CNP 666 static const struct midr_range cnp_erratum_cpus[] = { 667 #ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM 668 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 669 #endif 670 #ifdef CONFIG_HISILICON_ERRATUM_162100125 671 MIDR_ALL_VERSIONS(MIDR_HISI_HIP09), 672 #endif 673 {}, 674 }; 675 #endif 676 677 const struct arm64_cpu_capabilities arm64_errata[] = { 678 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 679 { 680 .desc = "ARM errata 826319, 827319, 824069, or 819472", 681 .capability = ARM64_WORKAROUND_CLEAN_CACHE, 682 ERRATA_MIDR_RANGE_LIST(workaround_clean_cache), 683 .cpu_enable = cpu_enable_cache_maint_trap, 684 }, 685 #endif 686 #ifdef CONFIG_ARM64_ERRATUM_832075 687 { 688 /* Cortex-A57 r0p0 - r1p2 */ 689 .desc = "ARM erratum 832075", 690 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, 691 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 692 0, 0, 693 1, 2), 694 }, 695 #endif 696 #ifdef CONFIG_ARM64_ERRATUM_834220 697 { 698 /* Cortex-A57 r0p0 - r1p2 */ 699 .desc = "ARM erratum 834220", 700 .capability = ARM64_WORKAROUND_834220, 701 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 702 0, 0, 703 1, 2), 704 }, 705 #endif 706 #ifdef CONFIG_ARM64_ERRATUM_843419 707 { 708 .desc = "ARM erratum 843419", 709 .capability = ARM64_WORKAROUND_843419, 710 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 711 .matches = cpucap_multi_entry_cap_matches, 712 .match_list = erratum_843419_list, 713 }, 714 #endif 715 #ifdef CONFIG_ARM64_ERRATUM_845719 716 { 717 .desc = "ARM erratum 845719", 718 .capability = ARM64_WORKAROUND_845719, 719 ERRATA_MIDR_RANGE_LIST(erratum_845719_list), 720 }, 721 #endif 722 #ifdef CONFIG_CAVIUM_ERRATUM_23154 723 { 724 .desc = "Cavium errata 23154 and 38545", 725 .capability = ARM64_WORKAROUND_CAVIUM_23154, 726 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 727 ERRATA_MIDR_RANGE_LIST(cavium_erratum_23154_cpus), 728 }, 729 #endif 730 #ifdef CONFIG_CAVIUM_ERRATUM_27456 731 { 732 .desc = "Cavium erratum 27456", 733 .capability = ARM64_WORKAROUND_CAVIUM_27456, 734 ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus), 735 }, 736 #endif 737 #ifdef CONFIG_CAVIUM_ERRATUM_30115 738 { 739 .desc = "Cavium erratum 30115", 740 .capability = ARM64_WORKAROUND_CAVIUM_30115, 741 ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus), 742 }, 743 #endif 744 { 745 .desc = "Mismatched cache type (CTR_EL0)", 746 .capability = ARM64_MISMATCHED_CACHE_TYPE, 747 .matches = has_mismatched_cache_type, 748 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 749 .cpu_enable = cpu_enable_trap_ctr_access, 750 }, 751 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 752 { 753 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003", 754 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003, 755 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 756 .matches = cpucap_multi_entry_cap_matches, 757 .match_list = qcom_erratum_1003_list, 758 }, 759 #endif 760 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI_SYNC 761 { 762 .desc = "Broken broadcast TLBI completion", 763 .capability = ARM64_WORKAROUND_REPEAT_TLBI_SYNC, 764 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 765 .matches = cpucap_multi_entry_cap_matches, 766 .match_list = arm64_repeat_tlbi_list, 767 }, 768 #endif 769 #ifdef CONFIG_ARM64_ERRATUM_858921 770 { 771 /* Cortex-A73 all versions */ 772 .desc = "ARM erratum 858921", 773 .capability = ARM64_WORKAROUND_858921, 774 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 775 }, 776 #endif 777 { 778 .desc = "Spectre-v2", 779 .capability = ARM64_SPECTRE_V2, 780 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 781 .matches = has_spectre_v2, 782 .cpu_enable = spectre_v2_enable_mitigation, 783 }, 784 #ifdef CONFIG_RANDOMIZE_BASE 785 { 786 /* Must come after the Spectre-v2 entry */ 787 .desc = "Spectre-v3a", 788 .capability = ARM64_SPECTRE_V3A, 789 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 790 .matches = has_spectre_v3a, 791 .cpu_enable = spectre_v3a_enable_mitigation, 792 }, 793 #endif 794 { 795 .desc = "Spectre-v4", 796 .capability = ARM64_SPECTRE_V4, 797 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 798 .matches = has_spectre_v4, 799 .cpu_enable = spectre_v4_enable_mitigation, 800 }, 801 { 802 .desc = "Spectre-BHB", 803 .capability = ARM64_SPECTRE_BHB, 804 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 805 .matches = is_spectre_bhb_affected, 806 .cpu_enable = spectre_bhb_enable_mitigation, 807 }, 808 #ifdef CONFIG_ARM64_ERRATUM_1418040 809 { 810 .desc = "ARM erratum 1418040", 811 .capability = ARM64_WORKAROUND_1418040, 812 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list), 813 /* 814 * We need to allow affected CPUs to come in late, but 815 * also need the non-affected CPUs to be able to come 816 * in at any point in time. Wonderful. 817 */ 818 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 819 }, 820 #endif 821 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 822 { 823 .desc = "ARM errata 1165522, 1319367, or 1530923", 824 .capability = ARM64_WORKAROUND_SPECULATIVE_AT, 825 ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list), 826 }, 827 #endif 828 #ifdef CONFIG_ARM64_ERRATUM_1463225 829 { 830 .desc = "ARM erratum 1463225", 831 .capability = ARM64_WORKAROUND_1463225, 832 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 833 .matches = has_cortex_a76_erratum_1463225, 834 .midr_range_list = erratum_1463225, 835 }, 836 #endif 837 #ifdef CONFIG_CAVIUM_TX2_ERRATUM_219 838 { 839 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)", 840 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM, 841 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 842 .matches = needs_tx2_tvm_workaround, 843 }, 844 { 845 .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)", 846 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM, 847 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 848 }, 849 #endif 850 #ifdef CONFIG_ARM64_ERRATUM_1542419 851 { 852 /* we depend on the firmware portion for correctness */ 853 .desc = "ARM erratum 1542419 (kernel portion)", 854 .capability = ARM64_WORKAROUND_1542419, 855 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 856 .matches = has_neoverse_n1_erratum_1542419, 857 .cpu_enable = cpu_enable_trap_ctr_access, 858 }, 859 #endif 860 #ifdef CONFIG_ARM64_ERRATUM_1508412 861 { 862 /* we depend on the firmware portion for correctness */ 863 .desc = "ARM erratum 1508412 (kernel portion)", 864 .capability = ARM64_WORKAROUND_1508412, 865 ERRATA_MIDR_RANGE(MIDR_CORTEX_A77, 866 0, 0, 867 1, 0), 868 }, 869 #endif 870 #ifdef CONFIG_ARM64_WORKAROUND_DISABLE_CNP 871 { 872 .desc = "NVIDIA Carmel CNP erratum, or Hisilicon erratum 162100125", 873 .capability = ARM64_WORKAROUND_DISABLE_CNP, 874 ERRATA_MIDR_RANGE_LIST(cnp_erratum_cpus), 875 }, 876 #endif 877 #ifdef CONFIG_NVIDIA_OLYMPUS_1027_ERRATUM 878 { 879 /* NVIDIA Olympus core */ 880 .desc = "NVIDIA Olympus device store/load ordering erratum", 881 .capability = ARM64_WORKAROUND_NVIDIA_OLYMPUS_1027, 882 ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), 883 }, 884 #endif 885 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 886 { 887 /* 888 * The erratum work around is handled within the TRBE 889 * driver and can be applied per-cpu. So, we can allow 890 * a late CPU to come online with this erratum. 891 */ 892 .desc = "ARM erratum 2119858 or 2139208", 893 .capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, 894 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 895 CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), 896 }, 897 #endif 898 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE 899 { 900 .desc = "ARM erratum 2067961 or 2054223", 901 .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE, 902 ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus), 903 }, 904 #endif 905 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 906 { 907 .desc = "ARM erratum 2253138 or 2224489", 908 .capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, 909 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 910 CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus), 911 }, 912 #endif 913 #ifdef CONFIG_ARM64_ERRATUM_2645198 914 { 915 .desc = "ARM erratum 2645198", 916 .capability = ARM64_WORKAROUND_2645198, 917 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A715) 918 }, 919 #endif 920 #ifdef CONFIG_ARM64_ERRATUM_2077057 921 { 922 .desc = "ARM erratum 2077057", 923 .capability = ARM64_WORKAROUND_2077057, 924 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 925 }, 926 #endif 927 #ifdef CONFIG_ARM64_ERRATUM_2064142 928 { 929 .desc = "ARM erratum 2064142", 930 .capability = ARM64_WORKAROUND_2064142, 931 932 /* Cortex-A510 r0p0 - r0p2 */ 933 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) 934 }, 935 #endif 936 #ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT 937 { 938 .desc = "Broken AMU AMEVCNTR01 (const counter)", 939 .capability = ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT, 940 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 941 CAP_MIDR_RANGE_LIST(workaround_amu_constcnt_list) 942 }, 943 #endif 944 #ifdef CONFIG_ARM64_ERRATUM_2038923 945 { 946 .desc = "ARM erratum 2038923", 947 .capability = ARM64_WORKAROUND_2038923, 948 949 /* Cortex-A510 r0p0 - r0p2 */ 950 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) 951 }, 952 #endif 953 #ifdef CONFIG_ARM64_ERRATUM_1902691 954 { 955 .desc = "ARM erratum 1902691", 956 .capability = ARM64_WORKAROUND_1902691, 957 958 /* Cortex-A510 r0p0 - r0p1 */ 959 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1) 960 }, 961 #endif 962 #ifdef CONFIG_ARM64_ERRATUM_1742098 963 { 964 .desc = "ARM erratum 1742098", 965 .capability = ARM64_WORKAROUND_1742098, 966 CAP_MIDR_RANGE_LIST(broken_aarch32_aes), 967 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 968 }, 969 #endif 970 #ifdef CONFIG_ARM64_ERRATUM_2658417 971 { 972 .desc = "ARM erratum 2658417", 973 .capability = ARM64_WORKAROUND_2658417, 974 /* Cortex-A510 r0p0 - r1p1 */ 975 ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), 976 MIDR_FIXED(MIDR_CPU_VAR_REV(1,1), BIT(25)), 977 }, 978 #endif 979 #ifdef CONFIG_ARM64_ERRATUM_3194386 980 { 981 .desc = "SSBS not fully self-synchronizing", 982 .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS, 983 ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list), 984 }, 985 #endif 986 #ifdef CONFIG_ARM64_ERRATUM_4311569 987 { 988 .capability = ARM64_WORKAROUND_4311569, 989 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 990 .matches = need_arm_si_l1_workaround_4311569, 991 }, 992 #endif 993 #ifdef CONFIG_ARM64_ERRATUM_4193714 994 { 995 .desc = "C1-Pro SME DVMSync early acknowledgement", 996 .capability = ARM64_WORKAROUND_4193714, 997 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 998 .matches = has_sme_dvmsync_erratum, 999 .cpu_enable = cpu_enable_sme_dvmsync, 1000 /* C1-Pro r0p0 - r1p2 (the latter only when REVIDR_EL1[0]==0) */ 1001 .midr_range = MIDR_RANGE(MIDR_C1_PRO, 0, 0, 1, 2), 1002 MIDR_FIXED(MIDR_CPU_VAR_REV(1, 2), BIT(0)), 1003 }, 1004 #endif 1005 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1006 { 1007 .desc = "ARM errata 2966298, 3117295", 1008 .capability = ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD, 1009 /* Cortex-A520 r0p0 - r0p1 */ 1010 ERRATA_MIDR_RANGE_LIST(erratum_spec_unpriv_load_list), 1011 }, 1012 #endif 1013 #ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38 1014 { 1015 .desc = "AmpereOne erratum AC03_CPU_38", 1016 .capability = ARM64_WORKAROUND_AMPERE_AC03_CPU_38, 1017 ERRATA_MIDR_RANGE_LIST(erratum_ac03_cpu_38_list), 1018 }, 1019 #endif 1020 #ifdef CONFIG_AMPERE_ERRATUM_AC04_CPU_23 1021 { 1022 .desc = "AmpereOne erratum AC04_CPU_23", 1023 .capability = ARM64_WORKAROUND_AMPERE_AC04_CPU_23, 1024 ERRATA_MIDR_RANGE_LIST(erratum_ac04_cpu_23_list), 1025 }, 1026 #endif 1027 { 1028 .desc = "Broken CNTVOFF_EL2", 1029 .capability = ARM64_WORKAROUND_QCOM_ORYON_CNTVOFF, 1030 ERRATA_MIDR_RANGE_LIST(((const struct midr_range[]) { 1031 MIDR_ALL_VERSIONS(MIDR_QCOM_ORYON_X1), 1032 {} 1033 })), 1034 }, 1035 { 1036 .desc = "Apple IMPDEF PMUv3 Traps", 1037 .capability = ARM64_WORKAROUND_PMUV3_IMPDEF_TRAPS, 1038 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 1039 .matches = has_impdef_pmuv3, 1040 .cpu_enable = cpu_enable_impdef_pmuv3_traps, 1041 }, 1042 { 1043 .desc = "Known broken GICv3 SEIS implementation", 1044 .capability = ARM64_WORKAROUND_GICv3_BROKEN_SEIS, 1045 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1046 .matches = has_broken_gic_v3_seis, 1047 }, 1048 { 1049 } 1050 }; 1051