1 /* Copyright 2018 Advanced Micro Devices, Inc.
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19 * OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * Authors: AMD
22 *
23 */
24
25 #include "power_helpers.h"
26 #include "dc/inc/hw/dmcu.h"
27 #include "dc/inc/hw/abm.h"
28 #include "dc.h"
29 #include "core_types.h"
30 #include "dmub_cmd.h"
31
32 #define DIV_ROUNDUP(a, b) (((a)+((b)/2))/(b))
33 #define bswap16_based_on_endian(big_endian, value) \
34 ((big_endian) ? cpu_to_be16(value) : cpu_to_le16(value))
35
36 /* Possible Min Reduction config from least aggressive to most aggressive
37 * 0 1 2 3 4 5 6 7 8 9 10 11 12
38 * 100 98.0 94.1 94.1 85.1 80.3 75.3 69.4 60.0 57.6 50.2 49.8 40.0 %
39 */
40 static const unsigned char min_reduction_table[13] = {
41 0xff, 0xfa, 0xf0, 0xf0, 0xd9, 0xcd, 0xc0, 0xb1, 0x99, 0x93, 0x80, 0x82, 0x66};
42
43 /* Possible Max Reduction configs from least aggressive to most aggressive
44 * 0 1 2 3 4 5 6 7 8 9 10 11 12
45 * 96.1 89.8 85.1 80.3 69.4 64.7 64.7 50.2 39.6 30.2 30.2 30.2 19.6 %
46 */
47 static const unsigned char max_reduction_table[13] = {
48 0xf5, 0xe5, 0xd9, 0xcd, 0xb1, 0xa5, 0xa5, 0x80, 0x65, 0x4d, 0x4d, 0x4d, 0x32};
49
50 /* Possible ABM 2.2 Min Reduction configs from least aggressive to most aggressive
51 * 0 1 2 3 4 5 6 7 8 9 10 11 12
52 * 100 100 100 100 100 100 100 100 100 92.2 83.1 75.3 75.3 %
53 */
54 static const unsigned char min_reduction_table_v_2_2[13] = {
55 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb, 0xd4, 0xc0, 0xc0};
56
57 /* Possible ABM 2.2 Max Reduction configs from least aggressive to most aggressive
58 * 0 1 2 3 4 5 6 7 8 9 10 11 12
59 * 96.1 89.8 74.9 69.4 64.7 52.2 48.6 39.6 30.2 25.1 19.6 12.5 12.5 %
60 */
61 static const unsigned char max_reduction_table_v_2_2[13] = {
62 0xf5, 0xe5, 0xbf, 0xb1, 0xa5, 0x85, 0x7c, 0x65, 0x4d, 0x40, 0x32, 0x20, 0x20};
63
64 /* Predefined ABM configuration sets. We may have different configuration sets
65 * in order to satisfy different power/quality requirements.
66 */
67 static const unsigned char abm_config[abm_defines_max_config][abm_defines_max_level] = {
68 /* ABM Level 1, ABM Level 2, ABM Level 3, ABM Level 4 */
69 { 2, 5, 7, 8 }, /* Default - Medium aggressiveness */
70 { 2, 5, 8, 11 }, /* Alt #1 - Increased aggressiveness */
71 { 0, 2, 4, 8 }, /* Alt #2 - Minimal aggressiveness */
72 { 3, 6, 10, 12 }, /* Alt #3 - Super aggressiveness */
73 };
74
75 struct abm_parameters {
76 unsigned char min_reduction;
77 unsigned char max_reduction;
78 unsigned char bright_pos_gain;
79 unsigned char dark_pos_gain;
80 unsigned char brightness_gain;
81 unsigned char contrast_factor;
82 unsigned char deviation_gain;
83 unsigned char min_knee;
84 unsigned char max_knee;
85 unsigned short blRampReduction;
86 unsigned short blRampStart;
87 };
88
89 static const struct abm_parameters abm_settings_config0[abm_defines_max_level] = {
90 // min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart
91 {0xff, 0xbf, 0x20, 0x00, 0xff, 0x99, 0xb3, 0x40, 0xe0, 0xf777, 0xcccc},
92 {0xde, 0x85, 0x20, 0x00, 0xe0, 0x90, 0xa8, 0x40, 0xc8, 0xf777, 0xcccc},
93 {0xb0, 0x50, 0x20, 0x00, 0xc0, 0x88, 0x78, 0x70, 0xa0, 0xeeee, 0x9999},
94 {0x82, 0x40, 0x20, 0x00, 0x00, 0xb8, 0xb3, 0x70, 0x70, 0xe333, 0xb333},
95 };
96
97 static const struct abm_parameters abm_settings_config1[abm_defines_max_level] = {
98 // min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart
99 {0xf0, 0xd9, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc},
100 {0xcd, 0xa5, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc},
101 {0x99, 0x65, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc},
102 {0x82, 0x4d, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc},
103 };
104
105 static const struct abm_parameters abm_settings_config2[abm_defines_max_level] = {
106 // min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart
107 {0xf0, 0xbf, 0x20, 0x00, 0x88, 0x99, 0xb3, 0x40, 0xe0, 0x0000, 0xcccc},
108 {0xd8, 0x85, 0x20, 0x00, 0x70, 0x90, 0xa8, 0x40, 0xc8, 0x0700, 0xb333},
109 {0xb8, 0x58, 0x20, 0x00, 0x64, 0x88, 0x78, 0x70, 0xa0, 0x7000, 0x9999},
110 {0x82, 0x40, 0x20, 0x00, 0x00, 0xb8, 0xb3, 0x70, 0x70, 0xc333, 0xb333},
111 };
112
113 static const struct abm_parameters * const abm_settings[] = {
114 abm_settings_config0,
115 abm_settings_config1,
116 abm_settings_config2,
117 };
118
119 static const struct dm_bl_data_point custom_backlight_curve0[] = {
120 {2, 14}, {4, 16}, {6, 18}, {8, 21}, {10, 23}, {12, 26}, {14, 29}, {16, 32}, {18, 35},
121 {20, 38}, {22, 41}, {24, 44}, {26, 48}, {28, 52}, {30, 55}, {32, 59}, {34, 62},
122 {36, 67}, {38, 71}, {40, 75}, {42, 80}, {44, 84}, {46, 88}, {48, 93}, {50, 98},
123 {52, 103}, {54, 108}, {56, 113}, {58, 118}, {60, 123}, {62, 129}, {64, 135}, {66, 140},
124 {68, 146}, {70, 152}, {72, 158}, {74, 164}, {76, 171}, {78, 177}, {80, 183}, {82, 190},
125 {84, 197}, {86, 204}, {88, 211}, {90, 218}, {92, 225}, {94, 232}, {96, 240}, {98, 247}};
126
127 struct custom_backlight_profile {
128 uint8_t ac_level_percentage;
129 uint8_t dc_level_percentage;
130 uint8_t min_input_signal;
131 uint8_t max_input_signal;
132 uint8_t num_data_points;
133 const struct dm_bl_data_point *data_points;
134 };
135
136 static const struct custom_backlight_profile custom_backlight_profiles[] = {
137 {100, 32, 12, 255, ARRAY_SIZE(custom_backlight_curve0), custom_backlight_curve0},
138 };
139
140 #define NUM_AMBI_LEVEL 5
141 #define NUM_AGGR_LEVEL 4
142 #define NUM_POWER_FN_SEGS 8
143 #define NUM_BL_CURVE_SEGS 16
144 #define IRAM_SIZE 256
145
146 #define IRAM_RESERVE_AREA_START_V2 0xF0 // reserve 0xF0~0xF6 are write by DMCU only
147 #define IRAM_RESERVE_AREA_END_V2 0xF6 // reserve 0xF0~0xF6 are write by DMCU only
148
149 #define IRAM_RESERVE_AREA_START_V2_2 0xF0 // reserve 0xF0~0xFF are write by DMCU only
150 #define IRAM_RESERVE_AREA_END_V2_2 0xFF // reserve 0xF0~0xFF are write by DMCU only
151
152 #pragma pack(push, 1)
153 /* NOTE: iRAM is 256B in size */
154 struct iram_table_v_2 {
155 /* flags */
156 uint16_t min_abm_backlight; /* 0x00 U16 */
157
158 /* parameters for ABM2.0 algorithm */
159 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x02 U0.8 */
160 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16 U0.8 */
161 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x2a U2.6 */
162 uint8_t bright_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e U2.6 */
163 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x52 U2.6 */
164 uint8_t dark_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x66 U2.6 */
165 uint8_t iir_curve[NUM_AMBI_LEVEL]; /* 0x7a U0.8 */
166 uint8_t deviation_gain; /* 0x7f U0.8 */
167
168 /* parameters for crgb conversion */
169 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; /* 0x80 U3.13 */
170 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; /* 0x90 U1.15 */
171 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; /* 0xa0 U4.12 */
172
173 /* parameters for custom curve */
174 /* thresholds for brightness --> backlight */
175 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; /* 0xb0 U16.0 */
176 /* offsets for brightness --> backlight */
177 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; /* 0xd0 U16.0 */
178
179 /* For reading PSR State directly from IRAM */
180 uint8_t psr_state; /* 0xf0 */
181 uint8_t dmcu_mcp_interface_version; /* 0xf1 */
182 uint8_t dmcu_abm_feature_version; /* 0xf2 */
183 uint8_t dmcu_psr_feature_version; /* 0xf3 */
184 uint16_t dmcu_version; /* 0xf4 */
185 uint8_t dmcu_state; /* 0xf6 */
186
187 uint16_t blRampReduction; /* 0xf7 */
188 uint16_t blRampStart; /* 0xf9 */
189 uint8_t dummy5; /* 0xfb */
190 uint8_t dummy6; /* 0xfc */
191 uint8_t dummy7; /* 0xfd */
192 uint8_t dummy8; /* 0xfe */
193 uint8_t dummy9; /* 0xff */
194 };
195
196 struct iram_table_v_2_2 {
197 /* flags */
198 uint16_t flags; /* 0x00 U16 */
199
200 /* parameters for ABM2.2 algorithm */
201 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x02 U0.8 */
202 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16 U0.8 */
203 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x2a U2.6 */
204 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e U2.6 */
205 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; /* 0x52 U0.8 */
206 uint8_t contrast_factor[NUM_AGGR_LEVEL]; /* 0x56 U0.8 */
207 uint8_t deviation_gain[NUM_AGGR_LEVEL]; /* 0x5a U0.8 */
208 uint8_t iir_curve[NUM_AMBI_LEVEL]; /* 0x5e U0.8 */
209 uint8_t min_knee[NUM_AGGR_LEVEL]; /* 0x63 U0.8 */
210 uint8_t max_knee[NUM_AGGR_LEVEL]; /* 0x67 U0.8 */
211 uint16_t min_abm_backlight; /* 0x6b U16 */
212 uint8_t pad[19]; /* 0x6d U0.8 */
213
214 /* parameters for crgb conversion */
215 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; /* 0x80 U3.13 */
216 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; /* 0x90 U1.15 */
217 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; /* 0xa0 U4.12 */
218
219 /* parameters for custom curve */
220 /* thresholds for brightness --> backlight */
221 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; /* 0xb0 U16.0 */
222 /* offsets for brightness --> backlight */
223 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; /* 0xd0 U16.0 */
224
225 /* For reading PSR State directly from IRAM */
226 uint8_t psr_state; /* 0xf0 */
227 uint8_t dmcu_mcp_interface_version; /* 0xf1 */
228 uint8_t dmcu_abm_feature_version; /* 0xf2 */
229 uint8_t dmcu_psr_feature_version; /* 0xf3 */
230 uint16_t dmcu_version; /* 0xf4 */
231 uint8_t dmcu_state; /* 0xf6 */
232
233 uint8_t dummy1; /* 0xf7 */
234 uint8_t dummy2; /* 0xf8 */
235 uint8_t dummy3; /* 0xf9 */
236 uint8_t dummy4; /* 0xfa */
237 uint8_t dummy5; /* 0xfb */
238 uint8_t dummy6; /* 0xfc */
239 uint8_t dummy7; /* 0xfd */
240 uint8_t dummy8; /* 0xfe */
241 uint8_t dummy9; /* 0xff */
242 };
243 #pragma pack(pop)
244
fill_backlight_transform_table(struct dmcu_iram_parameters params,struct iram_table_v_2 * table)245 static void fill_backlight_transform_table(struct dmcu_iram_parameters params,
246 struct iram_table_v_2 *table)
247 {
248 unsigned int i;
249 unsigned int num_entries = NUM_BL_CURVE_SEGS;
250 unsigned int lut_index;
251
252 table->backlight_thresholds[0] = 0;
253 ASSERT(params.backlight_lut_array[0] <= 0xFFFF);
254 table->backlight_offsets[0] = (uint16_t)params.backlight_lut_array[0];
255 table->backlight_thresholds[num_entries-1] = 0xFFFF;
256 ASSERT(params.backlight_lut_array[params.backlight_lut_array_size - 1] <= 0xFFFF);
257 table->backlight_offsets[num_entries-1] =
258 (uint16_t)params.backlight_lut_array[params.backlight_lut_array_size - 1];
259
260 /* Setup all brightness levels between 0% and 100% exclusive
261 * Fills brightness-to-backlight transform table. Backlight custom curve
262 * describes transform from brightness to backlight. It will be defined
263 * as set of thresholds and set of offsets, together, implying
264 * extrapolation of custom curve into 16 uniformly spanned linear
265 * segments. Each threshold/offset represented by 16 bit entry in
266 * format U4.10.
267 */
268 for (i = 1; i+1 < num_entries; i++) {
269 lut_index = (params.backlight_lut_array_size - 1) * i / (num_entries - 1);
270
271 ASSERT(lut_index < params.backlight_lut_array_size);
272
273 unsigned int threshold_val = DIV_ROUNDUP((i * 65536), num_entries);
274 unsigned int offset_val = params.backlight_lut_array[lut_index];
275
276 ASSERT(threshold_val <= 0xFFFF);
277 ASSERT(offset_val <= 0xFFFF);
278
279 table->backlight_thresholds[i] = cpu_to_be16((uint16_t)threshold_val);
280 table->backlight_offsets[i] = cpu_to_be16((uint16_t)offset_val);
281 }
282 }
283
fill_backlight_transform_table_v_2_2(struct dmcu_iram_parameters params,struct iram_table_v_2_2 * table,bool big_endian)284 static void fill_backlight_transform_table_v_2_2(struct dmcu_iram_parameters params,
285 struct iram_table_v_2_2 *table, bool big_endian)
286 {
287 unsigned int i;
288 unsigned int num_entries = NUM_BL_CURVE_SEGS;
289 unsigned int lut_index;
290
291 table->backlight_thresholds[0] = 0;
292 ASSERT(params.backlight_lut_array[0] <= 0xFFFF);
293 table->backlight_offsets[0] = (uint16_t)params.backlight_lut_array[0];
294 table->backlight_thresholds[num_entries-1] = 0xFFFF;
295 ASSERT(params.backlight_lut_array[params.backlight_lut_array_size - 1] <= 0xFFFF);
296 table->backlight_offsets[num_entries-1] =
297 (uint16_t)params.backlight_lut_array[params.backlight_lut_array_size - 1];
298
299 /* Setup all brightness levels between 0% and 100% exclusive
300 * Fills brightness-to-backlight transform table. Backlight custom curve
301 * describes transform from brightness to backlight. It will be defined
302 * as set of thresholds and set of offsets, together, implying
303 * extrapolation of custom curve into 16 uniformly spanned linear
304 * segments. Each threshold/offset represented by 16 bit entry in
305 * format U4.10.
306 */
307 for (i = 1; i+1 < num_entries; i++) {
308 lut_index = DIV_ROUNDUP((i * params.backlight_lut_array_size), num_entries);
309 ASSERT(lut_index < params.backlight_lut_array_size);
310
311 unsigned int threshold_val = DIV_ROUNDUP((i * 65536), num_entries);
312 unsigned int offset_val = params.backlight_lut_array[lut_index];
313
314 ASSERT(threshold_val <= 0xFFFF);
315 ASSERT(offset_val <= 0xFFFF);
316
317 table->backlight_thresholds[i] = (big_endian) ?
318 cpu_to_be16((uint16_t)threshold_val) : cpu_to_le16((uint16_t)threshold_val);
319 table->backlight_offsets[i] = (big_endian) ?
320 cpu_to_be16((uint16_t)offset_val) : cpu_to_le16((uint16_t)offset_val);
321 }
322 }
323
fill_iram_v_2(struct iram_table_v_2 * ram_table,struct dmcu_iram_parameters params)324 static void fill_iram_v_2(struct iram_table_v_2 *ram_table, struct dmcu_iram_parameters params)
325 {
326 unsigned int set = params.set;
327
328 ram_table->min_abm_backlight =
329 cpu_to_be16(params.min_abm_backlight);
330 ram_table->deviation_gain = 0xb3;
331
332 ram_table->blRampReduction =
333 cpu_to_be16(params.backlight_ramping_reduction);
334 ram_table->blRampStart =
335 cpu_to_be16(params.backlight_ramping_start);
336
337 ram_table->min_reduction[0][0] = min_reduction_table[abm_config[set][0]];
338 ram_table->min_reduction[1][0] = min_reduction_table[abm_config[set][0]];
339 ram_table->min_reduction[2][0] = min_reduction_table[abm_config[set][0]];
340 ram_table->min_reduction[3][0] = min_reduction_table[abm_config[set][0]];
341 ram_table->min_reduction[4][0] = min_reduction_table[abm_config[set][0]];
342 ram_table->max_reduction[0][0] = max_reduction_table[abm_config[set][0]];
343 ram_table->max_reduction[1][0] = max_reduction_table[abm_config[set][0]];
344 ram_table->max_reduction[2][0] = max_reduction_table[abm_config[set][0]];
345 ram_table->max_reduction[3][0] = max_reduction_table[abm_config[set][0]];
346 ram_table->max_reduction[4][0] = max_reduction_table[abm_config[set][0]];
347
348 ram_table->min_reduction[0][1] = min_reduction_table[abm_config[set][1]];
349 ram_table->min_reduction[1][1] = min_reduction_table[abm_config[set][1]];
350 ram_table->min_reduction[2][1] = min_reduction_table[abm_config[set][1]];
351 ram_table->min_reduction[3][1] = min_reduction_table[abm_config[set][1]];
352 ram_table->min_reduction[4][1] = min_reduction_table[abm_config[set][1]];
353 ram_table->max_reduction[0][1] = max_reduction_table[abm_config[set][1]];
354 ram_table->max_reduction[1][1] = max_reduction_table[abm_config[set][1]];
355 ram_table->max_reduction[2][1] = max_reduction_table[abm_config[set][1]];
356 ram_table->max_reduction[3][1] = max_reduction_table[abm_config[set][1]];
357 ram_table->max_reduction[4][1] = max_reduction_table[abm_config[set][1]];
358
359 ram_table->min_reduction[0][2] = min_reduction_table[abm_config[set][2]];
360 ram_table->min_reduction[1][2] = min_reduction_table[abm_config[set][2]];
361 ram_table->min_reduction[2][2] = min_reduction_table[abm_config[set][2]];
362 ram_table->min_reduction[3][2] = min_reduction_table[abm_config[set][2]];
363 ram_table->min_reduction[4][2] = min_reduction_table[abm_config[set][2]];
364 ram_table->max_reduction[0][2] = max_reduction_table[abm_config[set][2]];
365 ram_table->max_reduction[1][2] = max_reduction_table[abm_config[set][2]];
366 ram_table->max_reduction[2][2] = max_reduction_table[abm_config[set][2]];
367 ram_table->max_reduction[3][2] = max_reduction_table[abm_config[set][2]];
368 ram_table->max_reduction[4][2] = max_reduction_table[abm_config[set][2]];
369
370 ram_table->min_reduction[0][3] = min_reduction_table[abm_config[set][3]];
371 ram_table->min_reduction[1][3] = min_reduction_table[abm_config[set][3]];
372 ram_table->min_reduction[2][3] = min_reduction_table[abm_config[set][3]];
373 ram_table->min_reduction[3][3] = min_reduction_table[abm_config[set][3]];
374 ram_table->min_reduction[4][3] = min_reduction_table[abm_config[set][3]];
375 ram_table->max_reduction[0][3] = max_reduction_table[abm_config[set][3]];
376 ram_table->max_reduction[1][3] = max_reduction_table[abm_config[set][3]];
377 ram_table->max_reduction[2][3] = max_reduction_table[abm_config[set][3]];
378 ram_table->max_reduction[3][3] = max_reduction_table[abm_config[set][3]];
379 ram_table->max_reduction[4][3] = max_reduction_table[abm_config[set][3]];
380
381 ram_table->bright_pos_gain[0][0] = 0x20;
382 ram_table->bright_pos_gain[0][1] = 0x20;
383 ram_table->bright_pos_gain[0][2] = 0x20;
384 ram_table->bright_pos_gain[0][3] = 0x20;
385 ram_table->bright_pos_gain[1][0] = 0x20;
386 ram_table->bright_pos_gain[1][1] = 0x20;
387 ram_table->bright_pos_gain[1][2] = 0x20;
388 ram_table->bright_pos_gain[1][3] = 0x20;
389 ram_table->bright_pos_gain[2][0] = 0x20;
390 ram_table->bright_pos_gain[2][1] = 0x20;
391 ram_table->bright_pos_gain[2][2] = 0x20;
392 ram_table->bright_pos_gain[2][3] = 0x20;
393 ram_table->bright_pos_gain[3][0] = 0x20;
394 ram_table->bright_pos_gain[3][1] = 0x20;
395 ram_table->bright_pos_gain[3][2] = 0x20;
396 ram_table->bright_pos_gain[3][3] = 0x20;
397 ram_table->bright_pos_gain[4][0] = 0x20;
398 ram_table->bright_pos_gain[4][1] = 0x20;
399 ram_table->bright_pos_gain[4][2] = 0x20;
400 ram_table->bright_pos_gain[4][3] = 0x20;
401 ram_table->bright_neg_gain[0][0] = 0x00;
402 ram_table->bright_neg_gain[0][1] = 0x00;
403 ram_table->bright_neg_gain[0][2] = 0x00;
404 ram_table->bright_neg_gain[0][3] = 0x00;
405 ram_table->bright_neg_gain[1][0] = 0x00;
406 ram_table->bright_neg_gain[1][1] = 0x00;
407 ram_table->bright_neg_gain[1][2] = 0x00;
408 ram_table->bright_neg_gain[1][3] = 0x00;
409 ram_table->bright_neg_gain[2][0] = 0x00;
410 ram_table->bright_neg_gain[2][1] = 0x00;
411 ram_table->bright_neg_gain[2][2] = 0x00;
412 ram_table->bright_neg_gain[2][3] = 0x00;
413 ram_table->bright_neg_gain[3][0] = 0x00;
414 ram_table->bright_neg_gain[3][1] = 0x00;
415 ram_table->bright_neg_gain[3][2] = 0x00;
416 ram_table->bright_neg_gain[3][3] = 0x00;
417 ram_table->bright_neg_gain[4][0] = 0x00;
418 ram_table->bright_neg_gain[4][1] = 0x00;
419 ram_table->bright_neg_gain[4][2] = 0x00;
420 ram_table->bright_neg_gain[4][3] = 0x00;
421 ram_table->dark_pos_gain[0][0] = 0x00;
422 ram_table->dark_pos_gain[0][1] = 0x00;
423 ram_table->dark_pos_gain[0][2] = 0x00;
424 ram_table->dark_pos_gain[0][3] = 0x00;
425 ram_table->dark_pos_gain[1][0] = 0x00;
426 ram_table->dark_pos_gain[1][1] = 0x00;
427 ram_table->dark_pos_gain[1][2] = 0x00;
428 ram_table->dark_pos_gain[1][3] = 0x00;
429 ram_table->dark_pos_gain[2][0] = 0x00;
430 ram_table->dark_pos_gain[2][1] = 0x00;
431 ram_table->dark_pos_gain[2][2] = 0x00;
432 ram_table->dark_pos_gain[2][3] = 0x00;
433 ram_table->dark_pos_gain[3][0] = 0x00;
434 ram_table->dark_pos_gain[3][1] = 0x00;
435 ram_table->dark_pos_gain[3][2] = 0x00;
436 ram_table->dark_pos_gain[3][3] = 0x00;
437 ram_table->dark_pos_gain[4][0] = 0x00;
438 ram_table->dark_pos_gain[4][1] = 0x00;
439 ram_table->dark_pos_gain[4][2] = 0x00;
440 ram_table->dark_pos_gain[4][3] = 0x00;
441 ram_table->dark_neg_gain[0][0] = 0x00;
442 ram_table->dark_neg_gain[0][1] = 0x00;
443 ram_table->dark_neg_gain[0][2] = 0x00;
444 ram_table->dark_neg_gain[0][3] = 0x00;
445 ram_table->dark_neg_gain[1][0] = 0x00;
446 ram_table->dark_neg_gain[1][1] = 0x00;
447 ram_table->dark_neg_gain[1][2] = 0x00;
448 ram_table->dark_neg_gain[1][3] = 0x00;
449 ram_table->dark_neg_gain[2][0] = 0x00;
450 ram_table->dark_neg_gain[2][1] = 0x00;
451 ram_table->dark_neg_gain[2][2] = 0x00;
452 ram_table->dark_neg_gain[2][3] = 0x00;
453 ram_table->dark_neg_gain[3][0] = 0x00;
454 ram_table->dark_neg_gain[3][1] = 0x00;
455 ram_table->dark_neg_gain[3][2] = 0x00;
456 ram_table->dark_neg_gain[3][3] = 0x00;
457 ram_table->dark_neg_gain[4][0] = 0x00;
458 ram_table->dark_neg_gain[4][1] = 0x00;
459 ram_table->dark_neg_gain[4][2] = 0x00;
460 ram_table->dark_neg_gain[4][3] = 0x00;
461
462 ram_table->iir_curve[0] = 0x65;
463 ram_table->iir_curve[1] = 0x65;
464 ram_table->iir_curve[2] = 0x65;
465 ram_table->iir_curve[3] = 0x65;
466 ram_table->iir_curve[4] = 0x65;
467
468 //Gamma 2.4
469 ram_table->crgb_thresh[0] = cpu_to_be16(0x13b6);
470 ram_table->crgb_thresh[1] = cpu_to_be16(0x1648);
471 ram_table->crgb_thresh[2] = cpu_to_be16(0x18e3);
472 ram_table->crgb_thresh[3] = cpu_to_be16(0x1b41);
473 ram_table->crgb_thresh[4] = cpu_to_be16(0x1d46);
474 ram_table->crgb_thresh[5] = cpu_to_be16(0x1f21);
475 ram_table->crgb_thresh[6] = cpu_to_be16(0x2167);
476 ram_table->crgb_thresh[7] = cpu_to_be16(0x2384);
477 ram_table->crgb_offset[0] = cpu_to_be16(0x2999);
478 ram_table->crgb_offset[1] = cpu_to_be16(0x3999);
479 ram_table->crgb_offset[2] = cpu_to_be16(0x4666);
480 ram_table->crgb_offset[3] = cpu_to_be16(0x5999);
481 ram_table->crgb_offset[4] = cpu_to_be16(0x6333);
482 ram_table->crgb_offset[5] = cpu_to_be16(0x7800);
483 ram_table->crgb_offset[6] = cpu_to_be16(0x8c00);
484 ram_table->crgb_offset[7] = cpu_to_be16(0xa000);
485 ram_table->crgb_slope[0] = cpu_to_be16(0x3147);
486 ram_table->crgb_slope[1] = cpu_to_be16(0x2978);
487 ram_table->crgb_slope[2] = cpu_to_be16(0x23a2);
488 ram_table->crgb_slope[3] = cpu_to_be16(0x1f55);
489 ram_table->crgb_slope[4] = cpu_to_be16(0x1c63);
490 ram_table->crgb_slope[5] = cpu_to_be16(0x1a0f);
491 ram_table->crgb_slope[6] = cpu_to_be16(0x178d);
492 ram_table->crgb_slope[7] = cpu_to_be16(0x15ab);
493
494 fill_backlight_transform_table(
495 params, ram_table);
496 }
497
fill_iram_v_2_2(struct iram_table_v_2_2 * ram_table,struct dmcu_iram_parameters params)498 static void fill_iram_v_2_2(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params)
499 {
500 unsigned int set = params.set;
501
502 ram_table->flags = 0x0;
503
504 ram_table->min_abm_backlight =
505 cpu_to_be16(params.min_abm_backlight);
506
507 ram_table->deviation_gain[0] = 0xb3;
508 ram_table->deviation_gain[1] = 0xa8;
509 ram_table->deviation_gain[2] = 0x98;
510 ram_table->deviation_gain[3] = 0x68;
511
512 ram_table->min_reduction[0][0] = min_reduction_table_v_2_2[abm_config[set][0]];
513 ram_table->min_reduction[1][0] = min_reduction_table_v_2_2[abm_config[set][0]];
514 ram_table->min_reduction[2][0] = min_reduction_table_v_2_2[abm_config[set][0]];
515 ram_table->min_reduction[3][0] = min_reduction_table_v_2_2[abm_config[set][0]];
516 ram_table->min_reduction[4][0] = min_reduction_table_v_2_2[abm_config[set][0]];
517 ram_table->max_reduction[0][0] = max_reduction_table_v_2_2[abm_config[set][0]];
518 ram_table->max_reduction[1][0] = max_reduction_table_v_2_2[abm_config[set][0]];
519 ram_table->max_reduction[2][0] = max_reduction_table_v_2_2[abm_config[set][0]];
520 ram_table->max_reduction[3][0] = max_reduction_table_v_2_2[abm_config[set][0]];
521 ram_table->max_reduction[4][0] = max_reduction_table_v_2_2[abm_config[set][0]];
522
523 ram_table->min_reduction[0][1] = min_reduction_table_v_2_2[abm_config[set][1]];
524 ram_table->min_reduction[1][1] = min_reduction_table_v_2_2[abm_config[set][1]];
525 ram_table->min_reduction[2][1] = min_reduction_table_v_2_2[abm_config[set][1]];
526 ram_table->min_reduction[3][1] = min_reduction_table_v_2_2[abm_config[set][1]];
527 ram_table->min_reduction[4][1] = min_reduction_table_v_2_2[abm_config[set][1]];
528 ram_table->max_reduction[0][1] = max_reduction_table_v_2_2[abm_config[set][1]];
529 ram_table->max_reduction[1][1] = max_reduction_table_v_2_2[abm_config[set][1]];
530 ram_table->max_reduction[2][1] = max_reduction_table_v_2_2[abm_config[set][1]];
531 ram_table->max_reduction[3][1] = max_reduction_table_v_2_2[abm_config[set][1]];
532 ram_table->max_reduction[4][1] = max_reduction_table_v_2_2[abm_config[set][1]];
533
534 ram_table->min_reduction[0][2] = min_reduction_table_v_2_2[abm_config[set][2]];
535 ram_table->min_reduction[1][2] = min_reduction_table_v_2_2[abm_config[set][2]];
536 ram_table->min_reduction[2][2] = min_reduction_table_v_2_2[abm_config[set][2]];
537 ram_table->min_reduction[3][2] = min_reduction_table_v_2_2[abm_config[set][2]];
538 ram_table->min_reduction[4][2] = min_reduction_table_v_2_2[abm_config[set][2]];
539 ram_table->max_reduction[0][2] = max_reduction_table_v_2_2[abm_config[set][2]];
540 ram_table->max_reduction[1][2] = max_reduction_table_v_2_2[abm_config[set][2]];
541 ram_table->max_reduction[2][2] = max_reduction_table_v_2_2[abm_config[set][2]];
542 ram_table->max_reduction[3][2] = max_reduction_table_v_2_2[abm_config[set][2]];
543 ram_table->max_reduction[4][2] = max_reduction_table_v_2_2[abm_config[set][2]];
544
545 ram_table->min_reduction[0][3] = min_reduction_table_v_2_2[abm_config[set][3]];
546 ram_table->min_reduction[1][3] = min_reduction_table_v_2_2[abm_config[set][3]];
547 ram_table->min_reduction[2][3] = min_reduction_table_v_2_2[abm_config[set][3]];
548 ram_table->min_reduction[3][3] = min_reduction_table_v_2_2[abm_config[set][3]];
549 ram_table->min_reduction[4][3] = min_reduction_table_v_2_2[abm_config[set][3]];
550 ram_table->max_reduction[0][3] = max_reduction_table_v_2_2[abm_config[set][3]];
551 ram_table->max_reduction[1][3] = max_reduction_table_v_2_2[abm_config[set][3]];
552 ram_table->max_reduction[2][3] = max_reduction_table_v_2_2[abm_config[set][3]];
553 ram_table->max_reduction[3][3] = max_reduction_table_v_2_2[abm_config[set][3]];
554 ram_table->max_reduction[4][3] = max_reduction_table_v_2_2[abm_config[set][3]];
555
556 ram_table->bright_pos_gain[0][0] = 0x20;
557 ram_table->bright_pos_gain[0][1] = 0x20;
558 ram_table->bright_pos_gain[0][2] = 0x20;
559 ram_table->bright_pos_gain[0][3] = 0x20;
560 ram_table->bright_pos_gain[1][0] = 0x20;
561 ram_table->bright_pos_gain[1][1] = 0x20;
562 ram_table->bright_pos_gain[1][2] = 0x20;
563 ram_table->bright_pos_gain[1][3] = 0x20;
564 ram_table->bright_pos_gain[2][0] = 0x20;
565 ram_table->bright_pos_gain[2][1] = 0x20;
566 ram_table->bright_pos_gain[2][2] = 0x20;
567 ram_table->bright_pos_gain[2][3] = 0x20;
568 ram_table->bright_pos_gain[3][0] = 0x20;
569 ram_table->bright_pos_gain[3][1] = 0x20;
570 ram_table->bright_pos_gain[3][2] = 0x20;
571 ram_table->bright_pos_gain[3][3] = 0x20;
572 ram_table->bright_pos_gain[4][0] = 0x20;
573 ram_table->bright_pos_gain[4][1] = 0x20;
574 ram_table->bright_pos_gain[4][2] = 0x20;
575 ram_table->bright_pos_gain[4][3] = 0x20;
576
577 ram_table->dark_pos_gain[0][0] = 0x00;
578 ram_table->dark_pos_gain[0][1] = 0x00;
579 ram_table->dark_pos_gain[0][2] = 0x00;
580 ram_table->dark_pos_gain[0][3] = 0x00;
581 ram_table->dark_pos_gain[1][0] = 0x00;
582 ram_table->dark_pos_gain[1][1] = 0x00;
583 ram_table->dark_pos_gain[1][2] = 0x00;
584 ram_table->dark_pos_gain[1][3] = 0x00;
585 ram_table->dark_pos_gain[2][0] = 0x00;
586 ram_table->dark_pos_gain[2][1] = 0x00;
587 ram_table->dark_pos_gain[2][2] = 0x00;
588 ram_table->dark_pos_gain[2][3] = 0x00;
589 ram_table->dark_pos_gain[3][0] = 0x00;
590 ram_table->dark_pos_gain[3][1] = 0x00;
591 ram_table->dark_pos_gain[3][2] = 0x00;
592 ram_table->dark_pos_gain[3][3] = 0x00;
593 ram_table->dark_pos_gain[4][0] = 0x00;
594 ram_table->dark_pos_gain[4][1] = 0x00;
595 ram_table->dark_pos_gain[4][2] = 0x00;
596 ram_table->dark_pos_gain[4][3] = 0x00;
597
598 ram_table->hybrid_factor[0] = 0xff;
599 ram_table->hybrid_factor[1] = 0xff;
600 ram_table->hybrid_factor[2] = 0xff;
601 ram_table->hybrid_factor[3] = 0xc0;
602
603 ram_table->contrast_factor[0] = 0x99;
604 ram_table->contrast_factor[1] = 0x99;
605 ram_table->contrast_factor[2] = 0x90;
606 ram_table->contrast_factor[3] = 0x80;
607
608 ram_table->iir_curve[0] = 0x65;
609 ram_table->iir_curve[1] = 0x65;
610 ram_table->iir_curve[2] = 0x65;
611 ram_table->iir_curve[3] = 0x65;
612 ram_table->iir_curve[4] = 0x65;
613
614 //Gamma 2.2
615 ram_table->crgb_thresh[0] = cpu_to_be16(0x127c);
616 ram_table->crgb_thresh[1] = cpu_to_be16(0x151b);
617 ram_table->crgb_thresh[2] = cpu_to_be16(0x17d5);
618 ram_table->crgb_thresh[3] = cpu_to_be16(0x1a56);
619 ram_table->crgb_thresh[4] = cpu_to_be16(0x1c83);
620 ram_table->crgb_thresh[5] = cpu_to_be16(0x1e72);
621 ram_table->crgb_thresh[6] = cpu_to_be16(0x20f0);
622 ram_table->crgb_thresh[7] = cpu_to_be16(0x232b);
623 ram_table->crgb_offset[0] = cpu_to_be16(0x2999);
624 ram_table->crgb_offset[1] = cpu_to_be16(0x3999);
625 ram_table->crgb_offset[2] = cpu_to_be16(0x4666);
626 ram_table->crgb_offset[3] = cpu_to_be16(0x5999);
627 ram_table->crgb_offset[4] = cpu_to_be16(0x6333);
628 ram_table->crgb_offset[5] = cpu_to_be16(0x7800);
629 ram_table->crgb_offset[6] = cpu_to_be16(0x8c00);
630 ram_table->crgb_offset[7] = cpu_to_be16(0xa000);
631 ram_table->crgb_slope[0] = cpu_to_be16(0x3609);
632 ram_table->crgb_slope[1] = cpu_to_be16(0x2dfa);
633 ram_table->crgb_slope[2] = cpu_to_be16(0x27ea);
634 ram_table->crgb_slope[3] = cpu_to_be16(0x235d);
635 ram_table->crgb_slope[4] = cpu_to_be16(0x2042);
636 ram_table->crgb_slope[5] = cpu_to_be16(0x1dc3);
637 ram_table->crgb_slope[6] = cpu_to_be16(0x1b1a);
638 ram_table->crgb_slope[7] = cpu_to_be16(0x1910);
639
640 fill_backlight_transform_table_v_2_2(
641 params, ram_table, true);
642 }
643
fill_iram_v_2_3(struct iram_table_v_2_2 * ram_table,struct dmcu_iram_parameters params,bool big_endian)644 static void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params, bool big_endian)
645 {
646 unsigned int i, j;
647 unsigned int set = params.set;
648
649 ram_table->flags = 0x0;
650 ram_table->min_abm_backlight = (big_endian) ?
651 cpu_to_be16(params.min_abm_backlight) :
652 cpu_to_le16(params.min_abm_backlight);
653
654 for (i = 0; i < NUM_AGGR_LEVEL; i++) {
655 ram_table->hybrid_factor[i] = abm_settings[set][i].brightness_gain;
656 ram_table->contrast_factor[i] = abm_settings[set][i].contrast_factor;
657 ram_table->deviation_gain[i] = abm_settings[set][i].deviation_gain;
658 ram_table->min_knee[i] = abm_settings[set][i].min_knee;
659 ram_table->max_knee[i] = abm_settings[set][i].max_knee;
660
661 for (j = 0; j < NUM_AMBI_LEVEL; j++) {
662 ram_table->min_reduction[j][i] = abm_settings[set][i].min_reduction;
663 ram_table->max_reduction[j][i] = abm_settings[set][i].max_reduction;
664 ram_table->bright_pos_gain[j][i] = abm_settings[set][i].bright_pos_gain;
665 ram_table->dark_pos_gain[j][i] = abm_settings[set][i].dark_pos_gain;
666 }
667 }
668
669 ram_table->iir_curve[0] = 0x65;
670 ram_table->iir_curve[1] = 0x65;
671 ram_table->iir_curve[2] = 0x65;
672 ram_table->iir_curve[3] = 0x65;
673 ram_table->iir_curve[4] = 0x65;
674
675 //Gamma 2.2
676 ram_table->crgb_thresh[0] = bswap16_based_on_endian(big_endian, 0x127c);
677 ram_table->crgb_thresh[1] = bswap16_based_on_endian(big_endian, 0x151b);
678 ram_table->crgb_thresh[2] = bswap16_based_on_endian(big_endian, 0x17d5);
679 ram_table->crgb_thresh[3] = bswap16_based_on_endian(big_endian, 0x1a56);
680 ram_table->crgb_thresh[4] = bswap16_based_on_endian(big_endian, 0x1c83);
681 ram_table->crgb_thresh[5] = bswap16_based_on_endian(big_endian, 0x1e72);
682 ram_table->crgb_thresh[6] = bswap16_based_on_endian(big_endian, 0x20f0);
683 ram_table->crgb_thresh[7] = bswap16_based_on_endian(big_endian, 0x232b);
684 ram_table->crgb_offset[0] = bswap16_based_on_endian(big_endian, 0x2999);
685 ram_table->crgb_offset[1] = bswap16_based_on_endian(big_endian, 0x3999);
686 ram_table->crgb_offset[2] = bswap16_based_on_endian(big_endian, 0x4666);
687 ram_table->crgb_offset[3] = bswap16_based_on_endian(big_endian, 0x5999);
688 ram_table->crgb_offset[4] = bswap16_based_on_endian(big_endian, 0x6333);
689 ram_table->crgb_offset[5] = bswap16_based_on_endian(big_endian, 0x7800);
690 ram_table->crgb_offset[6] = bswap16_based_on_endian(big_endian, 0x8c00);
691 ram_table->crgb_offset[7] = bswap16_based_on_endian(big_endian, 0xa000);
692 ram_table->crgb_slope[0] = bswap16_based_on_endian(big_endian, 0x3609);
693 ram_table->crgb_slope[1] = bswap16_based_on_endian(big_endian, 0x2dfa);
694 ram_table->crgb_slope[2] = bswap16_based_on_endian(big_endian, 0x27ea);
695 ram_table->crgb_slope[3] = bswap16_based_on_endian(big_endian, 0x235d);
696 ram_table->crgb_slope[4] = bswap16_based_on_endian(big_endian, 0x2042);
697 ram_table->crgb_slope[5] = bswap16_based_on_endian(big_endian, 0x1dc3);
698 ram_table->crgb_slope[6] = bswap16_based_on_endian(big_endian, 0x1b1a);
699 ram_table->crgb_slope[7] = bswap16_based_on_endian(big_endian, 0x1910);
700
701 fill_backlight_transform_table_v_2_2(
702 params, ram_table, big_endian);
703 }
704
dmub_init_abm_config(struct resource_pool * res_pool,struct dmcu_iram_parameters params,unsigned int inst)705 bool dmub_init_abm_config(struct resource_pool *res_pool,
706 struct dmcu_iram_parameters params,
707 unsigned int inst)
708 {
709 struct iram_table_v_2_2 ram_table;
710 struct abm_config_table config;
711 unsigned int set = params.set;
712 bool result = false;
713 uint32_t i, j = 0;
714
715 if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)
716 return false;
717
718 memset(&ram_table, 0, sizeof(ram_table));
719 memset(&config, 0, sizeof(config));
720
721 fill_iram_v_2_3(&ram_table, params, false);
722
723 // We must copy to structure that is aligned to 32-bit
724 for (i = 0; i < NUM_POWER_FN_SEGS; i++) {
725 config.crgb_thresh[i] = ram_table.crgb_thresh[i];
726 config.crgb_offset[i] = ram_table.crgb_offset[i];
727 config.crgb_slope[i] = ram_table.crgb_slope[i];
728 }
729
730 for (i = 0; i < NUM_BL_CURVE_SEGS; i++) {
731 config.backlight_thresholds[i] = ram_table.backlight_thresholds[i];
732 config.backlight_offsets[i] = ram_table.backlight_offsets[i];
733 }
734
735 for (i = 0; i < NUM_AMBI_LEVEL; i++)
736 config.iir_curve[i] = ram_table.iir_curve[i];
737
738 for (i = 0; i < NUM_AMBI_LEVEL; i++) {
739 for (j = 0; j < NUM_AGGR_LEVEL; j++) {
740 config.min_reduction[i][j] = ram_table.min_reduction[i][j];
741 config.max_reduction[i][j] = ram_table.max_reduction[i][j];
742 config.bright_pos_gain[i][j] = ram_table.bright_pos_gain[i][j];
743 config.dark_pos_gain[i][j] = ram_table.dark_pos_gain[i][j];
744 }
745 }
746
747 for (i = 0; i < NUM_AGGR_LEVEL; i++) {
748 config.hybrid_factor[i] = ram_table.hybrid_factor[i];
749 config.contrast_factor[i] = ram_table.contrast_factor[i];
750 config.deviation_gain[i] = ram_table.deviation_gain[i];
751 config.min_knee[i] = ram_table.min_knee[i];
752 config.max_knee[i] = ram_table.max_knee[i];
753 }
754
755 if (params.backlight_ramping_override) {
756
757 ASSERT(params.backlight_ramping_reduction <= 0xFFFF);
758 ASSERT(params.backlight_ramping_start <= 0xFFFF);
759 for (i = 0; i < NUM_AGGR_LEVEL; i++) {
760 config.blRampReduction[i] = (uint16_t)params.backlight_ramping_reduction;
761 config.blRampStart[i] = (uint16_t)params.backlight_ramping_start;
762 }
763 } else {
764 for (i = 0; i < NUM_AGGR_LEVEL; i++) {
765 config.blRampReduction[i] = abm_settings[set][i].blRampReduction;
766 config.blRampStart[i] = abm_settings[set][i].blRampStart;
767 }
768 }
769
770 config.min_abm_backlight = ram_table.min_abm_backlight;
771
772 if (res_pool->multiple_abms[inst]) {
773 result = res_pool->multiple_abms[inst]->funcs->init_abm_config(
774 res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst);
775 } else
776 result = res_pool->abm->funcs->init_abm_config(
777 res_pool->abm, (char *)(&config), sizeof(struct abm_config_table), 0);
778
779 return result;
780 }
781
dmcu_load_iram(struct dmcu * dmcu,struct dmcu_iram_parameters params)782 bool dmcu_load_iram(struct dmcu *dmcu,
783 struct dmcu_iram_parameters params)
784 {
785 unsigned char ram_table[IRAM_SIZE];
786 bool result = false;
787
788 if (dmcu == NULL)
789 return false;
790
791 if (dmcu && !dmcu->funcs->is_dmcu_initialized(dmcu))
792 return true;
793
794 memset(&ram_table, 0, sizeof(ram_table));
795
796 if (dmcu->dmcu_version.abm_version == 0x24) {
797 fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true);
798 result = dmcu->funcs->load_iram(dmcu, 0, (char *)(&ram_table),
799 IRAM_RESERVE_AREA_START_V2_2);
800 } else if (dmcu->dmcu_version.abm_version == 0x23) {
801 fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true);
802
803 result = dmcu->funcs->load_iram(
804 dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
805 } else if (dmcu->dmcu_version.abm_version == 0x22) {
806 fill_iram_v_2_2((struct iram_table_v_2_2 *)ram_table, params);
807
808 result = dmcu->funcs->load_iram(
809 dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
810 } else {
811 fill_iram_v_2((struct iram_table_v_2 *)ram_table, params);
812
813 result = dmcu->funcs->load_iram(
814 dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2);
815
816 if (result)
817 result = dmcu->funcs->load_iram(
818 dmcu, IRAM_RESERVE_AREA_END_V2 + 1,
819 (char *)(&ram_table) + IRAM_RESERVE_AREA_END_V2 + 1,
820 sizeof(ram_table) - IRAM_RESERVE_AREA_END_V2 - 1);
821 }
822
823 return result;
824 }
825
826 /*
827 * is_psr_su_specific_panel() - check if sink is AMD vendor-specific PSR-SU
828 * supported eDP device.
829 *
830 * @link: dc link pointer
831 *
832 * Return: true if AMDGPU vendor specific PSR-SU eDP panel
833 */
is_psr_su_specific_panel(struct dc_link * link)834 bool is_psr_su_specific_panel(struct dc_link *link)
835 {
836 bool isPSRSUSupported = false;
837 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
838
839 if (dpcd_caps->edp_rev >= DP_EDP_14) {
840 if (dpcd_caps->psr_info.psr_version >= DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
841 isPSRSUSupported = true;
842 /*
843 * Some panels will report PSR capabilities over additional DPCD bits.
844 * Such panels are approved despite reporting only PSR v3, as long as
845 * the additional bits are reported.
846 */
847 if (dpcd_caps->sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8) {
848 /*
849 * This is the temporary workaround to disable PSRSU when system turned on
850 * DSC function on the sepcific sink.
851 */
852 if (dpcd_caps->psr_info.psr_version < DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)
853 isPSRSUSupported = false;
854 else if (dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
855 ((dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x08) ||
856 (dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x07)))
857 isPSRSUSupported = false;
858 else if (dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x03)
859 isPSRSUSupported = false;
860 else if (dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x01)
861 isPSRSUSupported = false;
862 else if (dpcd_caps->psr_info.force_psrsu_cap == 0x1)
863 isPSRSUSupported = true;
864 }
865 }
866
867 return isPSRSUSupported;
868 }
869
870 /**
871 * mod_power_calc_psr_configs() - calculate/update generic psr configuration fields.
872 * @psr_config: [output], psr configuration structure to be updated
873 * @link: [input] dc link pointer
874 * @stream: [input] dc stream state pointer
875 *
876 * calculate and update the psr configuration fields that are not DM specific, i.e. such
877 * fields which are based on DPCD caps or timing information. To setup PSR in DMUB FW,
878 * this helper is assumed to be called before the call of the DC helper dc_link_setup_psr().
879 *
880 * PSR config fields to be updated within the helper:
881 * - psr_rfb_setup_time
882 * - psr_sdp_transmit_line_num_deadline
883 * - line_time_in_us
884 * - su_y_granularity
885 * - su_granularity_required
886 * - psr_frame_capture_indication_req
887 * - psr_exit_link_training_required
888 *
889 * PSR config fields that are DM specific and NOT updated within the helper:
890 * - allow_smu_optimizations
891 * - allow_multi_disp_optimizations
892 */
mod_power_calc_psr_configs(struct psr_config * psr_config,struct dc_link * link,const struct dc_stream_state * stream)893 void mod_power_calc_psr_configs(struct psr_config *psr_config,
894 struct dc_link *link,
895 const struct dc_stream_state *stream)
896 {
897 unsigned int num_vblank_lines = 0;
898 unsigned int vblank_time_in_us = 0;
899 unsigned int sdp_tx_deadline_in_us = 0;
900 unsigned int line_time_in_us = 0;
901 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
902 const int psr_setup_time_step_in_us = 55; /* refer to eDP spec DPCD 0x071h */
903
904 /* timing parameters */
905 num_vblank_lines = stream->timing.v_total -
906 stream->timing.v_addressable -
907 stream->timing.v_border_top -
908 stream->timing.v_border_bottom;
909
910 vblank_time_in_us = (stream->timing.h_total * num_vblank_lines * 1000) / (stream->timing.pix_clk_100hz / 10);
911
912 line_time_in_us = ((stream->timing.h_total * 1000) / (stream->timing.pix_clk_100hz / 10)) + 1;
913
914 /**
915 * psr configuration fields
916 *
917 * as per eDP 1.5 pg. 377 of 459, DPCD 0x071h bits [3:1], psr setup time bits interpreted as below
918 * 000b <--> 330 us (default)
919 * 001b <--> 275 us
920 * 010b <--> 220 us
921 * 011b <--> 165 us
922 * 100b <--> 110 us
923 * 101b <--> 055 us
924 * 110b <--> 000 us
925 */
926 psr_config->psr_rfb_setup_time =
927 (6 - dpcd_caps->psr_info.psr_dpcd_caps.bits.PSR_SETUP_TIME) * psr_setup_time_step_in_us;
928
929 if (psr_config->psr_rfb_setup_time > vblank_time_in_us) {
930 link->psr_settings.psr_frame_capture_indication_req = true;
931 link->psr_settings.psr_sdp_transmit_line_num_deadline = num_vblank_lines;
932 } else {
933 sdp_tx_deadline_in_us = vblank_time_in_us - psr_config->psr_rfb_setup_time;
934
935 /* Set the last possible line SDP may be transmitted without violating the RFB setup time */
936 link->psr_settings.psr_frame_capture_indication_req = false;
937 link->psr_settings.psr_sdp_transmit_line_num_deadline = sdp_tx_deadline_in_us / line_time_in_us;
938 }
939
940 psr_config->psr_sdp_transmit_line_num_deadline = link->psr_settings.psr_sdp_transmit_line_num_deadline;
941 psr_config->line_time_in_us = line_time_in_us;
942 psr_config->su_y_granularity = dpcd_caps->psr_info.psr2_su_y_granularity_cap;
943 psr_config->su_granularity_required = dpcd_caps->psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED;
944 psr_config->psr_frame_capture_indication_req = link->psr_settings.psr_frame_capture_indication_req;
945 psr_config->psr_exit_link_training_required =
946 !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.LINK_TRAINING_ON_EXIT_NOT_REQUIRED;
947 }
948
init_replay_config(struct dc_link * link,struct replay_config * pr_config)949 void init_replay_config(struct dc_link *link, struct replay_config *pr_config)
950 {
951 link->replay_settings.config = *pr_config;
952 }
953
mod_power_only_edp(const struct dc_state * context,const struct dc_stream_state * stream)954 bool mod_power_only_edp(const struct dc_state *context, const struct dc_stream_state *stream)
955 {
956 return context && context->stream_count == 1 && dc_is_embedded_signal(stream->signal);
957 }
958
psr_su_set_dsc_slice_height(struct dc * dc,struct dc_link * link,struct dc_stream_state * stream,struct psr_config * config)959 bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,
960 struct dc_stream_state *stream,
961 struct psr_config *config)
962 {
963 uint16_t pic_height;
964 uint16_t slice_height;
965
966 config->dsc_slice_height = 0;
967 if (!(link->connector_signal & SIGNAL_TYPE_EDP) ||
968 !dc->caps.edp_dsc_support ||
969 link->panel_config.dsc.disable_dsc_edp ||
970 !link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
971 !stream->timing.dsc_cfg.num_slices_v)
972 return true;
973
974 pic_height = stream->timing.v_addressable +
975 stream->timing.v_border_top + stream->timing.v_border_bottom;
976
977 if (stream->timing.dsc_cfg.num_slices_v == 0)
978 return false;
979
980 slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v;
981 config->dsc_slice_height = slice_height;
982
983 if (slice_height) {
984 if (config->su_y_granularity &&
985 (slice_height % config->su_y_granularity)) {
986 ASSERT(0);
987 return false;
988 }
989 }
990
991 return true;
992 }
993
set_replay_frame_skip_number(struct dc_link * link,enum replay_coasting_vtotal_type type,uint32_t coasting_vtotal_refresh_rate_mhz,uint32_t flicker_free_refresh_rate_mhz,bool is_defer)994 void set_replay_frame_skip_number(struct dc_link *link,
995 enum replay_coasting_vtotal_type type,
996 uint32_t coasting_vtotal_refresh_rate_mhz,
997 uint32_t flicker_free_refresh_rate_mhz,
998 bool is_defer)
999 {
1000 uint32_t *frame_skip_number_array = NULL;
1001 uint32_t frame_skip_number = 0;
1002
1003 if (link == NULL)
1004 return;
1005
1006 if (false == link->replay_settings.config.frame_skip_supported)
1007 return;
1008
1009 if (flicker_free_refresh_rate_mhz == 0 || coasting_vtotal_refresh_rate_mhz == 0)
1010 return;
1011
1012 if (is_defer)
1013 frame_skip_number_array = link->replay_settings.defer_frame_skip_number_table;
1014 else
1015 frame_skip_number_array = link->replay_settings.frame_skip_number_table;
1016
1017 if (frame_skip_number_array == NULL)
1018 return;
1019
1020 frame_skip_number = coasting_vtotal_refresh_rate_mhz / flicker_free_refresh_rate_mhz;
1021
1022 if (frame_skip_number >= 1)
1023 frame_skip_number_array[type] = frame_skip_number - 1;
1024 else
1025 frame_skip_number_array[type] = 0;
1026 }
1027
set_replay_defer_update_coasting_vtotal(struct dc_link * link,enum replay_coasting_vtotal_type type,uint32_t vtotal)1028 void set_replay_defer_update_coasting_vtotal(struct dc_link *link,
1029 enum replay_coasting_vtotal_type type,
1030 uint32_t vtotal)
1031 {
1032 link->replay_settings.defer_update_coasting_vtotal_table[type] = vtotal;
1033 }
1034
update_replay_coasting_vtotal_from_defer(struct dc_link * link,enum replay_coasting_vtotal_type type)1035 void update_replay_coasting_vtotal_from_defer(struct dc_link *link,
1036 enum replay_coasting_vtotal_type type)
1037 {
1038 link->replay_settings.coasting_vtotal_table[type] =
1039 link->replay_settings.defer_update_coasting_vtotal_table[type];
1040 link->replay_settings.frame_skip_number_table[type] =
1041 link->replay_settings.defer_frame_skip_number_table[type];
1042 }
1043
set_replay_coasting_vtotal(struct dc_link * link,enum replay_coasting_vtotal_type type,uint32_t vtotal)1044 void set_replay_coasting_vtotal(struct dc_link *link,
1045 enum replay_coasting_vtotal_type type,
1046 uint32_t vtotal)
1047 {
1048 link->replay_settings.coasting_vtotal_table[type] = vtotal;
1049 }
1050
set_replay_low_rr_full_screen_video_src_vtotal(struct dc_link * link,uint16_t vtotal)1051 void set_replay_low_rr_full_screen_video_src_vtotal(struct dc_link *link, uint16_t vtotal)
1052 {
1053 link->replay_settings.low_rr_full_screen_video_pseudo_vtotal = vtotal;
1054 }
1055
calculate_replay_link_off_frame_count(struct dc_link * link,uint16_t vtotal,uint16_t htotal)1056 void calculate_replay_link_off_frame_count(struct dc_link *link,
1057 uint16_t vtotal, uint16_t htotal)
1058 {
1059 uint8_t max_link_off_frame_count = 0;
1060 uint16_t max_deviation_line = 0, pixel_deviation_per_line = 0;
1061
1062 if (!link || link->replay_settings.config.replay_version != DC_FREESYNC_REPLAY)
1063 return;
1064
1065 max_deviation_line = link->dpcd_caps.pr_info.max_deviation_line;
1066 pixel_deviation_per_line = link->dpcd_caps.pr_info.pixel_deviation_per_line;
1067
1068 if (htotal != 0 && vtotal != 0 && pixel_deviation_per_line != 0)
1069 max_link_off_frame_count = htotal * max_deviation_line / (pixel_deviation_per_line * vtotal);
1070 else
1071 ASSERT(0);
1072
1073 link->replay_settings.link_off_frame_count = max_link_off_frame_count;
1074 }
1075
fill_custom_backlight_caps(unsigned int config_no,struct dm_acpi_atif_backlight_caps * caps)1076 bool fill_custom_backlight_caps(unsigned int config_no, struct dm_acpi_atif_backlight_caps *caps)
1077 {
1078 unsigned int data_points_size;
1079 uint64_t caps_size;
1080
1081 if (config_no >= ARRAY_SIZE(custom_backlight_profiles))
1082 return false;
1083
1084 data_points_size = custom_backlight_profiles[config_no].num_data_points
1085 * sizeof(custom_backlight_profiles[config_no].data_points[0]);
1086
1087 caps_size = sizeof(struct dm_acpi_atif_backlight_caps) - sizeof(caps->data_points) + data_points_size;
1088 ASSERT(caps_size <= 0xFFFF);
1089 caps->size = (uint16_t)caps_size;
1090 caps->flags = 0;
1091 caps->error_code = 0;
1092 caps->ac_level_percentage = custom_backlight_profiles[config_no].ac_level_percentage;
1093 caps->dc_level_percentage = custom_backlight_profiles[config_no].dc_level_percentage;
1094 caps->min_input_signal = custom_backlight_profiles[config_no].min_input_signal;
1095 caps->max_input_signal = custom_backlight_profiles[config_no].max_input_signal;
1096 caps->num_data_points = custom_backlight_profiles[config_no].num_data_points;
1097 memcpy(caps->data_points, custom_backlight_profiles[config_no].data_points, data_points_size);
1098 return true;
1099 }
1100
reset_replay_dsync_error_count(struct dc_link * link)1101 void reset_replay_dsync_error_count(struct dc_link *link)
1102 {
1103 link->replay_settings.replay_desync_error_fail_count = 0;
1104 }
1105