1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2010 Broadcom Corporation 4 */ 5 6 #include <linux/types.h> 7 #include <linux/atomic.h> 8 #include <linux/kernel.h> 9 #include <linux/kthread.h> 10 #include <linux/printk.h> 11 #include <linux/pci_ids.h> 12 #include <linux/netdevice.h> 13 #include <linux/interrupt.h> 14 #include <linux/sched/signal.h> 15 #include <linux/mmc/sdio.h> 16 #include <linux/mmc/sdio_ids.h> 17 #include <linux/mmc/sdio_func.h> 18 #include <linux/mmc/card.h> 19 #include <linux/mmc/core.h> 20 #include <linux/semaphore.h> 21 #include <linux/firmware.h> 22 #include <linux/module.h> 23 #include <linux/bcma/bcma.h> 24 #include <linux/debugfs.h> 25 #include <linux/vmalloc.h> 26 #include <linux/unaligned.h> 27 #include <defs.h> 28 #include <brcmu_wifi.h> 29 #include <brcmu_utils.h> 30 #include <brcm_hw_ids.h> 31 #include <soc.h> 32 #include "sdio.h" 33 #include "chip.h" 34 #include "firmware.h" 35 #include "core.h" 36 #include "common.h" 37 #include "bcdc.h" 38 39 #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500) 40 #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500) 41 42 /* watermark expressed in number of words */ 43 #define DEFAULT_F2_WATERMARK 0x8 44 #define CY_4373_F2_WATERMARK 0x40 45 #define CY_4373_F1_MESBUSYCTRL (CY_4373_F2_WATERMARK | SBSDIO_MESBUSYCTRL_ENAB) 46 #define CY_43012_F2_WATERMARK 0x60 47 #define CY_43012_MES_WATERMARK 0x50 48 #define CY_43012_MESBUSYCTRL (CY_43012_MES_WATERMARK | \ 49 SBSDIO_MESBUSYCTRL_ENAB) 50 #define CY_4339_F2_WATERMARK 48 51 #define CY_4339_MES_WATERMARK 80 52 #define CY_4339_MESBUSYCTRL (CY_4339_MES_WATERMARK | \ 53 SBSDIO_MESBUSYCTRL_ENAB) 54 #define CY_43455_F2_WATERMARK 0x60 55 #define CY_43455_MES_WATERMARK 0x50 56 #define CY_43455_MESBUSYCTRL (CY_43455_MES_WATERMARK | \ 57 SBSDIO_MESBUSYCTRL_ENAB) 58 #define CY_435X_F2_WATERMARK 0x40 59 #define CY_435X_F1_MESBUSYCTRL (CY_435X_F2_WATERMARK | \ 60 SBSDIO_MESBUSYCTRL_ENAB) 61 62 #ifdef DEBUG 63 64 #define BRCMF_TRAP_INFO_SIZE 80 65 66 #define CBUF_LEN (128) 67 68 /* Device console log buffer state */ 69 #define CONSOLE_BUFFER_MAX 2024 70 71 struct rte_log_le { 72 __le32 buf; /* Can't be pointer on (64-bit) hosts */ 73 __le32 buf_size; 74 __le32 idx; 75 char *_buf_compat; /* Redundant pointer for backward compat. */ 76 }; 77 78 struct rte_console { 79 /* Virtual UART 80 * When there is no UART (e.g. Quickturn), 81 * the host should write a complete 82 * input line directly into cbuf and then write 83 * the length into vcons_in. 84 * This may also be used when there is a real UART 85 * (at risk of conflicting with 86 * the real UART). vcons_out is currently unused. 87 */ 88 uint vcons_in; 89 uint vcons_out; 90 91 /* Output (logging) buffer 92 * Console output is written to a ring buffer log_buf at index log_idx. 93 * The host may read the output when it sees log_idx advance. 94 * Output will be lost if the output wraps around faster than the host 95 * polls. 96 */ 97 struct rte_log_le log_le; 98 99 /* Console input line buffer 100 * Characters are read one at a time into cbuf 101 * until <CR> is received, then 102 * the buffer is processed as a command line. 103 * Also used for virtual UART. 104 */ 105 uint cbuf_idx; 106 char cbuf[CBUF_LEN]; 107 }; 108 109 #endif /* DEBUG */ 110 #include <chipcommon.h> 111 112 #include "bus.h" 113 #include "debug.h" 114 #include "tracepoint.h" 115 116 #define TXQLEN 2048 /* bulk tx queue length */ 117 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */ 118 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */ 119 #define PRIOMASK 7 120 121 #define TXRETRIES 2 /* # of retries for tx frames */ 122 123 #define BRCMF_RXBOUND 50 /* Default for max rx frames in 124 one scheduling */ 125 126 #define BRCMF_TXBOUND 20 /* Default for max tx frames in 127 one scheduling */ 128 129 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */ 130 131 #define MEMBLOCK 2048 /* Block size used for downloading 132 of dongle image */ 133 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold 134 biggest possible glom */ 135 136 #define BRCMF_FIRSTREAD (1 << 6) 137 138 /* SBSDIO_DEVICE_CTL */ 139 140 /* 1: device will assert busy signal when receiving CMD53 */ 141 #define SBSDIO_DEVCTL_SETBUSY 0x01 142 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */ 143 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 144 /* 1: mask all interrupts to host except the chipActive (rev 8) */ 145 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 146 /* 1: isolate internal sdio signals, put external pads in tri-state; requires 147 * sdio bus power cycle to clear (rev 9) */ 148 #define SBSDIO_DEVCTL_PADS_ISO 0x08 149 /* 1: enable F2 Watermark */ 150 #define SBSDIO_DEVCTL_F2WM_ENAB 0x10 151 /* Force SD->SB reset mapping (rev 11) */ 152 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30 153 /* Determined by CoreControl bit */ 154 #define SBSDIO_DEVCTL_RST_CORECTL 0x00 155 /* Force backplane reset */ 156 #define SBSDIO_DEVCTL_RST_BPRESET 0x10 157 /* Force no backplane reset */ 158 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 159 160 /* direct(mapped) cis space */ 161 162 /* MAPPED common CIS address */ 163 #define SBSDIO_CIS_BASE_COMMON 0x1000 164 /* maximum bytes in one CIS */ 165 #define SBSDIO_CIS_SIZE_LIMIT 0x200 166 /* cis offset addr is < 17 bits */ 167 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF 168 169 /* manfid tuple length, include tuple, link bytes */ 170 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6 171 172 #define SD_REG(field) \ 173 (offsetof(struct sdpcmd_regs, field)) 174 175 /* SDIO function 1 register CHIPCLKCSR */ 176 /* Force ALP request to backplane */ 177 #define SBSDIO_FORCE_ALP 0x01 178 /* Force HT request to backplane */ 179 #define SBSDIO_FORCE_HT 0x02 180 /* Force ILP request to backplane */ 181 #define SBSDIO_FORCE_ILP 0x04 182 /* Make ALP ready (power up xtal) */ 183 #define SBSDIO_ALP_AVAIL_REQ 0x08 184 /* Make HT ready (power up PLL) */ 185 #define SBSDIO_HT_AVAIL_REQ 0x10 186 /* Squelch clock requests from HW */ 187 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 188 /* Status: ALP is ready */ 189 #define SBSDIO_ALP_AVAIL 0x40 190 /* Status: HT is ready */ 191 #define SBSDIO_HT_AVAIL 0x80 192 #define SBSDIO_CSR_MASK 0x1F 193 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) 194 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) 195 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) 196 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) 197 #define SBSDIO_CLKAV(regval, alponly) \ 198 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval))) 199 200 /* intstatus */ 201 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ 202 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ 203 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ 204 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ 205 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ 206 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ 207 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ 208 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ 209 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ 210 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ 211 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ 212 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ 213 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ 214 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ 215 #define I_PC (1 << 10) /* descriptor error */ 216 #define I_PD (1 << 11) /* data error */ 217 #define I_DE (1 << 12) /* Descriptor protocol Error */ 218 #define I_RU (1 << 13) /* Receive descriptor Underflow */ 219 #define I_RO (1 << 14) /* Receive fifo Overflow */ 220 #define I_XU (1 << 15) /* Transmit fifo Underflow */ 221 #define I_RI (1 << 16) /* Receive Interrupt */ 222 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */ 223 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */ 224 #define I_XI (1 << 24) /* Transmit Interrupt */ 225 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */ 226 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */ 227 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */ 228 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */ 229 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */ 230 #define I_SRESET (1 << 30) /* CCCR RES interrupt */ 231 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */ 232 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) 233 #define I_DMA (I_RI | I_XI | I_ERRORS) 234 235 /* corecontrol */ 236 #define CC_CISRDY (1 << 0) /* CIS Ready */ 237 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */ 238 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */ 239 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */ 240 #define CC_XMTDATAAVAIL_MODE (1 << 4) 241 #define CC_XMTDATAAVAIL_CTRL (1 << 5) 242 243 /* SDA_FRAMECTRL */ 244 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ 245 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ 246 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */ 247 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */ 248 249 /* 250 * Software allocation of To SB Mailbox resources 251 */ 252 253 /* tosbmailbox bits corresponding to intstatus bits */ 254 #define SMB_NAK (1 << 0) /* Frame NAK */ 255 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */ 256 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */ 257 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */ 258 259 /* tosbmailboxdata */ 260 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */ 261 262 /* 263 * Software allocation of To Host Mailbox resources 264 */ 265 266 /* intstatus bits */ 267 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */ 268 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */ 269 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */ 270 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */ 271 272 /* tohostmailboxdata */ 273 #define HMB_DATA_NAKHANDLED 0x0001 /* retransmit NAK'd frame */ 274 #define HMB_DATA_DEVREADY 0x0002 /* talk to host after enable */ 275 #define HMB_DATA_FC 0x0004 /* per prio flowcontrol update flag */ 276 #define HMB_DATA_FWREADY 0x0008 /* fw ready for protocol activity */ 277 #define HMB_DATA_FWHALT 0x0010 /* firmware halted */ 278 279 #define HMB_DATA_FCDATA_MASK 0xff000000 280 #define HMB_DATA_FCDATA_SHIFT 24 281 282 #define HMB_DATA_VERSION_MASK 0x00ff0000 283 #define HMB_DATA_VERSION_SHIFT 16 284 285 /* 286 * Software-defined protocol header 287 */ 288 289 /* Current protocol version */ 290 #define SDPCM_PROT_VERSION 4 291 292 /* 293 * Shared structure between dongle and the host. 294 * The structure contains pointers to trap or assert information. 295 */ 296 #define SDPCM_SHARED_VERSION 0x0003 297 #define SDPCM_SHARED_VERSION_MASK 0x00FF 298 #define SDPCM_SHARED_ASSERT_BUILT 0x0100 299 #define SDPCM_SHARED_ASSERT 0x0200 300 #define SDPCM_SHARED_TRAP 0x0400 301 302 /* Space for header read, limit for data packets */ 303 #define MAX_HDR_READ (1 << 6) 304 #define MAX_RX_DATASZ 2048 305 306 /* Bump up limit on waiting for HT to account for first startup; 307 * if the image is doing a CRC calculation before programming the PMU 308 * for HT availability, it could take a couple hundred ms more, so 309 * max out at a 1 second (1000000us). 310 */ 311 #undef PMU_MAX_TRANSITION_DLY 312 #define PMU_MAX_TRANSITION_DLY 1000000 313 314 /* Value for ChipClockCSR during initial setup */ 315 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \ 316 SBSDIO_ALP_AVAIL_REQ) 317 318 /* Flags for SDH calls */ 319 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED) 320 321 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change 322 * when idle 323 */ 324 #define BRCMF_IDLE_INTERVAL 1 325 326 #define KSO_WAIT_US 50 327 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US) 328 #define BRCMF_SDIO_MAX_ACCESS_ERRORS 5 329 330 #ifdef DEBUG 331 /* Device console log buffer state */ 332 struct brcmf_console { 333 uint count; /* Poll interval msec counter */ 334 uint log_addr; /* Log struct address (fixed) */ 335 struct rte_log_le log_le; /* Log struct (host copy) */ 336 uint bufsize; /* Size of log buffer */ 337 u8 *buf; /* Log buffer (host copy) */ 338 uint last; /* Last buffer read index */ 339 }; 340 341 struct brcmf_trap_info { 342 __le32 type; 343 __le32 epc; 344 __le32 cpsr; 345 __le32 spsr; 346 __le32 r0; /* a1 */ 347 __le32 r1; /* a2 */ 348 __le32 r2; /* a3 */ 349 __le32 r3; /* a4 */ 350 __le32 r4; /* v1 */ 351 __le32 r5; /* v2 */ 352 __le32 r6; /* v3 */ 353 __le32 r7; /* v4 */ 354 __le32 r8; /* v5 */ 355 __le32 r9; /* sb/v6 */ 356 __le32 r10; /* sl/v7 */ 357 __le32 r11; /* fp/v8 */ 358 __le32 r12; /* ip */ 359 __le32 r13; /* sp */ 360 __le32 r14; /* lr */ 361 __le32 pc; /* r15 */ 362 }; 363 #endif /* DEBUG */ 364 365 struct sdpcm_shared { 366 u32 flags; 367 u32 trap_addr; 368 u32 assert_exp_addr; 369 u32 assert_file_addr; 370 u32 assert_line; 371 u32 console_addr; /* Address of struct rte_console */ 372 u32 msgtrace_addr; 373 u8 tag[32]; 374 u32 brpt_addr; 375 }; 376 377 struct sdpcm_shared_le { 378 __le32 flags; 379 __le32 trap_addr; 380 __le32 assert_exp_addr; 381 __le32 assert_file_addr; 382 __le32 assert_line; 383 __le32 console_addr; /* Address of struct rte_console */ 384 __le32 msgtrace_addr; 385 u8 tag[32]; 386 __le32 brpt_addr; 387 }; 388 389 /* dongle SDIO bus specific header info */ 390 struct brcmf_sdio_hdrinfo { 391 u8 seq_num; 392 u8 channel; 393 u16 len; 394 u16 len_left; 395 u16 len_nxtfrm; 396 u8 dat_offset; 397 bool lastfrm; 398 u16 tail_pad; 399 }; 400 401 /* 402 * hold counter variables 403 */ 404 struct brcmf_sdio_count { 405 uint intrcount; /* Count of device interrupt callbacks */ 406 uint lastintrs; /* Count as of last watchdog timer */ 407 uint pollcnt; /* Count of active polls */ 408 uint regfails; /* Count of R_REG failures */ 409 uint tx_sderrs; /* Count of tx attempts with sd errors */ 410 uint fcqueued; /* Tx packets that got queued */ 411 uint rxrtx; /* Count of rtx requests (NAK to dongle) */ 412 uint rx_toolong; /* Receive frames too long to receive */ 413 uint rxc_errors; /* SDIO errors when reading control frames */ 414 uint rx_hdrfail; /* SDIO errors on header reads */ 415 uint rx_badhdr; /* Bad received headers (roosync?) */ 416 uint rx_badseq; /* Mismatched rx sequence number */ 417 uint fc_rcvd; /* Number of flow-control events received */ 418 uint fc_xoff; /* Number which turned on flow-control */ 419 uint fc_xon; /* Number which turned off flow-control */ 420 uint rxglomfail; /* Failed deglom attempts */ 421 uint rxglomframes; /* Number of glom frames (superframes) */ 422 uint rxglompkts; /* Number of packets from glom frames */ 423 uint f2rxhdrs; /* Number of header reads */ 424 uint f2rxdata; /* Number of frame data reads */ 425 uint f2txdata; /* Number of f2 frame writes */ 426 uint f1regdata; /* Number of f1 register accesses */ 427 uint tickcnt; /* Number of watchdog been schedule */ 428 ulong tx_ctlerrs; /* Err of sending ctrl frames */ 429 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */ 430 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */ 431 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */ 432 ulong rx_readahead_cnt; /* packets where header read-ahead was used */ 433 }; 434 435 /* misc chip info needed by some of the routines */ 436 /* Private data for SDIO bus interaction */ 437 struct brcmf_sdio { 438 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */ 439 struct brcmf_chip *ci; /* Chip info struct */ 440 struct brcmf_core *sdio_core; /* sdio core info struct */ 441 442 u32 hostintmask; /* Copy of Host Interrupt Mask */ 443 atomic_t intstatus; /* Intstatus bits (events) pending */ 444 atomic_t fcstate; /* State of dongle flow-control */ 445 446 uint blocksize; /* Block size of SDIO transfers */ 447 uint roundup; /* Max roundup limit */ 448 449 struct pktq txq; /* Queue length used for flow-control */ 450 u8 flowcontrol; /* per prio flow control bitmask */ 451 u8 tx_seq; /* Transmit sequence number (next) */ 452 u8 tx_max; /* Maximum transmit sequence allowed */ 453 454 u8 *hdrbuf; /* buffer for handling rx frame */ 455 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */ 456 u8 rx_seq; /* Receive sequence number (expected) */ 457 struct brcmf_sdio_hdrinfo cur_read; 458 /* info of current read frame */ 459 bool rxskip; /* Skip receive (awaiting NAK ACK) */ 460 bool rxpending; /* Data frame pending in dongle */ 461 462 uint rxbound; /* Rx frames to read before resched */ 463 uint txbound; /* Tx frames to send before resched */ 464 uint txminmax; 465 466 struct sk_buff *glomd; /* Packet containing glomming descriptor */ 467 struct sk_buff_head glom; /* Packet list for glommed superframe */ 468 469 u8 *rxbuf; /* Buffer for receiving control packets */ 470 uint rxblen; /* Allocated length of rxbuf */ 471 u8 *rxctl; /* Aligned pointer into rxbuf */ 472 u8 *rxctl_orig; /* pointer for freeing rxctl */ 473 uint rxlen; /* Length of valid data in buffer */ 474 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */ 475 476 u8 sdpcm_ver; /* Bus protocol reported by dongle */ 477 478 bool intr; /* Use interrupts */ 479 bool poll; /* Use polling */ 480 atomic_t ipend; /* Device interrupt is pending */ 481 uint spurious; /* Count of spurious interrupts */ 482 uint pollrate; /* Ticks between device polls */ 483 uint polltick; /* Tick counter */ 484 485 #ifdef DEBUG 486 uint console_interval; 487 struct brcmf_console console; /* Console output polling support */ 488 uint console_addr; /* Console address from shared struct */ 489 #endif /* DEBUG */ 490 491 uint clkstate; /* State of sd and backplane clock(s) */ 492 s32 idletime; /* Control for activity timeout */ 493 s32 idlecount; /* Activity timeout counter */ 494 s32 idleclock; /* How to set bus driver when idle */ 495 bool rxflow_mode; /* Rx flow control mode */ 496 bool rxflow; /* Is rx flow control on */ 497 bool alp_only; /* Don't use HT clock (ALP only) */ 498 499 u8 *ctrl_frame_buf; 500 u16 ctrl_frame_len; 501 bool ctrl_frame_stat; 502 int ctrl_frame_err; 503 504 spinlock_t txq_lock; /* protect bus->txq */ 505 wait_queue_head_t ctrl_wait; 506 wait_queue_head_t dcmd_resp_wait; 507 508 struct timer_list timer; 509 struct completion watchdog_wait; 510 struct task_struct *watchdog_tsk; 511 bool wd_active; 512 513 struct workqueue_struct *brcmf_wq; 514 struct work_struct datawork; 515 bool dpc_triggered; 516 bool dpc_running; 517 518 bool txoff; /* Transmit flow-controlled */ 519 struct brcmf_sdio_count sdcnt; 520 bool sr_enabled; /* SaveRestore enabled */ 521 bool sleeping; 522 523 u8 tx_hdrlen; /* sdio bus header length for tx packet */ 524 bool txglom; /* host tx glomming enable flag */ 525 u16 head_align; /* buffer pointer alignment */ 526 u16 sgentry_align; /* scatter-gather buffer alignment */ 527 }; 528 529 /* clkstate */ 530 #define CLK_NONE 0 531 #define CLK_SDONLY 1 532 #define CLK_PENDING 2 533 #define CLK_AVAIL 3 534 535 #ifdef DEBUG 536 static int qcount[NUMPRIO]; 537 #endif /* DEBUG */ 538 539 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */ 540 541 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL) 542 543 /* Limit on rounding up frames */ 544 static const uint max_roundup = 512; 545 546 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 547 #define ALIGNMENT 8 548 #else 549 #define ALIGNMENT 4 550 #endif 551 552 enum brcmf_sdio_frmtype { 553 BRCMF_SDIO_FT_NORMAL, 554 BRCMF_SDIO_FT_SUPER, 555 BRCMF_SDIO_FT_SUB, 556 }; 557 558 #define SDIOD_DRVSTR_KEY(chip, pmu) (((unsigned int)(chip) << 16) | (pmu)) 559 560 /* SDIO Pad drive strength to select value mappings */ 561 struct sdiod_drive_str { 562 u8 strength; /* Pad Drive Strength in mA */ 563 u8 sel; /* Chip-specific select value */ 564 }; 565 566 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */ 567 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = { 568 {32, 0x6}, 569 {26, 0x7}, 570 {22, 0x4}, 571 {16, 0x5}, 572 {12, 0x2}, 573 {8, 0x3}, 574 {4, 0x0}, 575 {0, 0x1} 576 }; 577 578 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */ 579 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = { 580 {6, 0x7}, 581 {5, 0x6}, 582 {4, 0x5}, 583 {3, 0x4}, 584 {2, 0x2}, 585 {1, 0x1}, 586 {0, 0x0} 587 }; 588 589 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */ 590 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = { 591 {3, 0x3}, 592 {2, 0x2}, 593 {1, 0x1}, 594 {0, 0x0} }; 595 596 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */ 597 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = { 598 {16, 0x7}, 599 {12, 0x5}, 600 {8, 0x3}, 601 {4, 0x1} 602 }; 603 604 BRCMF_FW_DEF(43143, "brcmfmac43143-sdio"); 605 BRCMF_FW_DEF(43241B0, "brcmfmac43241b0-sdio"); 606 BRCMF_FW_DEF(43241B4, "brcmfmac43241b4-sdio"); 607 BRCMF_FW_DEF(43241B5, "brcmfmac43241b5-sdio"); 608 BRCMF_FW_DEF(4329, "brcmfmac4329-sdio"); 609 BRCMF_FW_DEF(4330, "brcmfmac4330-sdio"); 610 BRCMF_FW_DEF(4334, "brcmfmac4334-sdio"); 611 BRCMF_FW_DEF(43340, "brcmfmac43340-sdio"); 612 BRCMF_FW_DEF(4335, "brcmfmac4335-sdio"); 613 BRCMF_FW_DEF(43362, "brcmfmac43362-sdio"); 614 BRCMF_FW_DEF(4339, "brcmfmac4339-sdio"); 615 BRCMF_FW_DEF(43430A0, "brcmfmac43430a0-sdio"); 616 /* Note the names are not postfixed with a1 for backward compatibility */ 617 BRCMF_FW_CLM_DEF(43430A1, "brcmfmac43430-sdio"); 618 BRCMF_FW_DEF(43430B0, "brcmfmac43430b0-sdio"); 619 BRCMF_FW_CLM_DEF(43439, "brcmfmac43439-sdio"); 620 BRCMF_FW_CLM_DEF(43455, "brcmfmac43455-sdio"); 621 BRCMF_FW_CLM_DEF(43456, "brcmfmac43456-sdio"); 622 BRCMF_FW_CLM_DEF(4354, "brcmfmac4354-sdio"); 623 BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-sdio"); 624 BRCMF_FW_DEF(4359, "brcmfmac4359-sdio"); 625 BRCMF_FW_CLM_DEF(4373, "brcmfmac4373-sdio"); 626 BRCMF_FW_CLM_DEF(43012, "brcmfmac43012-sdio"); 627 BRCMF_FW_CLM_DEF(43752, "brcmfmac43752-sdio"); 628 629 /* firmware config files */ 630 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-sdio.*.txt"); 631 632 /* per-board firmware binaries */ 633 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-sdio.*.bin"); 634 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-sdio.*.clm_blob"); 635 636 static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = { 637 BRCMF_FW_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143), 638 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0), 639 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4), 640 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5), 641 BRCMF_FW_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329), 642 BRCMF_FW_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330), 643 BRCMF_FW_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334), 644 BRCMF_FW_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340), 645 BRCMF_FW_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43340), 646 BRCMF_FW_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335), 647 BRCMF_FW_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362), 648 BRCMF_FW_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339), 649 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000001, 43430A0), 650 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000002, 43430A1), 651 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFC, 43430B0), 652 BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0x00000200, 43456), 653 BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFDC0, 43455), 654 BRCMF_FW_ENTRY(BRCM_CC_43454_CHIP_ID, 0x00000040, 43455), 655 BRCMF_FW_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354), 656 BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356), 657 BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359), 658 BRCMF_FW_ENTRY(BRCM_CC_43751_CHIP_ID, 0xFFFFFFFF, 43752), 659 BRCMF_FW_ENTRY(BRCM_CC_43752_CHIP_ID, 0xFFFFFFFF, 43752), 660 BRCMF_FW_ENTRY(CY_CC_4373_CHIP_ID, 0xFFFFFFFF, 4373), 661 BRCMF_FW_ENTRY(CY_CC_43012_CHIP_ID, 0xFFFFFFFF, 43012), 662 BRCMF_FW_ENTRY(CY_CC_43439_CHIP_ID, 0xFFFFFFFF, 43439), 663 }; 664 665 #define TXCTL_CREDITS 2 666 667 static void pkt_align(struct sk_buff *p, int len, int align) 668 { 669 uint datalign; 670 datalign = (unsigned long)(p->data); 671 datalign = roundup(datalign, (align)) - datalign; 672 if (datalign) 673 skb_pull(p, datalign); 674 __skb_trim(p, len); 675 } 676 677 /* To check if there's window offered */ 678 static bool data_ok(struct brcmf_sdio *bus) 679 { 680 u8 tx_rsv = 0; 681 682 /* Reserve TXCTL_CREDITS credits for txctl when it is ready to send */ 683 if (bus->ctrl_frame_stat) 684 tx_rsv = TXCTL_CREDITS; 685 686 return (bus->tx_max - bus->tx_seq - tx_rsv) != 0 && 687 ((bus->tx_max - bus->tx_seq - tx_rsv) & 0x80) == 0; 688 689 } 690 691 /* To check if there's window offered */ 692 static bool txctl_ok(struct brcmf_sdio *bus) 693 { 694 return (bus->tx_max - bus->tx_seq) != 0 && 695 ((bus->tx_max - bus->tx_seq) & 0x80) == 0; 696 } 697 698 static int 699 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on) 700 { 701 u8 wr_val = 0, rd_val, cmp_val, bmask; 702 int err = 0; 703 int err_cnt = 0; 704 int try_cnt = 0; 705 706 brcmf_dbg(TRACE, "Enter: on=%d\n", on); 707 708 sdio_retune_crc_disable(bus->sdiodev->func1); 709 710 /* Cannot re-tune if device is asleep; defer till we're awake */ 711 if (on) 712 sdio_retune_hold_now(bus->sdiodev->func1); 713 714 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); 715 /* 1st KSO write goes to AOS wake up core if device is asleep */ 716 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err); 717 718 /* In case of 43012 chip, the chip could go down immediately after 719 * KSO bit is cleared. So the further reads of KSO register could 720 * fail. Thereby just bailing out immediately after clearing KSO 721 * bit, to avoid polling of KSO bit. 722 */ 723 if (!on && bus->ci->chip == CY_CC_43012_CHIP_ID) 724 return err; 725 726 if (on) { 727 /* device WAKEUP through KSO: 728 * write bit 0 & read back until 729 * both bits 0 (kso bit) & 1 (dev on status) are set 730 */ 731 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK | 732 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK; 733 bmask = cmp_val; 734 usleep_range(2000, 3000); 735 } else { 736 /* Put device to sleep, turn off KSO */ 737 cmp_val = 0; 738 /* only check for bit0, bit1(dev on status) may not 739 * get cleared right away 740 */ 741 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK; 742 } 743 744 do { 745 /* reliable KSO bit set/clr: 746 * the sdiod sleep write access is synced to PMU 32khz clk 747 * just one write attempt may fail, 748 * read it back until it matches written value 749 */ 750 rd_val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, 751 &err); 752 if (!err) { 753 if ((rd_val & bmask) == cmp_val) 754 break; 755 err_cnt = 0; 756 } 757 /* bail out upon subsequent access errors */ 758 if (err && (err_cnt++ > BRCMF_SDIO_MAX_ACCESS_ERRORS)) 759 break; 760 761 udelay(KSO_WAIT_US); 762 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val, 763 &err); 764 765 } while (try_cnt++ < MAX_KSO_ATTEMPTS); 766 767 if (try_cnt > 2) 768 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt, 769 rd_val, err); 770 771 if (try_cnt > MAX_KSO_ATTEMPTS) 772 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err); 773 774 if (on) 775 sdio_retune_release(bus->sdiodev->func1); 776 777 sdio_retune_crc_enable(bus->sdiodev->func1); 778 779 return err; 780 } 781 782 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE) 783 784 /* Turn backplane clock on or off */ 785 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok) 786 { 787 int err; 788 u8 clkctl, clkreq, devctl; 789 unsigned long timeout; 790 791 brcmf_dbg(SDIO, "Enter\n"); 792 793 clkctl = 0; 794 795 if (bus->sr_enabled) { 796 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY); 797 return 0; 798 } 799 800 if (on) { 801 /* Request HT Avail */ 802 clkreq = 803 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ; 804 805 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 806 clkreq, &err); 807 if (err) { 808 brcmf_err("HT Avail request error: %d\n", err); 809 return -EBADE; 810 } 811 812 /* Check current status */ 813 clkctl = brcmf_sdiod_readb(bus->sdiodev, 814 SBSDIO_FUNC1_CHIPCLKCSR, &err); 815 if (err) { 816 brcmf_err("HT Avail read error: %d\n", err); 817 return -EBADE; 818 } 819 820 /* Go to pending and await interrupt if appropriate */ 821 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) { 822 /* Allow only clock-available interrupt */ 823 devctl = brcmf_sdiod_readb(bus->sdiodev, 824 SBSDIO_DEVICE_CTL, &err); 825 if (err) { 826 brcmf_err("Devctl error setting CA: %d\n", err); 827 return -EBADE; 828 } 829 830 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY; 831 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL, 832 devctl, &err); 833 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n"); 834 bus->clkstate = CLK_PENDING; 835 836 return 0; 837 } else if (bus->clkstate == CLK_PENDING) { 838 /* Cancel CA-only interrupt filter */ 839 devctl = brcmf_sdiod_readb(bus->sdiodev, 840 SBSDIO_DEVICE_CTL, &err); 841 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 842 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL, 843 devctl, &err); 844 } 845 846 /* Otherwise, wait here (polling) for HT Avail */ 847 timeout = jiffies + 848 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000); 849 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { 850 clkctl = brcmf_sdiod_readb(bus->sdiodev, 851 SBSDIO_FUNC1_CHIPCLKCSR, 852 &err); 853 if (time_after(jiffies, timeout)) 854 break; 855 else 856 usleep_range(5000, 10000); 857 } 858 if (err) { 859 brcmf_err("HT Avail request error: %d\n", err); 860 return -EBADE; 861 } 862 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { 863 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n", 864 PMU_MAX_TRANSITION_DLY, clkctl); 865 return -EBADE; 866 } 867 868 /* Mark clock available */ 869 bus->clkstate = CLK_AVAIL; 870 brcmf_dbg(SDIO, "CLKCTL: turned ON\n"); 871 872 #if defined(DEBUG) 873 if (!bus->alp_only) { 874 if (SBSDIO_ALPONLY(clkctl)) 875 brcmf_err("HT Clock should be on\n"); 876 } 877 #endif /* defined (DEBUG) */ 878 879 } else { 880 clkreq = 0; 881 882 if (bus->clkstate == CLK_PENDING) { 883 /* Cancel CA-only interrupt filter */ 884 devctl = brcmf_sdiod_readb(bus->sdiodev, 885 SBSDIO_DEVICE_CTL, &err); 886 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 887 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL, 888 devctl, &err); 889 } 890 891 bus->clkstate = CLK_SDONLY; 892 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 893 clkreq, &err); 894 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n"); 895 if (err) { 896 brcmf_err("Failed access turning clock off: %d\n", 897 err); 898 return -EBADE; 899 } 900 } 901 return 0; 902 } 903 904 /* Change idle/active SD state */ 905 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on) 906 { 907 brcmf_dbg(SDIO, "Enter\n"); 908 909 if (on) 910 bus->clkstate = CLK_SDONLY; 911 else 912 bus->clkstate = CLK_NONE; 913 914 return 0; 915 } 916 917 /* Transition SD and backplane clock readiness */ 918 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok) 919 { 920 #ifdef DEBUG 921 uint oldstate = bus->clkstate; 922 #endif /* DEBUG */ 923 924 brcmf_dbg(SDIO, "Enter\n"); 925 926 /* Early exit if we're already there */ 927 if (bus->clkstate == target) 928 return 0; 929 930 switch (target) { 931 case CLK_AVAIL: 932 /* Make sure SD clock is available */ 933 if (bus->clkstate == CLK_NONE) 934 brcmf_sdio_sdclk(bus, true); 935 /* Now request HT Avail on the backplane */ 936 brcmf_sdio_htclk(bus, true, pendok); 937 break; 938 939 case CLK_SDONLY: 940 /* Remove HT request, or bring up SD clock */ 941 if (bus->clkstate == CLK_NONE) 942 brcmf_sdio_sdclk(bus, true); 943 else if (bus->clkstate == CLK_AVAIL) 944 brcmf_sdio_htclk(bus, false, false); 945 else 946 brcmf_err("request for %d -> %d\n", 947 bus->clkstate, target); 948 break; 949 950 case CLK_NONE: 951 /* Make sure to remove HT request */ 952 if (bus->clkstate == CLK_AVAIL) 953 brcmf_sdio_htclk(bus, false, false); 954 /* Now remove the SD clock */ 955 brcmf_sdio_sdclk(bus, false); 956 break; 957 } 958 #ifdef DEBUG 959 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate); 960 #endif /* DEBUG */ 961 962 return 0; 963 } 964 965 static int 966 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok) 967 { 968 int err = 0; 969 u8 clkcsr; 970 971 brcmf_dbg(SDIO, "Enter: request %s currently %s\n", 972 (sleep ? "SLEEP" : "WAKE"), 973 (bus->sleeping ? "SLEEP" : "WAKE")); 974 975 /* If SR is enabled control bus state with KSO */ 976 if (bus->sr_enabled) { 977 /* Done if we're already in the requested state */ 978 if (sleep == bus->sleeping) 979 goto end; 980 981 /* Going to sleep */ 982 if (sleep) { 983 clkcsr = brcmf_sdiod_readb(bus->sdiodev, 984 SBSDIO_FUNC1_CHIPCLKCSR, 985 &err); 986 if ((clkcsr & SBSDIO_CSR_MASK) == 0) { 987 brcmf_dbg(SDIO, "no clock, set ALP\n"); 988 brcmf_sdiod_writeb(bus->sdiodev, 989 SBSDIO_FUNC1_CHIPCLKCSR, 990 SBSDIO_ALP_AVAIL_REQ, &err); 991 } 992 err = brcmf_sdio_kso_control(bus, false); 993 } else { 994 err = brcmf_sdio_kso_control(bus, true); 995 } 996 if (err) { 997 brcmf_err("error while changing bus sleep state %d\n", 998 err); 999 goto done; 1000 } 1001 } 1002 1003 end: 1004 /* control clocks */ 1005 if (sleep) { 1006 if (!bus->sr_enabled) 1007 brcmf_sdio_clkctl(bus, CLK_NONE, pendok); 1008 } else { 1009 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok); 1010 brcmf_sdio_wd_timer(bus, true); 1011 } 1012 bus->sleeping = sleep; 1013 brcmf_dbg(SDIO, "new state %s\n", 1014 (sleep ? "SLEEP" : "WAKE")); 1015 done: 1016 brcmf_dbg(SDIO, "Exit: err=%d\n", err); 1017 return err; 1018 1019 } 1020 1021 #ifdef DEBUG 1022 static inline bool brcmf_sdio_valid_shared_address(u32 addr) 1023 { 1024 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)); 1025 } 1026 1027 static int brcmf_sdio_readshared(struct brcmf_sdio *bus, 1028 struct sdpcm_shared *sh) 1029 { 1030 u32 addr = 0; 1031 int rv; 1032 u32 shaddr = 0; 1033 struct sdpcm_shared_le sh_le; 1034 __le32 addr_le; 1035 1036 sdio_claim_host(bus->sdiodev->func1); 1037 brcmf_sdio_bus_sleep(bus, false, false); 1038 1039 /* 1040 * Read last word in socram to determine 1041 * address of sdpcm_shared structure 1042 */ 1043 shaddr = bus->ci->rambase + bus->ci->ramsize - 4; 1044 if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci)) 1045 shaddr -= bus->ci->srsize; 1046 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr, 1047 (u8 *)&addr_le, 4); 1048 if (rv < 0) 1049 goto fail; 1050 1051 /* 1052 * Check if addr is valid. 1053 * NVRAM length at the end of memory should have been overwritten. 1054 */ 1055 addr = le32_to_cpu(addr_le); 1056 if (!brcmf_sdio_valid_shared_address(addr)) { 1057 brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr); 1058 rv = -EINVAL; 1059 goto fail; 1060 } 1061 1062 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr); 1063 1064 /* Read hndrte_shared structure */ 1065 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le, 1066 sizeof(struct sdpcm_shared_le)); 1067 if (rv < 0) 1068 goto fail; 1069 1070 sdio_release_host(bus->sdiodev->func1); 1071 1072 /* Endianness */ 1073 sh->flags = le32_to_cpu(sh_le.flags); 1074 sh->trap_addr = le32_to_cpu(sh_le.trap_addr); 1075 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr); 1076 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr); 1077 sh->assert_line = le32_to_cpu(sh_le.assert_line); 1078 sh->console_addr = le32_to_cpu(sh_le.console_addr); 1079 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr); 1080 1081 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) { 1082 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n", 1083 SDPCM_SHARED_VERSION, 1084 sh->flags & SDPCM_SHARED_VERSION_MASK); 1085 return -EPROTO; 1086 } 1087 return 0; 1088 1089 fail: 1090 brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n", 1091 rv, addr); 1092 sdio_release_host(bus->sdiodev->func1); 1093 return rv; 1094 } 1095 1096 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) 1097 { 1098 struct sdpcm_shared sh; 1099 1100 if (brcmf_sdio_readshared(bus, &sh) == 0) 1101 bus->console_addr = sh.console_addr; 1102 } 1103 #else 1104 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) 1105 { 1106 } 1107 #endif /* DEBUG */ 1108 1109 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus) 1110 { 1111 struct brcmf_sdio_dev *sdiod = bus->sdiodev; 1112 struct brcmf_core *core = bus->sdio_core; 1113 u32 intstatus = 0; 1114 u32 hmb_data; 1115 u8 fcbits; 1116 int ret; 1117 1118 brcmf_dbg(SDIO, "Enter\n"); 1119 1120 /* Read mailbox data and ack that we did so */ 1121 hmb_data = brcmf_sdiod_readl(sdiod, 1122 core->base + SD_REG(tohostmailboxdata), 1123 &ret); 1124 1125 if (!ret) 1126 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox), 1127 SMB_INT_ACK, &ret); 1128 1129 bus->sdcnt.f1regdata += 2; 1130 1131 /* dongle indicates the firmware has halted/crashed */ 1132 if (hmb_data & HMB_DATA_FWHALT) { 1133 brcmf_dbg(SDIO, "mailbox indicates firmware halted\n"); 1134 brcmf_fw_crashed(&sdiod->func1->dev); 1135 } 1136 1137 /* Dongle recomposed rx frames, accept them again */ 1138 if (hmb_data & HMB_DATA_NAKHANDLED) { 1139 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n", 1140 bus->rx_seq); 1141 if (!bus->rxskip) 1142 brcmf_err("unexpected NAKHANDLED!\n"); 1143 1144 bus->rxskip = false; 1145 intstatus |= I_HMB_FRAME_IND; 1146 } 1147 1148 /* 1149 * DEVREADY does not occur with gSPI. 1150 */ 1151 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) { 1152 bus->sdpcm_ver = 1153 (hmb_data & HMB_DATA_VERSION_MASK) >> 1154 HMB_DATA_VERSION_SHIFT; 1155 if (bus->sdpcm_ver != SDPCM_PROT_VERSION) 1156 brcmf_err("Version mismatch, dongle reports %d, " 1157 "expecting %d\n", 1158 bus->sdpcm_ver, SDPCM_PROT_VERSION); 1159 else 1160 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n", 1161 bus->sdpcm_ver); 1162 1163 /* 1164 * Retrieve console state address now that firmware should have 1165 * updated it. 1166 */ 1167 brcmf_sdio_get_console_addr(bus); 1168 } 1169 1170 /* 1171 * Flow Control has been moved into the RX headers and this out of band 1172 * method isn't used any more. 1173 * remaining backward compatible with older dongles. 1174 */ 1175 if (hmb_data & HMB_DATA_FC) { 1176 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> 1177 HMB_DATA_FCDATA_SHIFT; 1178 1179 if (fcbits & ~bus->flowcontrol) 1180 bus->sdcnt.fc_xoff++; 1181 1182 if (bus->flowcontrol & ~fcbits) 1183 bus->sdcnt.fc_xon++; 1184 1185 bus->sdcnt.fc_rcvd++; 1186 bus->flowcontrol = fcbits; 1187 } 1188 1189 /* Shouldn't be any others */ 1190 if (hmb_data & ~(HMB_DATA_DEVREADY | 1191 HMB_DATA_NAKHANDLED | 1192 HMB_DATA_FC | 1193 HMB_DATA_FWREADY | 1194 HMB_DATA_FWHALT | 1195 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) 1196 brcmf_err("Unknown mailbox data content: 0x%02x\n", 1197 hmb_data); 1198 1199 return intstatus; 1200 } 1201 1202 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx) 1203 { 1204 struct brcmf_sdio_dev *sdiod = bus->sdiodev; 1205 struct brcmf_core *core = bus->sdio_core; 1206 uint retries = 0; 1207 u16 lastrbc; 1208 u8 hi, lo; 1209 int err; 1210 1211 brcmf_err("%sterminate frame%s\n", 1212 abort ? "abort command, " : "", 1213 rtx ? ", send NAK" : ""); 1214 1215 if (abort) 1216 brcmf_sdiod_abort(bus->sdiodev, bus->sdiodev->func2); 1217 1218 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM, 1219 &err); 1220 bus->sdcnt.f1regdata++; 1221 1222 /* Wait until the packet has been flushed (device/FIFO stable) */ 1223 for (lastrbc = retries = 0xffff; retries > 0; retries--) { 1224 hi = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCHI, 1225 &err); 1226 lo = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCLO, 1227 &err); 1228 bus->sdcnt.f1regdata += 2; 1229 1230 if ((hi == 0) && (lo == 0)) 1231 break; 1232 1233 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) { 1234 brcmf_err("count growing: last 0x%04x now 0x%04x\n", 1235 lastrbc, (hi << 8) + lo); 1236 } 1237 lastrbc = (hi << 8) + lo; 1238 } 1239 1240 if (!retries) 1241 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc); 1242 else 1243 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries); 1244 1245 if (rtx) { 1246 bus->sdcnt.rxrtx++; 1247 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox), 1248 SMB_NAK, &err); 1249 1250 bus->sdcnt.f1regdata++; 1251 if (err == 0) 1252 bus->rxskip = true; 1253 } 1254 1255 /* Clear partial in any case */ 1256 bus->cur_read.len = 0; 1257 } 1258 1259 static void brcmf_sdio_txfail(struct brcmf_sdio *bus) 1260 { 1261 struct brcmf_sdio_dev *sdiodev = bus->sdiodev; 1262 u8 i, hi, lo; 1263 1264 /* On failure, abort the command and terminate the frame */ 1265 brcmf_err("sdio error, abort command and terminate frame\n"); 1266 bus->sdcnt.tx_sderrs++; 1267 1268 brcmf_sdiod_abort(sdiodev, sdiodev->func2); 1269 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL); 1270 bus->sdcnt.f1regdata++; 1271 1272 for (i = 0; i < 3; i++) { 1273 hi = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL); 1274 lo = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL); 1275 bus->sdcnt.f1regdata += 2; 1276 if ((hi == 0) && (lo == 0)) 1277 break; 1278 } 1279 } 1280 1281 /* return total length of buffer chain */ 1282 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus) 1283 { 1284 struct sk_buff *p; 1285 uint total; 1286 1287 total = 0; 1288 skb_queue_walk(&bus->glom, p) 1289 total += p->len; 1290 return total; 1291 } 1292 1293 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus) 1294 { 1295 struct sk_buff *cur, *next; 1296 1297 skb_queue_walk_safe(&bus->glom, cur, next) { 1298 skb_unlink(cur, &bus->glom); 1299 brcmu_pkt_buf_free_skb(cur); 1300 } 1301 } 1302 1303 /* 1304 * brcmfmac sdio bus specific header 1305 * This is the lowest layer header wrapped on the packets transmitted between 1306 * host and WiFi dongle which contains information needed for SDIO core and 1307 * firmware 1308 * 1309 * It consists of 3 parts: hardware header, hardware extension header and 1310 * software header 1311 * hardware header (frame tag) - 4 bytes 1312 * Byte 0~1: Frame length 1313 * Byte 2~3: Checksum, bit-wise inverse of frame length 1314 * hardware extension header - 8 bytes 1315 * Tx glom mode only, N/A for Rx or normal Tx 1316 * Byte 0~1: Packet length excluding hw frame tag 1317 * Byte 2: Reserved 1318 * Byte 3: Frame flags, bit 0: last frame indication 1319 * Byte 4~5: Reserved 1320 * Byte 6~7: Tail padding length 1321 * software header - 8 bytes 1322 * Byte 0: Rx/Tx sequence number 1323 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag 1324 * Byte 2: Length of next data frame, reserved for Tx 1325 * Byte 3: Data offset 1326 * Byte 4: Flow control bits, reserved for Tx 1327 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet 1328 * Byte 6~7: Reserved 1329 */ 1330 #define SDPCM_HWHDR_LEN 4 1331 #define SDPCM_HWEXT_LEN 8 1332 #define SDPCM_SWHDR_LEN 8 1333 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN) 1334 /* software header */ 1335 #define SDPCM_SEQ_MASK 0x000000ff 1336 #define SDPCM_SEQ_WRAP 256 1337 #define SDPCM_CHANNEL_MASK 0x00000f00 1338 #define SDPCM_CHANNEL_SHIFT 8 1339 #define SDPCM_CONTROL_CHANNEL 0 /* Control */ 1340 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */ 1341 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */ 1342 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */ 1343 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */ 1344 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80) 1345 #define SDPCM_NEXTLEN_MASK 0x00ff0000 1346 #define SDPCM_NEXTLEN_SHIFT 16 1347 #define SDPCM_DOFFSET_MASK 0xff000000 1348 #define SDPCM_DOFFSET_SHIFT 24 1349 #define SDPCM_FCMASK_MASK 0x000000ff 1350 #define SDPCM_WINDOW_MASK 0x0000ff00 1351 #define SDPCM_WINDOW_SHIFT 8 1352 1353 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader) 1354 { 1355 u32 hdrvalue; 1356 hdrvalue = le32_to_cpu(*(__le32 *)swheader); 1357 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT); 1358 } 1359 1360 static inline bool brcmf_sdio_fromevntchan(u8 *swheader) 1361 { 1362 u32 hdrvalue; 1363 u8 ret; 1364 1365 hdrvalue = le32_to_cpu(*(__le32 *)swheader); 1366 ret = (u8)((hdrvalue & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT); 1367 1368 return (ret == SDPCM_EVENT_CHANNEL); 1369 } 1370 1371 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header, 1372 struct brcmf_sdio_hdrinfo *rd, 1373 enum brcmf_sdio_frmtype type) 1374 { 1375 u16 len, checksum; 1376 u8 rx_seq, fc, tx_seq_max; 1377 u32 swheader; 1378 1379 trace_brcmf_sdpcm_hdr(SDPCM_RX, header); 1380 1381 /* hw header */ 1382 len = get_unaligned_le16(header); 1383 checksum = get_unaligned_le16(header + sizeof(u16)); 1384 /* All zero means no more to read */ 1385 if (!(len | checksum)) { 1386 bus->rxpending = false; 1387 return -ENODATA; 1388 } 1389 if ((u16)(~(len ^ checksum))) { 1390 brcmf_err("HW header checksum error\n"); 1391 bus->sdcnt.rx_badhdr++; 1392 brcmf_sdio_rxfail(bus, false, false); 1393 return -EIO; 1394 } 1395 if (len < SDPCM_HDRLEN) { 1396 brcmf_err("HW header length error\n"); 1397 return -EPROTO; 1398 } 1399 if (type == BRCMF_SDIO_FT_SUPER && 1400 (roundup(len, bus->blocksize) != rd->len)) { 1401 brcmf_err("HW superframe header length error\n"); 1402 return -EPROTO; 1403 } 1404 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) { 1405 brcmf_err("HW subframe header length error\n"); 1406 return -EPROTO; 1407 } 1408 rd->len = len; 1409 1410 /* software header */ 1411 header += SDPCM_HWHDR_LEN; 1412 swheader = le32_to_cpu(*(__le32 *)header); 1413 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) { 1414 brcmf_err("Glom descriptor found in superframe head\n"); 1415 rd->len = 0; 1416 return -EINVAL; 1417 } 1418 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK); 1419 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT; 1420 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL && 1421 type != BRCMF_SDIO_FT_SUPER) { 1422 brcmf_err("HW header length too long\n"); 1423 bus->sdcnt.rx_toolong++; 1424 brcmf_sdio_rxfail(bus, false, false); 1425 rd->len = 0; 1426 return -EPROTO; 1427 } 1428 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) { 1429 brcmf_err("Wrong channel for superframe\n"); 1430 rd->len = 0; 1431 return -EINVAL; 1432 } 1433 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL && 1434 rd->channel != SDPCM_EVENT_CHANNEL) { 1435 brcmf_err("Wrong channel for subframe\n"); 1436 rd->len = 0; 1437 return -EINVAL; 1438 } 1439 rd->dat_offset = brcmf_sdio_getdatoffset(header); 1440 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) { 1441 brcmf_err("seq %d: bad data offset\n", rx_seq); 1442 bus->sdcnt.rx_badhdr++; 1443 brcmf_sdio_rxfail(bus, false, false); 1444 rd->len = 0; 1445 return -ENXIO; 1446 } 1447 if (rd->seq_num != rx_seq) { 1448 brcmf_dbg(SDIO, "seq %d, expected %d\n", rx_seq, rd->seq_num); 1449 bus->sdcnt.rx_badseq++; 1450 rd->seq_num = rx_seq; 1451 } 1452 /* no need to check the reset for subframe */ 1453 if (type == BRCMF_SDIO_FT_SUB) 1454 return 0; 1455 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT; 1456 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) { 1457 /* only warm for NON glom packet */ 1458 if (rd->channel != SDPCM_GLOM_CHANNEL) 1459 brcmf_err("seq %d: next length error\n", rx_seq); 1460 rd->len_nxtfrm = 0; 1461 } 1462 swheader = le32_to_cpu(*(__le32 *)(header + 4)); 1463 fc = swheader & SDPCM_FCMASK_MASK; 1464 if (bus->flowcontrol != fc) { 1465 if (~bus->flowcontrol & fc) 1466 bus->sdcnt.fc_xoff++; 1467 if (bus->flowcontrol & ~fc) 1468 bus->sdcnt.fc_xon++; 1469 bus->sdcnt.fc_rcvd++; 1470 bus->flowcontrol = fc; 1471 } 1472 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT; 1473 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) { 1474 brcmf_err("seq %d: max tx seq number error\n", rx_seq); 1475 tx_seq_max = bus->tx_seq + 2; 1476 } 1477 bus->tx_max = tx_seq_max; 1478 1479 return 0; 1480 } 1481 1482 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length) 1483 { 1484 *(__le16 *)header = cpu_to_le16(frm_length); 1485 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length); 1486 } 1487 1488 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header, 1489 struct brcmf_sdio_hdrinfo *hd_info) 1490 { 1491 u32 hdrval; 1492 u8 hdr_offset; 1493 1494 brcmf_sdio_update_hwhdr(header, hd_info->len); 1495 hdr_offset = SDPCM_HWHDR_LEN; 1496 1497 if (bus->txglom) { 1498 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24); 1499 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); 1500 hdrval = (u16)hd_info->tail_pad << 16; 1501 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval); 1502 hdr_offset += SDPCM_HWEXT_LEN; 1503 } 1504 1505 hdrval = hd_info->seq_num; 1506 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) & 1507 SDPCM_CHANNEL_MASK; 1508 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) & 1509 SDPCM_DOFFSET_MASK; 1510 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); 1511 *(((__le32 *)(header + hdr_offset)) + 1) = 0; 1512 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header); 1513 } 1514 1515 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq) 1516 { 1517 u16 dlen, totlen; 1518 u8 *dptr, num = 0; 1519 u16 sublen; 1520 struct sk_buff *pfirst, *pnext; 1521 1522 int errcode; 1523 u8 doff; 1524 1525 struct brcmf_sdio_hdrinfo rd_new; 1526 1527 /* If packets, issue read(s) and send up packet chain */ 1528 /* Return sequence numbers consumed? */ 1529 1530 brcmf_dbg(SDIO, "start: glomd %p glom %p\n", 1531 bus->glomd, skb_peek(&bus->glom)); 1532 1533 /* If there's a descriptor, generate the packet chain */ 1534 if (bus->glomd) { 1535 pfirst = pnext = NULL; 1536 dlen = (u16) (bus->glomd->len); 1537 dptr = bus->glomd->data; 1538 if (!dlen || (dlen & 1)) { 1539 brcmf_err("bad glomd len(%d), ignore descriptor\n", 1540 dlen); 1541 dlen = 0; 1542 } 1543 1544 for (totlen = num = 0; dlen; num++) { 1545 /* Get (and move past) next length */ 1546 sublen = get_unaligned_le16(dptr); 1547 dlen -= sizeof(u16); 1548 dptr += sizeof(u16); 1549 if ((sublen < SDPCM_HDRLEN) || 1550 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) { 1551 brcmf_err("descriptor len %d bad: %d\n", 1552 num, sublen); 1553 pnext = NULL; 1554 break; 1555 } 1556 if (sublen % bus->sgentry_align) { 1557 brcmf_err("sublen %d not multiple of %d\n", 1558 sublen, bus->sgentry_align); 1559 } 1560 totlen += sublen; 1561 1562 /* For last frame, adjust read len so total 1563 is a block multiple */ 1564 if (!dlen) { 1565 sublen += 1566 (roundup(totlen, bus->blocksize) - totlen); 1567 totlen = roundup(totlen, bus->blocksize); 1568 } 1569 1570 /* Allocate/chain packet for next subframe */ 1571 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align); 1572 if (pnext == NULL) { 1573 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n", 1574 num, sublen); 1575 break; 1576 } 1577 skb_queue_tail(&bus->glom, pnext); 1578 1579 /* Adhere to start alignment requirements */ 1580 pkt_align(pnext, sublen, bus->sgentry_align); 1581 } 1582 1583 /* If all allocations succeeded, save packet chain 1584 in bus structure */ 1585 if (pnext) { 1586 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n", 1587 totlen, num); 1588 if (BRCMF_GLOM_ON() && bus->cur_read.len && 1589 totlen != bus->cur_read.len) { 1590 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n", 1591 bus->cur_read.len, totlen, rxseq); 1592 } 1593 pfirst = pnext = NULL; 1594 } else { 1595 brcmf_sdio_free_glom(bus); 1596 num = 0; 1597 } 1598 1599 /* Done with descriptor packet */ 1600 brcmu_pkt_buf_free_skb(bus->glomd); 1601 bus->glomd = NULL; 1602 bus->cur_read.len = 0; 1603 } 1604 1605 /* Ok -- either we just generated a packet chain, 1606 or had one from before */ 1607 if (!skb_queue_empty(&bus->glom)) { 1608 if (BRCMF_GLOM_ON()) { 1609 brcmf_dbg(GLOM, "try superframe read, packet chain:\n"); 1610 skb_queue_walk(&bus->glom, pnext) { 1611 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n", 1612 pnext, (u8 *) (pnext->data), 1613 pnext->len, pnext->len); 1614 } 1615 } 1616 1617 pfirst = skb_peek(&bus->glom); 1618 dlen = (u16) brcmf_sdio_glom_len(bus); 1619 1620 /* Do an SDIO read for the superframe. Configurable iovar to 1621 * read directly into the chained packet, or allocate a large 1622 * packet and copy into the chain. 1623 */ 1624 sdio_claim_host(bus->sdiodev->func1); 1625 errcode = brcmf_sdiod_recv_chain(bus->sdiodev, 1626 &bus->glom, dlen); 1627 sdio_release_host(bus->sdiodev->func1); 1628 bus->sdcnt.f2rxdata++; 1629 1630 /* On failure, kill the superframe */ 1631 if (errcode < 0) { 1632 brcmf_err("glom read of %d bytes failed: %d\n", 1633 dlen, errcode); 1634 1635 sdio_claim_host(bus->sdiodev->func1); 1636 brcmf_sdio_rxfail(bus, true, false); 1637 bus->sdcnt.rxglomfail++; 1638 brcmf_sdio_free_glom(bus); 1639 sdio_release_host(bus->sdiodev->func1); 1640 return 0; 1641 } 1642 1643 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1644 pfirst->data, min_t(int, pfirst->len, 48), 1645 "SUPERFRAME:\n"); 1646 1647 rd_new.seq_num = rxseq; 1648 rd_new.len = dlen; 1649 sdio_claim_host(bus->sdiodev->func1); 1650 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new, 1651 BRCMF_SDIO_FT_SUPER); 1652 sdio_release_host(bus->sdiodev->func1); 1653 bus->cur_read.len = rd_new.len_nxtfrm << 4; 1654 1655 /* Remove superframe header, remember offset */ 1656 skb_pull(pfirst, rd_new.dat_offset); 1657 num = 0; 1658 1659 /* Validate all the subframe headers */ 1660 skb_queue_walk(&bus->glom, pnext) { 1661 /* leave when invalid subframe is found */ 1662 if (errcode) 1663 break; 1664 1665 rd_new.len = pnext->len; 1666 rd_new.seq_num = rxseq++; 1667 sdio_claim_host(bus->sdiodev->func1); 1668 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new, 1669 BRCMF_SDIO_FT_SUB); 1670 sdio_release_host(bus->sdiodev->func1); 1671 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1672 pnext->data, 32, "subframe:\n"); 1673 1674 num++; 1675 } 1676 1677 if (errcode) { 1678 /* Terminate frame on error */ 1679 sdio_claim_host(bus->sdiodev->func1); 1680 brcmf_sdio_rxfail(bus, true, false); 1681 bus->sdcnt.rxglomfail++; 1682 brcmf_sdio_free_glom(bus); 1683 sdio_release_host(bus->sdiodev->func1); 1684 bus->cur_read.len = 0; 1685 return 0; 1686 } 1687 1688 /* Basic SD framing looks ok - process each packet (header) */ 1689 1690 skb_queue_walk_safe(&bus->glom, pfirst, pnext) { 1691 dptr = (u8 *) (pfirst->data); 1692 sublen = get_unaligned_le16(dptr); 1693 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]); 1694 1695 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), 1696 dptr, pfirst->len, 1697 "Rx Subframe Data:\n"); 1698 1699 __skb_trim(pfirst, sublen); 1700 skb_pull(pfirst, doff); 1701 1702 if (pfirst->len == 0) { 1703 skb_unlink(pfirst, &bus->glom); 1704 brcmu_pkt_buf_free_skb(pfirst); 1705 continue; 1706 } 1707 1708 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1709 pfirst->data, 1710 min_t(int, pfirst->len, 32), 1711 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n", 1712 bus->glom.qlen, pfirst, pfirst->data, 1713 pfirst->len, pfirst->next, 1714 pfirst->prev); 1715 skb_unlink(pfirst, &bus->glom); 1716 if (brcmf_sdio_fromevntchan(&dptr[SDPCM_HWHDR_LEN])) 1717 brcmf_rx_event(bus->sdiodev->dev, pfirst); 1718 else 1719 brcmf_rx_frame(bus->sdiodev->dev, pfirst, 1720 false, false); 1721 bus->sdcnt.rxglompkts++; 1722 } 1723 1724 bus->sdcnt.rxglomframes++; 1725 } 1726 return num; 1727 } 1728 1729 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition, 1730 bool *pending) 1731 { 1732 DECLARE_WAITQUEUE(wait, current); 1733 int timeout = DCMD_RESP_TIMEOUT; 1734 1735 /* Wait until control frame is available */ 1736 add_wait_queue(&bus->dcmd_resp_wait, &wait); 1737 set_current_state(TASK_INTERRUPTIBLE); 1738 1739 while (!(*condition) && (!signal_pending(current) && timeout)) 1740 timeout = schedule_timeout(timeout); 1741 1742 if (signal_pending(current)) 1743 *pending = true; 1744 1745 set_current_state(TASK_RUNNING); 1746 remove_wait_queue(&bus->dcmd_resp_wait, &wait); 1747 1748 return timeout; 1749 } 1750 1751 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus) 1752 { 1753 wake_up_interruptible(&bus->dcmd_resp_wait); 1754 1755 return 0; 1756 } 1757 static void 1758 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff) 1759 { 1760 uint rdlen, pad; 1761 u8 *buf = NULL, *rbuf; 1762 int sdret; 1763 1764 brcmf_dbg(SDIO, "Enter\n"); 1765 if (bus->rxblen) 1766 buf = vzalloc(bus->rxblen); 1767 if (!buf) 1768 goto done; 1769 1770 rbuf = bus->rxbuf; 1771 pad = ((unsigned long)rbuf % bus->head_align); 1772 if (pad) 1773 rbuf += (bus->head_align - pad); 1774 1775 /* Copy the already-read portion over */ 1776 memcpy(buf, hdr, BRCMF_FIRSTREAD); 1777 if (len <= BRCMF_FIRSTREAD) 1778 goto gotpkt; 1779 1780 /* Raise rdlen to next SDIO block to avoid tail command */ 1781 rdlen = len - BRCMF_FIRSTREAD; 1782 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) { 1783 pad = bus->blocksize - (rdlen % bus->blocksize); 1784 if ((pad <= bus->roundup) && (pad < bus->blocksize) && 1785 ((len + pad) < bus->sdiodev->bus_if->maxctl)) 1786 rdlen += pad; 1787 } else if (rdlen % bus->head_align) { 1788 rdlen += bus->head_align - (rdlen % bus->head_align); 1789 } 1790 1791 /* Drop if the read is too big or it exceeds our maximum */ 1792 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) { 1793 brcmf_err("%d-byte control read exceeds %d-byte buffer\n", 1794 rdlen, bus->sdiodev->bus_if->maxctl); 1795 brcmf_sdio_rxfail(bus, false, false); 1796 goto done; 1797 } 1798 1799 if ((len - doff) > bus->sdiodev->bus_if->maxctl) { 1800 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n", 1801 len, len - doff, bus->sdiodev->bus_if->maxctl); 1802 bus->sdcnt.rx_toolong++; 1803 brcmf_sdio_rxfail(bus, false, false); 1804 goto done; 1805 } 1806 1807 /* Read remain of frame body */ 1808 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen); 1809 bus->sdcnt.f2rxdata++; 1810 1811 /* Control frame failures need retransmission */ 1812 if (sdret < 0) { 1813 brcmf_err("read %d control bytes failed: %d\n", 1814 rdlen, sdret); 1815 bus->sdcnt.rxc_errors++; 1816 brcmf_sdio_rxfail(bus, true, true); 1817 goto done; 1818 } else 1819 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen); 1820 1821 gotpkt: 1822 1823 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), 1824 buf, len, "RxCtrl:\n"); 1825 1826 /* Point to valid data and indicate its length */ 1827 spin_lock_bh(&bus->rxctl_lock); 1828 if (bus->rxctl) { 1829 brcmf_err("last control frame is being processed.\n"); 1830 spin_unlock_bh(&bus->rxctl_lock); 1831 goto done; 1832 } 1833 bus->rxctl = buf + doff; 1834 bus->rxctl_orig = buf; 1835 bus->rxlen = len - doff; 1836 spin_unlock_bh(&bus->rxctl_lock); 1837 buf = NULL; 1838 1839 done: 1840 /* Awake any waiters */ 1841 brcmf_sdio_dcmd_resp_wake(bus); 1842 vfree(buf); 1843 } 1844 1845 /* Pad read to blocksize for efficiency */ 1846 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen) 1847 { 1848 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) { 1849 *pad = bus->blocksize - (*rdlen % bus->blocksize); 1850 if (*pad <= bus->roundup && *pad < bus->blocksize && 1851 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ) 1852 *rdlen += *pad; 1853 } else if (*rdlen % bus->head_align) { 1854 *rdlen += bus->head_align - (*rdlen % bus->head_align); 1855 } 1856 } 1857 1858 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes) 1859 { 1860 struct sk_buff *pkt; /* Packet for event or data frames */ 1861 u16 pad; /* Number of pad bytes to read */ 1862 uint rxleft = 0; /* Remaining number of frames allowed */ 1863 int ret; /* Return code from calls */ 1864 uint rxcount = 0; /* Total frames read */ 1865 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new; 1866 u8 head_read = 0; 1867 1868 brcmf_dbg(SDIO, "Enter\n"); 1869 1870 /* Not finished unless we encounter no more frames indication */ 1871 bus->rxpending = true; 1872 1873 for (rd->seq_num = bus->rx_seq, rxleft = maxframes; 1874 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA; 1875 rd->seq_num++, rxleft--) { 1876 1877 /* Handle glomming separately */ 1878 if (bus->glomd || !skb_queue_empty(&bus->glom)) { 1879 u8 cnt; 1880 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n", 1881 bus->glomd, skb_peek(&bus->glom)); 1882 cnt = brcmf_sdio_rxglom(bus, rd->seq_num); 1883 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt); 1884 rd->seq_num += cnt - 1; 1885 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1; 1886 continue; 1887 } 1888 1889 rd->len_left = rd->len; 1890 /* read header first for unknown frame length */ 1891 sdio_claim_host(bus->sdiodev->func1); 1892 if (!rd->len) { 1893 ret = brcmf_sdiod_recv_buf(bus->sdiodev, 1894 bus->rxhdr, BRCMF_FIRSTREAD); 1895 bus->sdcnt.f2rxhdrs++; 1896 if (ret < 0) { 1897 brcmf_err("RXHEADER FAILED: %d\n", 1898 ret); 1899 bus->sdcnt.rx_hdrfail++; 1900 brcmf_sdio_rxfail(bus, true, true); 1901 sdio_release_host(bus->sdiodev->func1); 1902 continue; 1903 } 1904 1905 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(), 1906 bus->rxhdr, SDPCM_HDRLEN, 1907 "RxHdr:\n"); 1908 1909 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd, 1910 BRCMF_SDIO_FT_NORMAL)) { 1911 sdio_release_host(bus->sdiodev->func1); 1912 if (!bus->rxpending) 1913 break; 1914 else 1915 continue; 1916 } 1917 1918 if (rd->channel == SDPCM_CONTROL_CHANNEL) { 1919 brcmf_sdio_read_control(bus, bus->rxhdr, 1920 rd->len, 1921 rd->dat_offset); 1922 /* prepare the descriptor for the next read */ 1923 rd->len = rd->len_nxtfrm << 4; 1924 rd->len_nxtfrm = 0; 1925 /* treat all packet as event if we don't know */ 1926 rd->channel = SDPCM_EVENT_CHANNEL; 1927 sdio_release_host(bus->sdiodev->func1); 1928 continue; 1929 } 1930 rd->len_left = rd->len > BRCMF_FIRSTREAD ? 1931 rd->len - BRCMF_FIRSTREAD : 0; 1932 head_read = BRCMF_FIRSTREAD; 1933 } 1934 1935 brcmf_sdio_pad(bus, &pad, &rd->len_left); 1936 1937 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read + 1938 bus->head_align); 1939 if (!pkt) { 1940 /* Give up on data, request rtx of events */ 1941 brcmf_err("brcmu_pkt_buf_get_skb failed\n"); 1942 brcmf_sdio_rxfail(bus, false, 1943 RETRYCHAN(rd->channel)); 1944 sdio_release_host(bus->sdiodev->func1); 1945 continue; 1946 } 1947 skb_pull(pkt, head_read); 1948 pkt_align(pkt, rd->len_left, bus->head_align); 1949 1950 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt); 1951 bus->sdcnt.f2rxdata++; 1952 sdio_release_host(bus->sdiodev->func1); 1953 1954 if (ret < 0) { 1955 brcmf_err("read %d bytes from channel %d failed: %d\n", 1956 rd->len, rd->channel, ret); 1957 brcmu_pkt_buf_free_skb(pkt); 1958 sdio_claim_host(bus->sdiodev->func1); 1959 brcmf_sdio_rxfail(bus, true, 1960 RETRYCHAN(rd->channel)); 1961 sdio_release_host(bus->sdiodev->func1); 1962 continue; 1963 } 1964 1965 if (head_read) { 1966 skb_push(pkt, head_read); 1967 memcpy(pkt->data, bus->rxhdr, head_read); 1968 head_read = 0; 1969 } else { 1970 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN); 1971 rd_new.seq_num = rd->seq_num; 1972 sdio_claim_host(bus->sdiodev->func1); 1973 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new, 1974 BRCMF_SDIO_FT_NORMAL)) { 1975 rd->len = 0; 1976 brcmf_sdio_rxfail(bus, true, true); 1977 sdio_release_host(bus->sdiodev->func1); 1978 brcmu_pkt_buf_free_skb(pkt); 1979 continue; 1980 } 1981 bus->sdcnt.rx_readahead_cnt++; 1982 if (rd->len != roundup(rd_new.len, 16)) { 1983 brcmf_err("frame length mismatch:read %d, should be %d\n", 1984 rd->len, 1985 roundup(rd_new.len, 16) >> 4); 1986 rd->len = 0; 1987 brcmf_sdio_rxfail(bus, true, true); 1988 sdio_release_host(bus->sdiodev->func1); 1989 brcmu_pkt_buf_free_skb(pkt); 1990 continue; 1991 } 1992 sdio_release_host(bus->sdiodev->func1); 1993 rd->len_nxtfrm = rd_new.len_nxtfrm; 1994 rd->channel = rd_new.channel; 1995 rd->dat_offset = rd_new.dat_offset; 1996 1997 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && 1998 BRCMF_DATA_ON()) && 1999 BRCMF_HDRS_ON(), 2000 bus->rxhdr, SDPCM_HDRLEN, 2001 "RxHdr:\n"); 2002 2003 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) { 2004 brcmf_err("readahead on control packet %d?\n", 2005 rd_new.seq_num); 2006 /* Force retry w/normal header read */ 2007 rd->len = 0; 2008 sdio_claim_host(bus->sdiodev->func1); 2009 brcmf_sdio_rxfail(bus, false, true); 2010 sdio_release_host(bus->sdiodev->func1); 2011 brcmu_pkt_buf_free_skb(pkt); 2012 continue; 2013 } 2014 } 2015 2016 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), 2017 pkt->data, rd->len, "Rx Data:\n"); 2018 2019 /* Save superframe descriptor and allocate packet frame */ 2020 if (rd->channel == SDPCM_GLOM_CHANNEL) { 2021 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) { 2022 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n", 2023 rd->len); 2024 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 2025 pkt->data, rd->len, 2026 "Glom Data:\n"); 2027 __skb_trim(pkt, rd->len); 2028 skb_pull(pkt, SDPCM_HDRLEN); 2029 bus->glomd = pkt; 2030 } else { 2031 brcmf_err("%s: glom superframe w/o " 2032 "descriptor!\n", __func__); 2033 sdio_claim_host(bus->sdiodev->func1); 2034 brcmf_sdio_rxfail(bus, false, false); 2035 sdio_release_host(bus->sdiodev->func1); 2036 } 2037 /* prepare the descriptor for the next read */ 2038 rd->len = rd->len_nxtfrm << 4; 2039 rd->len_nxtfrm = 0; 2040 /* treat all packet as event if we don't know */ 2041 rd->channel = SDPCM_EVENT_CHANNEL; 2042 continue; 2043 } 2044 2045 /* Fill in packet len and prio, deliver upward */ 2046 __skb_trim(pkt, rd->len); 2047 skb_pull(pkt, rd->dat_offset); 2048 2049 if (pkt->len == 0) 2050 brcmu_pkt_buf_free_skb(pkt); 2051 else if (rd->channel == SDPCM_EVENT_CHANNEL) 2052 brcmf_rx_event(bus->sdiodev->dev, pkt); 2053 else 2054 brcmf_rx_frame(bus->sdiodev->dev, pkt, 2055 false, false); 2056 2057 /* prepare the descriptor for the next read */ 2058 rd->len = rd->len_nxtfrm << 4; 2059 rd->len_nxtfrm = 0; 2060 /* treat all packet as event if we don't know */ 2061 rd->channel = SDPCM_EVENT_CHANNEL; 2062 } 2063 2064 rxcount = maxframes - rxleft; 2065 /* Message if we hit the limit */ 2066 if (!rxleft) 2067 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes); 2068 else 2069 brcmf_dbg(DATA, "processed %d frames\n", rxcount); 2070 /* Back off rxseq if awaiting rtx, update rx_seq */ 2071 if (bus->rxskip) 2072 rd->seq_num--; 2073 bus->rx_seq = rd->seq_num; 2074 2075 return rxcount; 2076 } 2077 2078 static void 2079 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus) 2080 { 2081 wake_up_interruptible(&bus->ctrl_wait); 2082 return; 2083 } 2084 2085 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt) 2086 { 2087 struct brcmf_bus_stats *stats; 2088 u16 head_pad; 2089 u8 *dat_buf; 2090 2091 dat_buf = (u8 *)(pkt->data); 2092 2093 /* Check head padding */ 2094 head_pad = ((unsigned long)dat_buf % bus->head_align); 2095 if (head_pad) { 2096 if (skb_headroom(pkt) < head_pad) { 2097 stats = &bus->sdiodev->bus_if->stats; 2098 atomic_inc(&stats->pktcowed); 2099 if (skb_cow_head(pkt, head_pad)) { 2100 atomic_inc(&stats->pktcow_failed); 2101 return -ENOMEM; 2102 } 2103 head_pad = 0; 2104 } 2105 skb_push(pkt, head_pad); 2106 dat_buf = (u8 *)(pkt->data); 2107 } 2108 memset(dat_buf, 0, head_pad + bus->tx_hdrlen); 2109 return head_pad; 2110 } 2111 2112 /* 2113 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for 2114 * bus layer usage. 2115 */ 2116 /* flag marking a dummy skb added for DMA alignment requirement */ 2117 #define ALIGN_SKB_FLAG 0x8000 2118 /* bit mask of data length chopped from the previous packet */ 2119 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff 2120 2121 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus, 2122 struct sk_buff_head *pktq, 2123 struct sk_buff *pkt, u16 total_len) 2124 { 2125 struct brcmf_sdio_dev *sdiodev; 2126 struct sk_buff *pkt_pad; 2127 u16 tail_pad, tail_chop, chain_pad; 2128 unsigned int blksize; 2129 bool lastfrm; 2130 int ntail, ret; 2131 2132 sdiodev = bus->sdiodev; 2133 blksize = sdiodev->func2->cur_blksize; 2134 /* sg entry alignment should be a divisor of block size */ 2135 WARN_ON(blksize % bus->sgentry_align); 2136 2137 /* Check tail padding */ 2138 lastfrm = skb_queue_is_last(pktq, pkt); 2139 tail_pad = 0; 2140 tail_chop = pkt->len % bus->sgentry_align; 2141 if (tail_chop) 2142 tail_pad = bus->sgentry_align - tail_chop; 2143 chain_pad = (total_len + tail_pad) % blksize; 2144 if (lastfrm && chain_pad) 2145 tail_pad += blksize - chain_pad; 2146 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) { 2147 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop + 2148 bus->head_align); 2149 if (pkt_pad == NULL) 2150 return -ENOMEM; 2151 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad); 2152 if (unlikely(ret < 0)) { 2153 kfree_skb(pkt_pad); 2154 return ret; 2155 } 2156 memcpy(pkt_pad->data, 2157 pkt->data + pkt->len - tail_chop, 2158 tail_chop); 2159 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop; 2160 skb_trim(pkt, pkt->len - tail_chop); 2161 skb_trim(pkt_pad, tail_pad + tail_chop); 2162 __skb_queue_after(pktq, pkt, pkt_pad); 2163 } else { 2164 ntail = pkt->data_len + tail_pad - 2165 (pkt->end - pkt->tail); 2166 if (skb_cloned(pkt) || ntail > 0) 2167 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC)) 2168 return -ENOMEM; 2169 if (skb_linearize(pkt)) 2170 return -ENOMEM; 2171 __skb_put(pkt, tail_pad); 2172 } 2173 2174 return tail_pad; 2175 } 2176 2177 /** 2178 * brcmf_sdio_txpkt_prep - packet preparation for transmit 2179 * @bus: brcmf_sdio structure pointer 2180 * @pktq: packet list pointer 2181 * @chan: virtual channel to transmit the packet 2182 * 2183 * Processes to be applied to the packet 2184 * - Align data buffer pointer 2185 * - Align data buffer length 2186 * - Prepare header 2187 * Return: negative value if there is error 2188 */ 2189 static int 2190 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq, 2191 uint chan) 2192 { 2193 u16 head_pad, total_len; 2194 struct sk_buff *pkt_next; 2195 u8 txseq; 2196 int ret; 2197 struct brcmf_sdio_hdrinfo hd_info = {0}; 2198 2199 txseq = bus->tx_seq; 2200 total_len = 0; 2201 skb_queue_walk(pktq, pkt_next) { 2202 /* alignment packet inserted in previous 2203 * loop cycle can be skipped as it is 2204 * already properly aligned and does not 2205 * need an sdpcm header. 2206 */ 2207 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG) 2208 continue; 2209 2210 /* align packet data pointer */ 2211 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next); 2212 if (ret < 0) 2213 return ret; 2214 head_pad = (u16)ret; 2215 if (head_pad) 2216 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad); 2217 2218 total_len += pkt_next->len; 2219 2220 hd_info.len = pkt_next->len; 2221 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next); 2222 if (bus->txglom && pktq->qlen > 1) { 2223 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq, 2224 pkt_next, total_len); 2225 if (ret < 0) 2226 return ret; 2227 hd_info.tail_pad = (u16)ret; 2228 total_len += (u16)ret; 2229 } 2230 2231 hd_info.channel = chan; 2232 hd_info.dat_offset = head_pad + bus->tx_hdrlen; 2233 hd_info.seq_num = txseq++; 2234 2235 /* Now fill the header */ 2236 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info); 2237 2238 if (BRCMF_BYTES_ON() && 2239 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) || 2240 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL))) 2241 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len, 2242 "Tx Frame:\n"); 2243 else if (BRCMF_HDRS_ON()) 2244 brcmf_dbg_hex_dump(true, pkt_next->data, 2245 head_pad + bus->tx_hdrlen, 2246 "Tx Header:\n"); 2247 } 2248 /* Hardware length tag of the first packet should be total 2249 * length of the chain (including padding) 2250 */ 2251 if (bus->txglom) 2252 brcmf_sdio_update_hwhdr(__skb_peek(pktq)->data, total_len); 2253 return 0; 2254 } 2255 2256 /** 2257 * brcmf_sdio_txpkt_postp - packet post processing for transmit 2258 * @bus: brcmf_sdio structure pointer 2259 * @pktq: packet list pointer 2260 * 2261 * Processes to be applied to the packet 2262 * - Remove head padding 2263 * - Remove tail padding 2264 */ 2265 static void 2266 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq) 2267 { 2268 u8 *hdr; 2269 u32 dat_offset; 2270 u16 tail_pad; 2271 u16 dummy_flags, chop_len; 2272 struct sk_buff *pkt_next, *tmp, *pkt_prev; 2273 2274 skb_queue_walk_safe(pktq, pkt_next, tmp) { 2275 dummy_flags = *(u16 *)(pkt_next->cb); 2276 if (dummy_flags & ALIGN_SKB_FLAG) { 2277 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK; 2278 if (chop_len) { 2279 pkt_prev = pkt_next->prev; 2280 skb_put(pkt_prev, chop_len); 2281 } 2282 __skb_unlink(pkt_next, pktq); 2283 brcmu_pkt_buf_free_skb(pkt_next); 2284 } else { 2285 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN; 2286 dat_offset = le32_to_cpu(*(__le32 *)hdr); 2287 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >> 2288 SDPCM_DOFFSET_SHIFT; 2289 skb_pull(pkt_next, dat_offset); 2290 if (bus->txglom) { 2291 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2)); 2292 skb_trim(pkt_next, pkt_next->len - tail_pad); 2293 } 2294 } 2295 } 2296 } 2297 2298 /* Writes a HW/SW header into the packet and sends it. */ 2299 /* Assumes: (a) header space already there, (b) caller holds lock */ 2300 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq, 2301 uint chan) 2302 { 2303 int ret; 2304 struct sk_buff *pkt_next, *tmp; 2305 2306 brcmf_dbg(TRACE, "Enter\n"); 2307 2308 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan); 2309 if (ret) 2310 goto done; 2311 2312 sdio_claim_host(bus->sdiodev->func1); 2313 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq); 2314 bus->sdcnt.f2txdata++; 2315 2316 if (ret < 0) 2317 brcmf_sdio_txfail(bus); 2318 2319 sdio_release_host(bus->sdiodev->func1); 2320 2321 done: 2322 brcmf_sdio_txpkt_postp(bus, pktq); 2323 if (ret == 0) 2324 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP; 2325 skb_queue_walk_safe(pktq, pkt_next, tmp) { 2326 __skb_unlink(pkt_next, pktq); 2327 brcmf_proto_bcdc_txcomplete(bus->sdiodev->dev, pkt_next, 2328 ret == 0); 2329 } 2330 return ret; 2331 } 2332 2333 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes) 2334 { 2335 struct sk_buff *pkt; 2336 struct sk_buff_head pktq; 2337 u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus); 2338 u32 intstatus = 0; 2339 int ret = 0, prec_out, i; 2340 uint cnt = 0; 2341 u8 tx_prec_map, pkt_num; 2342 2343 brcmf_dbg(TRACE, "Enter\n"); 2344 2345 tx_prec_map = ~bus->flowcontrol; 2346 2347 /* Send frames until the limit or some other event */ 2348 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) { 2349 pkt_num = 1; 2350 if (bus->txglom) 2351 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq, 2352 bus->sdiodev->txglomsz); 2353 pkt_num = min_t(u32, pkt_num, 2354 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)); 2355 __skb_queue_head_init(&pktq); 2356 spin_lock_bh(&bus->txq_lock); 2357 for (i = 0; i < pkt_num; i++) { 2358 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, 2359 &prec_out); 2360 if (pkt == NULL) 2361 break; 2362 __skb_queue_tail(&pktq, pkt); 2363 } 2364 spin_unlock_bh(&bus->txq_lock); 2365 if (i == 0) 2366 break; 2367 2368 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL); 2369 2370 cnt += i; 2371 2372 /* In poll mode, need to check for other events */ 2373 if (!bus->intr) { 2374 /* Check device status, signal pending interrupt */ 2375 sdio_claim_host(bus->sdiodev->func1); 2376 intstatus = brcmf_sdiod_readl(bus->sdiodev, 2377 intstat_addr, &ret); 2378 sdio_release_host(bus->sdiodev->func1); 2379 2380 bus->sdcnt.f2txdata++; 2381 if (ret != 0) 2382 break; 2383 if (intstatus & bus->hostintmask) 2384 atomic_set(&bus->ipend, 1); 2385 } 2386 } 2387 2388 /* Deflow-control stack if needed */ 2389 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) && 2390 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) { 2391 bus->txoff = false; 2392 brcmf_proto_bcdc_txflowblock(bus->sdiodev->dev, false); 2393 } 2394 2395 return cnt; 2396 } 2397 2398 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len) 2399 { 2400 u8 doff; 2401 u16 pad; 2402 uint retries = 0; 2403 struct brcmf_sdio_hdrinfo hd_info = {0}; 2404 int ret; 2405 2406 brcmf_dbg(SDIO, "Enter\n"); 2407 2408 /* Back the pointer to make room for bus header */ 2409 frame -= bus->tx_hdrlen; 2410 len += bus->tx_hdrlen; 2411 2412 /* Add alignment padding (optional for ctl frames) */ 2413 doff = ((unsigned long)frame % bus->head_align); 2414 if (doff) { 2415 frame -= doff; 2416 len += doff; 2417 memset(frame + bus->tx_hdrlen, 0, doff); 2418 } 2419 2420 /* Round send length to next SDIO block */ 2421 pad = 0; 2422 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { 2423 pad = bus->blocksize - (len % bus->blocksize); 2424 if ((pad > bus->roundup) || (pad >= bus->blocksize)) 2425 pad = 0; 2426 } else if (len % bus->head_align) { 2427 pad = bus->head_align - (len % bus->head_align); 2428 } 2429 len += pad; 2430 2431 hd_info.len = len - pad; 2432 hd_info.channel = SDPCM_CONTROL_CHANNEL; 2433 hd_info.dat_offset = doff + bus->tx_hdrlen; 2434 hd_info.seq_num = bus->tx_seq; 2435 hd_info.lastfrm = true; 2436 hd_info.tail_pad = pad; 2437 brcmf_sdio_hdpack(bus, frame, &hd_info); 2438 2439 if (bus->txglom) 2440 brcmf_sdio_update_hwhdr(frame, len); 2441 2442 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), 2443 frame, len, "Tx Frame:\n"); 2444 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) && 2445 BRCMF_HDRS_ON(), 2446 frame, min_t(u16, len, 16), "TxHdr:\n"); 2447 2448 do { 2449 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len); 2450 2451 if (ret < 0) 2452 brcmf_sdio_txfail(bus); 2453 else 2454 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP; 2455 } while (ret < 0 && retries++ < TXRETRIES); 2456 2457 return ret; 2458 } 2459 2460 static bool brcmf_chip_is_ulp(struct brcmf_chip *ci) 2461 { 2462 if (ci->chip == CY_CC_43012_CHIP_ID) 2463 return true; 2464 else 2465 return false; 2466 } 2467 2468 static void brcmf_sdio_bus_stop(struct device *dev) 2469 { 2470 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2471 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2472 struct brcmf_sdio *bus = sdiodev->bus; 2473 struct brcmf_core *core = bus->sdio_core; 2474 u32 local_hostintmask; 2475 u8 saveclk, bpreq; 2476 int err; 2477 2478 brcmf_dbg(TRACE, "Enter\n"); 2479 2480 if (bus->watchdog_tsk) { 2481 get_task_struct(bus->watchdog_tsk); 2482 send_sig(SIGTERM, bus->watchdog_tsk, 1); 2483 kthread_stop_put(bus->watchdog_tsk); 2484 bus->watchdog_tsk = NULL; 2485 } 2486 2487 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) { 2488 sdio_claim_host(sdiodev->func1); 2489 2490 /* Enable clock for device interrupts */ 2491 brcmf_sdio_bus_sleep(bus, false, false); 2492 2493 /* Disable and clear interrupts at the chip level also */ 2494 brcmf_sdiod_writel(sdiodev, core->base + SD_REG(hostintmask), 2495 0, NULL); 2496 2497 local_hostintmask = bus->hostintmask; 2498 bus->hostintmask = 0; 2499 2500 /* Force backplane clocks to assure F2 interrupt propagates */ 2501 saveclk = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 2502 &err); 2503 if (!err) { 2504 bpreq = saveclk; 2505 bpreq |= brcmf_chip_is_ulp(bus->ci) ? 2506 SBSDIO_HT_AVAIL_REQ : SBSDIO_FORCE_HT; 2507 brcmf_sdiod_writeb(sdiodev, 2508 SBSDIO_FUNC1_CHIPCLKCSR, 2509 bpreq, &err); 2510 } 2511 if (err) 2512 brcmf_err("Failed to force clock for F2: err %d\n", 2513 err); 2514 2515 /* Turn off the bus (F2), free any pending packets */ 2516 brcmf_dbg(INTR, "disable SDIO interrupts\n"); 2517 sdio_disable_func(sdiodev->func2); 2518 2519 /* Clear any pending interrupts now that F2 is disabled */ 2520 brcmf_sdiod_writel(sdiodev, core->base + SD_REG(intstatus), 2521 local_hostintmask, NULL); 2522 2523 sdio_release_host(sdiodev->func1); 2524 } 2525 /* Clear the data packet queues */ 2526 brcmu_pktq_flush(&bus->txq, true, NULL, NULL); 2527 2528 /* Clear any held glomming stuff */ 2529 brcmu_pkt_buf_free_skb(bus->glomd); 2530 brcmf_sdio_free_glom(bus); 2531 2532 /* Clear rx control and wake any waiters */ 2533 spin_lock_bh(&bus->rxctl_lock); 2534 bus->rxlen = 0; 2535 spin_unlock_bh(&bus->rxctl_lock); 2536 brcmf_sdio_dcmd_resp_wake(bus); 2537 2538 /* Reset some F2 state stuff */ 2539 bus->rxskip = false; 2540 bus->tx_seq = bus->rx_seq = 0; 2541 } 2542 2543 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus) 2544 { 2545 struct brcmf_sdio_dev *sdiodev; 2546 unsigned long flags; 2547 2548 sdiodev = bus->sdiodev; 2549 if (sdiodev->oob_irq_requested) { 2550 spin_lock_irqsave(&sdiodev->irq_en_lock, flags); 2551 if (!sdiodev->irq_en && !atomic_read(&bus->ipend)) { 2552 enable_irq(sdiodev->settings->bus.sdio.oob_irq_nr); 2553 sdiodev->irq_en = true; 2554 } 2555 spin_unlock_irqrestore(&sdiodev->irq_en_lock, flags); 2556 } 2557 } 2558 2559 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus) 2560 { 2561 struct brcmf_core *core = bus->sdio_core; 2562 u32 addr; 2563 unsigned long val; 2564 int ret; 2565 2566 addr = core->base + SD_REG(intstatus); 2567 2568 val = brcmf_sdiod_readl(bus->sdiodev, addr, &ret); 2569 bus->sdcnt.f1regdata++; 2570 if (ret != 0) 2571 return ret; 2572 2573 val &= bus->hostintmask; 2574 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE)); 2575 2576 /* Clear interrupts */ 2577 if (val) { 2578 brcmf_sdiod_writel(bus->sdiodev, addr, val, &ret); 2579 bus->sdcnt.f1regdata++; 2580 atomic_or(val, &bus->intstatus); 2581 } 2582 2583 return ret; 2584 } 2585 2586 static void brcmf_sdio_dpc(struct brcmf_sdio *bus) 2587 { 2588 struct brcmf_sdio_dev *sdiod = bus->sdiodev; 2589 u32 newstatus = 0; 2590 u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus); 2591 unsigned long intstatus; 2592 uint txlimit = bus->txbound; /* Tx frames to send before resched */ 2593 uint framecnt; /* Temporary counter of tx/rx frames */ 2594 int err = 0; 2595 2596 brcmf_dbg(SDIO, "Enter\n"); 2597 2598 sdio_claim_host(bus->sdiodev->func1); 2599 2600 /* If waiting for HTAVAIL, check status */ 2601 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) { 2602 u8 clkctl, devctl = 0; 2603 2604 #ifdef DEBUG 2605 /* Check for inconsistent device control */ 2606 devctl = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_DEVICE_CTL, 2607 &err); 2608 #endif /* DEBUG */ 2609 2610 /* Read CSR, if clock on switch to AVAIL, else ignore */ 2611 clkctl = brcmf_sdiod_readb(bus->sdiodev, 2612 SBSDIO_FUNC1_CHIPCLKCSR, &err); 2613 2614 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", 2615 devctl, clkctl); 2616 2617 if (SBSDIO_HTAV(clkctl)) { 2618 devctl = brcmf_sdiod_readb(bus->sdiodev, 2619 SBSDIO_DEVICE_CTL, &err); 2620 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 2621 brcmf_sdiod_writeb(bus->sdiodev, 2622 SBSDIO_DEVICE_CTL, devctl, &err); 2623 bus->clkstate = CLK_AVAIL; 2624 } 2625 } 2626 2627 /* Make sure backplane clock is on */ 2628 brcmf_sdio_bus_sleep(bus, false, true); 2629 2630 /* Pending interrupt indicates new device status */ 2631 if (atomic_read(&bus->ipend) > 0) { 2632 atomic_set(&bus->ipend, 0); 2633 err = brcmf_sdio_intr_rstatus(bus); 2634 } 2635 2636 /* Start with leftover status bits */ 2637 intstatus = atomic_xchg(&bus->intstatus, 0); 2638 2639 /* Handle flow-control change: read new state in case our ack 2640 * crossed another change interrupt. If change still set, assume 2641 * FC ON for safety, let next loop through do the debounce. 2642 */ 2643 if (intstatus & I_HMB_FC_CHANGE) { 2644 intstatus &= ~I_HMB_FC_CHANGE; 2645 brcmf_sdiod_writel(sdiod, intstat_addr, I_HMB_FC_CHANGE, &err); 2646 2647 newstatus = brcmf_sdiod_readl(sdiod, intstat_addr, &err); 2648 2649 bus->sdcnt.f1regdata += 2; 2650 atomic_set(&bus->fcstate, 2651 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE))); 2652 intstatus |= (newstatus & bus->hostintmask); 2653 } 2654 2655 /* Handle host mailbox indication */ 2656 if (intstatus & I_HMB_HOST_INT) { 2657 intstatus &= ~I_HMB_HOST_INT; 2658 intstatus |= brcmf_sdio_hostmail(bus); 2659 } 2660 2661 sdio_release_host(bus->sdiodev->func1); 2662 2663 /* Generally don't ask for these, can get CRC errors... */ 2664 if (intstatus & I_WR_OOSYNC) { 2665 brcmf_err("Dongle reports WR_OOSYNC\n"); 2666 intstatus &= ~I_WR_OOSYNC; 2667 } 2668 2669 if (intstatus & I_RD_OOSYNC) { 2670 brcmf_err("Dongle reports RD_OOSYNC\n"); 2671 intstatus &= ~I_RD_OOSYNC; 2672 } 2673 2674 if (intstatus & I_SBINT) { 2675 brcmf_err("Dongle reports SBINT\n"); 2676 intstatus &= ~I_SBINT; 2677 } 2678 2679 /* Would be active due to wake-wlan in gSPI */ 2680 if (intstatus & I_CHIPACTIVE) { 2681 brcmf_dbg(SDIO, "Dongle reports CHIPACTIVE\n"); 2682 intstatus &= ~I_CHIPACTIVE; 2683 } 2684 2685 /* Ignore frame indications if rxskip is set */ 2686 if (bus->rxskip) 2687 intstatus &= ~I_HMB_FRAME_IND; 2688 2689 /* On frame indication, read available frames */ 2690 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) { 2691 brcmf_sdio_readframes(bus, bus->rxbound); 2692 if (!bus->rxpending) 2693 intstatus &= ~I_HMB_FRAME_IND; 2694 } 2695 2696 /* Keep still-pending events for next scheduling */ 2697 if (intstatus) 2698 atomic_or(intstatus, &bus->intstatus); 2699 2700 brcmf_sdio_clrintr(bus); 2701 2702 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) && 2703 txctl_ok(bus)) { 2704 sdio_claim_host(bus->sdiodev->func1); 2705 if (bus->ctrl_frame_stat) { 2706 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf, 2707 bus->ctrl_frame_len); 2708 bus->ctrl_frame_err = err; 2709 wmb(); 2710 bus->ctrl_frame_stat = false; 2711 if (err) 2712 brcmf_err("sdio ctrlframe tx failed err=%d\n", 2713 err); 2714 } 2715 sdio_release_host(bus->sdiodev->func1); 2716 brcmf_sdio_wait_event_wakeup(bus); 2717 } 2718 /* Send queued frames (limit 1 if rx may still be pending) */ 2719 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) && 2720 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit && 2721 data_ok(bus)) { 2722 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) : 2723 txlimit; 2724 brcmf_sdio_sendfromq(bus, framecnt); 2725 } 2726 2727 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) { 2728 brcmf_err("failed backplane access over SDIO, halting operation\n"); 2729 atomic_set(&bus->intstatus, 0); 2730 if (bus->ctrl_frame_stat) { 2731 sdio_claim_host(bus->sdiodev->func1); 2732 if (bus->ctrl_frame_stat) { 2733 bus->ctrl_frame_err = -ENODEV; 2734 wmb(); 2735 bus->ctrl_frame_stat = false; 2736 brcmf_sdio_wait_event_wakeup(bus); 2737 } 2738 sdio_release_host(bus->sdiodev->func1); 2739 } 2740 } else if (atomic_read(&bus->intstatus) || 2741 atomic_read(&bus->ipend) > 0 || 2742 (!atomic_read(&bus->fcstate) && 2743 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && 2744 data_ok(bus))) { 2745 bus->dpc_triggered = true; 2746 } 2747 } 2748 2749 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev) 2750 { 2751 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2752 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2753 struct brcmf_sdio *bus = sdiodev->bus; 2754 2755 return &bus->txq; 2756 } 2757 2758 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec) 2759 { 2760 struct sk_buff *p; 2761 int eprec = -1; /* precedence to evict from */ 2762 2763 /* Fast case, precedence queue is not full and we are also not 2764 * exceeding total queue length 2765 */ 2766 if (!pktq_pfull(q, prec) && !pktq_full(q)) { 2767 brcmu_pktq_penq(q, prec, pkt); 2768 return true; 2769 } 2770 2771 /* Determine precedence from which to evict packet, if any */ 2772 if (pktq_pfull(q, prec)) { 2773 eprec = prec; 2774 } else if (pktq_full(q)) { 2775 p = brcmu_pktq_peek_tail(q, &eprec); 2776 if (eprec > prec) 2777 return false; 2778 } 2779 2780 /* Evict if needed */ 2781 if (eprec >= 0) { 2782 /* Detect queueing to unconfigured precedence */ 2783 if (eprec == prec) 2784 return false; /* refuse newer (incoming) packet */ 2785 /* Evict packet according to discard policy */ 2786 p = brcmu_pktq_pdeq_tail(q, eprec); 2787 if (p == NULL) 2788 brcmf_err("brcmu_pktq_pdeq_tail() failed\n"); 2789 brcmu_pkt_buf_free_skb(p); 2790 } 2791 2792 /* Enqueue */ 2793 p = brcmu_pktq_penq(q, prec, pkt); 2794 if (p == NULL) 2795 brcmf_err("brcmu_pktq_penq() failed\n"); 2796 2797 return p != NULL; 2798 } 2799 2800 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt) 2801 { 2802 int ret = -EBADE; 2803 uint prec; 2804 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2805 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2806 struct brcmf_sdio *bus = sdiodev->bus; 2807 2808 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len); 2809 if (sdiodev->state != BRCMF_SDIOD_DATA) 2810 return -EIO; 2811 2812 /* Add space for the header */ 2813 skb_push(pkt, bus->tx_hdrlen); 2814 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */ 2815 2816 /* In WLAN, priority is always set by the AP using WMM parameters 2817 * and this need not always follow the standard 802.1d priority. 2818 * Based on AP WMM config, map from 802.1d priority to corresponding 2819 * precedence level. 2820 */ 2821 prec = brcmf_map_prio_to_prec(bus_if->drvr->config, 2822 (pkt->priority & PRIOMASK)); 2823 2824 /* Check for existing queue, current flow-control, 2825 pending event, or pending clock */ 2826 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq)); 2827 bus->sdcnt.fcqueued++; 2828 2829 /* Priority based enq */ 2830 spin_lock_bh(&bus->txq_lock); 2831 /* reset bus_flags in packet cb */ 2832 *(u16 *)(pkt->cb) = 0; 2833 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) { 2834 skb_pull(pkt, bus->tx_hdrlen); 2835 brcmf_err("out of bus->txq !!!\n"); 2836 ret = -ENOSR; 2837 } else { 2838 ret = 0; 2839 } 2840 2841 if (pktq_len(&bus->txq) >= TXHI) { 2842 bus->txoff = true; 2843 brcmf_proto_bcdc_txflowblock(dev, true); 2844 } 2845 spin_unlock_bh(&bus->txq_lock); 2846 2847 #ifdef DEBUG 2848 if (pktq_plen(&bus->txq, prec) > qcount[prec]) 2849 qcount[prec] = pktq_plen(&bus->txq, prec); 2850 #endif 2851 2852 brcmf_sdio_trigger_dpc(bus); 2853 return ret; 2854 } 2855 2856 #ifdef DEBUG 2857 #define CONSOLE_LINE_MAX 192 2858 2859 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus) 2860 { 2861 struct brcmf_console *c = &bus->console; 2862 u8 line[CONSOLE_LINE_MAX], ch; 2863 u32 n, idx, addr; 2864 int rv; 2865 2866 /* Don't do anything until FWREADY updates console address */ 2867 if (bus->console_addr == 0) 2868 return 0; 2869 2870 /* Read console log struct */ 2871 addr = bus->console_addr + offsetof(struct rte_console, log_le); 2872 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le, 2873 sizeof(c->log_le)); 2874 if (rv < 0) 2875 return rv; 2876 2877 /* Allocate console buffer (one time only) */ 2878 if (c->buf == NULL) { 2879 c->bufsize = le32_to_cpu(c->log_le.buf_size); 2880 c->buf = kmalloc(c->bufsize, GFP_ATOMIC); 2881 if (c->buf == NULL) 2882 return -ENOMEM; 2883 } 2884 2885 idx = le32_to_cpu(c->log_le.idx); 2886 2887 /* Protect against corrupt value */ 2888 if (idx > c->bufsize) 2889 return -EBADE; 2890 2891 /* Skip reading the console buffer if the index pointer 2892 has not moved */ 2893 if (idx == c->last) 2894 return 0; 2895 2896 /* Read the console buffer */ 2897 addr = le32_to_cpu(c->log_le.buf); 2898 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize); 2899 if (rv < 0) 2900 return rv; 2901 2902 while (c->last != idx) { 2903 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { 2904 if (c->last == idx) { 2905 /* This would output a partial line. 2906 * Instead, back up 2907 * the buffer pointer and output this 2908 * line next time around. 2909 */ 2910 if (c->last >= n) 2911 c->last -= n; 2912 else 2913 c->last = c->bufsize - n; 2914 goto break2; 2915 } 2916 ch = c->buf[c->last]; 2917 c->last = (c->last + 1) % c->bufsize; 2918 if (ch == '\n') 2919 break; 2920 line[n] = ch; 2921 } 2922 2923 if (n > 0) { 2924 if (line[n - 1] == '\r') 2925 n--; 2926 line[n] = 0; 2927 pr_debug("CONSOLE: %s\n", line); 2928 } 2929 } 2930 break2: 2931 2932 return 0; 2933 } 2934 #endif /* DEBUG */ 2935 2936 static int 2937 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen) 2938 { 2939 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2940 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2941 struct brcmf_sdio *bus = sdiodev->bus; 2942 int ret; 2943 2944 brcmf_dbg(TRACE, "Enter\n"); 2945 if (sdiodev->state != BRCMF_SDIOD_DATA) 2946 return -EIO; 2947 2948 /* Send from dpc */ 2949 bus->ctrl_frame_buf = msg; 2950 bus->ctrl_frame_len = msglen; 2951 wmb(); 2952 bus->ctrl_frame_stat = true; 2953 2954 brcmf_sdio_trigger_dpc(bus); 2955 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat, 2956 CTL_DONE_TIMEOUT); 2957 ret = 0; 2958 if (bus->ctrl_frame_stat) { 2959 sdio_claim_host(bus->sdiodev->func1); 2960 if (bus->ctrl_frame_stat) { 2961 brcmf_dbg(SDIO, "ctrl_frame timeout\n"); 2962 bus->ctrl_frame_stat = false; 2963 ret = -ETIMEDOUT; 2964 } 2965 sdio_release_host(bus->sdiodev->func1); 2966 } 2967 if (!ret) { 2968 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n", 2969 bus->ctrl_frame_err); 2970 rmb(); 2971 ret = bus->ctrl_frame_err; 2972 } 2973 2974 if (ret) 2975 bus->sdcnt.tx_ctlerrs++; 2976 else 2977 bus->sdcnt.tx_ctlpkts++; 2978 2979 return ret; 2980 } 2981 2982 #ifdef DEBUG 2983 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus, 2984 struct sdpcm_shared *sh) 2985 { 2986 u32 addr, console_ptr, console_size, console_index; 2987 char *conbuf = NULL; 2988 __le32 sh_val; 2989 int rv; 2990 2991 /* obtain console information from device memory */ 2992 addr = sh->console_addr + offsetof(struct rte_console, log_le); 2993 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 2994 (u8 *)&sh_val, sizeof(u32)); 2995 if (rv < 0) 2996 return rv; 2997 console_ptr = le32_to_cpu(sh_val); 2998 2999 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size); 3000 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 3001 (u8 *)&sh_val, sizeof(u32)); 3002 if (rv < 0) 3003 return rv; 3004 console_size = le32_to_cpu(sh_val); 3005 3006 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx); 3007 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 3008 (u8 *)&sh_val, sizeof(u32)); 3009 if (rv < 0) 3010 return rv; 3011 console_index = le32_to_cpu(sh_val); 3012 3013 /* allocate buffer for console data */ 3014 if (console_size <= CONSOLE_BUFFER_MAX) 3015 conbuf = vzalloc(console_size+1); 3016 3017 if (!conbuf) 3018 return -ENOMEM; 3019 3020 /* obtain the console data from device */ 3021 conbuf[console_size] = '\0'; 3022 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf, 3023 console_size); 3024 if (rv < 0) 3025 goto done; 3026 3027 rv = seq_write(seq, conbuf + console_index, 3028 console_size - console_index); 3029 if (rv < 0) 3030 goto done; 3031 3032 if (console_index > 0) 3033 rv = seq_write(seq, conbuf, console_index - 1); 3034 3035 done: 3036 vfree(conbuf); 3037 return rv; 3038 } 3039 3040 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus, 3041 struct sdpcm_shared *sh) 3042 { 3043 int error; 3044 struct brcmf_trap_info tr; 3045 3046 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) { 3047 brcmf_dbg(INFO, "no trap in firmware\n"); 3048 return 0; 3049 } 3050 3051 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr, 3052 sizeof(struct brcmf_trap_info)); 3053 if (error < 0) 3054 return error; 3055 3056 if (seq) 3057 seq_printf(seq, 3058 "dongle trap info: type 0x%x @ epc 0x%08x\n" 3059 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n" 3060 " lr 0x%08x pc 0x%08x offset 0x%x\n" 3061 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n" 3062 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", 3063 le32_to_cpu(tr.type), le32_to_cpu(tr.epc), 3064 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr), 3065 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14), 3066 le32_to_cpu(tr.pc), sh->trap_addr, 3067 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1), 3068 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3), 3069 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5), 3070 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7)); 3071 else 3072 pr_debug("dongle trap info: type 0x%x @ epc 0x%08x\n" 3073 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n" 3074 " lr 0x%08x pc 0x%08x offset 0x%x\n" 3075 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n" 3076 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", 3077 le32_to_cpu(tr.type), le32_to_cpu(tr.epc), 3078 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr), 3079 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14), 3080 le32_to_cpu(tr.pc), sh->trap_addr, 3081 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1), 3082 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3), 3083 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5), 3084 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7)); 3085 return 0; 3086 } 3087 3088 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus, 3089 struct sdpcm_shared *sh) 3090 { 3091 int error = 0; 3092 char file[80] = "?"; 3093 char expr[80] = "<???>"; 3094 3095 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) { 3096 brcmf_dbg(INFO, "firmware not built with -assert\n"); 3097 return 0; 3098 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) { 3099 brcmf_dbg(INFO, "no assert in dongle\n"); 3100 return 0; 3101 } 3102 3103 sdio_claim_host(bus->sdiodev->func1); 3104 if (sh->assert_file_addr != 0) { 3105 error = brcmf_sdiod_ramrw(bus->sdiodev, false, 3106 sh->assert_file_addr, (u8 *)file, 80); 3107 if (error < 0) 3108 return error; 3109 } 3110 if (sh->assert_exp_addr != 0) { 3111 error = brcmf_sdiod_ramrw(bus->sdiodev, false, 3112 sh->assert_exp_addr, (u8 *)expr, 80); 3113 if (error < 0) 3114 return error; 3115 } 3116 sdio_release_host(bus->sdiodev->func1); 3117 3118 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n", 3119 file, sh->assert_line, expr); 3120 return 0; 3121 } 3122 3123 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) 3124 { 3125 int error; 3126 struct sdpcm_shared sh; 3127 3128 error = brcmf_sdio_readshared(bus, &sh); 3129 3130 if (error < 0) 3131 return error; 3132 3133 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) 3134 brcmf_dbg(INFO, "firmware not built with -assert\n"); 3135 else if (sh.flags & SDPCM_SHARED_ASSERT) 3136 brcmf_err("assertion in dongle\n"); 3137 3138 if (sh.flags & SDPCM_SHARED_TRAP) { 3139 brcmf_err("firmware trap in dongle\n"); 3140 brcmf_sdio_trap_info(NULL, bus, &sh); 3141 } 3142 3143 return 0; 3144 } 3145 3146 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus) 3147 { 3148 int error = 0; 3149 struct sdpcm_shared sh; 3150 3151 error = brcmf_sdio_readshared(bus, &sh); 3152 if (error < 0) 3153 goto done; 3154 3155 error = brcmf_sdio_assert_info(seq, bus, &sh); 3156 if (error < 0) 3157 goto done; 3158 3159 error = brcmf_sdio_trap_info(seq, bus, &sh); 3160 if (error < 0) 3161 goto done; 3162 3163 error = brcmf_sdio_dump_console(seq, bus, &sh); 3164 3165 done: 3166 return error; 3167 } 3168 3169 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data) 3170 { 3171 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private); 3172 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus; 3173 3174 return brcmf_sdio_died_dump(seq, bus); 3175 } 3176 3177 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data) 3178 { 3179 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private); 3180 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3181 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt; 3182 3183 seq_printf(seq, 3184 "intrcount: %u\nlastintrs: %u\n" 3185 "pollcnt: %u\nregfails: %u\n" 3186 "tx_sderrs: %u\nfcqueued: %u\n" 3187 "rxrtx: %u\nrx_toolong: %u\n" 3188 "rxc_errors: %u\nrx_hdrfail: %u\n" 3189 "rx_badhdr: %u\nrx_badseq: %u\n" 3190 "fc_rcvd: %u\nfc_xoff: %u\n" 3191 "fc_xon: %u\nrxglomfail: %u\n" 3192 "rxglomframes: %u\nrxglompkts: %u\n" 3193 "f2rxhdrs: %u\nf2rxdata: %u\n" 3194 "f2txdata: %u\nf1regdata: %u\n" 3195 "tickcnt: %u\ntx_ctlerrs: %lu\n" 3196 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n" 3197 "rx_ctlpkts: %lu\nrx_readahead: %lu\n", 3198 sdcnt->intrcount, sdcnt->lastintrs, 3199 sdcnt->pollcnt, sdcnt->regfails, 3200 sdcnt->tx_sderrs, sdcnt->fcqueued, 3201 sdcnt->rxrtx, sdcnt->rx_toolong, 3202 sdcnt->rxc_errors, sdcnt->rx_hdrfail, 3203 sdcnt->rx_badhdr, sdcnt->rx_badseq, 3204 sdcnt->fc_rcvd, sdcnt->fc_xoff, 3205 sdcnt->fc_xon, sdcnt->rxglomfail, 3206 sdcnt->rxglomframes, sdcnt->rxglompkts, 3207 sdcnt->f2rxhdrs, sdcnt->f2rxdata, 3208 sdcnt->f2txdata, sdcnt->f1regdata, 3209 sdcnt->tickcnt, sdcnt->tx_ctlerrs, 3210 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs, 3211 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt); 3212 3213 return 0; 3214 } 3215 3216 static void brcmf_sdio_debugfs_create(struct device *dev) 3217 { 3218 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3219 struct brcmf_pub *drvr = bus_if->drvr; 3220 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3221 struct brcmf_sdio *bus = sdiodev->bus; 3222 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr); 3223 3224 if (IS_ERR_OR_NULL(dentry)) 3225 return; 3226 3227 bus->console_interval = BRCMF_CONSOLE; 3228 3229 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read); 3230 brcmf_debugfs_add_entry(drvr, "counters", 3231 brcmf_debugfs_sdio_count_read); 3232 debugfs_create_u32("console_interval", 0644, dentry, 3233 &bus->console_interval); 3234 } 3235 #else 3236 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) 3237 { 3238 return 0; 3239 } 3240 3241 static void brcmf_sdio_debugfs_create(struct device *dev) 3242 { 3243 } 3244 #endif /* DEBUG */ 3245 3246 static int 3247 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen) 3248 { 3249 int timeleft; 3250 uint rxlen = 0; 3251 bool pending; 3252 u8 *buf; 3253 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3254 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3255 struct brcmf_sdio *bus = sdiodev->bus; 3256 3257 brcmf_dbg(TRACE, "Enter\n"); 3258 if (sdiodev->state != BRCMF_SDIOD_DATA) 3259 return -EIO; 3260 3261 /* Wait until control frame is available */ 3262 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending); 3263 3264 spin_lock_bh(&bus->rxctl_lock); 3265 rxlen = bus->rxlen; 3266 memcpy(msg, bus->rxctl, min(msglen, rxlen)); 3267 bus->rxctl = NULL; 3268 buf = bus->rxctl_orig; 3269 bus->rxctl_orig = NULL; 3270 bus->rxlen = 0; 3271 spin_unlock_bh(&bus->rxctl_lock); 3272 vfree(buf); 3273 3274 if (rxlen) { 3275 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n", 3276 rxlen, msglen); 3277 } else if (timeleft == 0) { 3278 brcmf_err("resumed on timeout\n"); 3279 brcmf_sdio_checkdied(bus); 3280 } else if (pending) { 3281 brcmf_dbg(CTL, "cancelled\n"); 3282 return -ERESTARTSYS; 3283 } else { 3284 brcmf_dbg(CTL, "resumed for unknown reason?\n"); 3285 brcmf_sdio_checkdied(bus); 3286 } 3287 3288 if (rxlen) 3289 bus->sdcnt.rx_ctlpkts++; 3290 else 3291 bus->sdcnt.rx_ctlerrs++; 3292 3293 return rxlen ? (int)rxlen : -ETIMEDOUT; 3294 } 3295 3296 #ifdef DEBUG 3297 static bool 3298 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, 3299 u8 *ram_data, uint ram_sz) 3300 { 3301 char *ram_cmp; 3302 int err; 3303 bool ret = true; 3304 int address; 3305 int offset; 3306 int len; 3307 3308 /* read back and verify */ 3309 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr, 3310 ram_sz); 3311 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL); 3312 /* do not proceed while no memory but */ 3313 if (!ram_cmp) 3314 return true; 3315 3316 address = ram_addr; 3317 offset = 0; 3318 while (offset < ram_sz) { 3319 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK : 3320 ram_sz - offset; 3321 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len); 3322 if (err) { 3323 brcmf_err("error %d on reading %d membytes at 0x%08x\n", 3324 err, len, address); 3325 ret = false; 3326 break; 3327 } else if (memcmp(ram_cmp, &ram_data[offset], len)) { 3328 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n", 3329 offset, len); 3330 ret = false; 3331 break; 3332 } 3333 offset += len; 3334 address += len; 3335 } 3336 3337 kfree(ram_cmp); 3338 3339 return ret; 3340 } 3341 #else /* DEBUG */ 3342 static bool 3343 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, 3344 u8 *ram_data, uint ram_sz) 3345 { 3346 return true; 3347 } 3348 #endif /* DEBUG */ 3349 3350 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus, 3351 const struct firmware *fw) 3352 { 3353 int err; 3354 3355 brcmf_dbg(TRACE, "Enter\n"); 3356 3357 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase, 3358 (u8 *)fw->data, fw->size); 3359 if (err) 3360 brcmf_err("error %d on writing %d membytes at 0x%08x\n", 3361 err, (int)fw->size, bus->ci->rambase); 3362 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase, 3363 (u8 *)fw->data, fw->size)) 3364 err = -EIO; 3365 3366 return err; 3367 } 3368 3369 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus, 3370 void *vars, u32 varsz) 3371 { 3372 int address; 3373 int err; 3374 3375 brcmf_dbg(TRACE, "Enter\n"); 3376 3377 address = bus->ci->ramsize - varsz + bus->ci->rambase; 3378 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz); 3379 if (err) 3380 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n", 3381 err, varsz, address); 3382 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz)) 3383 err = -EIO; 3384 3385 return err; 3386 } 3387 3388 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus, 3389 const struct firmware *fw, 3390 void *nvram, u32 nvlen) 3391 { 3392 int bcmerror; 3393 u32 rstvec; 3394 3395 sdio_claim_host(bus->sdiodev->func1); 3396 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 3397 3398 rstvec = get_unaligned_le32(fw->data); 3399 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec); 3400 3401 bcmerror = brcmf_sdio_download_code_file(bus, fw); 3402 release_firmware(fw); 3403 if (bcmerror) { 3404 brcmf_err("dongle image file download failed\n"); 3405 brcmf_fw_nvram_free(nvram); 3406 goto err; 3407 } 3408 3409 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen); 3410 brcmf_fw_nvram_free(nvram); 3411 if (bcmerror) { 3412 brcmf_err("dongle nvram file download failed\n"); 3413 goto err; 3414 } 3415 3416 /* Take arm out of reset */ 3417 if (!brcmf_chip_set_active(bus->ci, rstvec)) { 3418 brcmf_err("error getting out of ARM core reset\n"); 3419 bcmerror = -EIO; 3420 goto err; 3421 } 3422 3423 err: 3424 brcmf_sdio_clkctl(bus, CLK_SDONLY, false); 3425 sdio_release_host(bus->sdiodev->func1); 3426 return bcmerror; 3427 } 3428 3429 static bool brcmf_sdio_aos_no_decode(struct brcmf_sdio *bus) 3430 { 3431 if (bus->ci->chip == BRCM_CC_43751_CHIP_ID || 3432 bus->ci->chip == BRCM_CC_43752_CHIP_ID || 3433 bus->ci->chip == CY_CC_43012_CHIP_ID) 3434 return true; 3435 else 3436 return false; 3437 } 3438 3439 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus) 3440 { 3441 int err = 0; 3442 u8 val; 3443 u8 wakeupctrl; 3444 u8 cardcap; 3445 u8 chipclkcsr; 3446 3447 brcmf_dbg(TRACE, "Enter\n"); 3448 3449 if (brcmf_chip_is_ulp(bus->ci)) { 3450 wakeupctrl = SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT; 3451 chipclkcsr = SBSDIO_HT_AVAIL_REQ; 3452 } else { 3453 wakeupctrl = SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT; 3454 chipclkcsr = SBSDIO_FORCE_HT; 3455 } 3456 3457 if (brcmf_sdio_aos_no_decode(bus)) { 3458 cardcap = SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC; 3459 } else { 3460 cardcap = (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT | 3461 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT); 3462 } 3463 3464 val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err); 3465 if (err) { 3466 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n"); 3467 return; 3468 } 3469 val |= 1 << wakeupctrl; 3470 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err); 3471 if (err) { 3472 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n"); 3473 return; 3474 } 3475 3476 /* Add CMD14 Support */ 3477 brcmf_sdiod_func0_wb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP, 3478 cardcap, 3479 &err); 3480 if (err) { 3481 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n"); 3482 return; 3483 } 3484 3485 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3486 chipclkcsr, &err); 3487 if (err) { 3488 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n"); 3489 return; 3490 } 3491 3492 /* set flag */ 3493 bus->sr_enabled = true; 3494 brcmf_dbg(INFO, "SR enabled\n"); 3495 } 3496 3497 /* enable KSO bit */ 3498 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus) 3499 { 3500 struct brcmf_core *core = bus->sdio_core; 3501 u8 val; 3502 int err = 0; 3503 3504 brcmf_dbg(TRACE, "Enter\n"); 3505 3506 /* KSO bit added in SDIO core rev 12 */ 3507 if (core->rev < 12) 3508 return 0; 3509 3510 val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err); 3511 if (err) { 3512 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n"); 3513 return err; 3514 } 3515 3516 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) { 3517 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN << 3518 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); 3519 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, 3520 val, &err); 3521 if (err) { 3522 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n"); 3523 return err; 3524 } 3525 } 3526 3527 return 0; 3528 } 3529 3530 3531 static int brcmf_sdio_bus_preinit(struct device *dev) 3532 { 3533 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3534 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3535 struct brcmf_sdio *bus = sdiodev->bus; 3536 struct brcmf_core *core = bus->sdio_core; 3537 u32 value; 3538 __le32 iovar; 3539 int err; 3540 3541 /* maxctl provided by common layer */ 3542 if (WARN_ON(!bus_if->maxctl)) 3543 return -EINVAL; 3544 3545 /* Allocate control receive buffer */ 3546 bus_if->maxctl += bus->roundup; 3547 value = roundup((bus_if->maxctl + SDPCM_HDRLEN), ALIGNMENT); 3548 value += bus->head_align; 3549 bus->rxbuf = kmalloc(value, GFP_ATOMIC); 3550 if (bus->rxbuf) 3551 bus->rxblen = value; 3552 3553 /* the commands below use the terms tx and rx from 3554 * a device perspective, ie. bus:txglom affects the 3555 * bus transfers from device to host. 3556 */ 3557 if (core->rev < 12) { 3558 /* for sdio core rev < 12, disable txgloming */ 3559 iovar = 0; 3560 err = brcmf_iovar_data_set(dev, "bus:txglom", &iovar, 3561 sizeof(iovar)); 3562 } else { 3563 /* otherwise, set txglomalign */ 3564 value = sdiodev->settings->bus.sdio.sd_sgentry_align; 3565 /* SDIO ADMA requires at least 32 bit alignment */ 3566 iovar = cpu_to_le32(max_t(u32, value, ALIGNMENT)); 3567 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &iovar, 3568 sizeof(iovar)); 3569 } 3570 3571 if (err < 0) 3572 goto done; 3573 3574 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; 3575 if (sdiodev->sg_support) { 3576 bus->txglom = false; 3577 iovar = cpu_to_le32(1); 3578 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom", 3579 &iovar, sizeof(iovar)); 3580 if (err < 0) { 3581 /* bus:rxglom is allowed to fail */ 3582 err = 0; 3583 } else { 3584 bus->txglom = true; 3585 bus->tx_hdrlen += SDPCM_HWEXT_LEN; 3586 } 3587 } 3588 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen); 3589 3590 done: 3591 return err; 3592 } 3593 3594 static size_t brcmf_sdio_bus_get_ramsize(struct device *dev) 3595 { 3596 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3597 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3598 struct brcmf_sdio *bus = sdiodev->bus; 3599 3600 return bus->ci->ramsize - bus->ci->srsize; 3601 } 3602 3603 static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data, 3604 size_t mem_size) 3605 { 3606 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3607 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3608 struct brcmf_sdio *bus = sdiodev->bus; 3609 int err; 3610 int address; 3611 int offset; 3612 int len; 3613 3614 brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase, 3615 mem_size); 3616 3617 address = bus->ci->rambase; 3618 offset = err = 0; 3619 sdio_claim_host(sdiodev->func1); 3620 while (offset < mem_size) { 3621 len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK : 3622 mem_size - offset; 3623 err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len); 3624 if (err) { 3625 brcmf_err("error %d on reading %d membytes at 0x%08x\n", 3626 err, len, address); 3627 goto done; 3628 } 3629 data += len; 3630 offset += len; 3631 address += len; 3632 } 3633 3634 done: 3635 sdio_release_host(sdiodev->func1); 3636 return err; 3637 } 3638 3639 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus) 3640 { 3641 if (!bus->dpc_triggered) { 3642 bus->dpc_triggered = true; 3643 queue_work(bus->brcmf_wq, &bus->datawork); 3644 } 3645 } 3646 3647 void brcmf_sdio_isr(struct brcmf_sdio *bus, bool in_isr) 3648 { 3649 brcmf_dbg(TRACE, "Enter\n"); 3650 3651 if (!bus) { 3652 brcmf_err("bus is null pointer, exiting\n"); 3653 return; 3654 } 3655 3656 /* Count the interrupt call */ 3657 bus->sdcnt.intrcount++; 3658 if (in_isr) 3659 atomic_set(&bus->ipend, 1); 3660 else 3661 if (brcmf_sdio_intr_rstatus(bus)) { 3662 brcmf_err("failed backplane access\n"); 3663 } 3664 3665 /* Disable additional interrupts (is this needed now)? */ 3666 if (!bus->intr) 3667 brcmf_err("isr w/o interrupt configured!\n"); 3668 3669 bus->dpc_triggered = true; 3670 queue_work(bus->brcmf_wq, &bus->datawork); 3671 } 3672 3673 static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus) 3674 { 3675 brcmf_dbg(TIMER, "Enter\n"); 3676 3677 /* Poll period: check device if appropriate. */ 3678 if (!bus->sr_enabled && 3679 bus->poll && (++bus->polltick >= bus->pollrate)) { 3680 u32 intstatus = 0; 3681 3682 /* Reset poll tick */ 3683 bus->polltick = 0; 3684 3685 /* Check device if no interrupts */ 3686 if (!bus->intr || 3687 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) { 3688 3689 if (!bus->dpc_triggered) { 3690 u8 devpend; 3691 3692 sdio_claim_host(bus->sdiodev->func1); 3693 devpend = brcmf_sdiod_func0_rb(bus->sdiodev, 3694 SDIO_CCCR_INTx, NULL); 3695 sdio_release_host(bus->sdiodev->func1); 3696 intstatus = devpend & (INTR_STATUS_FUNC1 | 3697 INTR_STATUS_FUNC2); 3698 } 3699 3700 /* If there is something, make like the ISR and 3701 schedule the DPC */ 3702 if (intstatus) { 3703 bus->sdcnt.pollcnt++; 3704 atomic_set(&bus->ipend, 1); 3705 3706 bus->dpc_triggered = true; 3707 queue_work(bus->brcmf_wq, &bus->datawork); 3708 } 3709 } 3710 3711 /* Update interrupt tracking */ 3712 bus->sdcnt.lastintrs = bus->sdcnt.intrcount; 3713 } 3714 #ifdef DEBUG 3715 /* Poll for console output periodically */ 3716 if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() && 3717 bus->console_interval != 0) { 3718 bus->console.count += jiffies_to_msecs(BRCMF_WD_POLL); 3719 if (bus->console.count >= bus->console_interval) { 3720 bus->console.count -= bus->console_interval; 3721 sdio_claim_host(bus->sdiodev->func1); 3722 /* Make sure backplane clock is on */ 3723 brcmf_sdio_bus_sleep(bus, false, false); 3724 if (brcmf_sdio_readconsole(bus) < 0) 3725 /* stop on error */ 3726 bus->console_interval = 0; 3727 sdio_release_host(bus->sdiodev->func1); 3728 } 3729 } 3730 #endif /* DEBUG */ 3731 3732 /* On idle timeout clear activity flag and/or turn off clock */ 3733 if (!bus->dpc_triggered) { 3734 rmb(); 3735 if ((!bus->dpc_running) && (bus->idletime > 0) && 3736 (bus->clkstate == CLK_AVAIL)) { 3737 bus->idlecount++; 3738 if (bus->idlecount > bus->idletime) { 3739 brcmf_dbg(SDIO, "idle\n"); 3740 sdio_claim_host(bus->sdiodev->func1); 3741 #ifdef DEBUG 3742 if (!BRCMF_FWCON_ON() || 3743 bus->console_interval == 0) 3744 #endif 3745 brcmf_sdio_wd_timer(bus, false); 3746 bus->idlecount = 0; 3747 brcmf_sdio_bus_sleep(bus, true, false); 3748 sdio_release_host(bus->sdiodev->func1); 3749 } 3750 } else { 3751 bus->idlecount = 0; 3752 } 3753 } else { 3754 bus->idlecount = 0; 3755 } 3756 } 3757 3758 static void brcmf_sdio_dataworker(struct work_struct *work) 3759 { 3760 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio, 3761 datawork); 3762 3763 bus->dpc_running = true; 3764 wmb(); 3765 while (READ_ONCE(bus->dpc_triggered)) { 3766 bus->dpc_triggered = false; 3767 brcmf_sdio_dpc(bus); 3768 bus->idlecount = 0; 3769 } 3770 bus->dpc_running = false; 3771 if (brcmf_sdiod_freezing(bus->sdiodev)) { 3772 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN); 3773 brcmf_sdiod_try_freeze(bus->sdiodev); 3774 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA); 3775 } 3776 } 3777 3778 static void 3779 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev, 3780 struct brcmf_chip *ci, u32 drivestrength) 3781 { 3782 const struct sdiod_drive_str *str_tab = NULL; 3783 u32 str_mask; 3784 u32 str_shift; 3785 u32 i; 3786 u32 drivestrength_sel = 0; 3787 u32 cc_data_temp; 3788 u32 addr; 3789 3790 if (!(ci->cc_caps & CC_CAP_PMU)) 3791 return; 3792 3793 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) { 3794 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12): 3795 str_tab = sdiod_drvstr_tab1_1v8; 3796 str_mask = 0x00003800; 3797 str_shift = 11; 3798 break; 3799 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17): 3800 str_tab = sdiod_drvstr_tab6_1v8; 3801 str_mask = 0x00001800; 3802 str_shift = 11; 3803 break; 3804 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17): 3805 /* note: 43143 does not support tristate */ 3806 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1; 3807 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) { 3808 str_tab = sdiod_drvstr_tab2_3v3; 3809 str_mask = 0x00000007; 3810 str_shift = 0; 3811 } else 3812 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n", 3813 ci->name, drivestrength); 3814 break; 3815 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13): 3816 str_tab = sdiod_drive_strength_tab5_1v8; 3817 str_mask = 0x00003800; 3818 str_shift = 11; 3819 break; 3820 default: 3821 brcmf_dbg(INFO, "No SDIO driver strength init needed for chip %s rev %d pmurev %d\n", 3822 ci->name, ci->chiprev, ci->pmurev); 3823 break; 3824 } 3825 3826 if (str_tab != NULL) { 3827 struct brcmf_core *pmu = brcmf_chip_get_pmu(ci); 3828 3829 for (i = 0; str_tab[i].strength != 0; i++) { 3830 if (drivestrength >= str_tab[i].strength) { 3831 drivestrength_sel = str_tab[i].sel; 3832 break; 3833 } 3834 } 3835 addr = CORE_CC_REG(pmu->base, chipcontrol_addr); 3836 brcmf_sdiod_writel(sdiodev, addr, 1, NULL); 3837 cc_data_temp = brcmf_sdiod_readl(sdiodev, addr, NULL); 3838 cc_data_temp &= ~str_mask; 3839 drivestrength_sel <<= str_shift; 3840 cc_data_temp |= drivestrength_sel; 3841 brcmf_sdiod_writel(sdiodev, addr, cc_data_temp, NULL); 3842 3843 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n", 3844 str_tab[i].strength, drivestrength, cc_data_temp); 3845 } 3846 } 3847 3848 static int brcmf_sdio_buscoreprep(void *ctx) 3849 { 3850 struct brcmf_sdio_dev *sdiodev = ctx; 3851 int err = 0; 3852 u8 clkval, clkset; 3853 3854 /* Try forcing SDIO core to do ALPAvail request only */ 3855 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ; 3856 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); 3857 if (err) { 3858 brcmf_err("error writing for HT off\n"); 3859 return err; 3860 } 3861 3862 /* If register supported, wait for ALPAvail and then force ALP */ 3863 /* This may take up to 15 milliseconds */ 3864 clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, NULL); 3865 3866 if ((clkval & ~SBSDIO_AVBITS) != clkset) { 3867 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n", 3868 clkset, clkval); 3869 return -EACCES; 3870 } 3871 3872 SPINWAIT(((clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3873 NULL)), 3874 !SBSDIO_ALPAV(clkval)), 3875 PMU_MAX_TRANSITION_DLY); 3876 3877 if (!SBSDIO_ALPAV(clkval)) { 3878 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n", 3879 clkval); 3880 return -EBUSY; 3881 } 3882 3883 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP; 3884 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); 3885 udelay(65); 3886 3887 /* Also, disable the extra SDIO pull-ups */ 3888 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL); 3889 3890 return 0; 3891 } 3892 3893 static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip, 3894 u32 rstvec) 3895 { 3896 struct brcmf_sdio_dev *sdiodev = ctx; 3897 struct brcmf_core *core = sdiodev->bus->sdio_core; 3898 u32 reg_addr; 3899 3900 /* clear all interrupts */ 3901 reg_addr = core->base + SD_REG(intstatus); 3902 brcmf_sdiod_writel(sdiodev, reg_addr, 0xFFFFFFFF, NULL); 3903 3904 if (rstvec) 3905 /* Write reset vector to address 0 */ 3906 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec, 3907 sizeof(rstvec)); 3908 } 3909 3910 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr) 3911 { 3912 struct brcmf_sdio_dev *sdiodev = ctx; 3913 u32 val, rev; 3914 3915 val = brcmf_sdiod_readl(sdiodev, addr, NULL); 3916 3917 /* 3918 * this is a bit of special handling if reading the chipcommon chipid 3919 * register. The 4339 is a next-gen of the 4335. It uses the same 3920 * SDIO device id as 4335 and the chipid register returns 4335 as well. 3921 * It can be identified as 4339 by looking at the chip revision. It 3922 * is corrected here so the chip.c module has the right info. 3923 */ 3924 if (addr == CORE_CC_REG(SI_ENUM_BASE_DEFAULT, chipid) && 3925 (sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4339 || 3926 sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4335_4339)) { 3927 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT; 3928 if (rev >= 2) { 3929 val &= ~CID_ID_MASK; 3930 val |= BRCM_CC_4339_CHIP_ID; 3931 } 3932 } 3933 3934 return val; 3935 } 3936 3937 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val) 3938 { 3939 struct brcmf_sdio_dev *sdiodev = ctx; 3940 3941 brcmf_sdiod_writel(sdiodev, addr, val, NULL); 3942 } 3943 3944 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = { 3945 .prepare = brcmf_sdio_buscoreprep, 3946 .activate = brcmf_sdio_buscore_activate, 3947 .read32 = brcmf_sdio_buscore_read32, 3948 .write32 = brcmf_sdio_buscore_write32, 3949 }; 3950 3951 static int 3952 brcmf_sdio_probe_attach(struct brcmf_sdio *bus) 3953 { 3954 struct brcmf_sdio_dev *sdiodev; 3955 u8 clkctl = 0; 3956 int err = 0; 3957 int reg_addr; 3958 u32 reg_val; 3959 u32 drivestrength; 3960 u32 enum_base; 3961 int ret = -EBADE; 3962 3963 sdiodev = bus->sdiodev; 3964 sdio_claim_host(sdiodev->func1); 3965 3966 enum_base = brcmf_chip_enum_base(sdiodev->func1->device); 3967 3968 pr_debug("F1 signature read @0x%08x=0x%4x\n", enum_base, 3969 brcmf_sdiod_readl(sdiodev, enum_base, NULL)); 3970 3971 /* 3972 * Force PLL off until brcmf_chip_attach() 3973 * programs PLL control regs 3974 */ 3975 3976 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, BRCMF_INIT_CLKCTL1, 3977 &err); 3978 if (!err) 3979 clkctl = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3980 &err); 3981 3982 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) { 3983 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n", 3984 err, BRCMF_INIT_CLKCTL1, clkctl); 3985 goto fail; 3986 } 3987 3988 bus->ci = brcmf_chip_attach(sdiodev, sdiodev->func1->device, 3989 &brcmf_sdio_buscore_ops); 3990 if (IS_ERR(bus->ci)) { 3991 brcmf_err("brcmf_chip_attach failed!\n"); 3992 bus->ci = NULL; 3993 goto fail; 3994 } 3995 3996 /* Pick up the SDIO core info struct from chip.c */ 3997 bus->sdio_core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); 3998 if (!bus->sdio_core) 3999 goto fail; 4000 4001 /* Pick up the CHIPCOMMON core info struct, for bulk IO in bcmsdh.c */ 4002 sdiodev->cc_core = brcmf_chip_get_core(bus->ci, BCMA_CORE_CHIPCOMMON); 4003 if (!sdiodev->cc_core) 4004 goto fail; 4005 4006 sdiodev->settings = brcmf_get_module_param(sdiodev->dev, 4007 BRCMF_BUSTYPE_SDIO, 4008 bus->ci->chip, 4009 bus->ci->chiprev); 4010 if (IS_ERR_OR_NULL(sdiodev->settings)) { 4011 brcmf_err("Failed to get device parameters\n"); 4012 ret = PTR_ERR_OR_ZERO(sdiodev->settings); 4013 goto fail; 4014 } 4015 /* platform specific configuration: 4016 * alignments must be at least 4 bytes for ADMA 4017 */ 4018 bus->head_align = ALIGNMENT; 4019 bus->sgentry_align = ALIGNMENT; 4020 if (sdiodev->settings->bus.sdio.sd_head_align > ALIGNMENT) 4021 bus->head_align = sdiodev->settings->bus.sdio.sd_head_align; 4022 if (sdiodev->settings->bus.sdio.sd_sgentry_align > ALIGNMENT) 4023 bus->sgentry_align = 4024 sdiodev->settings->bus.sdio.sd_sgentry_align; 4025 4026 /* allocate scatter-gather table. sg support 4027 * will be disabled upon allocation failure. 4028 */ 4029 brcmf_sdiod_sgtable_alloc(sdiodev); 4030 4031 /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ 4032 * is true or when platform data OOB irq is true). 4033 */ 4034 if (IS_ENABLED(CONFIG_PM_SLEEP) && 4035 (sdio_get_host_pm_caps(sdiodev->func1) & MMC_PM_KEEP_POWER) && 4036 ((sdio_get_host_pm_caps(sdiodev->func1) & MMC_PM_WAKE_SDIO_IRQ) || 4037 (sdiodev->settings->bus.sdio.oob_irq_supported))) 4038 sdiodev->bus_if->wowl_supported = true; 4039 4040 if (brcmf_sdio_kso_init(bus)) { 4041 brcmf_err("error enabling KSO\n"); 4042 goto fail; 4043 } 4044 4045 if (sdiodev->settings->bus.sdio.drive_strength) 4046 drivestrength = sdiodev->settings->bus.sdio.drive_strength; 4047 else 4048 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH; 4049 brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength); 4050 4051 /* Set card control so an SDIO card reset does a WLAN backplane reset */ 4052 reg_val = brcmf_sdiod_func0_rb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err); 4053 if (err) 4054 goto fail; 4055 4056 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET; 4057 4058 brcmf_sdiod_func0_wb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err); 4059 if (err) 4060 goto fail; 4061 4062 /* set PMUControl so a backplane reset does PMU state reload */ 4063 reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol); 4064 reg_val = brcmf_sdiod_readl(sdiodev, reg_addr, &err); 4065 if (err) 4066 goto fail; 4067 4068 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT); 4069 4070 brcmf_sdiod_writel(sdiodev, reg_addr, reg_val, &err); 4071 if (err) 4072 goto fail; 4073 4074 sdio_release_host(sdiodev->func1); 4075 4076 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN); 4077 4078 /* allocate header buffer */ 4079 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL); 4080 if (!bus->hdrbuf) 4081 return -ENOMEM; 4082 /* Locate an appropriately-aligned portion of hdrbuf */ 4083 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], 4084 bus->head_align); 4085 4086 /* Set the poll and/or interrupt flags */ 4087 bus->intr = true; 4088 bus->poll = false; 4089 if (bus->poll) 4090 bus->pollrate = 1; 4091 4092 return 0; 4093 4094 fail: 4095 sdio_release_host(sdiodev->func1); 4096 return ret; 4097 } 4098 4099 static int 4100 brcmf_sdio_watchdog_thread(void *data) 4101 { 4102 struct brcmf_sdio *bus = (struct brcmf_sdio *)data; 4103 int wait; 4104 4105 allow_signal(SIGTERM); 4106 /* Run until signal received */ 4107 brcmf_sdiod_freezer_count(bus->sdiodev); 4108 while (1) { 4109 if (kthread_should_stop()) 4110 break; 4111 brcmf_sdiod_freezer_uncount(bus->sdiodev); 4112 wait = wait_for_completion_interruptible(&bus->watchdog_wait); 4113 brcmf_sdiod_freezer_count(bus->sdiodev); 4114 brcmf_sdiod_try_freeze(bus->sdiodev); 4115 if (!wait) { 4116 brcmf_sdio_bus_watchdog(bus); 4117 /* Count the tick for reference */ 4118 bus->sdcnt.tickcnt++; 4119 reinit_completion(&bus->watchdog_wait); 4120 } else 4121 break; 4122 } 4123 return 0; 4124 } 4125 4126 static void 4127 brcmf_sdio_watchdog(struct timer_list *t) 4128 { 4129 struct brcmf_sdio *bus = timer_container_of(bus, t, timer); 4130 4131 if (bus->watchdog_tsk) { 4132 complete(&bus->watchdog_wait); 4133 /* Reschedule the watchdog */ 4134 if (bus->wd_active) 4135 mod_timer(&bus->timer, 4136 jiffies + BRCMF_WD_POLL); 4137 } 4138 } 4139 4140 static int brcmf_sdio_get_blob(struct device *dev, const struct firmware **fw, 4141 enum brcmf_blob_type type) 4142 { 4143 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 4144 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 4145 4146 switch (type) { 4147 case BRCMF_BLOB_CLM: 4148 *fw = sdiodev->clm_fw; 4149 sdiodev->clm_fw = NULL; 4150 break; 4151 default: 4152 return -ENOENT; 4153 } 4154 4155 if (!*fw) 4156 return -ENOENT; 4157 4158 return 0; 4159 } 4160 4161 static int brcmf_sdio_bus_reset(struct device *dev) 4162 { 4163 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 4164 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 4165 4166 brcmf_dbg(SDIO, "Enter\n"); 4167 4168 /* start by unregistering irqs */ 4169 brcmf_sdiod_intr_unregister(sdiodev); 4170 4171 brcmf_sdiod_remove(sdiodev); 4172 4173 /* reset the adapter */ 4174 sdio_claim_host(sdiodev->func1); 4175 mmc_hw_reset(sdiodev->func1->card); 4176 sdio_release_host(sdiodev->func1); 4177 4178 brcmf_bus_change_state(sdiodev->bus_if, BRCMF_BUS_DOWN); 4179 return 0; 4180 } 4181 4182 static void brcmf_sdio_bus_remove(struct device *dev) 4183 { 4184 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 4185 struct brcmf_sdio_dev *sdiod = bus_if->bus_priv.sdio; 4186 4187 device_release_driver(&sdiod->func2->dev); 4188 device_release_driver(&sdiod->func1->dev); 4189 } 4190 4191 static const struct brcmf_bus_ops brcmf_sdio_bus_ops = { 4192 .stop = brcmf_sdio_bus_stop, 4193 .preinit = brcmf_sdio_bus_preinit, 4194 .txdata = brcmf_sdio_bus_txdata, 4195 .txctl = brcmf_sdio_bus_txctl, 4196 .rxctl = brcmf_sdio_bus_rxctl, 4197 .gettxq = brcmf_sdio_bus_gettxq, 4198 .wowl_config = brcmf_sdio_wowl_config, 4199 .get_ramsize = brcmf_sdio_bus_get_ramsize, 4200 .get_memdump = brcmf_sdio_bus_get_memdump, 4201 .get_blob = brcmf_sdio_get_blob, 4202 .debugfs_create = brcmf_sdio_debugfs_create, 4203 .reset = brcmf_sdio_bus_reset, 4204 .remove = brcmf_sdio_bus_remove, 4205 }; 4206 4207 #define BRCMF_SDIO_FW_CODE 0 4208 #define BRCMF_SDIO_FW_NVRAM 1 4209 #define BRCMF_SDIO_FW_CLM 2 4210 4211 static void brcmf_sdio_firmware_callback(struct device *dev, int err, 4212 struct brcmf_fw_request *fwreq) 4213 { 4214 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 4215 struct brcmf_sdio_dev *sdiod = bus_if->bus_priv.sdio; 4216 struct brcmf_sdio *bus = sdiod->bus; 4217 struct brcmf_core *core = bus->sdio_core; 4218 const struct firmware *code; 4219 void *nvram; 4220 u32 nvram_len; 4221 u8 saveclk, bpreq; 4222 u8 devctl; 4223 4224 brcmf_dbg(TRACE, "Enter: dev=%s, err=%d\n", dev_name(dev), err); 4225 4226 if (err) 4227 goto fail; 4228 4229 code = fwreq->items[BRCMF_SDIO_FW_CODE].binary; 4230 nvram = fwreq->items[BRCMF_SDIO_FW_NVRAM].nv_data.data; 4231 nvram_len = fwreq->items[BRCMF_SDIO_FW_NVRAM].nv_data.len; 4232 sdiod->clm_fw = fwreq->items[BRCMF_SDIO_FW_CLM].binary; 4233 kfree(fwreq); 4234 4235 /* try to download image and nvram to the dongle */ 4236 bus->alp_only = true; 4237 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len); 4238 if (err) 4239 goto fail; 4240 bus->alp_only = false; 4241 4242 /* Start the watchdog timer */ 4243 bus->sdcnt.tickcnt = 0; 4244 brcmf_sdio_wd_timer(bus, true); 4245 4246 sdio_claim_host(sdiod->func1); 4247 4248 /* Make sure backplane clock is on, needed to generate F2 interrupt */ 4249 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 4250 if (bus->clkstate != CLK_AVAIL) 4251 goto release; 4252 4253 /* Force clocks on backplane to be sure F2 interrupt propagates */ 4254 saveclk = brcmf_sdiod_readb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, &err); 4255 if (!err) { 4256 bpreq = saveclk; 4257 bpreq |= brcmf_chip_is_ulp(bus->ci) ? 4258 SBSDIO_HT_AVAIL_REQ : SBSDIO_FORCE_HT; 4259 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, 4260 bpreq, &err); 4261 } 4262 if (err) { 4263 brcmf_err("Failed to force clock for F2: err %d\n", err); 4264 goto release; 4265 } 4266 4267 /* Enable function 2 (frame transfers) */ 4268 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailboxdata), 4269 SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT, NULL); 4270 4271 err = sdio_enable_func(sdiod->func2); 4272 4273 brcmf_dbg(INFO, "enable F2: err=%d\n", err); 4274 4275 /* If F2 successfully enabled, set core and enable interrupts */ 4276 if (!err) { 4277 /* Set up the interrupt mask and enable interrupts */ 4278 bus->hostintmask = HOSTINTMASK; 4279 brcmf_sdiod_writel(sdiod, core->base + SD_REG(hostintmask), 4280 bus->hostintmask, NULL); 4281 4282 switch (sdiod->func1->device) { 4283 case SDIO_DEVICE_ID_BROADCOM_43751: 4284 case SDIO_DEVICE_ID_BROADCOM_43752: 4285 case SDIO_DEVICE_ID_BROADCOM_CYPRESS_4373: 4286 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n", 4287 CY_4373_F2_WATERMARK); 4288 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4289 CY_4373_F2_WATERMARK, &err); 4290 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL, 4291 &err); 4292 devctl |= SBSDIO_DEVCTL_F2WM_ENAB; 4293 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl, 4294 &err); 4295 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL, 4296 CY_4373_F1_MESBUSYCTRL, &err); 4297 break; 4298 case SDIO_DEVICE_ID_BROADCOM_CYPRESS_43012: 4299 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n", 4300 CY_43012_F2_WATERMARK); 4301 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4302 CY_43012_F2_WATERMARK, &err); 4303 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL, 4304 &err); 4305 devctl |= SBSDIO_DEVCTL_F2WM_ENAB; 4306 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl, 4307 &err); 4308 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL, 4309 CY_43012_MESBUSYCTRL, &err); 4310 break; 4311 case SDIO_DEVICE_ID_BROADCOM_4329: 4312 case SDIO_DEVICE_ID_BROADCOM_4339: 4313 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n", 4314 CY_4339_F2_WATERMARK); 4315 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4316 CY_4339_F2_WATERMARK, &err); 4317 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL, 4318 &err); 4319 devctl |= SBSDIO_DEVCTL_F2WM_ENAB; 4320 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl, 4321 &err); 4322 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL, 4323 CY_4339_MESBUSYCTRL, &err); 4324 break; 4325 case SDIO_DEVICE_ID_BROADCOM_43455: 4326 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n", 4327 CY_43455_F2_WATERMARK); 4328 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4329 CY_43455_F2_WATERMARK, &err); 4330 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL, 4331 &err); 4332 devctl |= SBSDIO_DEVCTL_F2WM_ENAB; 4333 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl, 4334 &err); 4335 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL, 4336 CY_43455_MESBUSYCTRL, &err); 4337 break; 4338 case SDIO_DEVICE_ID_BROADCOM_4359: 4339 case SDIO_DEVICE_ID_BROADCOM_4354: 4340 case SDIO_DEVICE_ID_BROADCOM_4356: 4341 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n", 4342 CY_435X_F2_WATERMARK); 4343 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4344 CY_435X_F2_WATERMARK, &err); 4345 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL, 4346 &err); 4347 devctl |= SBSDIO_DEVCTL_F2WM_ENAB; 4348 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl, 4349 &err); 4350 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL, 4351 CY_435X_F1_MESBUSYCTRL, &err); 4352 break; 4353 default: 4354 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4355 DEFAULT_F2_WATERMARK, &err); 4356 break; 4357 } 4358 } else { 4359 /* Disable F2 again */ 4360 sdio_disable_func(sdiod->func2); 4361 goto checkdied; 4362 } 4363 4364 if (brcmf_chip_sr_capable(bus->ci)) { 4365 brcmf_sdio_sr_init(bus); 4366 } else { 4367 /* Restore previous clock setting */ 4368 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, 4369 saveclk, &err); 4370 } 4371 4372 if (err == 0) { 4373 /* Assign bus interface call back */ 4374 sdiod->bus_if->dev = sdiod->dev; 4375 sdiod->bus_if->ops = &brcmf_sdio_bus_ops; 4376 sdiod->bus_if->chip = bus->ci->chip; 4377 sdiod->bus_if->chiprev = bus->ci->chiprev; 4378 4379 /* Allow full data communication using DPC from now on. */ 4380 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA); 4381 4382 err = brcmf_sdiod_intr_register(sdiod); 4383 if (err != 0) 4384 brcmf_err("intr register failed:%d\n", err); 4385 } 4386 4387 /* If we didn't come up, turn off backplane clock */ 4388 if (err != 0) { 4389 brcmf_sdio_clkctl(bus, CLK_NONE, false); 4390 goto checkdied; 4391 } 4392 4393 sdio_release_host(sdiod->func1); 4394 4395 err = brcmf_alloc(sdiod->dev, sdiod->settings); 4396 if (err) { 4397 brcmf_err("brcmf_alloc failed\n"); 4398 goto claim; 4399 } 4400 4401 /* Attach to the common layer, reserve hdr space */ 4402 err = brcmf_attach(sdiod->dev); 4403 if (err != 0) { 4404 brcmf_err("brcmf_attach failed\n"); 4405 goto free; 4406 } 4407 4408 /* ready */ 4409 return; 4410 4411 free: 4412 brcmf_free(sdiod->dev); 4413 claim: 4414 sdio_claim_host(sdiod->func1); 4415 checkdied: 4416 brcmf_sdio_checkdied(bus); 4417 release: 4418 sdio_release_host(sdiod->func1); 4419 fail: 4420 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err); 4421 device_release_driver(&sdiod->func2->dev); 4422 device_release_driver(dev); 4423 } 4424 4425 static struct brcmf_fw_request * 4426 brcmf_sdio_prepare_fw_request(struct brcmf_sdio *bus) 4427 { 4428 struct brcmf_fw_request *fwreq; 4429 struct brcmf_fw_name fwnames[] = { 4430 { ".bin", bus->sdiodev->fw_name }, 4431 { ".txt", bus->sdiodev->nvram_name }, 4432 { ".clm_blob", bus->sdiodev->clm_name }, 4433 }; 4434 4435 fwreq = brcmf_fw_alloc_request(bus->ci->chip, bus->ci->chiprev, 4436 brcmf_sdio_fwnames, 4437 ARRAY_SIZE(brcmf_sdio_fwnames), 4438 fwnames, ARRAY_SIZE(fwnames)); 4439 if (!fwreq) 4440 return NULL; 4441 4442 fwreq->items[BRCMF_SDIO_FW_CODE].type = BRCMF_FW_TYPE_BINARY; 4443 fwreq->items[BRCMF_SDIO_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM; 4444 fwreq->items[BRCMF_SDIO_FW_CLM].type = BRCMF_FW_TYPE_BINARY; 4445 fwreq->items[BRCMF_SDIO_FW_CLM].flags = BRCMF_FW_REQF_OPTIONAL; 4446 fwreq->board_types[0] = bus->sdiodev->settings->board_type; 4447 4448 return fwreq; 4449 } 4450 4451 int brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev) 4452 { 4453 int ret; 4454 struct brcmf_sdio *bus; 4455 struct workqueue_struct *wq; 4456 struct brcmf_fw_request *fwreq; 4457 4458 brcmf_dbg(TRACE, "Enter\n"); 4459 4460 /* Allocate private bus interface state */ 4461 bus = kzalloc_obj(*bus, GFP_ATOMIC); 4462 if (!bus) { 4463 ret = -ENOMEM; 4464 goto fail; 4465 } 4466 4467 bus->sdiodev = sdiodev; 4468 sdiodev->bus = bus; 4469 skb_queue_head_init(&bus->glom); 4470 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker); 4471 bus->txbound = BRCMF_TXBOUND; 4472 bus->rxbound = BRCMF_RXBOUND; 4473 bus->txminmax = BRCMF_TXMINMAX; 4474 bus->tx_seq = SDPCM_SEQ_WRAP - 1; 4475 4476 /* single-threaded workqueue */ 4477 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM | WQ_HIGHPRI, 4478 dev_name(&sdiodev->func1->dev)); 4479 if (!wq) { 4480 brcmf_err("insufficient memory to create txworkqueue\n"); 4481 ret = -ENOMEM; 4482 goto fail; 4483 } 4484 brcmf_sdiod_freezer_count(sdiodev); 4485 bus->brcmf_wq = wq; 4486 4487 /* attempt to attach to the dongle */ 4488 ret = brcmf_sdio_probe_attach(bus); 4489 if (ret < 0) { 4490 brcmf_err("brcmf_sdio_probe_attach failed\n"); 4491 goto fail; 4492 } 4493 4494 spin_lock_init(&bus->rxctl_lock); 4495 spin_lock_init(&bus->txq_lock); 4496 init_waitqueue_head(&bus->ctrl_wait); 4497 init_waitqueue_head(&bus->dcmd_resp_wait); 4498 4499 /* Set up the watchdog timer */ 4500 timer_setup(&bus->timer, brcmf_sdio_watchdog, 0); 4501 /* Initialize watchdog thread */ 4502 init_completion(&bus->watchdog_wait); 4503 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread, 4504 bus, "brcmf_wdog/%s", 4505 dev_name(&sdiodev->func1->dev)); 4506 if (IS_ERR(bus->watchdog_tsk)) { 4507 pr_warn("brcmf_watchdog thread failed to start\n"); 4508 bus->watchdog_tsk = NULL; 4509 } 4510 /* Initialize DPC thread */ 4511 bus->dpc_triggered = false; 4512 bus->dpc_running = false; 4513 4514 /* default sdio bus header length for tx packet */ 4515 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; 4516 4517 /* Query the F2 block size, set roundup accordingly */ 4518 bus->blocksize = bus->sdiodev->func2->cur_blksize; 4519 bus->roundup = min(max_roundup, bus->blocksize); 4520 4521 sdio_claim_host(bus->sdiodev->func1); 4522 4523 /* Disable F2 to clear any intermediate frame state on the dongle */ 4524 sdio_disable_func(bus->sdiodev->func2); 4525 4526 bus->rxflow = false; 4527 4528 /* Done with backplane-dependent accesses, can drop clock... */ 4529 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); 4530 4531 sdio_release_host(bus->sdiodev->func1); 4532 4533 /* ...and initialize clock/power states */ 4534 bus->clkstate = CLK_SDONLY; 4535 bus->idletime = BRCMF_IDLE_INTERVAL; 4536 bus->idleclock = BRCMF_IDLE_ACTIVE; 4537 4538 /* SR state */ 4539 bus->sr_enabled = false; 4540 4541 brcmf_dbg(INFO, "completed!!\n"); 4542 4543 fwreq = brcmf_sdio_prepare_fw_request(bus); 4544 if (!fwreq) { 4545 ret = -ENOMEM; 4546 goto fail; 4547 } 4548 4549 ret = brcmf_fw_get_firmwares(sdiodev->dev, fwreq, 4550 brcmf_sdio_firmware_callback); 4551 if (ret != 0) { 4552 brcmf_err("async firmware request failed: %d\n", ret); 4553 kfree(fwreq); 4554 goto fail; 4555 } 4556 4557 return 0; 4558 4559 fail: 4560 brcmf_sdio_remove(bus); 4561 sdiodev->bus = NULL; 4562 return ret; 4563 } 4564 4565 void brcmf_sdio_cancel_datawork(struct brcmf_sdio *bus) 4566 { 4567 if (bus) 4568 cancel_work_sync(&bus->datawork); 4569 } 4570 4571 /* Detach and free everything */ 4572 void brcmf_sdio_remove(struct brcmf_sdio *bus) 4573 { 4574 brcmf_dbg(TRACE, "Enter\n"); 4575 4576 if (bus) { 4577 /* Stop watchdog task */ 4578 if (bus->watchdog_tsk) { 4579 get_task_struct(bus->watchdog_tsk); 4580 send_sig(SIGTERM, bus->watchdog_tsk, 1); 4581 kthread_stop_put(bus->watchdog_tsk); 4582 bus->watchdog_tsk = NULL; 4583 } 4584 4585 /* De-register interrupt handler */ 4586 brcmf_sdiod_intr_unregister(bus->sdiodev); 4587 4588 brcmf_detach(bus->sdiodev->dev); 4589 brcmf_free(bus->sdiodev->dev); 4590 4591 cancel_work_sync(&bus->datawork); 4592 if (bus->brcmf_wq) 4593 destroy_workqueue(bus->brcmf_wq); 4594 4595 if (bus->ci) { 4596 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) { 4597 sdio_claim_host(bus->sdiodev->func1); 4598 brcmf_sdio_wd_timer(bus, false); 4599 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 4600 /* Leave the device in state where it is 4601 * 'passive'. This is done by resetting all 4602 * necessary cores. 4603 */ 4604 msleep(20); 4605 brcmf_chip_set_passive(bus->ci); 4606 brcmf_sdio_clkctl(bus, CLK_NONE, false); 4607 sdio_release_host(bus->sdiodev->func1); 4608 } 4609 brcmf_chip_detach(bus->ci); 4610 } 4611 if (bus->sdiodev->settings) 4612 brcmf_release_module_param(bus->sdiodev->settings); 4613 4614 release_firmware(bus->sdiodev->clm_fw); 4615 bus->sdiodev->clm_fw = NULL; 4616 kfree(bus->rxbuf); 4617 kfree(bus->hdrbuf); 4618 kfree(bus); 4619 } 4620 4621 brcmf_dbg(TRACE, "Disconnected\n"); 4622 } 4623 4624 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active) 4625 { 4626 /* Totally stop the timer */ 4627 if (!active && bus->wd_active) { 4628 timer_delete_sync(&bus->timer); 4629 bus->wd_active = false; 4630 return; 4631 } 4632 4633 /* don't start the wd until fw is loaded */ 4634 if (bus->sdiodev->state != BRCMF_SDIOD_DATA) 4635 return; 4636 4637 if (active) { 4638 if (!bus->wd_active) { 4639 /* Create timer again when watchdog period is 4640 dynamically changed or in the first instance 4641 */ 4642 bus->timer.expires = jiffies + BRCMF_WD_POLL; 4643 add_timer(&bus->timer); 4644 bus->wd_active = true; 4645 } else { 4646 /* Re arm the timer, at last watchdog period */ 4647 mod_timer(&bus->timer, jiffies + BRCMF_WD_POLL); 4648 } 4649 } 4650 } 4651 4652 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep) 4653 { 4654 int ret; 4655 4656 sdio_claim_host(bus->sdiodev->func1); 4657 ret = brcmf_sdio_bus_sleep(bus, sleep, false); 4658 sdio_release_host(bus->sdiodev->func1); 4659 4660 return ret; 4661 } 4662