1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * bpf_jit_comp64.c: eBPF JIT compiler 4 * 5 * Copyright 2016 Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> 6 * IBM Corporation 7 * 8 * Based on the powerpc classic BPF JIT compiler by Matt Evans 9 */ 10 #include <linux/moduleloader.h> 11 #include <asm/cacheflush.h> 12 #include <asm/asm-compat.h> 13 #include <linux/netdevice.h> 14 #include <linux/filter.h> 15 #include <linux/if_vlan.h> 16 #include <asm/kprobes.h> 17 #include <linux/bpf.h> 18 #include <asm/security_features.h> 19 20 #include "bpf_jit.h" 21 22 /* 23 * Stack layout with frame: 24 * Layout when setting up our own stack frame. 25 * Note: r1 at bottom, component offsets positive wrt r1. 26 * Ensure the top half (upto local_tmp_var) stays consistent 27 * with our redzone usage. 28 * 29 * tail_call_info - stores tailcall count value in main program's 30 * frame, stores reference to tail_call_info of 31 * main's frame in sub-prog's frame. 32 * 33 * [ prev sp ] <------------- 34 * [ tail_call_info ] 8 | 35 * [ nv gpr save area ] (6 * 8) | 36 * [ addl. nv gpr save area] (12 * 8) | <--- exception boundary/callback program 37 * [ local_tmp_var ] 24 | 38 * fp (r31) --> [ ebpf stack space ] upto 512 | 39 * [ frame header ] 32/112 | 40 * sp (r1) ---> [ stack pointer ] -------------- 41 * 42 * Additional (12 * 8) in 'nv gpr save area' only in case of 43 * exception boundary/callback. 44 */ 45 46 /* BPF non-volatile registers save area size */ 47 #define BPF_PPC_STACK_SAVE (6 * 8) 48 49 /* for bpf JIT code internal usage */ 50 #define BPF_PPC_STACK_LOCALS 24 51 /* 52 * for additional non volatile registers(r14-r25) to be saved 53 * at exception boundary 54 */ 55 #define BPF_PPC_EXC_STACK_SAVE (12 * 8) 56 57 /* stack frame excluding BPF stack, ensure this is quadword aligned */ 58 #define BPF_PPC_STACKFRAME (STACK_FRAME_MIN_SIZE + \ 59 BPF_PPC_STACK_LOCALS + \ 60 BPF_PPC_STACK_SAVE + \ 61 BPF_PPC_TAILCALL) 62 63 /* 64 * same as BPF_PPC_STACKFRAME with save area for additional 65 * non volatile registers saved at exception boundary. 66 * This is quad-word aligned. 67 */ 68 #define BPF_PPC_EXC_STACKFRAME (BPF_PPC_STACKFRAME + BPF_PPC_EXC_STACK_SAVE) 69 70 /* BPF register usage */ 71 #define TMP_REG_1 (MAX_BPF_JIT_REG + 0) 72 #define TMP_REG_2 (MAX_BPF_JIT_REG + 1) 73 #define ARENA_VM_START (MAX_BPF_JIT_REG + 2) 74 75 /* BPF to ppc register mappings */ 76 void bpf_jit_init_reg_mapping(struct codegen_context *ctx) 77 { 78 /* function return value */ 79 ctx->b2p[BPF_REG_0] = _R8; 80 /* function arguments */ 81 ctx->b2p[BPF_REG_1] = _R3; 82 ctx->b2p[BPF_REG_2] = _R4; 83 ctx->b2p[BPF_REG_3] = _R5; 84 ctx->b2p[BPF_REG_4] = _R6; 85 ctx->b2p[BPF_REG_5] = _R7; 86 /* non volatile registers */ 87 ctx->b2p[BPF_REG_6] = _R27; 88 ctx->b2p[BPF_REG_7] = _R28; 89 ctx->b2p[BPF_REG_8] = _R29; 90 ctx->b2p[BPF_REG_9] = _R30; 91 /* frame pointer aka BPF_REG_10 */ 92 ctx->b2p[BPF_REG_FP] = _R31; 93 /* eBPF jit internal registers */ 94 ctx->b2p[BPF_REG_AX] = _R12; 95 ctx->b2p[TMP_REG_1] = _R9; 96 ctx->b2p[TMP_REG_2] = _R10; 97 /* non volatile register for kern_vm_start address */ 98 ctx->b2p[ARENA_VM_START] = _R26; 99 } 100 101 /* PPC NVR range -- update this if we ever use NVRs below r26 */ 102 #define BPF_PPC_NVR_MIN _R26 103 104 static inline bool bpf_has_stack_frame(struct codegen_context *ctx) 105 { 106 /* 107 * We only need a stack frame if: 108 * - we call other functions (kernel helpers), or 109 * - the bpf program uses its stack area 110 * The latter condition is deduced from the usage of BPF_REG_FP 111 * 112 * bpf_throw() leads to exception callback from a BPF (sub)program. 113 * The (sub)program is always marked as SEEN_FUNC, creating a stack 114 * frame. The exception callback uses the frame of the exception 115 * boundary, so the exception boundary program must have a frame. 116 */ 117 return ctx->seen & SEEN_FUNC || 118 bpf_is_seen_register(ctx, bpf_to_ppc(BPF_REG_FP)) || 119 ctx->exception_cb || 120 ctx->exception_boundary; 121 } 122 123 /* 124 * Stack layout with redzone: 125 * When not setting up our own stackframe, the redzone (288 bytes) usage is: 126 * Note: r1 from prev frame. Component offset negative wrt r1. 127 * 128 * [ prev sp ] <------------- 129 * [ ... ] | 130 * sp (r1) ---> [ stack pointer ] -------------- 131 * [ tail_call_info ] 8 132 * [ nv gpr save area ] (6 * 8) 133 * [ addl. nv gpr save area] (12 * 8) <--- exception boundary/callback program 134 * [ local_tmp_var ] 24 135 * [ unused red zone ] 224 136 * 137 * Additional (12 * 8) in 'nv gpr save area' only in case of 138 * exception boundary/callback. 139 */ 140 static int bpf_jit_stack_local(struct codegen_context *ctx) 141 { 142 if (bpf_has_stack_frame(ctx)) { 143 /* Stack layout with frame */ 144 return STACK_FRAME_MIN_SIZE + ctx->stack_size; 145 } else { 146 /* Stack layout with redzone */ 147 return -(BPF_PPC_TAILCALL 148 +BPF_PPC_STACK_SAVE 149 +(ctx->exception_boundary || ctx->exception_cb ? 150 BPF_PPC_EXC_STACK_SAVE : 0) 151 +BPF_PPC_STACK_LOCALS 152 ); 153 } 154 } 155 156 static int bpf_jit_stack_tailcallinfo_offset(struct codegen_context *ctx) 157 { 158 return bpf_jit_stack_local(ctx) + BPF_PPC_STACK_LOCALS + BPF_PPC_STACK_SAVE; 159 } 160 161 static int bpf_jit_stack_offsetof(struct codegen_context *ctx, int reg) 162 { 163 int min_valid_nvreg = BPF_PPC_NVR_MIN; 164 /* Default frame size for all cases except exception boundary */ 165 int frame_nvr_size = BPF_PPC_STACKFRAME; 166 167 /* Consider all nv regs for handling exceptions */ 168 if (ctx->exception_boundary || ctx->exception_cb) { 169 min_valid_nvreg = _R14; 170 frame_nvr_size = BPF_PPC_EXC_STACKFRAME; 171 } 172 173 if (reg >= min_valid_nvreg && reg < 32) 174 return (bpf_has_stack_frame(ctx) ? 175 (frame_nvr_size + ctx->stack_size) : 0) 176 - (8 * (32 - reg)) - BPF_PPC_TAILCALL; 177 178 pr_err("BPF JIT is asking about unknown registers"); 179 BUG(); 180 } 181 182 void prepare_for_fsession_fentry(u32 *image, struct codegen_context *ctx, int cookie_cnt, 183 int cookie_off, int retval_off) 184 { 185 EMIT(PPC_RAW_LI(bpf_to_ppc(TMP_REG_1), 0)); 186 187 for (int i = 0; i < cookie_cnt; i++) 188 EMIT(PPC_RAW_STD(bpf_to_ppc(TMP_REG_1), _R1, cookie_off + 8 * i)); 189 EMIT(PPC_RAW_STD(bpf_to_ppc(TMP_REG_1), _R1, retval_off)); 190 } 191 192 void store_func_meta(u32 *image, struct codegen_context *ctx, 193 u64 func_meta, int func_meta_off) 194 { 195 /* 196 * Store func_meta to stack at [R1 + func_meta_off] = func_meta 197 * 198 * func_meta : 199 * bit[63]: is_return flag 200 * byte[1]: cookie offset from ctx 201 * byte[0]: args count 202 */ 203 PPC_LI64(bpf_to_ppc(TMP_REG_1), func_meta); 204 EMIT(PPC_RAW_STD(bpf_to_ppc(TMP_REG_1), _R1, func_meta_off)); 205 } 206 207 void bpf_jit_realloc_regs(struct codegen_context *ctx) 208 { 209 } 210 211 static void emit_fp_priv_stack(u32 *image, struct codegen_context *ctx) 212 { 213 PPC_LI64(bpf_to_ppc(BPF_REG_FP), (__force long)ctx->priv_sp); 214 /* 215 * Load base percpu pointer of private stack allocation. 216 * Runtime per-cpu address = (base + data_offset) + (guard + stack_size) 217 */ 218 #ifdef CONFIG_SMP 219 /* Load percpu data offset */ 220 EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_1), _R13, 221 offsetof(struct paca_struct, data_offset))); 222 EMIT(PPC_RAW_ADD(bpf_to_ppc(BPF_REG_FP), 223 bpf_to_ppc(TMP_REG_1), bpf_to_ppc(BPF_REG_FP))); 224 #endif 225 EMIT(PPC_RAW_ADDI(bpf_to_ppc(BPF_REG_FP), bpf_to_ppc(BPF_REG_FP), 226 PRIV_STACK_GUARD_SZ + round_up(ctx->priv_stack_size, 16))); 227 } 228 229 /* 230 * For exception boundary & exception_cb progs: 231 * return increased size to accommodate additional NVRs. 232 */ 233 static int bpf_jit_stack_size(struct codegen_context *ctx) 234 { 235 return ctx->exception_boundary || ctx->exception_cb ? 236 BPF_PPC_EXC_STACKFRAME : 237 BPF_PPC_STACKFRAME; 238 } 239 240 void bpf_jit_build_prologue(u32 *image, struct codegen_context *ctx) 241 { 242 int i; 243 244 /* Instruction for trampoline attach */ 245 EMIT(PPC_RAW_NOP()); 246 247 #ifndef CONFIG_PPC_KERNEL_PCREL 248 if (IS_ENABLED(CONFIG_PPC64_ELF_ABI_V2)) 249 EMIT(PPC_RAW_LD(_R2, _R13, offsetof(struct paca_struct, kernel_toc))); 250 #endif 251 252 /* 253 * Tail call count(tcc) is saved & updated only in main 254 * program's frame and the address of tcc in main program's 255 * frame (tcc_ptr) is saved in subprogs frame. 256 * 257 * Offset of tail_call_info on any frame will be interpreted 258 * as either tcc_ptr or tcc value depending on whether it is 259 * greater than MAX_TAIL_CALL_CNT or not. 260 */ 261 if (!ctx->is_subprog) { 262 EMIT(PPC_RAW_LI(bpf_to_ppc(TMP_REG_1), 0)); 263 /* this goes in the redzone */ 264 EMIT(PPC_RAW_STD(bpf_to_ppc(TMP_REG_1), _R1, -(BPF_PPC_TAILCALL))); 265 } else if (!ctx->exception_cb) { 266 /* 267 * Tailcall jitting for non exception_cb progs only. 268 * exception_cb won't require tail_call_info to be setup. 269 * 270 * tail_call_info interpretation logic: 271 * 272 * if tail_call_info < MAX_TAIL_CALL_CNT 273 * main prog calling first subprog -> copy reference 274 * else 275 * subsequent subprog calling another subprog -> directly copy content 276 */ 277 EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_2), _R1, 0)); 278 EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_2), -(BPF_PPC_TAILCALL))); 279 EMIT(PPC_RAW_CMPLWI(bpf_to_ppc(TMP_REG_1), MAX_TAIL_CALL_CNT)); 280 PPC_BCC_CONST_SHORT(COND_GT, 8); 281 EMIT(PPC_RAW_ADDI(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_2), 282 -(BPF_PPC_TAILCALL))); 283 EMIT(PPC_RAW_STD(bpf_to_ppc(TMP_REG_1), _R1, -(BPF_PPC_TAILCALL))); 284 } 285 286 if (bpf_has_stack_frame(ctx) && !ctx->exception_cb) { 287 /* 288 * We need a stack frame, but we don't necessarily need to 289 * save/restore LR unless we call other functions 290 */ 291 if (ctx->seen & SEEN_FUNC) { 292 EMIT(PPC_RAW_MFLR(_R0)); 293 EMIT(PPC_RAW_STD(_R0, _R1, PPC_LR_STKOFF)); 294 } 295 296 EMIT(PPC_RAW_STDU(_R1, _R1, 297 -(bpf_jit_stack_size(ctx) + ctx->stack_size))); 298 } 299 300 /* 301 * Program acting as exception boundary pushes R14..R25 in addition to 302 * BPF callee-saved non volatile registers. Exception callback uses 303 * the boundary program's stack frame, recover additionally saved 304 * registers in epilogue of exception callback. 305 */ 306 if (ctx->exception_boundary) { 307 for (i = _R14; i <= _R25; i++) 308 EMIT(PPC_RAW_STD(i, _R1, bpf_jit_stack_offsetof(ctx, i))); 309 } 310 311 if (!ctx->exception_cb) { 312 /* 313 * Back up non-volatile regs -- BPF registers 6-10 314 * If we haven't created our own stack frame, we save these 315 * in the protected zone below the previous stack frame 316 */ 317 for (i = BPF_REG_6; i <= BPF_REG_10; i++) 318 if (ctx->exception_boundary || bpf_is_seen_register(ctx, bpf_to_ppc(i))) 319 EMIT(PPC_RAW_STD(bpf_to_ppc(i), _R1, 320 bpf_jit_stack_offsetof(ctx, bpf_to_ppc(i)))); 321 322 if (ctx->exception_boundary || ctx->arena_vm_start) 323 EMIT(PPC_RAW_STD(bpf_to_ppc(ARENA_VM_START), _R1, 324 bpf_jit_stack_offsetof(ctx, bpf_to_ppc(ARENA_VM_START)))); 325 } else { 326 /* 327 * Exception callback receives Frame Pointer of boundary 328 * program(main prog) as third arg 329 */ 330 EMIT(PPC_RAW_MR(_R1, _R5)); 331 /* 332 * Exception callback reuses the stack frame of exception boundary. 333 * But BPF stack depth of exception callback and exception boundary 334 * don't have to be same. If BPF stack depth is different, adjust the 335 * stack frame size considering BPF stack depth of exception callback. 336 * The non-volatile register save area remains unchanged. These non- 337 * volatile registers are restored in exception callback's epilogue. 338 */ 339 EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_1), _R5, 0)); 340 EMIT(PPC_RAW_SUB(bpf_to_ppc(TMP_REG_2), bpf_to_ppc(TMP_REG_1), _R1)); 341 EMIT(PPC_RAW_ADDI(bpf_to_ppc(TMP_REG_2), bpf_to_ppc(TMP_REG_2), 342 -BPF_PPC_EXC_STACKFRAME)); 343 EMIT(PPC_RAW_CMPLDI(bpf_to_ppc(TMP_REG_2), ctx->stack_size)); 344 PPC_BCC_CONST_SHORT(COND_EQ, 12); 345 EMIT(PPC_RAW_MR(_R1, bpf_to_ppc(TMP_REG_1))); 346 EMIT(PPC_RAW_STDU(_R1, _R1, -(BPF_PPC_EXC_STACKFRAME + ctx->stack_size))); 347 } 348 349 /* 350 * Exception_cb not restricted from using stack area or arena. 351 * Setup frame pointer to point to the bpf stack area 352 */ 353 if (bpf_is_seen_register(ctx, bpf_to_ppc(BPF_REG_FP))) { 354 if (ctx->priv_sp) { 355 /* Set up fp in private stack */ 356 emit_fp_priv_stack(image, ctx); 357 } else { 358 /* Setup frame pointer to point to the bpf stack area */ 359 EMIT(PPC_RAW_ADDI(bpf_to_ppc(BPF_REG_FP), _R1, 360 STACK_FRAME_MIN_SIZE + ctx->stack_size)); 361 } 362 } 363 364 if (ctx->arena_vm_start) 365 PPC_LI64(bpf_to_ppc(ARENA_VM_START), ctx->arena_vm_start); 366 } 367 368 static void bpf_jit_emit_common_epilogue(u32 *image, struct codegen_context *ctx) 369 { 370 int i; 371 372 /* Restore NVRs */ 373 for (i = BPF_REG_6; i <= BPF_REG_10; i++) 374 if (ctx->exception_cb || bpf_is_seen_register(ctx, bpf_to_ppc(i))) 375 EMIT(PPC_RAW_LD(bpf_to_ppc(i), _R1, bpf_jit_stack_offsetof(ctx, bpf_to_ppc(i)))); 376 377 if (ctx->exception_cb || ctx->arena_vm_start) 378 EMIT(PPC_RAW_LD(bpf_to_ppc(ARENA_VM_START), _R1, 379 bpf_jit_stack_offsetof(ctx, bpf_to_ppc(ARENA_VM_START)))); 380 381 if (ctx->exception_cb) { 382 /* 383 * Recover additionally saved non volatile registers from stack 384 * frame of exception boundary program. 385 */ 386 for (i = _R14; i <= _R25; i++) 387 EMIT(PPC_RAW_LD(i, _R1, bpf_jit_stack_offsetof(ctx, i))); 388 } 389 390 /* Tear down our stack frame */ 391 if (bpf_has_stack_frame(ctx)) { 392 EMIT(PPC_RAW_ADDI(_R1, _R1, bpf_jit_stack_size(ctx) + ctx->stack_size)); 393 394 if (ctx->seen & SEEN_FUNC || ctx->exception_cb) { 395 EMIT(PPC_RAW_LD(_R0, _R1, PPC_LR_STKOFF)); 396 EMIT(PPC_RAW_MTLR(_R0)); 397 } 398 } 399 } 400 401 void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx) 402 { 403 bpf_jit_emit_common_epilogue(image, ctx); 404 405 /* Move result to r3 */ 406 EMIT(PPC_RAW_MR(_R3, bpf_to_ppc(BPF_REG_0))); 407 408 EMIT(PPC_RAW_BLR()); 409 410 bpf_jit_build_fentry_stubs(image, ctx); 411 } 412 413 /* 414 * arch_bpf_stack_walk() - BPF stack walker for PowerPC 415 * 416 * Based on arch_stack_walk() from stacktrace.c. 417 * PowerPC uses stack frames rather than stack pointers. See [1] for 418 * the equivalence between frame pointers and stack pointers. 419 * Additional reference at [2]. 420 * TODO: refactor with arch_stack_walk() 421 * 422 * [1]: https://lore.kernel.org/all/20200220115141.2707-1-mpe@ellerman.id.au/ 423 * [2]: https://lore.kernel.org/bpf/20260122211854.5508-5-adubey@linux.ibm.com/ 424 */ 425 426 void arch_bpf_stack_walk(bool (*consume_fn)(void *, u64, u64, u64), void *cookie) 427 { 428 // callback processing always in current context 429 unsigned long sp = current_stack_frame(); 430 431 for (;;) { 432 unsigned long *stack = (unsigned long *) sp; 433 unsigned long ip; 434 435 if (!validate_sp(sp, current)) 436 return; 437 438 ip = stack[STACK_FRAME_LR_SAVE]; 439 if (!ip) 440 break; 441 442 /* 443 * consume_fn common code expects stack pointer in third 444 * argument. There is no sp in ppc64, rather pass frame 445 * pointer(named sp here). 446 */ 447 if (ip && !consume_fn(cookie, ip, sp, sp)) 448 break; 449 450 sp = stack[0]; 451 } 452 } 453 454 static int bpf_jit_emit_func_call(u32 *image, struct codegen_context *ctx, u64 func_addr, int reg) 455 { 456 long reladdr = func_addr - kernel_toc_addr(); 457 458 if (reladdr > 0x7FFFFFFF || reladdr < -(0x80000000L)) { 459 pr_err("eBPF: address of %ps out of range of kernel_toc.\n", (void *)func_addr); 460 return -ERANGE; 461 } 462 463 EMIT(PPC_RAW_ADDIS(reg, _R2, PPC_HA(reladdr))); 464 EMIT(PPC_RAW_ADDI(reg, reg, PPC_LO(reladdr))); 465 EMIT(PPC_RAW_MTCTR(reg)); 466 EMIT(PPC_RAW_BCTRL()); 467 468 return 0; 469 } 470 471 int bpf_jit_emit_func_call_rel(u32 *image, u32 *fimage, struct codegen_context *ctx, u64 func) 472 { 473 unsigned long func_addr = func ? ppc_function_entry((void *)func) : 0; 474 long __maybe_unused reladdr; 475 int ret; 476 477 /* bpf to bpf call, func is not known in the initial pass. Emit 5 nops as a placeholder */ 478 if (!func) { 479 for (int i = 0; i < 5; i++) 480 EMIT(PPC_RAW_NOP()); 481 /* elfv1 needs an additional instruction to load addr from descriptor */ 482 if (IS_ENABLED(CONFIG_PPC64_ELF_ABI_V1)) 483 EMIT(PPC_RAW_NOP()); 484 EMIT(PPC_RAW_MTCTR(_R12)); 485 EMIT(PPC_RAW_BCTRL()); 486 return 0; 487 } 488 489 #ifdef CONFIG_PPC_KERNEL_PCREL 490 reladdr = func_addr - local_paca->kernelbase; 491 492 /* 493 * If fimage is NULL (the initial pass to find image size), 494 * account for the maximum no. of instructions possible. 495 */ 496 if (!fimage) { 497 ctx->idx += 7; 498 return 0; 499 } else if (reladdr < (long)SZ_8G && reladdr >= -(long)SZ_8G) { 500 EMIT(PPC_RAW_LD(_R12, _R13, offsetof(struct paca_struct, kernelbase))); 501 /* Align for subsequent prefix instruction */ 502 if (!IS_ALIGNED((unsigned long)fimage + CTX_NIA(ctx), 8)) 503 EMIT(PPC_RAW_NOP()); 504 /* paddi r12,r12,addr */ 505 EMIT(PPC_PREFIX_MLS | __PPC_PRFX_R(0) | IMM_H18(reladdr)); 506 EMIT(PPC_INST_PADDI | ___PPC_RT(_R12) | ___PPC_RA(_R12) | IMM_L(reladdr)); 507 } else { 508 unsigned long pc = (unsigned long)fimage + CTX_NIA(ctx); 509 bool alignment_needed = !IS_ALIGNED(pc, 8); 510 511 reladdr = func_addr - (alignment_needed ? pc + 4 : pc); 512 513 if (reladdr < (long)SZ_8G && reladdr >= -(long)SZ_8G) { 514 if (alignment_needed) 515 EMIT(PPC_RAW_NOP()); 516 /* pla r12,addr */ 517 EMIT(PPC_PREFIX_MLS | __PPC_PRFX_R(1) | IMM_H18(reladdr)); 518 EMIT(PPC_INST_PADDI | ___PPC_RT(_R12) | IMM_L(reladdr)); 519 } else { 520 /* We can clobber r12 */ 521 PPC_LI64(_R12, func); 522 } 523 } 524 EMIT(PPC_RAW_MTCTR(_R12)); 525 EMIT(PPC_RAW_BCTRL()); 526 #else 527 if (core_kernel_text(func_addr)) { 528 ret = bpf_jit_emit_func_call(image, ctx, func_addr, _R12); 529 if (ret) 530 return ret; 531 } else { 532 if (IS_ENABLED(CONFIG_PPC64_ELF_ABI_V1)) { 533 /* func points to the function descriptor */ 534 PPC_LI64(bpf_to_ppc(TMP_REG_2), func); 535 /* Load actual entry point from function descriptor */ 536 EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_2), 0)); 537 /* ... and move it to CTR */ 538 EMIT(PPC_RAW_MTCTR(bpf_to_ppc(TMP_REG_1))); 539 /* 540 * Load TOC from function descriptor at offset 8. 541 * We can clobber r2 since we get called through a 542 * function pointer (so caller will save/restore r2). 543 */ 544 if (is_module_text_address(func_addr)) 545 EMIT(PPC_RAW_LD(_R2, bpf_to_ppc(TMP_REG_2), 8)); 546 } else { 547 PPC_LI64(_R12, func); 548 EMIT(PPC_RAW_MTCTR(_R12)); 549 } 550 EMIT(PPC_RAW_BCTRL()); 551 /* 552 * Load r2 with kernel TOC as kernel TOC is used if function address falls 553 * within core kernel text. 554 */ 555 if (is_module_text_address(func_addr)) 556 EMIT(PPC_RAW_LD(_R2, _R13, offsetof(struct paca_struct, kernel_toc))); 557 } 558 #endif 559 560 return 0; 561 } 562 563 static int zero_extend(u32 *image, struct codegen_context *ctx, u32 src_reg, u32 dst_reg, u32 size) 564 { 565 switch (size) { 566 case 1: 567 /* zero-extend 8 bits into 64 bits */ 568 EMIT(PPC_RAW_RLDICL(dst_reg, src_reg, 0, 56)); 569 return 0; 570 case 2: 571 /* zero-extend 16 bits into 64 bits */ 572 EMIT(PPC_RAW_RLDICL(dst_reg, src_reg, 0, 48)); 573 return 0; 574 case 4: 575 /* zero-extend 32 bits into 64 bits */ 576 EMIT(PPC_RAW_RLDICL(dst_reg, src_reg, 0, 32)); 577 fallthrough; 578 case 8: 579 /* Nothing to do */ 580 return 0; 581 default: 582 return -1; 583 } 584 } 585 586 static int sign_extend(u32 *image, struct codegen_context *ctx, u32 src_reg, u32 dst_reg, u32 size) 587 { 588 switch (size) { 589 case 1: 590 /* sign-extend 8 bits into 64 bits */ 591 EMIT(PPC_RAW_EXTSB(dst_reg, src_reg)); 592 return 0; 593 case 2: 594 /* sign-extend 16 bits into 64 bits */ 595 EMIT(PPC_RAW_EXTSH(dst_reg, src_reg)); 596 return 0; 597 case 4: 598 /* sign-extend 32 bits into 64 bits */ 599 EMIT(PPC_RAW_EXTSW(dst_reg, src_reg)); 600 fallthrough; 601 case 8: 602 /* Nothing to do */ 603 return 0; 604 default: 605 return -1; 606 } 607 } 608 609 /* 610 * Handle powerpc ABI expectations from caller: 611 * - Unsigned arguments are zero-extended. 612 * - Signed arguments are sign-extended. 613 */ 614 static int prepare_for_kfunc_call(const struct bpf_prog *fp, u32 *image, 615 struct codegen_context *ctx, 616 const struct bpf_insn *insn) 617 { 618 const struct btf_func_model *m = bpf_jit_find_kfunc_model(fp, insn); 619 int i; 620 621 if (!m) 622 return -1; 623 624 for (i = 0; i < m->nr_args; i++) { 625 /* Note that BPF ABI only allows up to 5 args for kfuncs */ 626 u32 reg = bpf_to_ppc(BPF_REG_1 + i), size = m->arg_size[i]; 627 628 if (!(m->arg_flags[i] & BTF_FMODEL_SIGNED_ARG)) { 629 if (zero_extend(image, ctx, reg, reg, size)) 630 return -1; 631 } else { 632 if (sign_extend(image, ctx, reg, reg, size)) 633 return -1; 634 } 635 } 636 637 return 0; 638 } 639 640 static int bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32 out) 641 { 642 /* 643 * By now, the eBPF program has already setup parameters in r3, r4 and r5 644 * r3/BPF_REG_1 - pointer to ctx -- passed as is to the next bpf program 645 * r4/BPF_REG_2 - pointer to bpf_array 646 * r5/BPF_REG_3 - index in bpf_array 647 */ 648 int b2p_bpf_array = bpf_to_ppc(BPF_REG_2); 649 int b2p_index = bpf_to_ppc(BPF_REG_3); 650 int bpf_tailcall_prologue_size = 12; 651 652 if (!IS_ENABLED(CONFIG_PPC_KERNEL_PCREL) && IS_ENABLED(CONFIG_PPC64_ELF_ABI_V2)) 653 bpf_tailcall_prologue_size += 4; /* skip past the toc load */ 654 655 /* 656 * if (index >= array->map.max_entries) 657 * goto out; 658 */ 659 EMIT(PPC_RAW_LWZ(bpf_to_ppc(TMP_REG_1), b2p_bpf_array, offsetof(struct bpf_array, map.max_entries))); 660 EMIT(PPC_RAW_RLWINM(b2p_index, b2p_index, 0, 0, 31)); 661 EMIT(PPC_RAW_CMPLW(b2p_index, bpf_to_ppc(TMP_REG_1))); 662 PPC_BCC_SHORT(COND_GE, out); 663 664 EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_1), _R1, bpf_jit_stack_tailcallinfo_offset(ctx))); 665 EMIT(PPC_RAW_CMPLWI(bpf_to_ppc(TMP_REG_1), MAX_TAIL_CALL_CNT)); 666 PPC_BCC_CONST_SHORT(COND_LE, 8); 667 668 /* dereference TMP_REG_1 */ 669 EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_1), 0)); 670 671 /* 672 * if (tail_call_info == MAX_TAIL_CALL_CNT) 673 * goto out; 674 */ 675 EMIT(PPC_RAW_CMPLWI(bpf_to_ppc(TMP_REG_1), MAX_TAIL_CALL_CNT)); 676 PPC_BCC_SHORT(COND_EQ, out); 677 678 /* 679 * tail_call_info++; <- Actual value of tcc here 680 * Writeback this updated value only if tailcall succeeds. 681 */ 682 EMIT(PPC_RAW_ADDI(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_1), 1)); 683 684 /* prog = array->ptrs[index]; */ 685 EMIT(PPC_RAW_MULI(bpf_to_ppc(TMP_REG_2), b2p_index, 8)); 686 EMIT(PPC_RAW_ADD(bpf_to_ppc(TMP_REG_2), bpf_to_ppc(TMP_REG_2), b2p_bpf_array)); 687 EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_2), bpf_to_ppc(TMP_REG_2), 688 offsetof(struct bpf_array, ptrs))); 689 690 /* 691 * if (prog == NULL) 692 * goto out; 693 */ 694 EMIT(PPC_RAW_CMPLDI(bpf_to_ppc(TMP_REG_2), 0)); 695 PPC_BCC_SHORT(COND_EQ, out); 696 697 /* goto *(prog->bpf_func + prologue_size); */ 698 EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_2), bpf_to_ppc(TMP_REG_2), 699 offsetof(struct bpf_prog, bpf_func))); 700 EMIT(PPC_RAW_ADDI(bpf_to_ppc(TMP_REG_2), bpf_to_ppc(TMP_REG_2), 701 FUNCTION_DESCR_SIZE + bpf_tailcall_prologue_size)); 702 EMIT(PPC_RAW_MTCTR(bpf_to_ppc(TMP_REG_2))); 703 704 /* 705 * Before writing updated tail_call_info, distinguish if current frame 706 * is storing a reference to tail_call_info or actual tcc value in 707 * tail_call_info. 708 */ 709 EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_2), _R1, bpf_jit_stack_tailcallinfo_offset(ctx))); 710 EMIT(PPC_RAW_CMPLWI(bpf_to_ppc(TMP_REG_2), MAX_TAIL_CALL_CNT)); 711 PPC_BCC_CONST_SHORT(COND_GT, 8); 712 713 /* First get address of tail_call_info */ 714 EMIT(PPC_RAW_ADDI(bpf_to_ppc(TMP_REG_2), _R1, bpf_jit_stack_tailcallinfo_offset(ctx))); 715 /* Writeback updated value to tail_call_info */ 716 EMIT(PPC_RAW_STD(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_2), 0)); 717 718 /* tear down stack, restore NVRs, ... */ 719 bpf_jit_emit_common_epilogue(image, ctx); 720 721 EMIT(PPC_RAW_BCTR()); 722 723 /* out: */ 724 return 0; 725 } 726 727 bool bpf_jit_bypass_spec_v1(void) 728 { 729 #if defined(CONFIG_PPC_E500) || defined(CONFIG_PPC_BOOK3S_64) 730 return !(security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && 731 security_ftr_enabled(SEC_FTR_BNDS_CHK_SPEC_BAR)); 732 #else 733 return true; 734 #endif 735 } 736 737 bool bpf_jit_bypass_spec_v4(void) 738 { 739 return !(security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && 740 security_ftr_enabled(SEC_FTR_STF_BARRIER) && 741 stf_barrier_type_get() != STF_BARRIER_NONE); 742 } 743 744 /* 745 * We spill into the redzone always, even if the bpf program has its own stackframe. 746 * Offsets hardcoded based on BPF_PPC_STACK_SAVE -- see bpf_jit_stack_local() 747 */ 748 void bpf_stf_barrier(void); 749 750 asm ( 751 " .global bpf_stf_barrier ;" 752 " bpf_stf_barrier: ;" 753 " std 21,-80(1) ;" 754 " std 22,-72(1) ;" 755 " sync ;" 756 " ld 21,-80(1) ;" 757 " ld 22,-72(1) ;" 758 " ori 31,31,0 ;" 759 " .rept 14 ;" 760 " b 1f ;" 761 " 1: ;" 762 " .endr ;" 763 " blr ;" 764 ); 765 766 static int bpf_jit_emit_atomic_ops(u32 *image, struct codegen_context *ctx, 767 const struct bpf_insn *insn, u32 *jmp_off, 768 u32 *tmp_idx, u32 *addrp) 769 { 770 u32 tmp1_reg = bpf_to_ppc(TMP_REG_1); 771 u32 tmp2_reg = bpf_to_ppc(TMP_REG_2); 772 u32 size = BPF_SIZE(insn->code); 773 u32 src_reg = bpf_to_ppc(insn->src_reg); 774 u32 dst_reg = bpf_to_ppc(insn->dst_reg); 775 s32 imm = insn->imm; 776 777 u32 save_reg = tmp2_reg; 778 u32 ret_reg = src_reg; 779 u32 fixup_idx; 780 781 /* Get offset into TMP_REG_1 */ 782 EMIT(PPC_RAW_LI(tmp1_reg, insn->off)); 783 /* 784 * Enforce full ordering for operations with BPF_FETCH by emitting a 'sync' 785 * before and after the operation. 786 * 787 * This is a requirement in the Linux Kernel Memory Model. 788 * See __cmpxchg_u64() in asm/cmpxchg.h as an example. 789 */ 790 if ((imm & BPF_FETCH) && IS_ENABLED(CONFIG_SMP)) 791 EMIT(PPC_RAW_SYNC()); 792 793 *tmp_idx = ctx->idx; 794 795 /* load value from memory into TMP_REG_2 */ 796 if (size == BPF_DW) 797 EMIT(PPC_RAW_LDARX(tmp2_reg, tmp1_reg, dst_reg, 0)); 798 else 799 EMIT(PPC_RAW_LWARX(tmp2_reg, tmp1_reg, dst_reg, 0)); 800 /* Save old value in _R0 */ 801 if (imm & BPF_FETCH) 802 EMIT(PPC_RAW_MR(_R0, tmp2_reg)); 803 804 switch (imm) { 805 case BPF_ADD: 806 case BPF_ADD | BPF_FETCH: 807 EMIT(PPC_RAW_ADD(tmp2_reg, tmp2_reg, src_reg)); 808 break; 809 case BPF_AND: 810 case BPF_AND | BPF_FETCH: 811 EMIT(PPC_RAW_AND(tmp2_reg, tmp2_reg, src_reg)); 812 break; 813 case BPF_OR: 814 case BPF_OR | BPF_FETCH: 815 EMIT(PPC_RAW_OR(tmp2_reg, tmp2_reg, src_reg)); 816 break; 817 case BPF_XOR: 818 case BPF_XOR | BPF_FETCH: 819 EMIT(PPC_RAW_XOR(tmp2_reg, tmp2_reg, src_reg)); 820 break; 821 case BPF_CMPXCHG: 822 /* 823 * Return old value in BPF_REG_0 for BPF_CMPXCHG & 824 * in src_reg for other cases. 825 */ 826 ret_reg = bpf_to_ppc(BPF_REG_0); 827 828 /* Compare with old value in BPF_R0 */ 829 if (size == BPF_DW) 830 EMIT(PPC_RAW_CMPD(bpf_to_ppc(BPF_REG_0), tmp2_reg)); 831 else 832 EMIT(PPC_RAW_CMPW(bpf_to_ppc(BPF_REG_0), tmp2_reg)); 833 /* Don't set if different from old value */ 834 PPC_BCC_SHORT(COND_NE, (ctx->idx + 3) * 4); 835 fallthrough; 836 case BPF_XCHG: 837 save_reg = src_reg; 838 break; 839 default: 840 return -EOPNOTSUPP; 841 } 842 843 /* store new value */ 844 if (size == BPF_DW) 845 EMIT(PPC_RAW_STDCX(save_reg, tmp1_reg, dst_reg)); 846 else 847 EMIT(PPC_RAW_STWCX(save_reg, tmp1_reg, dst_reg)); 848 /* we're done if this succeeded */ 849 PPC_BCC_SHORT(COND_NE, *tmp_idx * 4); 850 fixup_idx = ctx->idx; 851 852 if (imm & BPF_FETCH) { 853 /* Emit 'sync' to enforce full ordering */ 854 if (IS_ENABLED(CONFIG_SMP)) 855 EMIT(PPC_RAW_SYNC()); 856 EMIT(PPC_RAW_MR(ret_reg, _R0)); 857 /* 858 * Skip unnecessary zero-extension for 32-bit cmpxchg. 859 * For context, see commit 39491867ace5. 860 */ 861 if (size != BPF_DW && imm == BPF_CMPXCHG && 862 insn_is_zext(insn + 1)) 863 *addrp = ctx->idx * 4; 864 } 865 866 *jmp_off = (fixup_idx - *tmp_idx) * 4; 867 868 return 0; 869 } 870 871 static int bpf_jit_emit_probe_mem_store(struct codegen_context *ctx, u32 src_reg, s16 off, 872 u32 code, u32 *image) 873 { 874 u32 tmp1_reg = bpf_to_ppc(TMP_REG_1); 875 u32 tmp2_reg = bpf_to_ppc(TMP_REG_2); 876 877 switch (BPF_SIZE(code)) { 878 case BPF_B: 879 EMIT(PPC_RAW_STB(src_reg, tmp1_reg, off)); 880 break; 881 case BPF_H: 882 EMIT(PPC_RAW_STH(src_reg, tmp1_reg, off)); 883 break; 884 case BPF_W: 885 EMIT(PPC_RAW_STW(src_reg, tmp1_reg, off)); 886 break; 887 case BPF_DW: 888 if (off % 4) { 889 EMIT(PPC_RAW_LI(tmp2_reg, off)); 890 EMIT(PPC_RAW_STDX(src_reg, tmp1_reg, tmp2_reg)); 891 } else { 892 EMIT(PPC_RAW_STD(src_reg, tmp1_reg, off)); 893 } 894 break; 895 default: 896 return -EINVAL; 897 } 898 return 0; 899 } 900 901 static int emit_atomic_ld_st(const struct bpf_insn insn, struct codegen_context *ctx, u32 *image) 902 { 903 u32 code = insn.code; 904 u32 dst_reg = bpf_to_ppc(insn.dst_reg); 905 u32 src_reg = bpf_to_ppc(insn.src_reg); 906 u32 size = BPF_SIZE(code); 907 u32 tmp1_reg = bpf_to_ppc(TMP_REG_1); 908 u32 tmp2_reg = bpf_to_ppc(TMP_REG_2); 909 s16 off = insn.off; 910 s32 imm = insn.imm; 911 912 switch (imm) { 913 case BPF_LOAD_ACQ: 914 switch (size) { 915 case BPF_B: 916 EMIT(PPC_RAW_LBZ(dst_reg, src_reg, off)); 917 break; 918 case BPF_H: 919 EMIT(PPC_RAW_LHZ(dst_reg, src_reg, off)); 920 break; 921 case BPF_W: 922 EMIT(PPC_RAW_LWZ(dst_reg, src_reg, off)); 923 break; 924 case BPF_DW: 925 if (off % 4) { 926 EMIT(PPC_RAW_LI(tmp1_reg, off)); 927 EMIT(PPC_RAW_LDX(dst_reg, src_reg, tmp1_reg)); 928 } else { 929 EMIT(PPC_RAW_LD(dst_reg, src_reg, off)); 930 } 931 break; 932 } 933 EMIT(PPC_RAW_LWSYNC()); 934 break; 935 case BPF_STORE_REL: 936 EMIT(PPC_RAW_LWSYNC()); 937 switch (size) { 938 case BPF_B: 939 EMIT(PPC_RAW_STB(src_reg, dst_reg, off)); 940 break; 941 case BPF_H: 942 EMIT(PPC_RAW_STH(src_reg, dst_reg, off)); 943 break; 944 case BPF_W: 945 EMIT(PPC_RAW_STW(src_reg, dst_reg, off)); 946 break; 947 case BPF_DW: 948 if (off % 4) { 949 EMIT(PPC_RAW_LI(tmp2_reg, off)); 950 EMIT(PPC_RAW_STDX(src_reg, dst_reg, tmp2_reg)); 951 } else { 952 EMIT(PPC_RAW_STD(src_reg, dst_reg, off)); 953 } 954 break; 955 } 956 break; 957 default: 958 pr_err_ratelimited("unexpected atomic load/store op code %02x\n", 959 imm); 960 return -EINVAL; 961 } 962 963 return 0; 964 } 965 966 /* Assemble the body code between the prologue & epilogue */ 967 int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct codegen_context *ctx, 968 u32 *addrs, int pass, bool extra_pass) 969 { 970 enum stf_barrier_type stf_barrier = stf_barrier_type_get(); 971 bool sync_emitted, ori31_emitted; 972 const struct bpf_insn *insn = fp->insnsi; 973 int flen = fp->len; 974 int i, ret; 975 976 /* Start of epilogue code - will only be valid 2nd pass onwards */ 977 u32 exit_addr = addrs[flen]; 978 979 for (i = 0; i < flen; i++) { 980 u32 code = insn[i].code; 981 u32 dst_reg = bpf_to_ppc(insn[i].dst_reg); 982 u32 src_reg = bpf_to_ppc(insn[i].src_reg); 983 u32 size = BPF_SIZE(code); 984 u32 tmp1_reg = bpf_to_ppc(TMP_REG_1); 985 u32 tmp2_reg = bpf_to_ppc(TMP_REG_2); 986 s16 off = insn[i].off; 987 s32 imm = insn[i].imm; 988 bool func_addr_fixed; 989 u64 func_addr; 990 u64 imm64; 991 u32 true_cond; 992 u32 tmp_idx; 993 u32 jmp_off; 994 995 /* 996 * addrs[] maps a BPF bytecode address into a real offset from 997 * the start of the body code. 998 */ 999 addrs[i] = ctx->idx * 4; 1000 1001 /* 1002 * As an optimization, we note down which non-volatile registers 1003 * are used so that we can only save/restore those in our 1004 * prologue and epilogue. We do this here regardless of whether 1005 * the actual BPF instruction uses src/dst registers or not 1006 * (for instance, BPF_CALL does not use them). The expectation 1007 * is that those instructions will have src_reg/dst_reg set to 1008 * 0. Even otherwise, we just lose some prologue/epilogue 1009 * optimization but everything else should work without 1010 * any issues. 1011 */ 1012 if (dst_reg >= BPF_PPC_NVR_MIN && dst_reg < 32) 1013 bpf_set_seen_register(ctx, dst_reg); 1014 if (src_reg >= BPF_PPC_NVR_MIN && src_reg < 32) 1015 bpf_set_seen_register(ctx, src_reg); 1016 1017 switch (code) { 1018 /* 1019 * Arithmetic operations: ADD/SUB/MUL/DIV/MOD/NEG 1020 */ 1021 case BPF_ALU | BPF_ADD | BPF_X: /* (u32) dst += (u32) src */ 1022 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst += src */ 1023 EMIT(PPC_RAW_ADD(dst_reg, dst_reg, src_reg)); 1024 goto bpf_alu32_trunc; 1025 case BPF_ALU | BPF_SUB | BPF_X: /* (u32) dst -= (u32) src */ 1026 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst -= src */ 1027 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, src_reg)); 1028 goto bpf_alu32_trunc; 1029 case BPF_ALU | BPF_ADD | BPF_K: /* (u32) dst += (u32) imm */ 1030 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst += imm */ 1031 if (!imm) { 1032 goto bpf_alu32_trunc; 1033 } else if (imm >= -32768 && imm < 32768) { 1034 EMIT(PPC_RAW_ADDI(dst_reg, dst_reg, IMM_L(imm))); 1035 } else { 1036 PPC_LI32(tmp1_reg, imm); 1037 EMIT(PPC_RAW_ADD(dst_reg, dst_reg, tmp1_reg)); 1038 } 1039 goto bpf_alu32_trunc; 1040 case BPF_ALU | BPF_SUB | BPF_K: /* (u32) dst -= (u32) imm */ 1041 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst -= imm */ 1042 if (!imm) { 1043 goto bpf_alu32_trunc; 1044 } else if (imm > -32768 && imm <= 32768) { 1045 EMIT(PPC_RAW_ADDI(dst_reg, dst_reg, IMM_L(-imm))); 1046 } else { 1047 PPC_LI32(tmp1_reg, imm); 1048 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg)); 1049 } 1050 goto bpf_alu32_trunc; 1051 case BPF_ALU | BPF_MUL | BPF_X: /* (u32) dst *= (u32) src */ 1052 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst *= src */ 1053 if (BPF_CLASS(code) == BPF_ALU) 1054 EMIT(PPC_RAW_MULW(dst_reg, dst_reg, src_reg)); 1055 else 1056 EMIT(PPC_RAW_MULD(dst_reg, dst_reg, src_reg)); 1057 goto bpf_alu32_trunc; 1058 case BPF_ALU | BPF_MUL | BPF_K: /* (u32) dst *= (u32) imm */ 1059 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst *= imm */ 1060 if (imm >= -32768 && imm < 32768) 1061 EMIT(PPC_RAW_MULI(dst_reg, dst_reg, IMM_L(imm))); 1062 else { 1063 PPC_LI32(tmp1_reg, imm); 1064 if (BPF_CLASS(code) == BPF_ALU) 1065 EMIT(PPC_RAW_MULW(dst_reg, dst_reg, tmp1_reg)); 1066 else 1067 EMIT(PPC_RAW_MULD(dst_reg, dst_reg, tmp1_reg)); 1068 } 1069 goto bpf_alu32_trunc; 1070 case BPF_ALU | BPF_DIV | BPF_X: /* (u32) dst /= (u32) src */ 1071 case BPF_ALU | BPF_MOD | BPF_X: /* (u32) dst %= (u32) src */ 1072 if (BPF_OP(code) == BPF_MOD) { 1073 if (off) 1074 EMIT(PPC_RAW_DIVW(tmp1_reg, dst_reg, src_reg)); 1075 else 1076 EMIT(PPC_RAW_DIVWU(tmp1_reg, dst_reg, src_reg)); 1077 1078 EMIT(PPC_RAW_MULW(tmp1_reg, src_reg, tmp1_reg)); 1079 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg)); 1080 } else 1081 if (off) 1082 EMIT(PPC_RAW_DIVW(dst_reg, dst_reg, src_reg)); 1083 else 1084 EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, src_reg)); 1085 goto bpf_alu32_trunc; 1086 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst /= src */ 1087 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst %= src */ 1088 if (BPF_OP(code) == BPF_MOD) { 1089 if (off) 1090 EMIT(PPC_RAW_DIVD(tmp1_reg, dst_reg, src_reg)); 1091 else 1092 EMIT(PPC_RAW_DIVDU(tmp1_reg, dst_reg, src_reg)); 1093 EMIT(PPC_RAW_MULD(tmp1_reg, src_reg, tmp1_reg)); 1094 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg)); 1095 } else 1096 if (off) 1097 EMIT(PPC_RAW_DIVD(dst_reg, dst_reg, src_reg)); 1098 else 1099 EMIT(PPC_RAW_DIVDU(dst_reg, dst_reg, src_reg)); 1100 break; 1101 case BPF_ALU | BPF_MOD | BPF_K: /* (u32) dst %= (u32) imm */ 1102 case BPF_ALU | BPF_DIV | BPF_K: /* (u32) dst /= (u32) imm */ 1103 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst %= imm */ 1104 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst /= imm */ 1105 if (imm == 0) 1106 return -EINVAL; 1107 if (imm == 1) { 1108 if (BPF_OP(code) == BPF_DIV) { 1109 goto bpf_alu32_trunc; 1110 } else { 1111 EMIT(PPC_RAW_LI(dst_reg, 0)); 1112 break; 1113 } 1114 } 1115 1116 PPC_LI32(tmp1_reg, imm); 1117 switch (BPF_CLASS(code)) { 1118 case BPF_ALU: 1119 if (BPF_OP(code) == BPF_MOD) { 1120 if (off) 1121 EMIT(PPC_RAW_DIVW(tmp2_reg, dst_reg, tmp1_reg)); 1122 else 1123 EMIT(PPC_RAW_DIVWU(tmp2_reg, dst_reg, tmp1_reg)); 1124 EMIT(PPC_RAW_MULW(tmp1_reg, tmp1_reg, tmp2_reg)); 1125 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg)); 1126 } else 1127 if (off) 1128 EMIT(PPC_RAW_DIVW(dst_reg, dst_reg, tmp1_reg)); 1129 else 1130 EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, tmp1_reg)); 1131 break; 1132 case BPF_ALU64: 1133 if (BPF_OP(code) == BPF_MOD) { 1134 if (off) 1135 EMIT(PPC_RAW_DIVD(tmp2_reg, dst_reg, tmp1_reg)); 1136 else 1137 EMIT(PPC_RAW_DIVDU(tmp2_reg, dst_reg, tmp1_reg)); 1138 EMIT(PPC_RAW_MULD(tmp1_reg, tmp1_reg, tmp2_reg)); 1139 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg)); 1140 } else 1141 if (off) 1142 EMIT(PPC_RAW_DIVD(dst_reg, dst_reg, tmp1_reg)); 1143 else 1144 EMIT(PPC_RAW_DIVDU(dst_reg, dst_reg, tmp1_reg)); 1145 break; 1146 } 1147 goto bpf_alu32_trunc; 1148 case BPF_ALU | BPF_NEG: /* (u32) dst = -dst */ 1149 case BPF_ALU64 | BPF_NEG: /* dst = -dst */ 1150 EMIT(PPC_RAW_NEG(dst_reg, dst_reg)); 1151 goto bpf_alu32_trunc; 1152 1153 /* 1154 * Logical operations: AND/OR/XOR/[A]LSH/[A]RSH 1155 */ 1156 case BPF_ALU | BPF_AND | BPF_X: /* (u32) dst = dst & src */ 1157 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */ 1158 EMIT(PPC_RAW_AND(dst_reg, dst_reg, src_reg)); 1159 goto bpf_alu32_trunc; 1160 case BPF_ALU | BPF_AND | BPF_K: /* (u32) dst = dst & imm */ 1161 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */ 1162 if (!IMM_H(imm)) 1163 EMIT(PPC_RAW_ANDI(dst_reg, dst_reg, IMM_L(imm))); 1164 else { 1165 /* Sign-extended */ 1166 PPC_LI32(tmp1_reg, imm); 1167 EMIT(PPC_RAW_AND(dst_reg, dst_reg, tmp1_reg)); 1168 } 1169 goto bpf_alu32_trunc; 1170 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */ 1171 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */ 1172 EMIT(PPC_RAW_OR(dst_reg, dst_reg, src_reg)); 1173 goto bpf_alu32_trunc; 1174 case BPF_ALU | BPF_OR | BPF_K:/* dst = (u32) dst | (u32) imm */ 1175 case BPF_ALU64 | BPF_OR | BPF_K:/* dst = dst | imm */ 1176 if (imm < 0 && BPF_CLASS(code) == BPF_ALU64) { 1177 /* Sign-extended */ 1178 PPC_LI32(tmp1_reg, imm); 1179 EMIT(PPC_RAW_OR(dst_reg, dst_reg, tmp1_reg)); 1180 } else { 1181 if (IMM_L(imm)) 1182 EMIT(PPC_RAW_ORI(dst_reg, dst_reg, IMM_L(imm))); 1183 if (IMM_H(imm)) 1184 EMIT(PPC_RAW_ORIS(dst_reg, dst_reg, IMM_H(imm))); 1185 } 1186 goto bpf_alu32_trunc; 1187 case BPF_ALU | BPF_XOR | BPF_X: /* (u32) dst ^= src */ 1188 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst ^= src */ 1189 EMIT(PPC_RAW_XOR(dst_reg, dst_reg, src_reg)); 1190 goto bpf_alu32_trunc; 1191 case BPF_ALU | BPF_XOR | BPF_K: /* (u32) dst ^= (u32) imm */ 1192 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst ^= imm */ 1193 if (imm < 0 && BPF_CLASS(code) == BPF_ALU64) { 1194 /* Sign-extended */ 1195 PPC_LI32(tmp1_reg, imm); 1196 EMIT(PPC_RAW_XOR(dst_reg, dst_reg, tmp1_reg)); 1197 } else { 1198 if (IMM_L(imm)) 1199 EMIT(PPC_RAW_XORI(dst_reg, dst_reg, IMM_L(imm))); 1200 if (IMM_H(imm)) 1201 EMIT(PPC_RAW_XORIS(dst_reg, dst_reg, IMM_H(imm))); 1202 } 1203 goto bpf_alu32_trunc; 1204 case BPF_ALU | BPF_LSH | BPF_X: /* (u32) dst <<= (u32) src */ 1205 /* slw clears top 32 bits */ 1206 EMIT(PPC_RAW_SLW(dst_reg, dst_reg, src_reg)); 1207 /* skip zero extension move, but set address map. */ 1208 if (insn_is_zext(&insn[i + 1])) 1209 addrs[++i] = ctx->idx * 4; 1210 break; 1211 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst <<= src; */ 1212 EMIT(PPC_RAW_SLD(dst_reg, dst_reg, src_reg)); 1213 break; 1214 case BPF_ALU | BPF_LSH | BPF_K: /* (u32) dst <<== (u32) imm */ 1215 /* with imm 0, we still need to clear top 32 bits */ 1216 EMIT(PPC_RAW_SLWI(dst_reg, dst_reg, imm)); 1217 if (insn_is_zext(&insn[i + 1])) 1218 addrs[++i] = ctx->idx * 4; 1219 break; 1220 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst <<== imm */ 1221 if (imm != 0) 1222 EMIT(PPC_RAW_SLDI(dst_reg, dst_reg, imm)); 1223 break; 1224 case BPF_ALU | BPF_RSH | BPF_X: /* (u32) dst >>= (u32) src */ 1225 EMIT(PPC_RAW_SRW(dst_reg, dst_reg, src_reg)); 1226 if (insn_is_zext(&insn[i + 1])) 1227 addrs[++i] = ctx->idx * 4; 1228 break; 1229 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst >>= src */ 1230 EMIT(PPC_RAW_SRD(dst_reg, dst_reg, src_reg)); 1231 break; 1232 case BPF_ALU | BPF_RSH | BPF_K: /* (u32) dst >>= (u32) imm */ 1233 EMIT(PPC_RAW_SRWI(dst_reg, dst_reg, imm)); 1234 if (insn_is_zext(&insn[i + 1])) 1235 addrs[++i] = ctx->idx * 4; 1236 break; 1237 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst >>= imm */ 1238 if (imm != 0) 1239 EMIT(PPC_RAW_SRDI(dst_reg, dst_reg, imm)); 1240 break; 1241 case BPF_ALU | BPF_ARSH | BPF_X: /* (s32) dst >>= src */ 1242 EMIT(PPC_RAW_SRAW(dst_reg, dst_reg, src_reg)); 1243 goto bpf_alu32_trunc; 1244 case BPF_ALU64 | BPF_ARSH | BPF_X: /* (s64) dst >>= src */ 1245 EMIT(PPC_RAW_SRAD(dst_reg, dst_reg, src_reg)); 1246 break; 1247 case BPF_ALU | BPF_ARSH | BPF_K: /* (s32) dst >>= imm */ 1248 EMIT(PPC_RAW_SRAWI(dst_reg, dst_reg, imm)); 1249 goto bpf_alu32_trunc; 1250 case BPF_ALU64 | BPF_ARSH | BPF_K: /* (s64) dst >>= imm */ 1251 if (imm != 0) 1252 EMIT(PPC_RAW_SRADI(dst_reg, dst_reg, imm)); 1253 break; 1254 1255 /* 1256 * MOV 1257 */ 1258 case BPF_ALU | BPF_MOV | BPF_X: /* (u32) dst = src */ 1259 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */ 1260 1261 if (insn_is_mov_percpu_addr(&insn[i])) { 1262 if (IS_ENABLED(CONFIG_SMP)) { 1263 EMIT(PPC_RAW_LD(tmp1_reg, _R13, offsetof(struct paca_struct, data_offset))); 1264 EMIT(PPC_RAW_ADD(dst_reg, src_reg, tmp1_reg)); 1265 } else if (src_reg != dst_reg) { 1266 EMIT(PPC_RAW_MR(dst_reg, src_reg)); 1267 } 1268 break; 1269 } 1270 1271 if (insn_is_cast_user(&insn[i])) { 1272 EMIT(PPC_RAW_RLDICL_DOT(tmp1_reg, src_reg, 0, 32)); 1273 PPC_LI64(dst_reg, (ctx->user_vm_start & 0xffffffff00000000UL)); 1274 PPC_BCC_SHORT(COND_EQ, (ctx->idx + 2) * 4); 1275 EMIT(PPC_RAW_OR(tmp1_reg, dst_reg, tmp1_reg)); 1276 EMIT(PPC_RAW_MR(dst_reg, tmp1_reg)); 1277 break; 1278 } 1279 1280 if (imm == 1) { 1281 /* special mov32 for zext */ 1282 EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 0, 0, 31)); 1283 break; 1284 } 1285 if (off == 0) { 1286 /* MOV */ 1287 if (dst_reg != src_reg) 1288 EMIT(PPC_RAW_MR(dst_reg, src_reg)); 1289 } else { 1290 /* MOVSX: dst = (s8,s16,s32)src (off = 8,16,32) */ 1291 if (sign_extend(image, ctx, src_reg, dst_reg, off / 8)) 1292 return -1; 1293 } 1294 goto bpf_alu32_trunc; 1295 case BPF_ALU | BPF_MOV | BPF_K: /* (u32) dst = imm */ 1296 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = (s64) imm */ 1297 PPC_LI32(dst_reg, imm); 1298 if (imm < 0) 1299 goto bpf_alu32_trunc; 1300 else if (insn_is_zext(&insn[i + 1])) 1301 addrs[++i] = ctx->idx * 4; 1302 break; 1303 1304 bpf_alu32_trunc: 1305 /* Truncate to 32-bits */ 1306 if (BPF_CLASS(code) == BPF_ALU && !fp->aux->verifier_zext) 1307 EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 0, 0, 31)); 1308 break; 1309 1310 /* 1311 * BPF_FROM_BE/LE 1312 */ 1313 case BPF_ALU | BPF_END | BPF_FROM_LE: 1314 case BPF_ALU | BPF_END | BPF_FROM_BE: 1315 case BPF_ALU64 | BPF_END | BPF_FROM_LE: 1316 #ifdef __BIG_ENDIAN__ 1317 if (BPF_SRC(code) == BPF_FROM_BE) 1318 goto emit_clear; 1319 #else /* !__BIG_ENDIAN__ */ 1320 if (BPF_CLASS(code) == BPF_ALU && BPF_SRC(code) == BPF_FROM_LE) 1321 goto emit_clear; 1322 #endif 1323 switch (imm) { 1324 case 16: 1325 /* Rotate 8 bits left & mask with 0x0000ff00 */ 1326 EMIT(PPC_RAW_RLWINM(tmp1_reg, dst_reg, 8, 16, 23)); 1327 /* Rotate 8 bits right & insert LSB to reg */ 1328 EMIT(PPC_RAW_RLWIMI(tmp1_reg, dst_reg, 24, 24, 31)); 1329 /* Move result back to dst_reg */ 1330 EMIT(PPC_RAW_MR(dst_reg, tmp1_reg)); 1331 break; 1332 case 32: 1333 /* 1334 * Rotate word left by 8 bits: 1335 * 2 bytes are already in their final position 1336 * -- byte 2 and 4 (of bytes 1, 2, 3 and 4) 1337 */ 1338 EMIT(PPC_RAW_RLWINM(tmp1_reg, dst_reg, 8, 0, 31)); 1339 /* Rotate 24 bits and insert byte 1 */ 1340 EMIT(PPC_RAW_RLWIMI(tmp1_reg, dst_reg, 24, 0, 7)); 1341 /* Rotate 24 bits and insert byte 3 */ 1342 EMIT(PPC_RAW_RLWIMI(tmp1_reg, dst_reg, 24, 16, 23)); 1343 EMIT(PPC_RAW_MR(dst_reg, tmp1_reg)); 1344 break; 1345 case 64: 1346 /* Store the value to stack and then use byte-reverse loads */ 1347 EMIT(PPC_RAW_STD(dst_reg, _R1, bpf_jit_stack_local(ctx))); 1348 EMIT(PPC_RAW_ADDI(tmp1_reg, _R1, bpf_jit_stack_local(ctx))); 1349 if (cpu_has_feature(CPU_FTR_ARCH_206)) { 1350 EMIT(PPC_RAW_LDBRX(dst_reg, 0, tmp1_reg)); 1351 } else { 1352 EMIT(PPC_RAW_LWBRX(dst_reg, 0, tmp1_reg)); 1353 if (IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN)) 1354 EMIT(PPC_RAW_SLDI(dst_reg, dst_reg, 32)); 1355 EMIT(PPC_RAW_LI(tmp2_reg, 4)); 1356 EMIT(PPC_RAW_LWBRX(tmp2_reg, tmp2_reg, tmp1_reg)); 1357 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 1358 EMIT(PPC_RAW_SLDI(tmp2_reg, tmp2_reg, 32)); 1359 EMIT(PPC_RAW_OR(dst_reg, dst_reg, tmp2_reg)); 1360 } 1361 break; 1362 } 1363 break; 1364 1365 emit_clear: 1366 switch (imm) { 1367 case 16: 1368 /* zero-extend 16 bits into 64 bits */ 1369 EMIT(PPC_RAW_RLDICL(dst_reg, dst_reg, 0, 48)); 1370 if (insn_is_zext(&insn[i + 1])) 1371 addrs[++i] = ctx->idx * 4; 1372 break; 1373 case 32: 1374 if (!fp->aux->verifier_zext) 1375 /* zero-extend 32 bits into 64 bits */ 1376 EMIT(PPC_RAW_RLDICL(dst_reg, dst_reg, 0, 32)); 1377 break; 1378 case 64: 1379 /* nop */ 1380 break; 1381 } 1382 break; 1383 1384 /* 1385 * BPF_ST NOSPEC (speculation barrier) 1386 * 1387 * The following must act as a barrier against both Spectre v1 1388 * and v4 if we requested both mitigations. Therefore, also emit 1389 * 'isync; sync' on E500 or 'ori31' on BOOK3S_64 in addition to 1390 * the insns needed for a Spectre v4 barrier. 1391 * 1392 * If we requested only !bypass_spec_v1 OR only !bypass_spec_v4, 1393 * we can skip the respective other barrier type as an 1394 * optimization. 1395 */ 1396 case BPF_ST | BPF_NOSPEC: 1397 sync_emitted = false; 1398 ori31_emitted = false; 1399 if (IS_ENABLED(CONFIG_PPC_E500) && 1400 !bpf_jit_bypass_spec_v1()) { 1401 EMIT(PPC_RAW_ISYNC()); 1402 EMIT(PPC_RAW_SYNC()); 1403 sync_emitted = true; 1404 } 1405 if (!bpf_jit_bypass_spec_v4()) { 1406 switch (stf_barrier) { 1407 case STF_BARRIER_EIEIO: 1408 EMIT(PPC_RAW_EIEIO() | 0x02000000); 1409 break; 1410 case STF_BARRIER_SYNC_ORI: 1411 if (!sync_emitted) 1412 EMIT(PPC_RAW_SYNC()); 1413 EMIT(PPC_RAW_LD(tmp1_reg, _R13, 0)); 1414 EMIT(PPC_RAW_ORI(_R31, _R31, 0)); 1415 ori31_emitted = true; 1416 break; 1417 case STF_BARRIER_FALLBACK: 1418 ctx->seen |= SEEN_FUNC; 1419 PPC_LI64(_R12, dereference_kernel_function_descriptor(bpf_stf_barrier)); 1420 EMIT(PPC_RAW_MTCTR(_R12)); 1421 EMIT(PPC_RAW_BCTRL()); 1422 break; 1423 case STF_BARRIER_NONE: 1424 break; 1425 } 1426 } 1427 if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && 1428 !bpf_jit_bypass_spec_v1() && 1429 !ori31_emitted) 1430 EMIT(PPC_RAW_ORI(_R31, _R31, 0)); 1431 break; 1432 1433 /* 1434 * BPF_ST(X) 1435 */ 1436 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src */ 1437 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */ 1438 if (BPF_CLASS(code) == BPF_ST) { 1439 EMIT(PPC_RAW_LI(tmp1_reg, imm)); 1440 src_reg = tmp1_reg; 1441 } 1442 EMIT(PPC_RAW_STB(src_reg, dst_reg, off)); 1443 break; 1444 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */ 1445 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */ 1446 if (BPF_CLASS(code) == BPF_ST) { 1447 EMIT(PPC_RAW_LI(tmp1_reg, imm)); 1448 src_reg = tmp1_reg; 1449 } 1450 EMIT(PPC_RAW_STH(src_reg, dst_reg, off)); 1451 break; 1452 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */ 1453 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */ 1454 if (BPF_CLASS(code) == BPF_ST) { 1455 PPC_LI32(tmp1_reg, imm); 1456 src_reg = tmp1_reg; 1457 } 1458 EMIT(PPC_RAW_STW(src_reg, dst_reg, off)); 1459 break; 1460 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */ 1461 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */ 1462 if (BPF_CLASS(code) == BPF_ST) { 1463 PPC_LI32(tmp1_reg, imm); 1464 src_reg = tmp1_reg; 1465 } 1466 if (off % 4) { 1467 EMIT(PPC_RAW_LI(tmp2_reg, off)); 1468 EMIT(PPC_RAW_STDX(src_reg, dst_reg, tmp2_reg)); 1469 } else { 1470 EMIT(PPC_RAW_STD(src_reg, dst_reg, off)); 1471 } 1472 break; 1473 1474 case BPF_STX | BPF_PROBE_MEM32 | BPF_B: 1475 case BPF_STX | BPF_PROBE_MEM32 | BPF_H: 1476 case BPF_STX | BPF_PROBE_MEM32 | BPF_W: 1477 case BPF_STX | BPF_PROBE_MEM32 | BPF_DW: 1478 1479 EMIT(PPC_RAW_ADD(tmp1_reg, dst_reg, bpf_to_ppc(ARENA_VM_START))); 1480 1481 ret = bpf_jit_emit_probe_mem_store(ctx, src_reg, off, code, image); 1482 if (ret) 1483 return ret; 1484 1485 ret = bpf_add_extable_entry(fp, image, fimage, pass, ctx, 1486 ctx->idx - 1, 4, -1, code); 1487 if (ret) 1488 return ret; 1489 1490 break; 1491 1492 case BPF_ST | BPF_PROBE_MEM32 | BPF_B: 1493 case BPF_ST | BPF_PROBE_MEM32 | BPF_H: 1494 case BPF_ST | BPF_PROBE_MEM32 | BPF_W: 1495 case BPF_ST | BPF_PROBE_MEM32 | BPF_DW: 1496 1497 EMIT(PPC_RAW_ADD(tmp1_reg, dst_reg, bpf_to_ppc(ARENA_VM_START))); 1498 1499 if (BPF_SIZE(code) == BPF_W || BPF_SIZE(code) == BPF_DW) { 1500 PPC_LI32(tmp2_reg, imm); 1501 src_reg = tmp2_reg; 1502 } else { 1503 EMIT(PPC_RAW_LI(tmp2_reg, imm)); 1504 src_reg = tmp2_reg; 1505 } 1506 1507 ret = bpf_jit_emit_probe_mem_store(ctx, src_reg, off, code, image); 1508 if (ret) 1509 return ret; 1510 1511 ret = bpf_add_extable_entry(fp, image, fimage, pass, ctx, 1512 ctx->idx - 1, 4, -1, code); 1513 if (ret) 1514 return ret; 1515 1516 break; 1517 1518 /* 1519 * BPF_STX PROBE_ATOMIC (arena atomic ops) 1520 */ 1521 case BPF_STX | BPF_PROBE_ATOMIC | BPF_W: 1522 case BPF_STX | BPF_PROBE_ATOMIC | BPF_DW: 1523 EMIT(PPC_RAW_ADD(dst_reg, dst_reg, bpf_to_ppc(ARENA_VM_START))); 1524 ret = bpf_jit_emit_atomic_ops(image, ctx, &insn[i], 1525 &jmp_off, &tmp_idx, &addrs[i + 1]); 1526 if (ret) { 1527 if (ret == -EOPNOTSUPP) { 1528 pr_err_ratelimited( 1529 "eBPF filter atomic op code %02x (@%d) unsupported\n", 1530 code, i); 1531 } 1532 return ret; 1533 } 1534 /* LDARX/LWARX should land here on exception. */ 1535 ret = bpf_add_extable_entry(fp, image, fimage, pass, ctx, 1536 tmp_idx, jmp_off, dst_reg, code); 1537 if (ret) 1538 return ret; 1539 1540 /* Retrieve the dst_reg */ 1541 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, bpf_to_ppc(ARENA_VM_START))); 1542 break; 1543 1544 /* 1545 * BPF_STX ATOMIC (atomic ops) 1546 */ 1547 case BPF_STX | BPF_ATOMIC | BPF_B: 1548 case BPF_STX | BPF_ATOMIC | BPF_H: 1549 case BPF_STX | BPF_ATOMIC | BPF_W: 1550 case BPF_STX | BPF_ATOMIC | BPF_DW: 1551 if (bpf_atomic_is_load_store(&insn[i])) { 1552 ret = emit_atomic_ld_st(insn[i], ctx, image); 1553 if (ret) 1554 return ret; 1555 1556 if (size != BPF_DW && insn_is_zext(&insn[i + 1])) 1557 addrs[++i] = ctx->idx * 4; 1558 break; 1559 } else if (size == BPF_B || size == BPF_H) { 1560 pr_err_ratelimited( 1561 "eBPF filter atomic op code %02x (@%d) unsupported\n", 1562 code, i); 1563 return -EOPNOTSUPP; 1564 } 1565 1566 ret = bpf_jit_emit_atomic_ops(image, ctx, &insn[i], 1567 &jmp_off, &tmp_idx, &addrs[i + 1]); 1568 if (ret) { 1569 if (ret == -EOPNOTSUPP) { 1570 pr_err_ratelimited( 1571 "eBPF filter atomic op code %02x (@%d) unsupported\n", 1572 code, i); 1573 } 1574 return ret; 1575 } 1576 break; 1577 1578 /* 1579 * BPF_LDX 1580 */ 1581 /* dst = *(u8 *)(ul) (src + off) */ 1582 case BPF_LDX | BPF_MEM | BPF_B: 1583 case BPF_LDX | BPF_MEMSX | BPF_B: 1584 case BPF_LDX | BPF_PROBE_MEM | BPF_B: 1585 case BPF_LDX | BPF_PROBE_MEMSX | BPF_B: 1586 /* dst = *(u16 *)(ul) (src + off) */ 1587 case BPF_LDX | BPF_MEM | BPF_H: 1588 case BPF_LDX | BPF_MEMSX | BPF_H: 1589 case BPF_LDX | BPF_PROBE_MEM | BPF_H: 1590 case BPF_LDX | BPF_PROBE_MEMSX | BPF_H: 1591 /* dst = *(u32 *)(ul) (src + off) */ 1592 case BPF_LDX | BPF_MEM | BPF_W: 1593 case BPF_LDX | BPF_MEMSX | BPF_W: 1594 case BPF_LDX | BPF_PROBE_MEM | BPF_W: 1595 case BPF_LDX | BPF_PROBE_MEMSX | BPF_W: 1596 /* dst = *(u64 *)(ul) (src + off) */ 1597 case BPF_LDX | BPF_MEM | BPF_DW: 1598 case BPF_LDX | BPF_PROBE_MEM | BPF_DW: 1599 /* 1600 * As PTR_TO_BTF_ID that uses BPF_PROBE_MEM mode could either be a valid 1601 * kernel pointer or NULL but not a userspace address, execute BPF_PROBE_MEM 1602 * load only if addr is kernel address (see is_kernel_addr()), otherwise 1603 * set dst_reg=0 and move on. 1604 */ 1605 if (BPF_MODE(code) == BPF_PROBE_MEM || BPF_MODE(code) == BPF_PROBE_MEMSX) { 1606 EMIT(PPC_RAW_ADDI(tmp1_reg, src_reg, off)); 1607 if (IS_ENABLED(CONFIG_PPC_BOOK3E_64)) 1608 PPC_LI64(tmp2_reg, 0x8000000000000000ul); 1609 else /* BOOK3S_64 */ 1610 PPC_LI64(tmp2_reg, PAGE_OFFSET); 1611 EMIT(PPC_RAW_CMPLD(tmp1_reg, tmp2_reg)); 1612 PPC_BCC_SHORT(COND_GT, (ctx->idx + 3) * 4); 1613 EMIT(PPC_RAW_LI(dst_reg, 0)); 1614 /* 1615 * Check if 'off' is word aligned for BPF_DW, because 1616 * we might generate two instructions. 1617 */ 1618 if ((BPF_SIZE(code) == BPF_DW && (off & 3)) || 1619 (BPF_SIZE(code) == BPF_B && 1620 BPF_MODE(code) == BPF_PROBE_MEMSX) || 1621 (BPF_SIZE(code) == BPF_B && BPF_MODE(code) == BPF_MEMSX)) 1622 PPC_JMP((ctx->idx + 3) * 4); 1623 else 1624 PPC_JMP((ctx->idx + 2) * 4); 1625 } 1626 1627 if (BPF_MODE(code) == BPF_MEMSX || BPF_MODE(code) == BPF_PROBE_MEMSX) { 1628 switch (size) { 1629 case BPF_B: 1630 EMIT(PPC_RAW_LBZ(dst_reg, src_reg, off)); 1631 EMIT(PPC_RAW_EXTSB(dst_reg, dst_reg)); 1632 break; 1633 case BPF_H: 1634 EMIT(PPC_RAW_LHA(dst_reg, src_reg, off)); 1635 break; 1636 case BPF_W: 1637 EMIT(PPC_RAW_LWA(dst_reg, src_reg, off)); 1638 break; 1639 } 1640 } else { 1641 switch (size) { 1642 case BPF_B: 1643 EMIT(PPC_RAW_LBZ(dst_reg, src_reg, off)); 1644 break; 1645 case BPF_H: 1646 EMIT(PPC_RAW_LHZ(dst_reg, src_reg, off)); 1647 break; 1648 case BPF_W: 1649 EMIT(PPC_RAW_LWZ(dst_reg, src_reg, off)); 1650 break; 1651 case BPF_DW: 1652 if (off % 4) { 1653 EMIT(PPC_RAW_LI(tmp1_reg, off)); 1654 EMIT(PPC_RAW_LDX(dst_reg, src_reg, tmp1_reg)); 1655 } else { 1656 EMIT(PPC_RAW_LD(dst_reg, src_reg, off)); 1657 } 1658 break; 1659 } 1660 } 1661 1662 if (size != BPF_DW && insn_is_zext(&insn[i + 1])) 1663 addrs[++i] = ctx->idx * 4; 1664 1665 if (BPF_MODE(code) == BPF_PROBE_MEM) { 1666 ret = bpf_add_extable_entry(fp, image, fimage, pass, ctx, 1667 ctx->idx - 1, 4, dst_reg, code); 1668 if (ret) 1669 return ret; 1670 } 1671 break; 1672 1673 /* dst = *(u64 *)(ul) (src + ARENA_VM_START + off) */ 1674 case BPF_LDX | BPF_PROBE_MEM32 | BPF_B: 1675 case BPF_LDX | BPF_PROBE_MEM32 | BPF_H: 1676 case BPF_LDX | BPF_PROBE_MEM32 | BPF_W: 1677 case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW: 1678 1679 EMIT(PPC_RAW_ADD(tmp1_reg, src_reg, bpf_to_ppc(ARENA_VM_START))); 1680 1681 switch (size) { 1682 case BPF_B: 1683 EMIT(PPC_RAW_LBZ(dst_reg, tmp1_reg, off)); 1684 break; 1685 case BPF_H: 1686 EMIT(PPC_RAW_LHZ(dst_reg, tmp1_reg, off)); 1687 break; 1688 case BPF_W: 1689 EMIT(PPC_RAW_LWZ(dst_reg, tmp1_reg, off)); 1690 break; 1691 case BPF_DW: 1692 if (off % 4) { 1693 EMIT(PPC_RAW_LI(tmp2_reg, off)); 1694 EMIT(PPC_RAW_LDX(dst_reg, tmp1_reg, tmp2_reg)); 1695 } else { 1696 EMIT(PPC_RAW_LD(dst_reg, tmp1_reg, off)); 1697 } 1698 break; 1699 } 1700 1701 if (size != BPF_DW && insn_is_zext(&insn[i + 1])) 1702 addrs[++i] = ctx->idx * 4; 1703 1704 ret = bpf_add_extable_entry(fp, image, fimage, pass, ctx, 1705 ctx->idx - 1, 4, dst_reg, code); 1706 if (ret) 1707 return ret; 1708 break; 1709 1710 /* 1711 * Doubleword load 1712 * 16 byte instruction that uses two 'struct bpf_insn' 1713 */ 1714 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */ 1715 imm64 = ((u64)(u32) insn[i].imm) | 1716 (((u64)(u32) insn[i+1].imm) << 32); 1717 PPC_LI64(dst_reg, imm64); 1718 /* Adjust for two bpf instructions */ 1719 addrs[++i] = ctx->idx * 4; 1720 break; 1721 1722 /* 1723 * JUMP reg 1724 */ 1725 case BPF_JMP | BPF_JA | BPF_X: 1726 EMIT(PPC_RAW_MTCTR(dst_reg)); 1727 EMIT(PPC_RAW_BCTR()); 1728 break; 1729 1730 /* 1731 * Return/Exit 1732 */ 1733 case BPF_JMP | BPF_EXIT: 1734 /* 1735 * If this isn't the very last instruction, branch to 1736 * the epilogue. If we _are_ the last instruction, 1737 * we'll just fall through to the epilogue. 1738 */ 1739 if (i != flen - 1) { 1740 ret = bpf_jit_emit_exit_insn(image, ctx, tmp1_reg, exit_addr); 1741 if (ret) 1742 return ret; 1743 } 1744 /* else fall through to the epilogue */ 1745 break; 1746 1747 /* 1748 * Call kernel helper or bpf function 1749 */ 1750 case BPF_JMP | BPF_CALL: 1751 ctx->seen |= SEEN_FUNC; 1752 1753 if (src_reg == bpf_to_ppc(BPF_REG_0)) { 1754 if (imm == BPF_FUNC_get_smp_processor_id) { 1755 EMIT(PPC_RAW_LHZ(src_reg, _R13, offsetof(struct paca_struct, paca_index))); 1756 break; 1757 } else if (imm == BPF_FUNC_get_current_task || 1758 imm == BPF_FUNC_get_current_task_btf) { 1759 EMIT(PPC_RAW_LD(src_reg, _R13, offsetof(struct paca_struct, __current))); 1760 break; 1761 } 1762 } 1763 1764 ret = bpf_jit_get_func_addr(fp, &insn[i], extra_pass, 1765 &func_addr, &func_addr_fixed); 1766 if (ret < 0) 1767 return ret; 1768 1769 /* 1770 * Call to arch_bpf_timed_may_goto() is emitted by the 1771 * verifier and called with custom calling convention with 1772 * first argument and return value in BPF_REG_AX (_R12). 1773 * 1774 * The generic helper or bpf function call emission path 1775 * may use the same scratch register as BPF_REG_AX to 1776 * materialize the target address. This would clobber AX 1777 * and break timed may_goto semantics. 1778 * 1779 * Emit a minimal indirect call sequence here using a temp 1780 * register and skip the normal post-call return-value move. 1781 */ 1782 1783 if (func_addr == (u64)arch_bpf_timed_may_goto) { 1784 ret = 0; 1785 if (!IS_ENABLED(CONFIG_PPC_KERNEL_PCREL)) 1786 ret = bpf_jit_emit_func_call(image, ctx, func_addr, 1787 tmp1_reg); 1788 1789 if (ret || IS_ENABLED(CONFIG_PPC_KERNEL_PCREL)) { 1790 PPC_LI_ADDR(tmp1_reg, func_addr); 1791 EMIT(PPC_RAW_MTCTR(tmp1_reg)); 1792 EMIT(PPC_RAW_BCTRL()); 1793 } 1794 1795 break; 1796 } 1797 1798 /* Take care of powerpc ABI requirements before kfunc call */ 1799 if (insn[i].src_reg == BPF_PSEUDO_KFUNC_CALL) { 1800 if (prepare_for_kfunc_call(fp, image, ctx, &insn[i])) 1801 return -1; 1802 } 1803 1804 ret = bpf_jit_emit_func_call_rel(image, fimage, ctx, func_addr); 1805 if (ret) 1806 return ret; 1807 1808 /* move return value from r3 to BPF_REG_0 */ 1809 EMIT(PPC_RAW_MR(bpf_to_ppc(BPF_REG_0), _R3)); 1810 break; 1811 1812 /* 1813 * Jumps and branches 1814 */ 1815 case BPF_JMP | BPF_JA: 1816 PPC_JMP(addrs[i + 1 + off]); 1817 break; 1818 case BPF_JMP32 | BPF_JA: 1819 PPC_JMP(addrs[i + 1 + imm]); 1820 break; 1821 1822 case BPF_JMP | BPF_JGT | BPF_K: 1823 case BPF_JMP | BPF_JGT | BPF_X: 1824 case BPF_JMP | BPF_JSGT | BPF_K: 1825 case BPF_JMP | BPF_JSGT | BPF_X: 1826 case BPF_JMP32 | BPF_JGT | BPF_K: 1827 case BPF_JMP32 | BPF_JGT | BPF_X: 1828 case BPF_JMP32 | BPF_JSGT | BPF_K: 1829 case BPF_JMP32 | BPF_JSGT | BPF_X: 1830 true_cond = COND_GT; 1831 goto cond_branch; 1832 case BPF_JMP | BPF_JLT | BPF_K: 1833 case BPF_JMP | BPF_JLT | BPF_X: 1834 case BPF_JMP | BPF_JSLT | BPF_K: 1835 case BPF_JMP | BPF_JSLT | BPF_X: 1836 case BPF_JMP32 | BPF_JLT | BPF_K: 1837 case BPF_JMP32 | BPF_JLT | BPF_X: 1838 case BPF_JMP32 | BPF_JSLT | BPF_K: 1839 case BPF_JMP32 | BPF_JSLT | BPF_X: 1840 true_cond = COND_LT; 1841 goto cond_branch; 1842 case BPF_JMP | BPF_JGE | BPF_K: 1843 case BPF_JMP | BPF_JGE | BPF_X: 1844 case BPF_JMP | BPF_JSGE | BPF_K: 1845 case BPF_JMP | BPF_JSGE | BPF_X: 1846 case BPF_JMP32 | BPF_JGE | BPF_K: 1847 case BPF_JMP32 | BPF_JGE | BPF_X: 1848 case BPF_JMP32 | BPF_JSGE | BPF_K: 1849 case BPF_JMP32 | BPF_JSGE | BPF_X: 1850 true_cond = COND_GE; 1851 goto cond_branch; 1852 case BPF_JMP | BPF_JLE | BPF_K: 1853 case BPF_JMP | BPF_JLE | BPF_X: 1854 case BPF_JMP | BPF_JSLE | BPF_K: 1855 case BPF_JMP | BPF_JSLE | BPF_X: 1856 case BPF_JMP32 | BPF_JLE | BPF_K: 1857 case BPF_JMP32 | BPF_JLE | BPF_X: 1858 case BPF_JMP32 | BPF_JSLE | BPF_K: 1859 case BPF_JMP32 | BPF_JSLE | BPF_X: 1860 true_cond = COND_LE; 1861 goto cond_branch; 1862 case BPF_JMP | BPF_JEQ | BPF_K: 1863 case BPF_JMP | BPF_JEQ | BPF_X: 1864 case BPF_JMP32 | BPF_JEQ | BPF_K: 1865 case BPF_JMP32 | BPF_JEQ | BPF_X: 1866 true_cond = COND_EQ; 1867 goto cond_branch; 1868 case BPF_JMP | BPF_JNE | BPF_K: 1869 case BPF_JMP | BPF_JNE | BPF_X: 1870 case BPF_JMP32 | BPF_JNE | BPF_K: 1871 case BPF_JMP32 | BPF_JNE | BPF_X: 1872 true_cond = COND_NE; 1873 goto cond_branch; 1874 case BPF_JMP | BPF_JSET | BPF_K: 1875 case BPF_JMP | BPF_JSET | BPF_X: 1876 case BPF_JMP32 | BPF_JSET | BPF_K: 1877 case BPF_JMP32 | BPF_JSET | BPF_X: 1878 true_cond = COND_NE; 1879 /* Fall through */ 1880 1881 cond_branch: 1882 switch (code) { 1883 case BPF_JMP | BPF_JGT | BPF_X: 1884 case BPF_JMP | BPF_JLT | BPF_X: 1885 case BPF_JMP | BPF_JGE | BPF_X: 1886 case BPF_JMP | BPF_JLE | BPF_X: 1887 case BPF_JMP | BPF_JEQ | BPF_X: 1888 case BPF_JMP | BPF_JNE | BPF_X: 1889 case BPF_JMP32 | BPF_JGT | BPF_X: 1890 case BPF_JMP32 | BPF_JLT | BPF_X: 1891 case BPF_JMP32 | BPF_JGE | BPF_X: 1892 case BPF_JMP32 | BPF_JLE | BPF_X: 1893 case BPF_JMP32 | BPF_JEQ | BPF_X: 1894 case BPF_JMP32 | BPF_JNE | BPF_X: 1895 /* unsigned comparison */ 1896 if (BPF_CLASS(code) == BPF_JMP32) 1897 EMIT(PPC_RAW_CMPLW(dst_reg, src_reg)); 1898 else 1899 EMIT(PPC_RAW_CMPLD(dst_reg, src_reg)); 1900 break; 1901 case BPF_JMP | BPF_JSGT | BPF_X: 1902 case BPF_JMP | BPF_JSLT | BPF_X: 1903 case BPF_JMP | BPF_JSGE | BPF_X: 1904 case BPF_JMP | BPF_JSLE | BPF_X: 1905 case BPF_JMP32 | BPF_JSGT | BPF_X: 1906 case BPF_JMP32 | BPF_JSLT | BPF_X: 1907 case BPF_JMP32 | BPF_JSGE | BPF_X: 1908 case BPF_JMP32 | BPF_JSLE | BPF_X: 1909 /* signed comparison */ 1910 if (BPF_CLASS(code) == BPF_JMP32) 1911 EMIT(PPC_RAW_CMPW(dst_reg, src_reg)); 1912 else 1913 EMIT(PPC_RAW_CMPD(dst_reg, src_reg)); 1914 break; 1915 case BPF_JMP | BPF_JSET | BPF_X: 1916 case BPF_JMP32 | BPF_JSET | BPF_X: 1917 if (BPF_CLASS(code) == BPF_JMP) { 1918 EMIT(PPC_RAW_AND_DOT(tmp1_reg, dst_reg, src_reg)); 1919 } else { 1920 EMIT(PPC_RAW_AND(tmp1_reg, dst_reg, src_reg)); 1921 EMIT(PPC_RAW_RLWINM_DOT(tmp1_reg, tmp1_reg, 0, 0, 31)); 1922 } 1923 break; 1924 case BPF_JMP | BPF_JNE | BPF_K: 1925 case BPF_JMP | BPF_JEQ | BPF_K: 1926 case BPF_JMP | BPF_JGT | BPF_K: 1927 case BPF_JMP | BPF_JLT | BPF_K: 1928 case BPF_JMP | BPF_JGE | BPF_K: 1929 case BPF_JMP | BPF_JLE | BPF_K: 1930 case BPF_JMP32 | BPF_JNE | BPF_K: 1931 case BPF_JMP32 | BPF_JEQ | BPF_K: 1932 case BPF_JMP32 | BPF_JGT | BPF_K: 1933 case BPF_JMP32 | BPF_JLT | BPF_K: 1934 case BPF_JMP32 | BPF_JGE | BPF_K: 1935 case BPF_JMP32 | BPF_JLE | BPF_K: 1936 { 1937 bool is_jmp32 = BPF_CLASS(code) == BPF_JMP32; 1938 1939 /* 1940 * Need sign-extended load, so only positive 1941 * values can be used as imm in cmpldi 1942 */ 1943 if (imm >= 0 && imm < 32768) { 1944 if (is_jmp32) 1945 EMIT(PPC_RAW_CMPLWI(dst_reg, imm)); 1946 else 1947 EMIT(PPC_RAW_CMPLDI(dst_reg, imm)); 1948 } else { 1949 /* sign-extending load */ 1950 PPC_LI32(tmp1_reg, imm); 1951 /* ... but unsigned comparison */ 1952 if (is_jmp32) 1953 EMIT(PPC_RAW_CMPLW(dst_reg, tmp1_reg)); 1954 else 1955 EMIT(PPC_RAW_CMPLD(dst_reg, tmp1_reg)); 1956 } 1957 break; 1958 } 1959 case BPF_JMP | BPF_JSGT | BPF_K: 1960 case BPF_JMP | BPF_JSLT | BPF_K: 1961 case BPF_JMP | BPF_JSGE | BPF_K: 1962 case BPF_JMP | BPF_JSLE | BPF_K: 1963 case BPF_JMP32 | BPF_JSGT | BPF_K: 1964 case BPF_JMP32 | BPF_JSLT | BPF_K: 1965 case BPF_JMP32 | BPF_JSGE | BPF_K: 1966 case BPF_JMP32 | BPF_JSLE | BPF_K: 1967 { 1968 bool is_jmp32 = BPF_CLASS(code) == BPF_JMP32; 1969 1970 /* 1971 * signed comparison, so any 16-bit value 1972 * can be used in cmpdi 1973 */ 1974 if (imm >= -32768 && imm < 32768) { 1975 if (is_jmp32) 1976 EMIT(PPC_RAW_CMPWI(dst_reg, imm)); 1977 else 1978 EMIT(PPC_RAW_CMPDI(dst_reg, imm)); 1979 } else { 1980 PPC_LI32(tmp1_reg, imm); 1981 if (is_jmp32) 1982 EMIT(PPC_RAW_CMPW(dst_reg, tmp1_reg)); 1983 else 1984 EMIT(PPC_RAW_CMPD(dst_reg, tmp1_reg)); 1985 } 1986 break; 1987 } 1988 case BPF_JMP | BPF_JSET | BPF_K: 1989 case BPF_JMP32 | BPF_JSET | BPF_K: 1990 /* andi does not sign-extend the immediate */ 1991 if (imm >= 0 && imm < 32768) 1992 /* PPC_ANDI is _only/always_ dot-form */ 1993 EMIT(PPC_RAW_ANDI(tmp1_reg, dst_reg, imm)); 1994 else { 1995 PPC_LI32(tmp1_reg, imm); 1996 if (BPF_CLASS(code) == BPF_JMP) { 1997 EMIT(PPC_RAW_AND_DOT(tmp1_reg, dst_reg, 1998 tmp1_reg)); 1999 } else { 2000 EMIT(PPC_RAW_AND(tmp1_reg, dst_reg, tmp1_reg)); 2001 EMIT(PPC_RAW_RLWINM_DOT(tmp1_reg, tmp1_reg, 2002 0, 0, 31)); 2003 } 2004 } 2005 break; 2006 } 2007 PPC_BCC(true_cond, addrs[i + 1 + off]); 2008 break; 2009 2010 /* 2011 * Tail call 2012 */ 2013 case BPF_JMP | BPF_TAIL_CALL: 2014 ctx->seen |= SEEN_TAILCALL; 2015 ret = bpf_jit_emit_tail_call(image, ctx, addrs[i + 1]); 2016 if (ret < 0) 2017 return ret; 2018 break; 2019 2020 default: 2021 /* 2022 * The filter contains something cruel & unusual. 2023 * We don't handle it, but also there shouldn't be 2024 * anything missing from our list. 2025 */ 2026 pr_err_ratelimited("eBPF filter opcode %04x (@%d) unsupported\n", 2027 code, i); 2028 return -ENOTSUPP; 2029 } 2030 } 2031 2032 /* Set end-of-body-code address for exit. */ 2033 addrs[i] = ctx->idx * 4; 2034 2035 return 0; 2036 } 2037