1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: IB Verbs interpreter 37 */ 38 39 #include <linux/interrupt.h> 40 #include <linux/types.h> 41 #include <linux/pci.h> 42 #include <linux/netdevice.h> 43 #include <linux/if_ether.h> 44 #include <net/addrconf.h> 45 46 #include <rdma/ib_verbs.h> 47 #include <rdma/ib_user_verbs.h> 48 #include <rdma/ib_umem.h> 49 #include <rdma/ib_addr.h> 50 #include <rdma/ib_mad.h> 51 #include <rdma/ib_cache.h> 52 #include <rdma/ib_pma.h> 53 #include <rdma/uverbs_ioctl.h> 54 #include <linux/hashtable.h> 55 56 #include "roce_hsi.h" 57 #include "qplib_res.h" 58 #include "qplib_sp.h" 59 #include "qplib_fp.h" 60 #include "qplib_rcfw.h" 61 62 #include "bnxt_re.h" 63 #include "ib_verbs.h" 64 #include "debugfs.h" 65 66 #include <rdma/uverbs_types.h> 67 #include <rdma/uverbs_std_types.h> 68 69 #include <rdma/ib_user_ioctl_cmds.h> 70 71 #define UVERBS_MODULE_NAME bnxt_re 72 #include <rdma/uverbs_named_ioctl.h> 73 74 #include <rdma/bnxt_re-abi.h> 75 76 static int __from_ib_access_flags(int iflags) 77 { 78 int qflags = 0; 79 80 if (iflags & IB_ACCESS_LOCAL_WRITE) 81 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 82 if (iflags & IB_ACCESS_REMOTE_READ) 83 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ; 84 if (iflags & IB_ACCESS_REMOTE_WRITE) 85 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE; 86 if (iflags & IB_ACCESS_REMOTE_ATOMIC) 87 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC; 88 if (iflags & IB_ACCESS_MW_BIND) 89 qflags |= BNXT_QPLIB_ACCESS_MW_BIND; 90 if (iflags & IB_ZERO_BASED) 91 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED; 92 if (iflags & IB_ACCESS_ON_DEMAND) 93 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND; 94 return qflags; 95 }; 96 97 static int __to_ib_access_flags(int qflags) 98 { 99 int iflags = 0; 100 101 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE) 102 iflags |= IB_ACCESS_LOCAL_WRITE; 103 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE) 104 iflags |= IB_ACCESS_REMOTE_WRITE; 105 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ) 106 iflags |= IB_ACCESS_REMOTE_READ; 107 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC) 108 iflags |= IB_ACCESS_REMOTE_ATOMIC; 109 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND) 110 iflags |= IB_ACCESS_MW_BIND; 111 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED) 112 iflags |= IB_ZERO_BASED; 113 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND) 114 iflags |= IB_ACCESS_ON_DEMAND; 115 return iflags; 116 } 117 118 static u8 __qp_access_flags_from_ib(struct bnxt_qplib_chip_ctx *cctx, int iflags) 119 { 120 u8 qflags = 0; 121 122 if (!bnxt_qplib_is_chip_gen_p5_p7(cctx)) 123 /* For Wh+ */ 124 return (u8)__from_ib_access_flags(iflags); 125 126 /* For P5, P7 and later chips */ 127 if (iflags & IB_ACCESS_LOCAL_WRITE) 128 qflags |= CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE; 129 if (iflags & IB_ACCESS_REMOTE_WRITE) 130 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE; 131 if (iflags & IB_ACCESS_REMOTE_READ) 132 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ; 133 if (iflags & IB_ACCESS_REMOTE_ATOMIC) 134 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC; 135 136 return qflags; 137 } 138 139 static int __qp_access_flags_to_ib(struct bnxt_qplib_chip_ctx *cctx, u8 qflags) 140 { 141 int iflags = 0; 142 143 if (!bnxt_qplib_is_chip_gen_p5_p7(cctx)) 144 /* For Wh+ */ 145 return __to_ib_access_flags(qflags); 146 147 /* For P5, P7 and later chips */ 148 if (qflags & CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE) 149 iflags |= IB_ACCESS_LOCAL_WRITE; 150 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE) 151 iflags |= IB_ACCESS_REMOTE_WRITE; 152 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_READ) 153 iflags |= IB_ACCESS_REMOTE_READ; 154 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC) 155 iflags |= IB_ACCESS_REMOTE_ATOMIC; 156 157 return iflags; 158 } 159 160 static void bnxt_re_check_and_set_relaxed_ordering(struct bnxt_re_dev *rdev, 161 struct bnxt_qplib_mrw *qplib_mr) 162 { 163 if (_is_relaxed_ordering_supported(rdev->dev_attr->dev_cap_flags2) && 164 pcie_relaxed_ordering_enabled(rdev->en_dev->pdev)) 165 qplib_mr->flags |= CMDQ_REGISTER_MR_FLAGS_ENABLE_RO; 166 } 167 168 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list, 169 struct bnxt_qplib_sge *sg_list, int num) 170 { 171 int i, total = 0; 172 173 for (i = 0; i < num; i++) { 174 sg_list[i].addr = ib_sg_list[i].addr; 175 sg_list[i].lkey = ib_sg_list[i].lkey; 176 sg_list[i].size = ib_sg_list[i].length; 177 total += sg_list[i].size; 178 } 179 return total; 180 } 181 182 /* Device */ 183 int bnxt_re_query_device(struct ib_device *ibdev, 184 struct ib_device_attr *ib_attr, 185 struct ib_udata *udata) 186 { 187 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 188 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 189 struct bnxt_re_query_device_ex_resp resp = {}; 190 size_t outlen = (udata) ? udata->outlen : 0; 191 int rc = 0; 192 193 memset(ib_attr, 0, sizeof(*ib_attr)); 194 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver, 195 min(sizeof(dev_attr->fw_ver), 196 sizeof(ib_attr->fw_ver))); 197 addrconf_addr_eui48((u8 *)&ib_attr->sys_image_guid, 198 rdev->netdev->dev_addr); 199 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE; 200 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_SUPPORTED; 201 202 ib_attr->vendor_id = rdev->en_dev->pdev->vendor; 203 ib_attr->vendor_part_id = rdev->en_dev->pdev->device; 204 ib_attr->hw_ver = rdev->en_dev->pdev->revision; 205 ib_attr->max_qp = dev_attr->max_qp; 206 ib_attr->max_qp_wr = dev_attr->max_qp_wqes; 207 ib_attr->device_cap_flags = 208 IB_DEVICE_CURR_QP_STATE_MOD 209 | IB_DEVICE_RC_RNR_NAK_GEN 210 | IB_DEVICE_SHUTDOWN_PORT 211 | IB_DEVICE_SYS_IMAGE_GUID 212 | IB_DEVICE_RESIZE_MAX_WR 213 | IB_DEVICE_PORT_ACTIVE_EVENT 214 | IB_DEVICE_N_NOTIFY_CQ 215 | IB_DEVICE_MEM_WINDOW 216 | IB_DEVICE_MEM_WINDOW_TYPE_2B 217 | IB_DEVICE_MEM_MGT_EXTENSIONS; 218 ib_attr->kernel_cap_flags = IBK_LOCAL_DMA_LKEY; 219 ib_attr->max_send_sge = dev_attr->max_qp_sges; 220 ib_attr->max_recv_sge = dev_attr->max_qp_sges; 221 ib_attr->max_sge_rd = dev_attr->max_qp_sges; 222 ib_attr->max_cq = dev_attr->max_cq; 223 ib_attr->max_cqe = dev_attr->max_cq_wqes; 224 ib_attr->max_mr = dev_attr->max_mr; 225 ib_attr->max_pd = dev_attr->max_pd; 226 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom; 227 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom; 228 ib_attr->atomic_cap = IB_ATOMIC_NONE; 229 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE; 230 if (dev_attr->is_atomic) { 231 ib_attr->atomic_cap = IB_ATOMIC_GLOB; 232 ib_attr->masked_atomic_cap = IB_ATOMIC_GLOB; 233 } 234 235 ib_attr->max_ee_rd_atom = 0; 236 ib_attr->max_res_rd_atom = 0; 237 ib_attr->max_ee_init_rd_atom = 0; 238 ib_attr->max_ee = 0; 239 ib_attr->max_rdd = 0; 240 ib_attr->max_mw = dev_attr->max_mw; 241 ib_attr->max_raw_ipv6_qp = 0; 242 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp; 243 ib_attr->max_mcast_grp = 0; 244 ib_attr->max_mcast_qp_attach = 0; 245 ib_attr->max_total_mcast_qp_attach = 0; 246 ib_attr->max_ah = dev_attr->max_ah; 247 248 ib_attr->max_srq = dev_attr->max_srq; 249 ib_attr->max_srq_wr = dev_attr->max_srq_wqes; 250 ib_attr->max_srq_sge = dev_attr->max_srq_sges; 251 252 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS; 253 254 ib_attr->max_pkeys = 1; 255 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY; 256 257 if ((offsetofend(typeof(resp), packet_pacing_caps) <= outlen) && 258 _is_modify_qp_rate_limit_supported(dev_attr->dev_cap_flags2)) { 259 resp.packet_pacing_caps.qp_rate_limit_min = 260 dev_attr->rate_limit_min; 261 resp.packet_pacing_caps.qp_rate_limit_max = 262 dev_attr->rate_limit_max; 263 resp.packet_pacing_caps.supported_qpts = 264 1 << IB_QPT_RC; 265 } 266 if (outlen) 267 rc = ib_copy_to_udata(udata, &resp, 268 min(sizeof(resp), outlen)); 269 270 return rc; 271 } 272 273 int bnxt_re_modify_device(struct ib_device *ibdev, 274 int device_modify_mask, 275 struct ib_device_modify *device_modify) 276 { 277 ibdev_dbg(ibdev, "Modify device with mask 0x%x", device_modify_mask); 278 279 if (device_modify_mask & ~IB_DEVICE_MODIFY_NODE_DESC) 280 return -EOPNOTSUPP; 281 282 if (!(device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC)) 283 return 0; 284 285 memcpy(ibdev->node_desc, device_modify->node_desc, IB_DEVICE_NODE_DESC_MAX); 286 return 0; 287 } 288 289 /* Port */ 290 int bnxt_re_query_port(struct ib_device *ibdev, u32 port_num, 291 struct ib_port_attr *port_attr) 292 { 293 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 294 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 295 int rc; 296 297 memset(port_attr, 0, sizeof(*port_attr)); 298 299 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) { 300 port_attr->state = IB_PORT_ACTIVE; 301 port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 302 } else { 303 port_attr->state = IB_PORT_DOWN; 304 port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED; 305 } 306 port_attr->max_mtu = IB_MTU_4096; 307 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu); 308 /* One GID is reserved for RawEth QP. Report one less */ 309 port_attr->gid_tbl_len = (rdev->rcfw.roce_mirror ? (dev_attr->max_sgid - 1) : 310 dev_attr->max_sgid); 311 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 312 IB_PORT_DEVICE_MGMT_SUP | 313 IB_PORT_VENDOR_CLASS_SUP; 314 port_attr->ip_gids = true; 315 316 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW; 317 port_attr->bad_pkey_cntr = 0; 318 port_attr->qkey_viol_cntr = 0; 319 port_attr->pkey_tbl_len = dev_attr->max_pkey; 320 port_attr->lid = 0; 321 port_attr->sm_lid = 0; 322 port_attr->lmc = 0; 323 port_attr->max_vl_num = 4; 324 port_attr->sm_sl = 0; 325 port_attr->subnet_timeout = 0; 326 port_attr->init_type_reply = 0; 327 rc = ib_get_eth_speed(&rdev->ibdev, port_num, &port_attr->active_speed, 328 &port_attr->active_width); 329 330 return rc; 331 } 332 333 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u32 port_num, 334 struct ib_port_immutable *immutable) 335 { 336 struct ib_port_attr port_attr; 337 338 if (bnxt_re_query_port(ibdev, port_num, &port_attr)) 339 return -EINVAL; 340 341 immutable->pkey_tbl_len = port_attr.pkey_tbl_len; 342 immutable->gid_tbl_len = port_attr.gid_tbl_len; 343 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 344 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP; 345 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 346 return 0; 347 } 348 349 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str) 350 { 351 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 352 353 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d", 354 rdev->dev_attr->fw_ver[0], rdev->dev_attr->fw_ver[1], 355 rdev->dev_attr->fw_ver[2], rdev->dev_attr->fw_ver[3]); 356 } 357 358 int bnxt_re_query_pkey(struct ib_device *ibdev, u32 port_num, 359 u16 index, u16 *pkey) 360 { 361 if (index > 0) 362 return -EINVAL; 363 364 *pkey = IB_DEFAULT_PKEY_FULL; 365 366 return 0; 367 } 368 369 int bnxt_re_query_gid(struct ib_device *ibdev, u32 port_num, 370 int index, union ib_gid *gid) 371 { 372 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 373 int rc; 374 375 /* Ignore port_num */ 376 memset(gid, 0, sizeof(*gid)); 377 rc = bnxt_qplib_get_sgid(&rdev->qplib_res, 378 &rdev->qplib_res.sgid_tbl, index, 379 (struct bnxt_qplib_gid *)gid); 380 return rc; 381 } 382 383 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context) 384 { 385 int rc = 0; 386 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 387 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 388 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 389 struct bnxt_qplib_gid *gid_to_del; 390 u16 vlan_id = 0xFFFF; 391 392 /* Delete the entry from the hardware */ 393 ctx = *context; 394 if (!ctx) 395 return -EINVAL; 396 397 if (sgid_tbl->active) { 398 if (ctx->idx >= sgid_tbl->max) 399 return -EINVAL; 400 gid_to_del = &sgid_tbl->tbl[ctx->idx].gid; 401 vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id; 402 /* DEL_GID is called in WQ context(netdevice_event_work_handler) 403 * or via the ib_unregister_device path. In the former case QP1 404 * may not be destroyed yet, in which case just return as FW 405 * needs that entry to be present and will fail it's deletion. 406 * We could get invoked again after QP1 is destroyed OR get an 407 * ADD_GID call with a different GID value for the same index 408 * where we issue MODIFY_GID cmd to update the GID entry -- TBD 409 */ 410 if (ctx->idx == 0 && 411 rdma_link_local_addr((struct in6_addr *)gid_to_del) && 412 ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) { 413 ibdev_dbg(&rdev->ibdev, 414 "Trying to delete GID0 while QP1 is alive\n"); 415 return -EFAULT; 416 } 417 ctx->refcnt--; 418 if (!ctx->refcnt) { 419 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del, 420 vlan_id, true); 421 if (rc) { 422 ibdev_err(&rdev->ibdev, 423 "Failed to remove GID: %#x", rc); 424 } else { 425 ctx_tbl = sgid_tbl->ctx; 426 ctx_tbl[ctx->idx] = NULL; 427 kfree(ctx); 428 } 429 } 430 } else { 431 return -EINVAL; 432 } 433 return rc; 434 } 435 436 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context) 437 { 438 int rc; 439 u32 tbl_idx = 0; 440 u16 vlan_id = 0xFFFF; 441 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 442 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 443 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 444 445 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL); 446 if (rc) 447 return rc; 448 449 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid, 450 rdev->qplib_res.netdev->dev_addr, 451 vlan_id, true, &tbl_idx, false, 0); 452 if (rc == -EALREADY) { 453 ctx_tbl = sgid_tbl->ctx; 454 ctx_tbl[tbl_idx]->refcnt++; 455 *context = ctx_tbl[tbl_idx]; 456 return 0; 457 } 458 459 if (rc < 0) { 460 ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc); 461 return rc; 462 } 463 464 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 465 if (!ctx) 466 return -ENOMEM; 467 ctx_tbl = sgid_tbl->ctx; 468 ctx->idx = tbl_idx; 469 ctx->refcnt = 1; 470 ctx_tbl[tbl_idx] = ctx; 471 *context = ctx; 472 473 return rc; 474 } 475 476 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev, 477 u32 port_num) 478 { 479 return IB_LINK_LAYER_ETHERNET; 480 } 481 482 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE) 483 484 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd) 485 { 486 struct bnxt_re_fence_data *fence = &pd->fence; 487 struct ib_mr *ib_mr = &fence->mr->ib_mr; 488 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe; 489 struct bnxt_re_dev *rdev = pd->rdev; 490 491 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 492 return; 493 494 memset(wqe, 0, sizeof(*wqe)); 495 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW; 496 wqe->wr_id = BNXT_QPLIB_FENCE_WRID; 497 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 498 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 499 wqe->bind.zero_based = false; 500 wqe->bind.parent_l_key = ib_mr->lkey; 501 wqe->bind.va = (u64)(unsigned long)fence->va; 502 wqe->bind.length = fence->size; 503 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ); 504 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1; 505 506 /* Save the initial rkey in fence structure for now; 507 * wqe->bind.r_key will be set at (re)bind time. 508 */ 509 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey); 510 } 511 512 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp) 513 { 514 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp, 515 qplib_qp); 516 struct ib_pd *ib_pd = qp->ib_qp.pd; 517 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 518 struct bnxt_re_fence_data *fence = &pd->fence; 519 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe; 520 struct bnxt_qplib_swqe wqe; 521 int rc; 522 523 memcpy(&wqe, fence_wqe, sizeof(wqe)); 524 wqe.bind.r_key = fence->bind_rkey; 525 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey); 526 527 ibdev_dbg(&qp->rdev->ibdev, 528 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n", 529 wqe.bind.r_key, qp->qplib_qp.id, pd); 530 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 531 if (rc) { 532 ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n"); 533 return rc; 534 } 535 bnxt_qplib_post_send_db(&qp->qplib_qp); 536 537 return rc; 538 } 539 540 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd) 541 { 542 struct bnxt_re_fence_data *fence = &pd->fence; 543 struct bnxt_re_dev *rdev = pd->rdev; 544 struct device *dev = &rdev->en_dev->pdev->dev; 545 struct bnxt_re_mr *mr = fence->mr; 546 547 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 548 return; 549 550 if (fence->mw) { 551 bnxt_re_dealloc_mw(fence->mw); 552 fence->mw = NULL; 553 } 554 if (mr) { 555 if (mr->ib_mr.rkey) 556 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr, 557 true); 558 if (mr->ib_mr.lkey) 559 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 560 kfree(mr); 561 fence->mr = NULL; 562 } 563 if (fence->dma_addr) { 564 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES, 565 DMA_BIDIRECTIONAL); 566 fence->dma_addr = 0; 567 } 568 } 569 570 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd) 571 { 572 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND; 573 struct bnxt_re_fence_data *fence = &pd->fence; 574 struct bnxt_re_dev *rdev = pd->rdev; 575 struct device *dev = &rdev->en_dev->pdev->dev; 576 struct bnxt_re_mr *mr = NULL; 577 dma_addr_t dma_addr = 0; 578 struct ib_mw *mw; 579 int rc; 580 581 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 582 return 0; 583 584 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES, 585 DMA_BIDIRECTIONAL); 586 rc = dma_mapping_error(dev, dma_addr); 587 if (rc) { 588 ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n"); 589 rc = -EIO; 590 fence->dma_addr = 0; 591 goto fail; 592 } 593 fence->dma_addr = dma_addr; 594 595 /* Allocate a MR */ 596 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 597 if (!mr) { 598 rc = -ENOMEM; 599 goto fail; 600 } 601 fence->mr = mr; 602 mr->rdev = rdev; 603 mr->qplib_mr.pd = &pd->qplib_pd; 604 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 605 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags); 606 if (!_is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags)) { 607 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 608 if (rc) { 609 ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n"); 610 goto fail; 611 } 612 613 /* Register MR */ 614 mr->ib_mr.lkey = mr->qplib_mr.lkey; 615 } else { 616 mr->qplib_mr.flags = CMDQ_REGISTER_MR_FLAGS_ALLOC_MR; 617 } 618 mr->qplib_mr.va = (u64)(unsigned long)fence->va; 619 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES; 620 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 621 BNXT_RE_FENCE_PBL_SIZE, PAGE_SIZE, 622 _is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags)); 623 if (rc) { 624 ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n"); 625 goto fail; 626 } 627 mr->ib_mr.rkey = mr->qplib_mr.rkey; 628 629 /* Create a fence MW only for kernel consumers */ 630 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL); 631 if (IS_ERR(mw)) { 632 ibdev_err(&rdev->ibdev, 633 "Failed to create fence-MW for PD: %p\n", pd); 634 rc = PTR_ERR(mw); 635 goto fail; 636 } 637 fence->mw = mw; 638 639 bnxt_re_create_fence_wqe(pd); 640 return 0; 641 642 fail: 643 bnxt_re_destroy_fence_mr(pd); 644 return rc; 645 } 646 647 static struct bnxt_re_user_mmap_entry* 648 bnxt_re_mmap_entry_insert(struct bnxt_re_ucontext *uctx, u64 mem_offset, 649 enum bnxt_re_mmap_flag mmap_flag, u64 *offset) 650 { 651 struct bnxt_re_user_mmap_entry *entry; 652 int ret; 653 654 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 655 if (!entry) 656 return NULL; 657 658 entry->mem_offset = mem_offset; 659 entry->mmap_flag = mmap_flag; 660 entry->uctx = uctx; 661 662 switch (mmap_flag) { 663 case BNXT_RE_MMAP_SH_PAGE: 664 ret = rdma_user_mmap_entry_insert_exact(&uctx->ib_uctx, 665 &entry->rdma_entry, PAGE_SIZE, 0); 666 break; 667 case BNXT_RE_MMAP_UC_DB: 668 case BNXT_RE_MMAP_WC_DB: 669 case BNXT_RE_MMAP_DBR_BAR: 670 case BNXT_RE_MMAP_DBR_PAGE: 671 case BNXT_RE_MMAP_TOGGLE_PAGE: 672 ret = rdma_user_mmap_entry_insert(&uctx->ib_uctx, 673 &entry->rdma_entry, PAGE_SIZE); 674 break; 675 default: 676 ret = -EINVAL; 677 break; 678 } 679 680 if (ret) { 681 kfree(entry); 682 return NULL; 683 } 684 if (offset) 685 *offset = rdma_user_mmap_get_offset(&entry->rdma_entry); 686 687 return entry; 688 } 689 690 /* Protection Domains */ 691 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata) 692 { 693 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 694 struct bnxt_re_dev *rdev = pd->rdev; 695 696 if (udata) { 697 rdma_user_mmap_entry_remove(pd->pd_db_mmap); 698 pd->pd_db_mmap = NULL; 699 } 700 701 bnxt_re_destroy_fence_mr(pd); 702 703 if (pd->qplib_pd.id) { 704 if (!bnxt_qplib_dealloc_pd(&rdev->qplib_res, 705 &rdev->qplib_res.pd_tbl, 706 &pd->qplib_pd)) 707 atomic_dec(&rdev->stats.res.pd_count); 708 } 709 return 0; 710 } 711 712 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 713 { 714 struct ib_device *ibdev = ibpd->device; 715 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 716 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context( 717 udata, struct bnxt_re_ucontext, ib_uctx); 718 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd); 719 struct bnxt_re_user_mmap_entry *entry = NULL; 720 u32 active_pds; 721 int rc = 0; 722 723 pd->rdev = rdev; 724 if (bnxt_qplib_alloc_pd(&rdev->qplib_res, &pd->qplib_pd)) { 725 ibdev_err(&rdev->ibdev, "Failed to allocate HW PD"); 726 rc = -ENOMEM; 727 goto fail; 728 } 729 730 if (udata) { 731 struct bnxt_re_pd_resp resp = {}; 732 733 if (!ucntx->dpi.dbr) { 734 /* Allocate DPI in alloc_pd to avoid failing of 735 * ibv_devinfo and family of application when DPIs 736 * are depleted. 737 */ 738 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, 739 &ucntx->dpi, ucntx, BNXT_QPLIB_DPI_TYPE_UC)) { 740 rc = -ENOMEM; 741 goto dbfail; 742 } 743 } 744 745 resp.pdid = pd->qplib_pd.id; 746 /* Still allow mapping this DBR to the new user PD. */ 747 resp.dpi = ucntx->dpi.dpi; 748 749 entry = bnxt_re_mmap_entry_insert(ucntx, (u64)ucntx->dpi.umdbr, 750 BNXT_RE_MMAP_UC_DB, &resp.dbr); 751 752 if (!entry) { 753 rc = -ENOMEM; 754 goto dbfail; 755 } 756 757 pd->pd_db_mmap = &entry->rdma_entry; 758 759 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen)); 760 if (rc) { 761 rdma_user_mmap_entry_remove(pd->pd_db_mmap); 762 rc = -EFAULT; 763 goto dbfail; 764 } 765 } 766 767 if (!udata) 768 if (bnxt_re_create_fence_mr(pd)) 769 ibdev_warn(&rdev->ibdev, 770 "Failed to create Fence-MR\n"); 771 active_pds = atomic_inc_return(&rdev->stats.res.pd_count); 772 if (active_pds > rdev->stats.res.pd_watermark) 773 rdev->stats.res.pd_watermark = active_pds; 774 775 return 0; 776 dbfail: 777 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl, 778 &pd->qplib_pd); 779 fail: 780 return rc; 781 } 782 783 /* Address Handles */ 784 int bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags) 785 { 786 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 787 struct bnxt_re_dev *rdev = ah->rdev; 788 bool block = true; 789 int rc; 790 791 block = !(flags & RDMA_DESTROY_AH_SLEEPABLE); 792 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah, block); 793 if (BNXT_RE_CHECK_RC(rc)) { 794 if (rc == -ETIMEDOUT) 795 rc = 0; 796 else 797 goto fail; 798 } 799 atomic_dec(&rdev->stats.res.ah_count); 800 fail: 801 return rc; 802 } 803 804 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype) 805 { 806 u8 nw_type; 807 808 switch (ntype) { 809 case RDMA_NETWORK_IPV4: 810 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4; 811 break; 812 case RDMA_NETWORK_IPV6: 813 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6; 814 break; 815 default: 816 nw_type = CMDQ_CREATE_AH_TYPE_V1; 817 break; 818 } 819 return nw_type; 820 } 821 822 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_init_attr *init_attr, 823 struct ib_udata *udata) 824 { 825 struct ib_pd *ib_pd = ib_ah->pd; 826 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 827 struct rdma_ah_attr *ah_attr = init_attr->ah_attr; 828 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 829 struct bnxt_re_dev *rdev = pd->rdev; 830 const struct ib_gid_attr *sgid_attr; 831 struct bnxt_re_gid_ctx *ctx; 832 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 833 u32 active_ahs; 834 u8 nw_type; 835 int rc; 836 837 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) { 838 ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set"); 839 return -EINVAL; 840 } 841 842 ah->rdev = rdev; 843 ah->qplib_ah.pd = &pd->qplib_pd; 844 845 /* Supply the configuration for the HW */ 846 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw, 847 sizeof(union ib_gid)); 848 sgid_attr = grh->sgid_attr; 849 /* Get the HW context of the GID. The reference 850 * of GID table entry is already taken by the caller. 851 */ 852 ctx = rdma_read_gid_hw_context(sgid_attr); 853 ah->qplib_ah.sgid_index = ctx->idx; 854 ah->qplib_ah.host_sgid_index = grh->sgid_index; 855 ah->qplib_ah.traffic_class = grh->traffic_class; 856 ah->qplib_ah.flow_label = grh->flow_label; 857 ah->qplib_ah.hop_limit = grh->hop_limit; 858 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr); 859 860 /* Get network header type for this GID */ 861 nw_type = rdma_gid_attr_network_type(sgid_attr); 862 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type); 863 864 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN); 865 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, 866 !(init_attr->flags & 867 RDMA_CREATE_AH_SLEEPABLE)); 868 if (rc) { 869 ibdev_err(&rdev->ibdev, "Failed to allocate HW AH"); 870 return rc; 871 } 872 873 /* Write AVID to shared page. */ 874 if (udata) { 875 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context( 876 udata, struct bnxt_re_ucontext, ib_uctx); 877 unsigned long flag; 878 u32 *wrptr; 879 880 spin_lock_irqsave(&uctx->sh_lock, flag); 881 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT); 882 *wrptr = ah->qplib_ah.id; 883 wmb(); /* make sure cache is updated. */ 884 spin_unlock_irqrestore(&uctx->sh_lock, flag); 885 } 886 active_ahs = atomic_inc_return(&rdev->stats.res.ah_count); 887 if (active_ahs > rdev->stats.res.ah_watermark) 888 rdev->stats.res.ah_watermark = active_ahs; 889 890 return 0; 891 } 892 893 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 894 { 895 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 896 897 ah_attr->type = ib_ah->type; 898 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl); 899 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN); 900 rdma_ah_set_grh(ah_attr, NULL, 0, 901 ah->qplib_ah.host_sgid_index, 902 0, ah->qplib_ah.traffic_class); 903 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data); 904 rdma_ah_set_port_num(ah_attr, 1); 905 rdma_ah_set_static_rate(ah_attr, 0); 906 return 0; 907 } 908 909 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp) 910 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock) 911 { 912 unsigned long flags; 913 914 spin_lock_irqsave(&qp->scq->cq_lock, flags); 915 if (qp->rcq != qp->scq) 916 spin_lock(&qp->rcq->cq_lock); 917 else 918 __acquire(&qp->rcq->cq_lock); 919 920 return flags; 921 } 922 923 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp, 924 unsigned long flags) 925 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock) 926 { 927 if (qp->rcq != qp->scq) 928 spin_unlock(&qp->rcq->cq_lock); 929 else 930 __release(&qp->rcq->cq_lock); 931 spin_unlock_irqrestore(&qp->scq->cq_lock, flags); 932 } 933 934 static void bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp) 935 { 936 struct bnxt_re_qp *gsi_sqp; 937 struct bnxt_re_ah *gsi_sah; 938 struct bnxt_re_dev *rdev; 939 int rc; 940 941 rdev = qp->rdev; 942 gsi_sqp = rdev->gsi_ctx.gsi_sqp; 943 gsi_sah = rdev->gsi_ctx.gsi_sah; 944 945 ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n"); 946 bnxt_qplib_destroy_ah(&rdev->qplib_res, 947 &gsi_sah->qplib_ah, 948 true); 949 atomic_dec(&rdev->stats.res.ah_count); 950 bnxt_qplib_clean_qp(&qp->qplib_qp); 951 952 ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n"); 953 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp); 954 if (rc) 955 ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed"); 956 957 bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp); 958 959 /* remove from active qp list */ 960 mutex_lock(&rdev->qp_lock); 961 list_del(&gsi_sqp->list); 962 mutex_unlock(&rdev->qp_lock); 963 atomic_dec(&rdev->stats.res.qp_count); 964 965 kfree(rdev->gsi_ctx.sqp_tbl); 966 kfree(gsi_sah); 967 kfree(gsi_sqp); 968 rdev->gsi_ctx.gsi_sqp = NULL; 969 rdev->gsi_ctx.gsi_sah = NULL; 970 rdev->gsi_ctx.sqp_tbl = NULL; 971 } 972 973 static void bnxt_re_del_unique_gid(struct bnxt_re_dev *rdev) 974 { 975 int rc; 976 977 if (!rdev->rcfw.roce_mirror) 978 return; 979 980 rc = bnxt_qplib_del_sgid(&rdev->qplib_res.sgid_tbl, 981 (struct bnxt_qplib_gid *)&rdev->ugid, 982 0xFFFF, true); 983 if (rc) 984 dev_err(rdev_to_dev(rdev), "Failed to delete unique GID, rc: %d\n", rc); 985 } 986 987 /* Queue Pairs */ 988 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata) 989 { 990 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 991 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp; 992 struct bnxt_re_dev *rdev = qp->rdev; 993 struct bnxt_qplib_nq *scq_nq = NULL; 994 struct bnxt_qplib_nq *rcq_nq = NULL; 995 unsigned int flags; 996 int rc; 997 998 bnxt_re_debug_rem_qpinfo(rdev, qp); 999 1000 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp); 1001 1002 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 1003 if (rc) 1004 ibdev_err(&rdev->ibdev, "Failed to destroy HW QP"); 1005 1006 if (rdma_is_kernel_res(&qp->ib_qp.res)) { 1007 flags = bnxt_re_lock_cqs(qp); 1008 bnxt_qplib_clean_qp(&qp->qplib_qp); 1009 bnxt_re_unlock_cqs(qp, flags); 1010 } 1011 1012 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp); 1013 1014 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) 1015 bnxt_re_destroy_gsi_sqp(qp); 1016 1017 mutex_lock(&rdev->qp_lock); 1018 list_del(&qp->list); 1019 mutex_unlock(&rdev->qp_lock); 1020 atomic_dec(&rdev->stats.res.qp_count); 1021 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_RC) 1022 atomic_dec(&rdev->stats.res.rc_qp_count); 1023 else if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD) 1024 atomic_dec(&rdev->stats.res.ud_qp_count); 1025 1026 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE) 1027 bnxt_re_del_unique_gid(rdev); 1028 1029 ib_umem_release(qp->rumem); 1030 ib_umem_release(qp->sumem); 1031 1032 /* Flush all the entries of notification queue associated with 1033 * given qp. 1034 */ 1035 scq_nq = qplib_qp->scq->nq; 1036 rcq_nq = qplib_qp->rcq->nq; 1037 bnxt_re_synchronize_nq(scq_nq); 1038 if (scq_nq != rcq_nq) 1039 bnxt_re_synchronize_nq(rcq_nq); 1040 1041 return 0; 1042 } 1043 1044 static u8 __from_ib_qp_type(enum ib_qp_type type) 1045 { 1046 switch (type) { 1047 case IB_QPT_GSI: 1048 return CMDQ_CREATE_QP1_TYPE_GSI; 1049 case IB_QPT_RC: 1050 return CMDQ_CREATE_QP_TYPE_RC; 1051 case IB_QPT_UD: 1052 return CMDQ_CREATE_QP_TYPE_UD; 1053 case IB_QPT_RAW_PACKET: 1054 return CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE; 1055 default: 1056 return IB_QPT_MAX; 1057 } 1058 } 1059 1060 static u16 bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp *qplqp, 1061 int rsge, int max) 1062 { 1063 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) 1064 rsge = max; 1065 return bnxt_re_get_rwqe_size(rsge); 1066 } 1067 1068 static u16 bnxt_re_get_wqe_size(int ilsize, int nsge) 1069 { 1070 u16 wqe_size, calc_ils; 1071 1072 wqe_size = bnxt_re_get_swqe_size(nsge); 1073 if (ilsize) { 1074 calc_ils = sizeof(struct sq_send_hdr) + ilsize; 1075 wqe_size = max_t(u16, calc_ils, wqe_size); 1076 wqe_size = ALIGN(wqe_size, sizeof(struct sq_send_hdr)); 1077 } 1078 return wqe_size; 1079 } 1080 1081 static int bnxt_re_setup_swqe_size(struct bnxt_re_qp *qp, 1082 struct ib_qp_init_attr *init_attr) 1083 { 1084 struct bnxt_qplib_dev_attr *dev_attr; 1085 struct bnxt_qplib_qp *qplqp; 1086 struct bnxt_re_dev *rdev; 1087 struct bnxt_qplib_q *sq; 1088 int align, ilsize; 1089 1090 rdev = qp->rdev; 1091 qplqp = &qp->qplib_qp; 1092 sq = &qplqp->sq; 1093 dev_attr = rdev->dev_attr; 1094 1095 align = sizeof(struct sq_send_hdr); 1096 ilsize = ALIGN(init_attr->cap.max_inline_data, align); 1097 1098 /* For gen p4 and gen p5 fixed wqe compatibility mode 1099 * wqe size is fixed to 128 bytes - ie 6 SGEs 1100 */ 1101 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) { 1102 sq->wqe_size = bnxt_re_get_swqe_size(BNXT_STATIC_MAX_SGE); 1103 sq->max_sge = BNXT_STATIC_MAX_SGE; 1104 } else { 1105 sq->wqe_size = bnxt_re_get_wqe_size(ilsize, sq->max_sge); 1106 if (sq->wqe_size > bnxt_re_get_swqe_size(dev_attr->max_qp_sges)) 1107 return -EINVAL; 1108 } 1109 1110 if (init_attr->cap.max_inline_data) { 1111 qplqp->max_inline_data = sq->wqe_size - 1112 sizeof(struct sq_send_hdr); 1113 init_attr->cap.max_inline_data = qplqp->max_inline_data; 1114 } 1115 1116 return 0; 1117 } 1118 1119 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd, 1120 struct bnxt_re_qp *qp, struct bnxt_re_ucontext *cntx, 1121 struct bnxt_re_qp_req *ureq) 1122 { 1123 struct bnxt_qplib_qp *qplib_qp; 1124 int bytes = 0, psn_sz; 1125 struct ib_umem *umem; 1126 int psn_nume; 1127 1128 qplib_qp = &qp->qplib_qp; 1129 1130 bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size); 1131 /* Consider mapping PSN search memory only for RC QPs. */ 1132 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) { 1133 psn_sz = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ? 1134 sizeof(struct sq_psn_search_ext) : 1135 sizeof(struct sq_psn_search); 1136 if (cntx && bnxt_re_is_var_size_supported(rdev, cntx)) { 1137 psn_nume = ureq->sq_slots; 1138 } else { 1139 psn_nume = (qplib_qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ? 1140 qplib_qp->sq.max_wqe : ((qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size) / 1141 sizeof(struct bnxt_qplib_sge)); 1142 } 1143 if (_is_host_msn_table(rdev->qplib_res.dattr->dev_cap_flags2)) 1144 psn_nume = roundup_pow_of_two(psn_nume); 1145 bytes += (psn_nume * psn_sz); 1146 } 1147 1148 bytes = PAGE_ALIGN(bytes); 1149 umem = ib_umem_get(&rdev->ibdev, ureq->qpsva, bytes, 1150 IB_ACCESS_LOCAL_WRITE); 1151 if (IS_ERR(umem)) 1152 return PTR_ERR(umem); 1153 1154 qp->sumem = umem; 1155 qplib_qp->sq.sg_info.umem = umem; 1156 qplib_qp->sq.sg_info.pgsize = PAGE_SIZE; 1157 qplib_qp->sq.sg_info.pgshft = PAGE_SHIFT; 1158 qplib_qp->qp_handle = ureq->qp_handle; 1159 1160 if (!qp->qplib_qp.srq) { 1161 bytes = (qplib_qp->rq.max_wqe * qplib_qp->rq.wqe_size); 1162 bytes = PAGE_ALIGN(bytes); 1163 umem = ib_umem_get(&rdev->ibdev, ureq->qprva, bytes, 1164 IB_ACCESS_LOCAL_WRITE); 1165 if (IS_ERR(umem)) 1166 goto rqfail; 1167 qp->rumem = umem; 1168 qplib_qp->rq.sg_info.umem = umem; 1169 qplib_qp->rq.sg_info.pgsize = PAGE_SIZE; 1170 qplib_qp->rq.sg_info.pgshft = PAGE_SHIFT; 1171 } 1172 1173 qplib_qp->dpi = &cntx->dpi; 1174 return 0; 1175 rqfail: 1176 ib_umem_release(qp->sumem); 1177 qp->sumem = NULL; 1178 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info)); 1179 1180 return PTR_ERR(umem); 1181 } 1182 1183 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah 1184 (struct bnxt_re_pd *pd, 1185 struct bnxt_qplib_res *qp1_res, 1186 struct bnxt_qplib_qp *qp1_qp) 1187 { 1188 struct bnxt_re_dev *rdev = pd->rdev; 1189 struct bnxt_re_ah *ah; 1190 union ib_gid sgid; 1191 int rc; 1192 1193 ah = kzalloc(sizeof(*ah), GFP_KERNEL); 1194 if (!ah) 1195 return NULL; 1196 1197 ah->rdev = rdev; 1198 ah->qplib_ah.pd = &pd->qplib_pd; 1199 1200 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid); 1201 if (rc) 1202 goto fail; 1203 1204 /* supply the dgid data same as sgid */ 1205 memcpy(ah->qplib_ah.dgid.data, &sgid.raw, 1206 sizeof(union ib_gid)); 1207 ah->qplib_ah.sgid_index = 0; 1208 1209 ah->qplib_ah.traffic_class = 0; 1210 ah->qplib_ah.flow_label = 0; 1211 ah->qplib_ah.hop_limit = 1; 1212 ah->qplib_ah.sl = 0; 1213 /* Have DMAC same as SMAC */ 1214 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr); 1215 1216 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false); 1217 if (rc) { 1218 ibdev_err(&rdev->ibdev, 1219 "Failed to allocate HW AH for Shadow QP"); 1220 goto fail; 1221 } 1222 atomic_inc(&rdev->stats.res.ah_count); 1223 1224 return ah; 1225 1226 fail: 1227 kfree(ah); 1228 return NULL; 1229 } 1230 1231 static struct bnxt_re_qp *bnxt_re_create_shadow_qp 1232 (struct bnxt_re_pd *pd, 1233 struct bnxt_qplib_res *qp1_res, 1234 struct bnxt_qplib_qp *qp1_qp) 1235 { 1236 struct bnxt_re_dev *rdev = pd->rdev; 1237 struct bnxt_re_qp *qp; 1238 int rc; 1239 1240 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1241 if (!qp) 1242 return NULL; 1243 1244 qp->rdev = rdev; 1245 1246 /* Initialize the shadow QP structure from the QP1 values */ 1247 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 1248 1249 qp->qplib_qp.pd = &pd->qplib_pd; 1250 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 1251 qp->qplib_qp.type = IB_QPT_UD; 1252 1253 qp->qplib_qp.max_inline_data = 0; 1254 qp->qplib_qp.sig_type = true; 1255 1256 /* Shadow QP SQ depth should be same as QP1 RQ depth */ 1257 qp->qplib_qp.sq.wqe_size = bnxt_re_get_wqe_size(0, 6); 1258 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe; 1259 qp->qplib_qp.sq.max_sw_wqe = qp1_qp->rq.max_wqe; 1260 qp->qplib_qp.sq.max_sge = 2; 1261 /* Q full delta can be 1 since it is internal QP */ 1262 qp->qplib_qp.sq.q_full_delta = 1; 1263 qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE; 1264 qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT; 1265 1266 qp->qplib_qp.scq = qp1_qp->scq; 1267 qp->qplib_qp.rcq = qp1_qp->rcq; 1268 1269 qp->qplib_qp.rq.wqe_size = bnxt_re_get_rwqe_size(6); 1270 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe; 1271 qp->qplib_qp.rq.max_sw_wqe = qp1_qp->rq.max_wqe; 1272 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge; 1273 /* Q full delta can be 1 since it is internal QP */ 1274 qp->qplib_qp.rq.q_full_delta = 1; 1275 qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE; 1276 qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT; 1277 1278 qp->qplib_qp.mtu = qp1_qp->mtu; 1279 1280 qp->qplib_qp.sq_hdr_buf_size = 0; 1281 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 1282 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1283 1284 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp); 1285 if (rc) 1286 goto fail; 1287 1288 spin_lock_init(&qp->sq_lock); 1289 INIT_LIST_HEAD(&qp->list); 1290 mutex_lock(&rdev->qp_lock); 1291 list_add_tail(&qp->list, &rdev->qp_list); 1292 atomic_inc(&rdev->stats.res.qp_count); 1293 mutex_unlock(&rdev->qp_lock); 1294 return qp; 1295 fail: 1296 kfree(qp); 1297 return NULL; 1298 } 1299 1300 static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp, 1301 struct ib_qp_init_attr *init_attr, 1302 struct bnxt_re_ucontext *uctx) 1303 { 1304 struct bnxt_qplib_dev_attr *dev_attr; 1305 struct bnxt_qplib_qp *qplqp; 1306 struct bnxt_re_dev *rdev; 1307 struct bnxt_qplib_q *rq; 1308 int entries; 1309 1310 rdev = qp->rdev; 1311 qplqp = &qp->qplib_qp; 1312 rq = &qplqp->rq; 1313 dev_attr = rdev->dev_attr; 1314 1315 if (init_attr->srq) { 1316 struct bnxt_re_srq *srq; 1317 1318 srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq); 1319 qplqp->srq = &srq->qplib_srq; 1320 rq->max_wqe = 0; 1321 } else { 1322 rq->max_sge = init_attr->cap.max_recv_sge; 1323 if (rq->max_sge > dev_attr->max_qp_sges) 1324 rq->max_sge = dev_attr->max_qp_sges; 1325 init_attr->cap.max_recv_sge = rq->max_sge; 1326 rq->wqe_size = bnxt_re_setup_rwqe_size(qplqp, rq->max_sge, 1327 dev_attr->max_qp_sges); 1328 /* Allocate 1 more than what's provided so posting max doesn't 1329 * mean empty. 1330 */ 1331 entries = bnxt_re_init_depth(init_attr->cap.max_recv_wr + 1, uctx); 1332 rq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1); 1333 rq->max_sw_wqe = rq->max_wqe; 1334 rq->q_full_delta = 0; 1335 rq->sg_info.pgsize = PAGE_SIZE; 1336 rq->sg_info.pgshft = PAGE_SHIFT; 1337 } 1338 1339 return 0; 1340 } 1341 1342 static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp) 1343 { 1344 struct bnxt_qplib_dev_attr *dev_attr; 1345 struct bnxt_qplib_qp *qplqp; 1346 struct bnxt_re_dev *rdev; 1347 1348 rdev = qp->rdev; 1349 qplqp = &qp->qplib_qp; 1350 dev_attr = rdev->dev_attr; 1351 1352 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 1353 qplqp->rq.max_sge = dev_attr->max_qp_sges; 1354 if (qplqp->rq.max_sge > dev_attr->max_qp_sges) 1355 qplqp->rq.max_sge = dev_attr->max_qp_sges; 1356 qplqp->rq.max_sge = 6; 1357 } 1358 } 1359 1360 static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp, 1361 struct ib_qp_init_attr *init_attr, 1362 struct bnxt_re_ucontext *uctx, 1363 struct bnxt_re_qp_req *ureq) 1364 { 1365 struct bnxt_qplib_dev_attr *dev_attr; 1366 struct bnxt_qplib_qp *qplqp; 1367 struct bnxt_re_dev *rdev; 1368 struct bnxt_qplib_q *sq; 1369 int diff = 0; 1370 int entries; 1371 int rc; 1372 1373 rdev = qp->rdev; 1374 qplqp = &qp->qplib_qp; 1375 sq = &qplqp->sq; 1376 dev_attr = rdev->dev_attr; 1377 1378 sq->max_sge = init_attr->cap.max_send_sge; 1379 entries = init_attr->cap.max_send_wr; 1380 if (uctx && qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) { 1381 sq->max_wqe = ureq->sq_slots; 1382 sq->max_sw_wqe = ureq->sq_slots; 1383 sq->wqe_size = sizeof(struct sq_sge); 1384 } else { 1385 if (sq->max_sge > dev_attr->max_qp_sges) { 1386 sq->max_sge = dev_attr->max_qp_sges; 1387 init_attr->cap.max_send_sge = sq->max_sge; 1388 } 1389 1390 rc = bnxt_re_setup_swqe_size(qp, init_attr); 1391 if (rc) 1392 return rc; 1393 1394 /* Allocate 128 + 1 more than what's provided */ 1395 diff = (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) ? 1396 0 : BNXT_QPLIB_RESERVED_QP_WRS; 1397 entries = bnxt_re_init_depth(entries + diff + 1, uctx); 1398 sq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + diff + 1); 1399 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) 1400 sq->max_sw_wqe = bnxt_qplib_get_depth(sq, qplqp->wqe_mode, true); 1401 else 1402 sq->max_sw_wqe = sq->max_wqe; 1403 1404 } 1405 sq->q_full_delta = diff + 1; 1406 /* 1407 * Reserving one slot for Phantom WQE. Application can 1408 * post one extra entry in this case. But allowing this to avoid 1409 * unexpected Queue full condition 1410 */ 1411 qplqp->sq.q_full_delta -= 1; 1412 qplqp->sq.sg_info.pgsize = PAGE_SIZE; 1413 qplqp->sq.sg_info.pgshft = PAGE_SHIFT; 1414 1415 return 0; 1416 } 1417 1418 static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp, 1419 struct ib_qp_init_attr *init_attr, 1420 struct bnxt_re_ucontext *uctx) 1421 { 1422 struct bnxt_qplib_dev_attr *dev_attr; 1423 struct bnxt_qplib_qp *qplqp; 1424 struct bnxt_re_dev *rdev; 1425 int entries; 1426 1427 rdev = qp->rdev; 1428 qplqp = &qp->qplib_qp; 1429 dev_attr = rdev->dev_attr; 1430 1431 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 1432 entries = bnxt_re_init_depth(init_attr->cap.max_send_wr + 1, uctx); 1433 qplqp->sq.max_wqe = min_t(u32, entries, 1434 dev_attr->max_qp_wqes + 1); 1435 qplqp->sq.q_full_delta = qplqp->sq.max_wqe - 1436 init_attr->cap.max_send_wr; 1437 qplqp->sq.max_sge++; /* Need one extra sge to put UD header */ 1438 if (qplqp->sq.max_sge > dev_attr->max_qp_sges) 1439 qplqp->sq.max_sge = dev_attr->max_qp_sges; 1440 } 1441 } 1442 1443 static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev, 1444 struct ib_qp_init_attr *init_attr) 1445 { 1446 struct bnxt_qplib_chip_ctx *chip_ctx; 1447 int qptype; 1448 1449 chip_ctx = rdev->chip_ctx; 1450 1451 qptype = __from_ib_qp_type(init_attr->qp_type); 1452 if (qptype == IB_QPT_MAX) { 1453 ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype); 1454 qptype = -EOPNOTSUPP; 1455 goto out; 1456 } 1457 1458 if (bnxt_qplib_is_chip_gen_p5_p7(chip_ctx) && 1459 init_attr->qp_type == IB_QPT_GSI) 1460 qptype = CMDQ_CREATE_QP_TYPE_GSI; 1461 out: 1462 return qptype; 1463 } 1464 1465 static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 1466 struct ib_qp_init_attr *init_attr, 1467 struct bnxt_re_ucontext *uctx, 1468 struct bnxt_re_qp_req *ureq) 1469 { 1470 struct bnxt_qplib_dev_attr *dev_attr; 1471 struct bnxt_qplib_qp *qplqp; 1472 struct bnxt_re_dev *rdev; 1473 struct bnxt_re_cq *cq; 1474 int rc = 0, qptype; 1475 1476 rdev = qp->rdev; 1477 qplqp = &qp->qplib_qp; 1478 dev_attr = rdev->dev_attr; 1479 1480 /* Setup misc params */ 1481 ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr); 1482 qplqp->pd = &pd->qplib_pd; 1483 qplqp->qp_handle = (u64)qplqp; 1484 qplqp->max_inline_data = init_attr->cap.max_inline_data; 1485 qplqp->sig_type = init_attr->sq_sig_type == IB_SIGNAL_ALL_WR; 1486 qptype = bnxt_re_init_qp_type(rdev, init_attr); 1487 if (qptype < 0) { 1488 rc = qptype; 1489 goto out; 1490 } 1491 qplqp->type = (u8)qptype; 1492 qplqp->wqe_mode = bnxt_re_is_var_size_supported(rdev, uctx); 1493 if (init_attr->qp_type == IB_QPT_RC) { 1494 qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom; 1495 qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom; 1496 } 1497 qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1498 qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */ 1499 if (init_attr->create_flags) { 1500 ibdev_dbg(&rdev->ibdev, 1501 "QP create flags 0x%x not supported", 1502 init_attr->create_flags); 1503 return -EOPNOTSUPP; 1504 } 1505 1506 /* Setup CQs */ 1507 if (init_attr->send_cq) { 1508 cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq); 1509 qplqp->scq = &cq->qplib_cq; 1510 qp->scq = cq; 1511 } 1512 1513 if (init_attr->recv_cq) { 1514 cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq); 1515 qplqp->rcq = &cq->qplib_cq; 1516 qp->rcq = cq; 1517 } 1518 1519 /* Setup RQ/SRQ */ 1520 rc = bnxt_re_init_rq_attr(qp, init_attr, uctx); 1521 if (rc) 1522 goto out; 1523 if (init_attr->qp_type == IB_QPT_GSI) 1524 bnxt_re_adjust_gsi_rq_attr(qp); 1525 1526 /* Setup SQ */ 1527 rc = bnxt_re_init_sq_attr(qp, init_attr, uctx, ureq); 1528 if (rc) 1529 goto out; 1530 if (init_attr->qp_type == IB_QPT_GSI) 1531 bnxt_re_adjust_gsi_sq_attr(qp, init_attr, uctx); 1532 1533 if (uctx) /* This will update DPI and qp_handle */ 1534 rc = bnxt_re_init_user_qp(rdev, pd, qp, uctx, ureq); 1535 out: 1536 return rc; 1537 } 1538 1539 static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp, 1540 struct bnxt_re_pd *pd) 1541 { 1542 struct bnxt_re_sqp_entries *sqp_tbl; 1543 struct bnxt_re_dev *rdev; 1544 struct bnxt_re_qp *sqp; 1545 struct bnxt_re_ah *sah; 1546 int rc = 0; 1547 1548 rdev = qp->rdev; 1549 /* Create a shadow QP to handle the QP1 traffic */ 1550 sqp_tbl = kcalloc(BNXT_RE_MAX_GSI_SQP_ENTRIES, sizeof(*sqp_tbl), 1551 GFP_KERNEL); 1552 if (!sqp_tbl) 1553 return -ENOMEM; 1554 rdev->gsi_ctx.sqp_tbl = sqp_tbl; 1555 1556 sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp); 1557 if (!sqp) { 1558 rc = -ENODEV; 1559 ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1"); 1560 goto out; 1561 } 1562 rdev->gsi_ctx.gsi_sqp = sqp; 1563 1564 sqp->rcq = qp->rcq; 1565 sqp->scq = qp->scq; 1566 sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res, 1567 &qp->qplib_qp); 1568 if (!sah) { 1569 bnxt_qplib_destroy_qp(&rdev->qplib_res, 1570 &sqp->qplib_qp); 1571 rc = -ENODEV; 1572 ibdev_err(&rdev->ibdev, 1573 "Failed to create AH entry for ShadowQP"); 1574 goto out; 1575 } 1576 rdev->gsi_ctx.gsi_sah = sah; 1577 1578 return 0; 1579 out: 1580 kfree(sqp_tbl); 1581 return rc; 1582 } 1583 1584 static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 1585 struct ib_qp_init_attr *init_attr) 1586 { 1587 struct bnxt_re_dev *rdev; 1588 struct bnxt_qplib_qp *qplqp; 1589 int rc; 1590 1591 rdev = qp->rdev; 1592 qplqp = &qp->qplib_qp; 1593 1594 qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 1595 qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2; 1596 1597 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp); 1598 if (rc) { 1599 ibdev_err(&rdev->ibdev, "create HW QP1 failed!"); 1600 goto out; 1601 } 1602 1603 rc = bnxt_re_create_shadow_gsi(qp, pd); 1604 out: 1605 return rc; 1606 } 1607 1608 static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev, 1609 struct ib_qp_init_attr *init_attr, 1610 struct bnxt_qplib_dev_attr *dev_attr) 1611 { 1612 bool rc = true; 1613 1614 if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes || 1615 init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes || 1616 init_attr->cap.max_send_sge > dev_attr->max_qp_sges || 1617 init_attr->cap.max_recv_sge > dev_attr->max_qp_sges || 1618 init_attr->cap.max_inline_data > dev_attr->max_inline_data) { 1619 ibdev_err(&rdev->ibdev, 1620 "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x", 1621 init_attr->cap.max_send_wr, dev_attr->max_qp_wqes, 1622 init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes, 1623 init_attr->cap.max_send_sge, dev_attr->max_qp_sges, 1624 init_attr->cap.max_recv_sge, dev_attr->max_qp_sges, 1625 init_attr->cap.max_inline_data, 1626 dev_attr->max_inline_data); 1627 rc = false; 1628 } 1629 return rc; 1630 } 1631 1632 static int bnxt_re_add_unique_gid(struct bnxt_re_dev *rdev) 1633 { 1634 struct bnxt_qplib_ctx *hctx = &rdev->qplib_ctx; 1635 struct bnxt_qplib_res *res = &rdev->qplib_res; 1636 int rc; 1637 1638 if (!rdev->rcfw.roce_mirror) 1639 return 0; 1640 1641 rdev->ugid.global.subnet_prefix = cpu_to_be64(0xfe8000000000abcdLL); 1642 addrconf_ifid_eui48(&rdev->ugid.raw[8], rdev->netdev); 1643 1644 rc = bnxt_qplib_add_sgid(&res->sgid_tbl, 1645 (struct bnxt_qplib_gid *)&rdev->ugid, 1646 rdev->qplib_res.netdev->dev_addr, 1647 0xFFFF, true, &rdev->ugid_index, true, 1648 hctx->stats3.fw_id); 1649 if (rc) 1650 dev_err(rdev_to_dev(rdev), "Failed to add unique GID. rc = %d\n", rc); 1651 1652 return rc; 1653 } 1654 1655 int bnxt_re_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *qp_init_attr, 1656 struct ib_udata *udata) 1657 { 1658 struct bnxt_qplib_dev_attr *dev_attr; 1659 struct bnxt_re_ucontext *uctx; 1660 struct bnxt_re_qp_req ureq; 1661 struct bnxt_re_dev *rdev; 1662 struct bnxt_re_pd *pd; 1663 struct bnxt_re_qp *qp; 1664 struct ib_pd *ib_pd; 1665 u32 active_qps; 1666 int rc; 1667 1668 ib_pd = ib_qp->pd; 1669 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1670 rdev = pd->rdev; 1671 dev_attr = rdev->dev_attr; 1672 qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1673 1674 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 1675 if (udata) 1676 if (ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq)))) 1677 return -EFAULT; 1678 1679 rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr); 1680 if (!rc) { 1681 rc = -EINVAL; 1682 goto fail; 1683 } 1684 1685 qp->rdev = rdev; 1686 rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, uctx, &ureq); 1687 if (rc) 1688 goto fail; 1689 1690 if (qp_init_attr->qp_type == IB_QPT_GSI && 1691 !(bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))) { 1692 rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr); 1693 if (rc == -ENODEV) 1694 goto qp_destroy; 1695 if (rc) 1696 goto fail; 1697 } else { 1698 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp); 1699 if (rc) { 1700 ibdev_err(&rdev->ibdev, "Failed to create HW QP"); 1701 goto free_umem; 1702 } 1703 if (udata) { 1704 struct bnxt_re_qp_resp resp; 1705 1706 resp.qpid = qp->qplib_qp.id; 1707 resp.rsvd = 0; 1708 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1709 if (rc) { 1710 ibdev_err(&rdev->ibdev, "Failed to copy QP udata"); 1711 goto qp_destroy; 1712 } 1713 } 1714 } 1715 1716 /* Support for RawEth QP is added to capture TCP pkt dump. 1717 * So unique SGID is used to avoid incorrect statistics on per 1718 * function stats_ctx 1719 */ 1720 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE) { 1721 rc = bnxt_re_add_unique_gid(rdev); 1722 if (rc) 1723 goto qp_destroy; 1724 qp->qplib_qp.ugid_index = rdev->ugid_index; 1725 } 1726 1727 qp->ib_qp.qp_num = qp->qplib_qp.id; 1728 if (qp_init_attr->qp_type == IB_QPT_GSI) 1729 rdev->gsi_ctx.gsi_qp = qp; 1730 spin_lock_init(&qp->sq_lock); 1731 spin_lock_init(&qp->rq_lock); 1732 INIT_LIST_HEAD(&qp->list); 1733 mutex_lock(&rdev->qp_lock); 1734 list_add_tail(&qp->list, &rdev->qp_list); 1735 mutex_unlock(&rdev->qp_lock); 1736 active_qps = atomic_inc_return(&rdev->stats.res.qp_count); 1737 if (active_qps > rdev->stats.res.qp_watermark) 1738 rdev->stats.res.qp_watermark = active_qps; 1739 if (qp_init_attr->qp_type == IB_QPT_RC) { 1740 active_qps = atomic_inc_return(&rdev->stats.res.rc_qp_count); 1741 if (active_qps > rdev->stats.res.rc_qp_watermark) 1742 rdev->stats.res.rc_qp_watermark = active_qps; 1743 } else if (qp_init_attr->qp_type == IB_QPT_UD) { 1744 active_qps = atomic_inc_return(&rdev->stats.res.ud_qp_count); 1745 if (active_qps > rdev->stats.res.ud_qp_watermark) 1746 rdev->stats.res.ud_qp_watermark = active_qps; 1747 } 1748 bnxt_re_debug_add_qpinfo(rdev, qp); 1749 1750 return 0; 1751 qp_destroy: 1752 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 1753 free_umem: 1754 ib_umem_release(qp->rumem); 1755 ib_umem_release(qp->sumem); 1756 fail: 1757 return rc; 1758 } 1759 1760 static u8 __from_ib_qp_state(enum ib_qp_state state) 1761 { 1762 switch (state) { 1763 case IB_QPS_RESET: 1764 return CMDQ_MODIFY_QP_NEW_STATE_RESET; 1765 case IB_QPS_INIT: 1766 return CMDQ_MODIFY_QP_NEW_STATE_INIT; 1767 case IB_QPS_RTR: 1768 return CMDQ_MODIFY_QP_NEW_STATE_RTR; 1769 case IB_QPS_RTS: 1770 return CMDQ_MODIFY_QP_NEW_STATE_RTS; 1771 case IB_QPS_SQD: 1772 return CMDQ_MODIFY_QP_NEW_STATE_SQD; 1773 case IB_QPS_SQE: 1774 return CMDQ_MODIFY_QP_NEW_STATE_SQE; 1775 case IB_QPS_ERR: 1776 default: 1777 return CMDQ_MODIFY_QP_NEW_STATE_ERR; 1778 } 1779 } 1780 1781 static enum ib_qp_state __to_ib_qp_state(u8 state) 1782 { 1783 switch (state) { 1784 case CMDQ_MODIFY_QP_NEW_STATE_RESET: 1785 return IB_QPS_RESET; 1786 case CMDQ_MODIFY_QP_NEW_STATE_INIT: 1787 return IB_QPS_INIT; 1788 case CMDQ_MODIFY_QP_NEW_STATE_RTR: 1789 return IB_QPS_RTR; 1790 case CMDQ_MODIFY_QP_NEW_STATE_RTS: 1791 return IB_QPS_RTS; 1792 case CMDQ_MODIFY_QP_NEW_STATE_SQD: 1793 return IB_QPS_SQD; 1794 case CMDQ_MODIFY_QP_NEW_STATE_SQE: 1795 return IB_QPS_SQE; 1796 case CMDQ_MODIFY_QP_NEW_STATE_ERR: 1797 default: 1798 return IB_QPS_ERR; 1799 } 1800 } 1801 1802 static u32 __from_ib_mtu(enum ib_mtu mtu) 1803 { 1804 switch (mtu) { 1805 case IB_MTU_256: 1806 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256; 1807 case IB_MTU_512: 1808 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512; 1809 case IB_MTU_1024: 1810 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024; 1811 case IB_MTU_2048: 1812 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1813 case IB_MTU_4096: 1814 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096; 1815 default: 1816 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1817 } 1818 } 1819 1820 static enum ib_mtu __to_ib_mtu(u32 mtu) 1821 { 1822 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) { 1823 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256: 1824 return IB_MTU_256; 1825 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512: 1826 return IB_MTU_512; 1827 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024: 1828 return IB_MTU_1024; 1829 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048: 1830 return IB_MTU_2048; 1831 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096: 1832 return IB_MTU_4096; 1833 default: 1834 return IB_MTU_2048; 1835 } 1836 } 1837 1838 /* Shared Receive Queues */ 1839 int bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata) 1840 { 1841 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1842 ib_srq); 1843 struct bnxt_re_dev *rdev = srq->rdev; 1844 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1845 1846 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) { 1847 free_page((unsigned long)srq->uctx_srq_page); 1848 hash_del(&srq->hash_entry); 1849 } 1850 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq); 1851 ib_umem_release(srq->umem); 1852 atomic_dec(&rdev->stats.res.srq_count); 1853 return 0; 1854 } 1855 1856 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev, 1857 struct bnxt_re_pd *pd, 1858 struct bnxt_re_srq *srq, 1859 struct ib_udata *udata) 1860 { 1861 struct bnxt_re_srq_req ureq; 1862 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1863 struct ib_umem *umem; 1864 int bytes = 0; 1865 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context( 1866 udata, struct bnxt_re_ucontext, ib_uctx); 1867 1868 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 1869 return -EFAULT; 1870 1871 bytes = (qplib_srq->max_wqe * qplib_srq->wqe_size); 1872 bytes = PAGE_ALIGN(bytes); 1873 umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes, 1874 IB_ACCESS_LOCAL_WRITE); 1875 if (IS_ERR(umem)) 1876 return PTR_ERR(umem); 1877 1878 srq->umem = umem; 1879 qplib_srq->sg_info.umem = umem; 1880 qplib_srq->sg_info.pgsize = PAGE_SIZE; 1881 qplib_srq->sg_info.pgshft = PAGE_SHIFT; 1882 qplib_srq->srq_handle = ureq.srq_handle; 1883 qplib_srq->dpi = &cntx->dpi; 1884 1885 return 0; 1886 } 1887 1888 int bnxt_re_create_srq(struct ib_srq *ib_srq, 1889 struct ib_srq_init_attr *srq_init_attr, 1890 struct ib_udata *udata) 1891 { 1892 struct bnxt_qplib_dev_attr *dev_attr; 1893 struct bnxt_re_ucontext *uctx; 1894 struct bnxt_re_dev *rdev; 1895 struct bnxt_re_srq *srq; 1896 struct bnxt_re_pd *pd; 1897 struct ib_pd *ib_pd; 1898 u32 active_srqs; 1899 int rc, entries; 1900 1901 ib_pd = ib_srq->pd; 1902 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1903 rdev = pd->rdev; 1904 dev_attr = rdev->dev_attr; 1905 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq); 1906 1907 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) { 1908 ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded"); 1909 rc = -EINVAL; 1910 goto exit; 1911 } 1912 1913 if (srq_init_attr->srq_type != IB_SRQT_BASIC) { 1914 rc = -EOPNOTSUPP; 1915 goto exit; 1916 } 1917 1918 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 1919 srq->rdev = rdev; 1920 srq->qplib_srq.pd = &pd->qplib_pd; 1921 srq->qplib_srq.dpi = &rdev->dpi_privileged; 1922 /* Allocate 1 more than what's provided so posting max doesn't 1923 * mean empty 1924 */ 1925 entries = bnxt_re_init_depth(srq_init_attr->attr.max_wr + 1, uctx); 1926 if (entries > dev_attr->max_srq_wqes + 1) 1927 entries = dev_attr->max_srq_wqes + 1; 1928 srq->qplib_srq.max_wqe = entries; 1929 1930 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge; 1931 /* 128 byte wqe size for SRQ . So use max sges */ 1932 srq->qplib_srq.wqe_size = bnxt_re_get_rwqe_size(dev_attr->max_srq_sges); 1933 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit; 1934 srq->srq_limit = srq_init_attr->attr.srq_limit; 1935 srq->qplib_srq.eventq_hw_ring_id = rdev->nqr->nq[0].ring_id; 1936 srq->qplib_srq.sg_info.pgsize = PAGE_SIZE; 1937 srq->qplib_srq.sg_info.pgshft = PAGE_SHIFT; 1938 1939 if (udata) { 1940 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata); 1941 if (rc) 1942 goto fail; 1943 } 1944 1945 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq); 1946 if (rc) { 1947 ibdev_err(&rdev->ibdev, "Create HW SRQ failed!"); 1948 goto fail; 1949 } 1950 1951 if (udata) { 1952 struct bnxt_re_srq_resp resp = {}; 1953 1954 resp.srqid = srq->qplib_srq.id; 1955 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) { 1956 hash_add(rdev->srq_hash, &srq->hash_entry, srq->qplib_srq.id); 1957 srq->uctx_srq_page = (void *)get_zeroed_page(GFP_KERNEL); 1958 if (!srq->uctx_srq_page) { 1959 rc = -ENOMEM; 1960 goto fail; 1961 } 1962 resp.comp_mask |= BNXT_RE_SRQ_TOGGLE_PAGE_SUPPORT; 1963 } 1964 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1965 if (rc) { 1966 ibdev_err(&rdev->ibdev, "SRQ copy to udata failed!"); 1967 bnxt_qplib_destroy_srq(&rdev->qplib_res, 1968 &srq->qplib_srq); 1969 goto fail; 1970 } 1971 } 1972 active_srqs = atomic_inc_return(&rdev->stats.res.srq_count); 1973 if (active_srqs > rdev->stats.res.srq_watermark) 1974 rdev->stats.res.srq_watermark = active_srqs; 1975 spin_lock_init(&srq->lock); 1976 1977 return 0; 1978 1979 fail: 1980 ib_umem_release(srq->umem); 1981 exit: 1982 return rc; 1983 } 1984 1985 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr, 1986 enum ib_srq_attr_mask srq_attr_mask, 1987 struct ib_udata *udata) 1988 { 1989 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1990 ib_srq); 1991 struct bnxt_re_dev *rdev = srq->rdev; 1992 1993 switch (srq_attr_mask) { 1994 case IB_SRQ_MAX_WR: 1995 /* SRQ resize is not supported */ 1996 return -EINVAL; 1997 case IB_SRQ_LIMIT: 1998 /* Change the SRQ threshold */ 1999 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe) 2000 return -EINVAL; 2001 2002 srq->qplib_srq.threshold = srq_attr->srq_limit; 2003 bnxt_qplib_srq_arm_db(&srq->qplib_srq.dbinfo, srq->qplib_srq.threshold); 2004 2005 /* On success, update the shadow */ 2006 srq->srq_limit = srq_attr->srq_limit; 2007 /* No need to Build and send response back to udata */ 2008 return 0; 2009 default: 2010 ibdev_err(&rdev->ibdev, 2011 "Unsupported srq_attr_mask 0x%x", srq_attr_mask); 2012 return -EINVAL; 2013 } 2014 } 2015 2016 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr) 2017 { 2018 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 2019 ib_srq); 2020 struct bnxt_re_srq tsrq; 2021 struct bnxt_re_dev *rdev = srq->rdev; 2022 int rc; 2023 2024 /* Get live SRQ attr */ 2025 tsrq.qplib_srq.id = srq->qplib_srq.id; 2026 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq); 2027 if (rc) { 2028 ibdev_err(&rdev->ibdev, "Query HW SRQ failed!"); 2029 return rc; 2030 } 2031 srq_attr->max_wr = srq->qplib_srq.max_wqe; 2032 srq_attr->max_sge = srq->qplib_srq.max_sge; 2033 srq_attr->srq_limit = tsrq.qplib_srq.threshold; 2034 2035 return 0; 2036 } 2037 2038 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr, 2039 const struct ib_recv_wr **bad_wr) 2040 { 2041 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 2042 ib_srq); 2043 struct bnxt_qplib_swqe wqe; 2044 unsigned long flags; 2045 int rc = 0; 2046 2047 spin_lock_irqsave(&srq->lock, flags); 2048 while (wr) { 2049 /* Transcribe each ib_recv_wr to qplib_swqe */ 2050 wqe.num_sge = wr->num_sge; 2051 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 2052 wqe.wr_id = wr->wr_id; 2053 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2054 2055 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe); 2056 if (rc) { 2057 *bad_wr = wr; 2058 break; 2059 } 2060 wr = wr->next; 2061 } 2062 spin_unlock_irqrestore(&srq->lock, flags); 2063 2064 return rc; 2065 } 2066 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev, 2067 struct bnxt_re_qp *qp1_qp, 2068 int qp_attr_mask) 2069 { 2070 struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp; 2071 int rc; 2072 2073 if (qp_attr_mask & IB_QP_STATE) { 2074 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 2075 qp->qplib_qp.state = qp1_qp->qplib_qp.state; 2076 } 2077 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 2078 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 2079 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index; 2080 } 2081 2082 if (qp_attr_mask & IB_QP_QKEY) { 2083 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 2084 /* Using a Random QKEY */ 2085 qp->qplib_qp.qkey = 0x81818181; 2086 } 2087 if (qp_attr_mask & IB_QP_SQ_PSN) { 2088 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 2089 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn; 2090 } 2091 2092 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 2093 if (rc) 2094 ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1"); 2095 return rc; 2096 } 2097 2098 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 2099 int qp_attr_mask, struct ib_udata *udata) 2100 { 2101 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2102 struct bnxt_re_dev *rdev = qp->rdev; 2103 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 2104 enum ib_qp_state curr_qp_state, new_qp_state; 2105 int rc, entries; 2106 unsigned int flags; 2107 u8 nw_type; 2108 2109 if (qp_attr_mask & ~(IB_QP_ATTR_STANDARD_BITS | IB_QP_RATE_LIMIT)) 2110 return -EOPNOTSUPP; 2111 2112 qp->qplib_qp.modify_flags = 0; 2113 qp->qplib_qp.ext_modify_flags = 0; 2114 if (qp_attr_mask & IB_QP_STATE) { 2115 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state); 2116 new_qp_state = qp_attr->qp_state; 2117 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state, 2118 ib_qp->qp_type, qp_attr_mask)) { 2119 ibdev_err(&rdev->ibdev, 2120 "Invalid attribute mask: %#x specified ", 2121 qp_attr_mask); 2122 ibdev_err(&rdev->ibdev, 2123 "for qpn: %#x type: %#x", 2124 ib_qp->qp_num, ib_qp->qp_type); 2125 ibdev_err(&rdev->ibdev, 2126 "curr_qp_state=0x%x, new_qp_state=0x%x\n", 2127 curr_qp_state, new_qp_state); 2128 return -EINVAL; 2129 } 2130 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 2131 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state); 2132 2133 if (!qp->sumem && 2134 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) { 2135 ibdev_dbg(&rdev->ibdev, 2136 "Move QP = %p to flush list\n", qp); 2137 flags = bnxt_re_lock_cqs(qp); 2138 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 2139 bnxt_re_unlock_cqs(qp, flags); 2140 } 2141 if (!qp->sumem && 2142 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) { 2143 ibdev_dbg(&rdev->ibdev, 2144 "Move QP = %p out of flush list\n", qp); 2145 flags = bnxt_re_lock_cqs(qp); 2146 bnxt_qplib_clean_qp(&qp->qplib_qp); 2147 bnxt_re_unlock_cqs(qp, flags); 2148 } 2149 } 2150 2151 if (qp_attr_mask & IB_QP_RATE_LIMIT) { 2152 if (qp->qplib_qp.type != IB_QPT_RC || 2153 !_is_modify_qp_rate_limit_supported(dev_attr->dev_cap_flags2)) 2154 return -EOPNOTSUPP; 2155 qp->qplib_qp.ext_modify_flags |= 2156 CMDQ_MODIFY_QP_EXT_MODIFY_MASK_RATE_LIMIT_VALID; 2157 qp->qplib_qp.rate_limit = qp_attr->rate_limit; 2158 } 2159 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) { 2160 qp->qplib_qp.modify_flags |= 2161 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY; 2162 qp->qplib_qp.en_sqd_async_notify = true; 2163 } 2164 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 2165 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS; 2166 qp->qplib_qp.access = 2167 __qp_access_flags_from_ib(qp->qplib_qp.cctx, 2168 qp_attr->qp_access_flags); 2169 /* LOCAL_WRITE access must be set to allow RC receive */ 2170 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE; 2171 } 2172 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 2173 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 2174 qp->qplib_qp.pkey_index = qp_attr->pkey_index; 2175 } 2176 if (qp_attr_mask & IB_QP_QKEY) { 2177 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 2178 qp->qplib_qp.qkey = qp_attr->qkey; 2179 } 2180 if (qp_attr_mask & IB_QP_AV) { 2181 const struct ib_global_route *grh = 2182 rdma_ah_read_grh(&qp_attr->ah_attr); 2183 const struct ib_gid_attr *sgid_attr; 2184 struct bnxt_re_gid_ctx *ctx; 2185 2186 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID | 2187 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL | 2188 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX | 2189 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT | 2190 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS | 2191 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC | 2192 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID; 2193 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw, 2194 sizeof(qp->qplib_qp.ah.dgid.data)); 2195 qp->qplib_qp.ah.flow_label = grh->flow_label; 2196 sgid_attr = grh->sgid_attr; 2197 /* Get the HW context of the GID. The reference 2198 * of GID table entry is already taken by the caller. 2199 */ 2200 ctx = rdma_read_gid_hw_context(sgid_attr); 2201 qp->qplib_qp.ah.sgid_index = ctx->idx; 2202 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index; 2203 qp->qplib_qp.ah.hop_limit = grh->hop_limit; 2204 qp->qplib_qp.ah.traffic_class = grh->traffic_class >> 2; 2205 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr); 2206 ether_addr_copy(qp->qplib_qp.ah.dmac, 2207 qp_attr->ah_attr.roce.dmac); 2208 2209 rc = rdma_read_gid_l2_fields(sgid_attr, NULL, 2210 &qp->qplib_qp.smac[0]); 2211 if (rc) 2212 return rc; 2213 2214 nw_type = rdma_gid_attr_network_type(sgid_attr); 2215 switch (nw_type) { 2216 case RDMA_NETWORK_IPV4: 2217 qp->qplib_qp.nw_type = 2218 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4; 2219 break; 2220 case RDMA_NETWORK_IPV6: 2221 qp->qplib_qp.nw_type = 2222 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6; 2223 break; 2224 default: 2225 qp->qplib_qp.nw_type = 2226 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1; 2227 break; 2228 } 2229 } 2230 2231 if (qp_attr->qp_state == IB_QPS_RTR) { 2232 enum ib_mtu qpmtu; 2233 2234 qpmtu = iboe_get_mtu(rdev->netdev->mtu); 2235 if (qp_attr_mask & IB_QP_PATH_MTU) { 2236 if (ib_mtu_enum_to_int(qp_attr->path_mtu) > 2237 ib_mtu_enum_to_int(qpmtu)) 2238 return -EINVAL; 2239 qpmtu = qp_attr->path_mtu; 2240 } 2241 2242 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 2243 qp->qplib_qp.path_mtu = __from_ib_mtu(qpmtu); 2244 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qpmtu); 2245 } 2246 2247 if (qp_attr_mask & IB_QP_TIMEOUT) { 2248 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT; 2249 qp->qplib_qp.timeout = qp_attr->timeout; 2250 } 2251 if (qp_attr_mask & IB_QP_RETRY_CNT) { 2252 qp->qplib_qp.modify_flags |= 2253 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT; 2254 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt; 2255 } 2256 if (qp_attr_mask & IB_QP_RNR_RETRY) { 2257 qp->qplib_qp.modify_flags |= 2258 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY; 2259 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry; 2260 } 2261 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) { 2262 qp->qplib_qp.modify_flags |= 2263 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER; 2264 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer; 2265 } 2266 if (qp_attr_mask & IB_QP_RQ_PSN) { 2267 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN; 2268 qp->qplib_qp.rq.psn = qp_attr->rq_psn; 2269 } 2270 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2271 qp->qplib_qp.modify_flags |= 2272 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC; 2273 /* Cap the max_rd_atomic to device max */ 2274 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic, 2275 dev_attr->max_qp_rd_atom); 2276 } 2277 if (qp_attr_mask & IB_QP_SQ_PSN) { 2278 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 2279 qp->qplib_qp.sq.psn = qp_attr->sq_psn; 2280 } 2281 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2282 if (qp_attr->max_dest_rd_atomic > 2283 dev_attr->max_qp_init_rd_atom) { 2284 ibdev_err(&rdev->ibdev, 2285 "max_dest_rd_atomic requested%d is > dev_max%d", 2286 qp_attr->max_dest_rd_atomic, 2287 dev_attr->max_qp_init_rd_atom); 2288 return -EINVAL; 2289 } 2290 2291 qp->qplib_qp.modify_flags |= 2292 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC; 2293 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic; 2294 } 2295 if (qp_attr_mask & IB_QP_CAP) { 2296 struct bnxt_re_ucontext *uctx = 2297 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 2298 2299 qp->qplib_qp.modify_flags |= 2300 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE | 2301 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE | 2302 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE | 2303 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE | 2304 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA; 2305 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) || 2306 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) || 2307 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) || 2308 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) || 2309 (qp_attr->cap.max_inline_data >= 2310 dev_attr->max_inline_data)) { 2311 ibdev_err(&rdev->ibdev, 2312 "Create QP failed - max exceeded"); 2313 return -EINVAL; 2314 } 2315 entries = bnxt_re_init_depth(qp_attr->cap.max_send_wr, uctx); 2316 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 2317 dev_attr->max_qp_wqes + 1); 2318 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 2319 qp_attr->cap.max_send_wr; 2320 /* 2321 * Reserving one slot for Phantom WQE. Some application can 2322 * post one extra entry in this case. Allowing this to avoid 2323 * unexpected Queue full condition 2324 */ 2325 qp->qplib_qp.sq.q_full_delta -= 1; 2326 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge; 2327 if (qp->qplib_qp.rq.max_wqe) { 2328 entries = bnxt_re_init_depth(qp_attr->cap.max_recv_wr, uctx); 2329 qp->qplib_qp.rq.max_wqe = 2330 min_t(u32, entries, dev_attr->max_qp_wqes + 1); 2331 qp->qplib_qp.rq.max_sw_wqe = qp->qplib_qp.rq.max_wqe; 2332 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 2333 qp_attr->cap.max_recv_wr; 2334 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge; 2335 } else { 2336 /* SRQ was used prior, just ignore the RQ caps */ 2337 } 2338 } 2339 if (qp_attr_mask & IB_QP_DEST_QPN) { 2340 qp->qplib_qp.modify_flags |= 2341 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID; 2342 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num; 2343 } 2344 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 2345 if (rc) { 2346 ibdev_err(&rdev->ibdev, "Failed to modify HW QP"); 2347 return rc; 2348 } 2349 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) 2350 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask); 2351 return rc; 2352 } 2353 2354 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 2355 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 2356 { 2357 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2358 struct bnxt_re_dev *rdev = qp->rdev; 2359 struct bnxt_qplib_qp *qplib_qp; 2360 int rc; 2361 2362 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL); 2363 if (!qplib_qp) 2364 return -ENOMEM; 2365 2366 qplib_qp->id = qp->qplib_qp.id; 2367 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index; 2368 2369 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp); 2370 if (rc) { 2371 ibdev_err(&rdev->ibdev, "Failed to query HW QP"); 2372 goto out; 2373 } 2374 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state); 2375 qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state); 2376 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0; 2377 qp_attr->qp_access_flags = __qp_access_flags_to_ib(qp->qplib_qp.cctx, 2378 qplib_qp->access); 2379 qp_attr->pkey_index = qplib_qp->pkey_index; 2380 qp_attr->qkey = qplib_qp->qkey; 2381 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2382 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->udp_sport, 2383 qplib_qp->ah.host_sgid_index, 2384 qplib_qp->ah.hop_limit, 2385 qplib_qp->ah.traffic_class); 2386 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data); 2387 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl); 2388 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac); 2389 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu); 2390 qp_attr->timeout = qplib_qp->timeout; 2391 qp_attr->retry_cnt = qplib_qp->retry_cnt; 2392 qp_attr->rnr_retry = qplib_qp->rnr_retry; 2393 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer; 2394 qp_attr->port_num = __to_ib_port_num(qplib_qp->port_id); 2395 qp_attr->rq_psn = qplib_qp->rq.psn; 2396 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic; 2397 qp_attr->sq_psn = qplib_qp->sq.psn; 2398 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic; 2399 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR : 2400 IB_SIGNAL_REQ_WR; 2401 qp_attr->dest_qp_num = qplib_qp->dest_qpn; 2402 2403 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe; 2404 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge; 2405 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe; 2406 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge; 2407 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data; 2408 qp_init_attr->cap = qp_attr->cap; 2409 2410 out: 2411 kfree(qplib_qp); 2412 return rc; 2413 } 2414 2415 /* Routine for sending QP1 packets for RoCE V1 an V2 2416 */ 2417 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp, 2418 const struct ib_send_wr *wr, 2419 struct bnxt_qplib_swqe *wqe, 2420 int payload_size) 2421 { 2422 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, 2423 ib_ah); 2424 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah; 2425 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr; 2426 struct bnxt_qplib_sge sge; 2427 u8 nw_type; 2428 u16 ether_type; 2429 union ib_gid dgid; 2430 bool is_eth = false; 2431 bool is_vlan = false; 2432 bool is_grh = false; 2433 bool is_udp = false; 2434 u8 ip_version = 0; 2435 u16 vlan_id = 0xFFFF; 2436 void *buf; 2437 int i, rc; 2438 2439 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr)); 2440 2441 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL); 2442 if (rc) 2443 return rc; 2444 2445 /* Get network header type for this GID */ 2446 nw_type = rdma_gid_attr_network_type(sgid_attr); 2447 switch (nw_type) { 2448 case RDMA_NETWORK_IPV4: 2449 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET; 2450 break; 2451 case RDMA_NETWORK_IPV6: 2452 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET; 2453 break; 2454 default: 2455 nw_type = BNXT_RE_ROCE_V1_PACKET; 2456 break; 2457 } 2458 memcpy(&dgid.raw, &qplib_ah->dgid, 16); 2459 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 2460 if (is_udp) { 2461 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) { 2462 ip_version = 4; 2463 ether_type = ETH_P_IP; 2464 } else { 2465 ip_version = 6; 2466 ether_type = ETH_P_IPV6; 2467 } 2468 is_grh = false; 2469 } else { 2470 ether_type = ETH_P_IBOE; 2471 is_grh = true; 2472 } 2473 2474 is_eth = true; 2475 is_vlan = vlan_id && (vlan_id < 0x1000); 2476 2477 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh, 2478 ip_version, is_udp, 0, &qp->qp1_hdr); 2479 2480 /* ETH */ 2481 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac); 2482 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac); 2483 2484 /* For vlan, check the sgid for vlan existence */ 2485 2486 if (!is_vlan) { 2487 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type); 2488 } else { 2489 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type); 2490 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id); 2491 } 2492 2493 if (is_grh || (ip_version == 6)) { 2494 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw, 2495 sizeof(sgid_attr->gid)); 2496 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data, 2497 sizeof(sgid_attr->gid)); 2498 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit; 2499 } 2500 2501 if (ip_version == 4) { 2502 qp->qp1_hdr.ip4.tos = 0; 2503 qp->qp1_hdr.ip4.id = 0; 2504 qp->qp1_hdr.ip4.frag_off = htons(IP_DF); 2505 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit; 2506 2507 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4); 2508 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4); 2509 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr); 2510 } 2511 2512 if (is_udp) { 2513 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT); 2514 qp->qp1_hdr.udp.sport = htons(0x8CD1); 2515 qp->qp1_hdr.udp.csum = 0; 2516 } 2517 2518 /* BTH */ 2519 if (wr->opcode == IB_WR_SEND_WITH_IMM) { 2520 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 2521 qp->qp1_hdr.immediate_present = 1; 2522 } else { 2523 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2524 } 2525 if (wr->send_flags & IB_SEND_SOLICITED) 2526 qp->qp1_hdr.bth.solicited_event = 1; 2527 /* pad_count */ 2528 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3; 2529 2530 /* P_key for QP1 is for all members */ 2531 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF); 2532 qp->qp1_hdr.bth.destination_qpn = IB_QP1; 2533 qp->qp1_hdr.bth.ack_req = 0; 2534 qp->send_psn++; 2535 qp->send_psn &= BTH_PSN_MASK; 2536 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn); 2537 /* DETH */ 2538 /* Use the priviledged Q_Key for QP1 */ 2539 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY); 2540 qp->qp1_hdr.deth.source_qpn = IB_QP1; 2541 2542 /* Pack the QP1 to the transmit buffer */ 2543 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge); 2544 if (buf) { 2545 ib_ud_header_pack(&qp->qp1_hdr, buf); 2546 for (i = wqe->num_sge; i; i--) { 2547 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr; 2548 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey; 2549 wqe->sg_list[i].size = wqe->sg_list[i - 1].size; 2550 } 2551 2552 /* 2553 * Max Header buf size for IPV6 RoCE V2 is 86, 2554 * which is same as the QP1 SQ header buffer. 2555 * Header buf size for IPV4 RoCE V2 can be 66. 2556 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20). 2557 * Subtract 20 bytes from QP1 SQ header buf size 2558 */ 2559 if (is_udp && ip_version == 4) 2560 sge.size -= 20; 2561 /* 2562 * Max Header buf size for RoCE V1 is 78. 2563 * ETH(14) + VLAN(4) + GRH(40) + BTH(20). 2564 * Subtract 8 bytes from QP1 SQ header buf size 2565 */ 2566 if (!is_udp) 2567 sge.size -= 8; 2568 2569 /* Subtract 4 bytes for non vlan packets */ 2570 if (!is_vlan) 2571 sge.size -= 4; 2572 2573 wqe->sg_list[0].addr = sge.addr; 2574 wqe->sg_list[0].lkey = sge.lkey; 2575 wqe->sg_list[0].size = sge.size; 2576 wqe->num_sge++; 2577 2578 } else { 2579 ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!"); 2580 rc = -ENOMEM; 2581 } 2582 return rc; 2583 } 2584 2585 /* For the MAD layer, it only provides the recv SGE the size of 2586 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH, 2587 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire 2588 * receive packet (334 bytes) with no VLAN and then copy the GRH 2589 * and the MAD datagram out to the provided SGE. 2590 */ 2591 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp, 2592 const struct ib_recv_wr *wr, 2593 struct bnxt_qplib_swqe *wqe, 2594 int payload_size) 2595 { 2596 struct bnxt_re_sqp_entries *sqp_entry; 2597 struct bnxt_qplib_sge ref, sge; 2598 struct bnxt_re_dev *rdev; 2599 u32 rq_prod_index; 2600 2601 rdev = qp->rdev; 2602 2603 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp); 2604 2605 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge)) 2606 return -ENOMEM; 2607 2608 /* Create 1 SGE to receive the entire 2609 * ethernet packet 2610 */ 2611 /* Save the reference from ULP */ 2612 ref.addr = wqe->sg_list[0].addr; 2613 ref.lkey = wqe->sg_list[0].lkey; 2614 ref.size = wqe->sg_list[0].size; 2615 2616 sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index]; 2617 2618 /* SGE 1 */ 2619 wqe->sg_list[0].addr = sge.addr; 2620 wqe->sg_list[0].lkey = sge.lkey; 2621 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 2622 sge.size -= wqe->sg_list[0].size; 2623 2624 sqp_entry->sge.addr = ref.addr; 2625 sqp_entry->sge.lkey = ref.lkey; 2626 sqp_entry->sge.size = ref.size; 2627 /* Store the wrid for reporting completion */ 2628 sqp_entry->wrid = wqe->wr_id; 2629 /* change the wqe->wrid to table index */ 2630 wqe->wr_id = rq_prod_index; 2631 return 0; 2632 } 2633 2634 static int is_ud_qp(struct bnxt_re_qp *qp) 2635 { 2636 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD || 2637 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI); 2638 } 2639 2640 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp, 2641 const struct ib_send_wr *wr, 2642 struct bnxt_qplib_swqe *wqe) 2643 { 2644 struct bnxt_re_ah *ah = NULL; 2645 2646 if (is_ud_qp(qp)) { 2647 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah); 2648 wqe->send.q_key = ud_wr(wr)->remote_qkey; 2649 wqe->send.dst_qp = ud_wr(wr)->remote_qpn; 2650 wqe->send.avid = ah->qplib_ah.id; 2651 } 2652 switch (wr->opcode) { 2653 case IB_WR_SEND: 2654 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND; 2655 break; 2656 case IB_WR_SEND_WITH_IMM: 2657 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM; 2658 wqe->send.imm_data = be32_to_cpu(wr->ex.imm_data); 2659 break; 2660 case IB_WR_SEND_WITH_INV: 2661 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV; 2662 wqe->send.inv_key = wr->ex.invalidate_rkey; 2663 break; 2664 default: 2665 return -EINVAL; 2666 } 2667 if (wr->send_flags & IB_SEND_SIGNALED) 2668 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2669 if (wr->send_flags & IB_SEND_FENCE) 2670 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2671 if (wr->send_flags & IB_SEND_SOLICITED) 2672 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2673 if (wr->send_flags & IB_SEND_INLINE) 2674 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2675 2676 return 0; 2677 } 2678 2679 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr, 2680 struct bnxt_qplib_swqe *wqe) 2681 { 2682 switch (wr->opcode) { 2683 case IB_WR_RDMA_WRITE: 2684 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE; 2685 break; 2686 case IB_WR_RDMA_WRITE_WITH_IMM: 2687 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM; 2688 wqe->rdma.imm_data = be32_to_cpu(wr->ex.imm_data); 2689 break; 2690 case IB_WR_RDMA_READ: 2691 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ; 2692 wqe->rdma.inv_key = wr->ex.invalidate_rkey; 2693 break; 2694 default: 2695 return -EINVAL; 2696 } 2697 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr; 2698 wqe->rdma.r_key = rdma_wr(wr)->rkey; 2699 if (wr->send_flags & IB_SEND_SIGNALED) 2700 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2701 if (wr->send_flags & IB_SEND_FENCE) 2702 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2703 if (wr->send_flags & IB_SEND_SOLICITED) 2704 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2705 if (wr->send_flags & IB_SEND_INLINE) 2706 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2707 2708 return 0; 2709 } 2710 2711 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr, 2712 struct bnxt_qplib_swqe *wqe) 2713 { 2714 switch (wr->opcode) { 2715 case IB_WR_ATOMIC_CMP_AND_SWP: 2716 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP; 2717 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2718 wqe->atomic.swap_data = atomic_wr(wr)->swap; 2719 break; 2720 case IB_WR_ATOMIC_FETCH_AND_ADD: 2721 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD; 2722 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2723 break; 2724 default: 2725 return -EINVAL; 2726 } 2727 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr; 2728 wqe->atomic.r_key = atomic_wr(wr)->rkey; 2729 if (wr->send_flags & IB_SEND_SIGNALED) 2730 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2731 if (wr->send_flags & IB_SEND_FENCE) 2732 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2733 if (wr->send_flags & IB_SEND_SOLICITED) 2734 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2735 return 0; 2736 } 2737 2738 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr, 2739 struct bnxt_qplib_swqe *wqe) 2740 { 2741 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV; 2742 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey; 2743 2744 if (wr->send_flags & IB_SEND_SIGNALED) 2745 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2746 if (wr->send_flags & IB_SEND_SOLICITED) 2747 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2748 2749 return 0; 2750 } 2751 2752 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr, 2753 struct bnxt_qplib_swqe *wqe) 2754 { 2755 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr); 2756 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl; 2757 int access = wr->access; 2758 2759 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0]; 2760 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0]; 2761 wqe->frmr.page_list = mr->pages; 2762 wqe->frmr.page_list_len = mr->npages; 2763 wqe->frmr.levels = qplib_frpl->hwq.level; 2764 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR; 2765 2766 if (wr->wr.send_flags & IB_SEND_SIGNALED) 2767 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2768 2769 if (access & IB_ACCESS_LOCAL_WRITE) 2770 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE; 2771 if (access & IB_ACCESS_REMOTE_READ) 2772 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ; 2773 if (access & IB_ACCESS_REMOTE_WRITE) 2774 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE; 2775 if (access & IB_ACCESS_REMOTE_ATOMIC) 2776 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC; 2777 if (access & IB_ACCESS_MW_BIND) 2778 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND; 2779 2780 wqe->frmr.l_key = wr->key; 2781 wqe->frmr.length = wr->mr->length; 2782 wqe->frmr.pbl_pg_sz_log = ilog2(PAGE_SIZE >> PAGE_SHIFT_4K); 2783 wqe->frmr.pg_sz_log = ilog2(wr->mr->page_size >> PAGE_SHIFT_4K); 2784 wqe->frmr.va = wr->mr->iova; 2785 return 0; 2786 } 2787 2788 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev, 2789 const struct ib_send_wr *wr, 2790 struct bnxt_qplib_swqe *wqe) 2791 { 2792 /* Copy the inline data to the data field */ 2793 u8 *in_data; 2794 u32 i, sge_len; 2795 void *sge_addr; 2796 2797 in_data = wqe->inline_data; 2798 for (i = 0; i < wr->num_sge; i++) { 2799 sge_addr = (void *)(unsigned long) 2800 wr->sg_list[i].addr; 2801 sge_len = wr->sg_list[i].length; 2802 2803 if ((sge_len + wqe->inline_len) > 2804 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) { 2805 ibdev_err(&rdev->ibdev, 2806 "Inline data size requested > supported value"); 2807 return -EINVAL; 2808 } 2809 sge_len = wr->sg_list[i].length; 2810 2811 memcpy(in_data, sge_addr, sge_len); 2812 in_data += wr->sg_list[i].length; 2813 wqe->inline_len += wr->sg_list[i].length; 2814 } 2815 return wqe->inline_len; 2816 } 2817 2818 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev, 2819 const struct ib_send_wr *wr, 2820 struct bnxt_qplib_swqe *wqe) 2821 { 2822 int payload_sz = 0; 2823 2824 if (wr->send_flags & IB_SEND_INLINE) 2825 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe); 2826 else 2827 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list, 2828 wqe->num_sge); 2829 2830 return payload_sz; 2831 } 2832 2833 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp) 2834 { 2835 if ((qp->ib_qp.qp_type == IB_QPT_UD || 2836 qp->ib_qp.qp_type == IB_QPT_GSI || 2837 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) && 2838 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) { 2839 int qp_attr_mask; 2840 struct ib_qp_attr qp_attr; 2841 2842 qp_attr_mask = IB_QP_STATE; 2843 qp_attr.qp_state = IB_QPS_RTS; 2844 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL); 2845 qp->qplib_qp.wqe_cnt = 0; 2846 } 2847 } 2848 2849 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev, 2850 struct bnxt_re_qp *qp, 2851 const struct ib_send_wr *wr) 2852 { 2853 int rc = 0, payload_sz = 0; 2854 unsigned long flags; 2855 2856 spin_lock_irqsave(&qp->sq_lock, flags); 2857 while (wr) { 2858 struct bnxt_qplib_swqe wqe = {}; 2859 2860 /* Common */ 2861 wqe.num_sge = wr->num_sge; 2862 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2863 ibdev_err(&rdev->ibdev, 2864 "Limit exceeded for Send SGEs"); 2865 rc = -EINVAL; 2866 goto bad; 2867 } 2868 2869 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2870 if (payload_sz < 0) { 2871 rc = -EINVAL; 2872 goto bad; 2873 } 2874 wqe.wr_id = wr->wr_id; 2875 2876 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND; 2877 2878 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2879 if (!rc) 2880 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2881 bad: 2882 if (rc) { 2883 ibdev_err(&rdev->ibdev, 2884 "Post send failed opcode = %#x rc = %d", 2885 wr->opcode, rc); 2886 break; 2887 } 2888 wr = wr->next; 2889 } 2890 bnxt_qplib_post_send_db(&qp->qplib_qp); 2891 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx)) 2892 bnxt_ud_qp_hw_stall_workaround(qp); 2893 spin_unlock_irqrestore(&qp->sq_lock, flags); 2894 return rc; 2895 } 2896 2897 static void bnxt_re_legacy_set_uc_fence(struct bnxt_qplib_swqe *wqe) 2898 { 2899 /* Need unconditional fence for non-wire memory opcode 2900 * to work as expected. 2901 */ 2902 if (wqe->type == BNXT_QPLIB_SWQE_TYPE_LOCAL_INV || 2903 wqe->type == BNXT_QPLIB_SWQE_TYPE_FAST_REG_MR || 2904 wqe->type == BNXT_QPLIB_SWQE_TYPE_REG_MR || 2905 wqe->type == BNXT_QPLIB_SWQE_TYPE_BIND_MW) 2906 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2907 } 2908 2909 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr, 2910 const struct ib_send_wr **bad_wr) 2911 { 2912 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2913 struct bnxt_qplib_swqe wqe; 2914 int rc = 0, payload_sz = 0; 2915 unsigned long flags; 2916 2917 spin_lock_irqsave(&qp->sq_lock, flags); 2918 while (wr) { 2919 /* House keeping */ 2920 memset(&wqe, 0, sizeof(wqe)); 2921 2922 /* Common */ 2923 wqe.num_sge = wr->num_sge; 2924 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2925 ibdev_err(&qp->rdev->ibdev, 2926 "Limit exceeded for Send SGEs"); 2927 rc = -EINVAL; 2928 goto bad; 2929 } 2930 2931 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2932 if (payload_sz < 0) { 2933 rc = -EINVAL; 2934 goto bad; 2935 } 2936 wqe.wr_id = wr->wr_id; 2937 2938 switch (wr->opcode) { 2939 case IB_WR_SEND: 2940 case IB_WR_SEND_WITH_IMM: 2941 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) { 2942 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe, 2943 payload_sz); 2944 if (rc) 2945 goto bad; 2946 wqe.rawqp1.lflags |= 2947 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC; 2948 } 2949 if (wr->send_flags & IB_SEND_IP_CSUM) 2950 wqe.rawqp1.lflags |= 2951 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM; 2952 fallthrough; 2953 case IB_WR_SEND_WITH_INV: 2954 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2955 break; 2956 case IB_WR_RDMA_WRITE: 2957 case IB_WR_RDMA_WRITE_WITH_IMM: 2958 case IB_WR_RDMA_READ: 2959 rc = bnxt_re_build_rdma_wqe(wr, &wqe); 2960 break; 2961 case IB_WR_ATOMIC_CMP_AND_SWP: 2962 case IB_WR_ATOMIC_FETCH_AND_ADD: 2963 rc = bnxt_re_build_atomic_wqe(wr, &wqe); 2964 break; 2965 case IB_WR_RDMA_READ_WITH_INV: 2966 ibdev_err(&qp->rdev->ibdev, 2967 "RDMA Read with Invalidate is not supported"); 2968 rc = -EINVAL; 2969 goto bad; 2970 case IB_WR_LOCAL_INV: 2971 rc = bnxt_re_build_inv_wqe(wr, &wqe); 2972 break; 2973 case IB_WR_REG_MR: 2974 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe); 2975 break; 2976 default: 2977 /* Unsupported WRs */ 2978 ibdev_err(&qp->rdev->ibdev, 2979 "WR (%#x) is not supported", wr->opcode); 2980 rc = -EINVAL; 2981 goto bad; 2982 } 2983 if (!rc) { 2984 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx)) 2985 bnxt_re_legacy_set_uc_fence(&wqe); 2986 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2987 } 2988 bad: 2989 if (rc) { 2990 ibdev_err(&qp->rdev->ibdev, 2991 "post_send failed op:%#x qps = %#x rc = %d\n", 2992 wr->opcode, qp->qplib_qp.state, rc); 2993 *bad_wr = wr; 2994 break; 2995 } 2996 wr = wr->next; 2997 } 2998 bnxt_qplib_post_send_db(&qp->qplib_qp); 2999 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx)) 3000 bnxt_ud_qp_hw_stall_workaround(qp); 3001 spin_unlock_irqrestore(&qp->sq_lock, flags); 3002 3003 return rc; 3004 } 3005 3006 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev, 3007 struct bnxt_re_qp *qp, 3008 const struct ib_recv_wr *wr) 3009 { 3010 struct bnxt_qplib_swqe wqe; 3011 int rc = 0; 3012 3013 while (wr) { 3014 /* House keeping */ 3015 memset(&wqe, 0, sizeof(wqe)); 3016 3017 /* Common */ 3018 wqe.num_sge = wr->num_sge; 3019 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 3020 ibdev_err(&rdev->ibdev, 3021 "Limit exceeded for Receive SGEs"); 3022 rc = -EINVAL; 3023 break; 3024 } 3025 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 3026 wqe.wr_id = wr->wr_id; 3027 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 3028 3029 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 3030 if (rc) 3031 break; 3032 3033 wr = wr->next; 3034 } 3035 if (!rc) 3036 bnxt_qplib_post_recv_db(&qp->qplib_qp); 3037 return rc; 3038 } 3039 3040 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr, 3041 const struct ib_recv_wr **bad_wr) 3042 { 3043 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 3044 struct bnxt_qplib_swqe wqe; 3045 int rc = 0, payload_sz = 0; 3046 unsigned long flags; 3047 u32 count = 0; 3048 3049 spin_lock_irqsave(&qp->rq_lock, flags); 3050 while (wr) { 3051 /* House keeping */ 3052 memset(&wqe, 0, sizeof(wqe)); 3053 3054 /* Common */ 3055 wqe.num_sge = wr->num_sge; 3056 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 3057 ibdev_err(&qp->rdev->ibdev, 3058 "Limit exceeded for Receive SGEs"); 3059 rc = -EINVAL; 3060 *bad_wr = wr; 3061 break; 3062 } 3063 3064 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, 3065 wr->num_sge); 3066 wqe.wr_id = wr->wr_id; 3067 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 3068 3069 if (ib_qp->qp_type == IB_QPT_GSI && 3070 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI) 3071 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe, 3072 payload_sz); 3073 if (!rc) 3074 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 3075 if (rc) { 3076 *bad_wr = wr; 3077 break; 3078 } 3079 3080 /* Ring DB if the RQEs posted reaches a threshold value */ 3081 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) { 3082 bnxt_qplib_post_recv_db(&qp->qplib_qp); 3083 count = 0; 3084 } 3085 3086 wr = wr->next; 3087 } 3088 3089 if (count) 3090 bnxt_qplib_post_recv_db(&qp->qplib_qp); 3091 3092 spin_unlock_irqrestore(&qp->rq_lock, flags); 3093 3094 return rc; 3095 } 3096 3097 static struct bnxt_qplib_nq *bnxt_re_get_nq(struct bnxt_re_dev *rdev) 3098 { 3099 int min, indx; 3100 3101 mutex_lock(&rdev->nqr->load_lock); 3102 for (indx = 0, min = 0; indx < (rdev->nqr->num_msix - 1); indx++) { 3103 if (rdev->nqr->nq[min].load > rdev->nqr->nq[indx].load) 3104 min = indx; 3105 } 3106 rdev->nqr->nq[min].load++; 3107 mutex_unlock(&rdev->nqr->load_lock); 3108 3109 return &rdev->nqr->nq[min]; 3110 } 3111 3112 static void bnxt_re_put_nq(struct bnxt_re_dev *rdev, struct bnxt_qplib_nq *nq) 3113 { 3114 mutex_lock(&rdev->nqr->load_lock); 3115 nq->load--; 3116 mutex_unlock(&rdev->nqr->load_lock); 3117 } 3118 3119 /* Completion Queues */ 3120 int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) 3121 { 3122 struct bnxt_qplib_chip_ctx *cctx; 3123 struct bnxt_qplib_nq *nq; 3124 struct bnxt_re_dev *rdev; 3125 struct bnxt_re_cq *cq; 3126 3127 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3128 rdev = cq->rdev; 3129 nq = cq->qplib_cq.nq; 3130 cctx = rdev->chip_ctx; 3131 3132 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) { 3133 free_page((unsigned long)cq->uctx_cq_page); 3134 hash_del(&cq->hash_entry); 3135 } 3136 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 3137 3138 bnxt_re_put_nq(rdev, nq); 3139 ib_umem_release(cq->umem); 3140 3141 atomic_dec(&rdev->stats.res.cq_count); 3142 kfree(cq->cql); 3143 return 0; 3144 } 3145 3146 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 3147 struct uverbs_attr_bundle *attrs) 3148 { 3149 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 3150 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev); 3151 struct ib_udata *udata = &attrs->driver_udata; 3152 struct bnxt_re_ucontext *uctx = 3153 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 3154 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 3155 struct bnxt_qplib_chip_ctx *cctx; 3156 int cqe = attr->cqe; 3157 int rc, entries; 3158 u32 active_cqs; 3159 3160 if (attr->flags) 3161 return -EOPNOTSUPP; 3162 3163 /* Validate CQ fields */ 3164 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 3165 ibdev_err(&rdev->ibdev, "Failed to create CQ -max exceeded"); 3166 return -EINVAL; 3167 } 3168 3169 cq->rdev = rdev; 3170 cctx = rdev->chip_ctx; 3171 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq); 3172 3173 entries = bnxt_re_init_depth(cqe + 1, uctx); 3174 if (entries > dev_attr->max_cq_wqes + 1) 3175 entries = dev_attr->max_cq_wqes + 1; 3176 3177 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE; 3178 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT; 3179 if (udata) { 3180 struct bnxt_re_cq_req req; 3181 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 3182 rc = -EFAULT; 3183 goto fail; 3184 } 3185 3186 cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va, 3187 entries * sizeof(struct cq_base), 3188 IB_ACCESS_LOCAL_WRITE); 3189 if (IS_ERR(cq->umem)) { 3190 rc = PTR_ERR(cq->umem); 3191 goto fail; 3192 } 3193 cq->qplib_cq.sg_info.umem = cq->umem; 3194 cq->qplib_cq.dpi = &uctx->dpi; 3195 } else { 3196 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL); 3197 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe), 3198 GFP_KERNEL); 3199 if (!cq->cql) { 3200 rc = -ENOMEM; 3201 goto fail; 3202 } 3203 3204 cq->qplib_cq.dpi = &rdev->dpi_privileged; 3205 } 3206 cq->qplib_cq.max_wqe = entries; 3207 cq->qplib_cq.coalescing = &rdev->cq_coalescing; 3208 cq->qplib_cq.nq = bnxt_re_get_nq(rdev); 3209 cq->qplib_cq.cnq_hw_ring_id = cq->qplib_cq.nq->ring_id; 3210 3211 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq); 3212 if (rc) { 3213 ibdev_err(&rdev->ibdev, "Failed to create HW CQ"); 3214 goto fail; 3215 } 3216 3217 cq->ib_cq.cqe = entries; 3218 cq->cq_period = cq->qplib_cq.period; 3219 3220 active_cqs = atomic_inc_return(&rdev->stats.res.cq_count); 3221 if (active_cqs > rdev->stats.res.cq_watermark) 3222 rdev->stats.res.cq_watermark = active_cqs; 3223 spin_lock_init(&cq->cq_lock); 3224 3225 if (udata) { 3226 struct bnxt_re_cq_resp resp = {}; 3227 3228 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) { 3229 hash_add(rdev->cq_hash, &cq->hash_entry, cq->qplib_cq.id); 3230 /* Allocate a page */ 3231 cq->uctx_cq_page = (void *)get_zeroed_page(GFP_KERNEL); 3232 if (!cq->uctx_cq_page) { 3233 rc = -ENOMEM; 3234 goto c2fail; 3235 } 3236 resp.comp_mask |= BNXT_RE_CQ_TOGGLE_PAGE_SUPPORT; 3237 } 3238 resp.cqid = cq->qplib_cq.id; 3239 resp.tail = cq->qplib_cq.hwq.cons; 3240 resp.phase = cq->qplib_cq.period; 3241 resp.rsvd = 0; 3242 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen)); 3243 if (rc) { 3244 ibdev_err(&rdev->ibdev, "Failed to copy CQ udata"); 3245 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 3246 goto free_mem; 3247 } 3248 } 3249 3250 return 0; 3251 3252 free_mem: 3253 free_page((unsigned long)cq->uctx_cq_page); 3254 c2fail: 3255 ib_umem_release(cq->umem); 3256 fail: 3257 kfree(cq->cql); 3258 return rc; 3259 } 3260 3261 static void bnxt_re_resize_cq_complete(struct bnxt_re_cq *cq) 3262 { 3263 struct bnxt_re_dev *rdev = cq->rdev; 3264 3265 bnxt_qplib_resize_cq_complete(&rdev->qplib_res, &cq->qplib_cq); 3266 3267 cq->qplib_cq.max_wqe = cq->resize_cqe; 3268 if (cq->resize_umem) { 3269 ib_umem_release(cq->umem); 3270 cq->umem = cq->resize_umem; 3271 cq->resize_umem = NULL; 3272 cq->resize_cqe = 0; 3273 } 3274 } 3275 3276 int bnxt_re_resize_cq(struct ib_cq *ibcq, int cqe, struct ib_udata *udata) 3277 { 3278 struct bnxt_qplib_sg_info sg_info = {}; 3279 struct bnxt_qplib_dpi *orig_dpi = NULL; 3280 struct bnxt_qplib_dev_attr *dev_attr; 3281 struct bnxt_re_ucontext *uctx = NULL; 3282 struct bnxt_re_resize_cq_req req; 3283 struct bnxt_re_dev *rdev; 3284 struct bnxt_re_cq *cq; 3285 int rc, entries; 3286 3287 cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 3288 rdev = cq->rdev; 3289 dev_attr = rdev->dev_attr; 3290 if (!ibcq->uobject) { 3291 ibdev_err(&rdev->ibdev, "Kernel CQ Resize not supported"); 3292 return -EOPNOTSUPP; 3293 } 3294 3295 if (cq->resize_umem) { 3296 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - Busy", 3297 cq->qplib_cq.id); 3298 return -EBUSY; 3299 } 3300 3301 /* Check the requested cq depth out of supported depth */ 3302 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 3303 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - out of range cqe %d", 3304 cq->qplib_cq.id, cqe); 3305 return -EINVAL; 3306 } 3307 3308 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 3309 entries = bnxt_re_init_depth(cqe + 1, uctx); 3310 if (entries > dev_attr->max_cq_wqes + 1) 3311 entries = dev_attr->max_cq_wqes + 1; 3312 3313 /* uverbs consumer */ 3314 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 3315 rc = -EFAULT; 3316 goto fail; 3317 } 3318 3319 cq->resize_umem = ib_umem_get(&rdev->ibdev, req.cq_va, 3320 entries * sizeof(struct cq_base), 3321 IB_ACCESS_LOCAL_WRITE); 3322 if (IS_ERR(cq->resize_umem)) { 3323 rc = PTR_ERR(cq->resize_umem); 3324 ibdev_err(&rdev->ibdev, "%s: ib_umem_get failed! rc = %pe\n", 3325 __func__, cq->resize_umem); 3326 cq->resize_umem = NULL; 3327 goto fail; 3328 } 3329 cq->resize_cqe = entries; 3330 memcpy(&sg_info, &cq->qplib_cq.sg_info, sizeof(sg_info)); 3331 orig_dpi = cq->qplib_cq.dpi; 3332 3333 cq->qplib_cq.sg_info.umem = cq->resize_umem; 3334 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE; 3335 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT; 3336 cq->qplib_cq.dpi = &uctx->dpi; 3337 3338 rc = bnxt_qplib_resize_cq(&rdev->qplib_res, &cq->qplib_cq, entries); 3339 if (rc) { 3340 ibdev_err(&rdev->ibdev, "Resize HW CQ %#x failed!", 3341 cq->qplib_cq.id); 3342 goto fail; 3343 } 3344 3345 cq->ib_cq.cqe = cq->resize_cqe; 3346 atomic_inc(&rdev->stats.res.resize_count); 3347 3348 return 0; 3349 3350 fail: 3351 if (cq->resize_umem) { 3352 ib_umem_release(cq->resize_umem); 3353 cq->resize_umem = NULL; 3354 cq->resize_cqe = 0; 3355 memcpy(&cq->qplib_cq.sg_info, &sg_info, sizeof(sg_info)); 3356 cq->qplib_cq.dpi = orig_dpi; 3357 } 3358 return rc; 3359 } 3360 3361 static u8 __req_to_ib_wc_status(u8 qstatus) 3362 { 3363 switch (qstatus) { 3364 case CQ_REQ_STATUS_OK: 3365 return IB_WC_SUCCESS; 3366 case CQ_REQ_STATUS_BAD_RESPONSE_ERR: 3367 return IB_WC_BAD_RESP_ERR; 3368 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR: 3369 return IB_WC_LOC_LEN_ERR; 3370 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR: 3371 return IB_WC_LOC_QP_OP_ERR; 3372 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR: 3373 return IB_WC_LOC_PROT_ERR; 3374 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR: 3375 return IB_WC_GENERAL_ERR; 3376 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR: 3377 return IB_WC_REM_INV_REQ_ERR; 3378 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR: 3379 return IB_WC_REM_ACCESS_ERR; 3380 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR: 3381 return IB_WC_REM_OP_ERR; 3382 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR: 3383 return IB_WC_RNR_RETRY_EXC_ERR; 3384 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR: 3385 return IB_WC_RETRY_EXC_ERR; 3386 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR: 3387 return IB_WC_WR_FLUSH_ERR; 3388 default: 3389 return IB_WC_GENERAL_ERR; 3390 } 3391 return 0; 3392 } 3393 3394 static u8 __rawqp1_to_ib_wc_status(u8 qstatus) 3395 { 3396 switch (qstatus) { 3397 case CQ_RES_RAWETH_QP1_STATUS_OK: 3398 return IB_WC_SUCCESS; 3399 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR: 3400 return IB_WC_LOC_ACCESS_ERR; 3401 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR: 3402 return IB_WC_LOC_LEN_ERR; 3403 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR: 3404 return IB_WC_LOC_PROT_ERR; 3405 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR: 3406 return IB_WC_LOC_QP_OP_ERR; 3407 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR: 3408 return IB_WC_GENERAL_ERR; 3409 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR: 3410 return IB_WC_WR_FLUSH_ERR; 3411 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR: 3412 return IB_WC_WR_FLUSH_ERR; 3413 default: 3414 return IB_WC_GENERAL_ERR; 3415 } 3416 } 3417 3418 static u8 __rc_to_ib_wc_status(u8 qstatus) 3419 { 3420 switch (qstatus) { 3421 case CQ_RES_RC_STATUS_OK: 3422 return IB_WC_SUCCESS; 3423 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR: 3424 return IB_WC_LOC_ACCESS_ERR; 3425 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR: 3426 return IB_WC_LOC_LEN_ERR; 3427 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR: 3428 return IB_WC_LOC_PROT_ERR; 3429 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR: 3430 return IB_WC_LOC_QP_OP_ERR; 3431 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR: 3432 return IB_WC_GENERAL_ERR; 3433 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR: 3434 return IB_WC_REM_INV_REQ_ERR; 3435 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR: 3436 return IB_WC_WR_FLUSH_ERR; 3437 case CQ_RES_RC_STATUS_HW_FLUSH_ERR: 3438 return IB_WC_WR_FLUSH_ERR; 3439 default: 3440 return IB_WC_GENERAL_ERR; 3441 } 3442 } 3443 3444 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe) 3445 { 3446 switch (cqe->type) { 3447 case BNXT_QPLIB_SWQE_TYPE_SEND: 3448 wc->opcode = IB_WC_SEND; 3449 break; 3450 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM: 3451 wc->opcode = IB_WC_SEND; 3452 wc->wc_flags |= IB_WC_WITH_IMM; 3453 break; 3454 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV: 3455 wc->opcode = IB_WC_SEND; 3456 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3457 break; 3458 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE: 3459 wc->opcode = IB_WC_RDMA_WRITE; 3460 break; 3461 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM: 3462 wc->opcode = IB_WC_RDMA_WRITE; 3463 wc->wc_flags |= IB_WC_WITH_IMM; 3464 break; 3465 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ: 3466 wc->opcode = IB_WC_RDMA_READ; 3467 break; 3468 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP: 3469 wc->opcode = IB_WC_COMP_SWAP; 3470 break; 3471 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD: 3472 wc->opcode = IB_WC_FETCH_ADD; 3473 break; 3474 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV: 3475 wc->opcode = IB_WC_LOCAL_INV; 3476 break; 3477 case BNXT_QPLIB_SWQE_TYPE_REG_MR: 3478 wc->opcode = IB_WC_REG_MR; 3479 break; 3480 default: 3481 wc->opcode = IB_WC_SEND; 3482 break; 3483 } 3484 3485 wc->status = __req_to_ib_wc_status(cqe->status); 3486 } 3487 3488 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags, 3489 u16 raweth_qp1_flags2) 3490 { 3491 bool is_ipv6 = false, is_ipv4 = false; 3492 3493 /* raweth_qp1_flags Bit 9-6 indicates itype */ 3494 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 3495 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 3496 return -1; 3497 3498 if (raweth_qp1_flags2 & 3499 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC && 3500 raweth_qp1_flags2 & 3501 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) { 3502 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */ 3503 (raweth_qp1_flags2 & 3504 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ? 3505 (is_ipv6 = true) : (is_ipv4 = true); 3506 return ((is_ipv6) ? 3507 BNXT_RE_ROCEV2_IPV6_PACKET : 3508 BNXT_RE_ROCEV2_IPV4_PACKET); 3509 } else { 3510 return BNXT_RE_ROCE_V1_PACKET; 3511 } 3512 } 3513 3514 static int bnxt_re_to_ib_nw_type(int nw_type) 3515 { 3516 u8 nw_hdr_type = 0xFF; 3517 3518 switch (nw_type) { 3519 case BNXT_RE_ROCE_V1_PACKET: 3520 nw_hdr_type = RDMA_NETWORK_ROCE_V1; 3521 break; 3522 case BNXT_RE_ROCEV2_IPV4_PACKET: 3523 nw_hdr_type = RDMA_NETWORK_IPV4; 3524 break; 3525 case BNXT_RE_ROCEV2_IPV6_PACKET: 3526 nw_hdr_type = RDMA_NETWORK_IPV6; 3527 break; 3528 } 3529 return nw_hdr_type; 3530 } 3531 3532 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev, 3533 void *rq_hdr_buf) 3534 { 3535 u8 *tmp_buf = NULL; 3536 struct ethhdr *eth_hdr; 3537 u16 eth_type; 3538 bool rc = false; 3539 3540 tmp_buf = (u8 *)rq_hdr_buf; 3541 /* 3542 * If dest mac is not same as I/F mac, this could be a 3543 * loopback address or multicast address, check whether 3544 * it is a loopback packet 3545 */ 3546 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) { 3547 tmp_buf += 4; 3548 /* Check the ether type */ 3549 eth_hdr = (struct ethhdr *)tmp_buf; 3550 eth_type = ntohs(eth_hdr->h_proto); 3551 switch (eth_type) { 3552 case ETH_P_IBOE: 3553 rc = true; 3554 break; 3555 case ETH_P_IP: 3556 case ETH_P_IPV6: { 3557 u32 len; 3558 struct udphdr *udp_hdr; 3559 3560 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) : 3561 sizeof(struct ipv6hdr)); 3562 tmp_buf += sizeof(struct ethhdr) + len; 3563 udp_hdr = (struct udphdr *)tmp_buf; 3564 if (ntohs(udp_hdr->dest) == 3565 ROCE_V2_UDP_DPORT) 3566 rc = true; 3567 break; 3568 } 3569 default: 3570 break; 3571 } 3572 } 3573 3574 return rc; 3575 } 3576 3577 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp, 3578 struct bnxt_qplib_cqe *cqe) 3579 { 3580 struct bnxt_re_dev *rdev = gsi_qp->rdev; 3581 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3582 struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp; 3583 dma_addr_t shrq_hdr_buf_map; 3584 struct ib_sge s_sge[2] = {}; 3585 struct ib_sge r_sge[2] = {}; 3586 struct bnxt_re_ah *gsi_sah; 3587 struct ib_recv_wr rwr = {}; 3588 dma_addr_t rq_hdr_buf_map; 3589 struct ib_ud_wr udwr = {}; 3590 struct ib_send_wr *swr; 3591 u32 skip_bytes = 0; 3592 int pkt_type = 0; 3593 void *rq_hdr_buf; 3594 u32 offset = 0; 3595 u32 tbl_idx; 3596 int rc; 3597 3598 swr = &udwr.wr; 3599 tbl_idx = cqe->wr_id; 3600 3601 rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf + 3602 (tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size); 3603 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp, 3604 tbl_idx); 3605 3606 /* Shadow QP header buffer */ 3607 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp, 3608 tbl_idx); 3609 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3610 3611 /* Store this cqe */ 3612 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe)); 3613 sqp_entry->qp1_qp = gsi_qp; 3614 3615 /* Find packet type from the cqe */ 3616 3617 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags, 3618 cqe->raweth_qp1_flags2); 3619 if (pkt_type < 0) { 3620 ibdev_err(&rdev->ibdev, "Invalid packet\n"); 3621 return -EINVAL; 3622 } 3623 3624 /* Adjust the offset for the user buffer and post in the rq */ 3625 3626 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET) 3627 offset = 20; 3628 3629 /* 3630 * QP1 loopback packet has 4 bytes of internal header before 3631 * ether header. Skip these four bytes. 3632 */ 3633 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf)) 3634 skip_bytes = 4; 3635 3636 /* First send SGE . Skip the ether header*/ 3637 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE 3638 + skip_bytes; 3639 s_sge[0].lkey = 0xFFFFFFFF; 3640 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 : 3641 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 3642 3643 /* Second Send SGE */ 3644 s_sge[1].addr = s_sge[0].addr + s_sge[0].length + 3645 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE; 3646 if (pkt_type != BNXT_RE_ROCE_V1_PACKET) 3647 s_sge[1].addr += 8; 3648 s_sge[1].lkey = 0xFFFFFFFF; 3649 s_sge[1].length = 256; 3650 3651 /* First recv SGE */ 3652 3653 r_sge[0].addr = shrq_hdr_buf_map; 3654 r_sge[0].lkey = 0xFFFFFFFF; 3655 r_sge[0].length = 40; 3656 3657 r_sge[1].addr = sqp_entry->sge.addr + offset; 3658 r_sge[1].lkey = sqp_entry->sge.lkey; 3659 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset; 3660 3661 /* Create receive work request */ 3662 rwr.num_sge = 2; 3663 rwr.sg_list = r_sge; 3664 rwr.wr_id = tbl_idx; 3665 rwr.next = NULL; 3666 3667 rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr); 3668 if (rc) { 3669 ibdev_err(&rdev->ibdev, 3670 "Failed to post Rx buffers to shadow QP"); 3671 return -ENOMEM; 3672 } 3673 3674 swr->num_sge = 2; 3675 swr->sg_list = s_sge; 3676 swr->wr_id = tbl_idx; 3677 swr->opcode = IB_WR_SEND; 3678 swr->next = NULL; 3679 gsi_sah = rdev->gsi_ctx.gsi_sah; 3680 udwr.ah = &gsi_sah->ib_ah; 3681 udwr.remote_qpn = gsi_sqp->qplib_qp.id; 3682 udwr.remote_qkey = gsi_sqp->qplib_qp.qkey; 3683 3684 /* post data received in the send queue */ 3685 return bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr); 3686 } 3687 3688 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc, 3689 struct bnxt_qplib_cqe *cqe) 3690 { 3691 wc->opcode = IB_WC_RECV; 3692 wc->status = __rawqp1_to_ib_wc_status(cqe->status); 3693 wc->wc_flags |= IB_WC_GRH; 3694 } 3695 3696 static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev, 3697 u16 vlan_id) 3698 { 3699 /* 3700 * Check if the vlan is configured in the host. If not configured, it 3701 * can be a transparent VLAN. So dont report the vlan id. 3702 */ 3703 if (!__vlan_find_dev_deep_rcu(rdev->netdev, 3704 htons(ETH_P_8021Q), vlan_id)) 3705 return false; 3706 return true; 3707 } 3708 3709 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe, 3710 u16 *vid, u8 *sl) 3711 { 3712 bool ret = false; 3713 u32 metadata; 3714 u16 tpid; 3715 3716 metadata = orig_cqe->raweth_qp1_metadata; 3717 if (orig_cqe->raweth_qp1_flags2 & 3718 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) { 3719 tpid = ((metadata & 3720 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >> 3721 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT); 3722 if (tpid == ETH_P_8021Q) { 3723 *vid = metadata & 3724 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK; 3725 *sl = (metadata & 3726 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >> 3727 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT; 3728 ret = true; 3729 } 3730 } 3731 3732 return ret; 3733 } 3734 3735 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc, 3736 struct bnxt_qplib_cqe *cqe) 3737 { 3738 wc->opcode = IB_WC_RECV; 3739 wc->status = __rc_to_ib_wc_status(cqe->status); 3740 3741 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 3742 wc->wc_flags |= IB_WC_WITH_IMM; 3743 if (cqe->flags & CQ_RES_RC_FLAGS_INV) 3744 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3745 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) == 3746 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) 3747 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 3748 } 3749 3750 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp, 3751 struct ib_wc *wc, 3752 struct bnxt_qplib_cqe *cqe) 3753 { 3754 struct bnxt_re_dev *rdev = gsi_sqp->rdev; 3755 struct bnxt_re_qp *gsi_qp = NULL; 3756 struct bnxt_qplib_cqe *orig_cqe = NULL; 3757 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3758 int nw_type; 3759 u32 tbl_idx; 3760 u16 vlan_id; 3761 u8 sl; 3762 3763 tbl_idx = cqe->wr_id; 3764 3765 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3766 gsi_qp = sqp_entry->qp1_qp; 3767 orig_cqe = &sqp_entry->cqe; 3768 3769 wc->wr_id = sqp_entry->wrid; 3770 wc->byte_len = orig_cqe->length; 3771 wc->qp = &gsi_qp->ib_qp; 3772 3773 wc->ex.imm_data = cpu_to_be32(orig_cqe->immdata); 3774 wc->src_qp = orig_cqe->src_qp; 3775 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN); 3776 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) { 3777 if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) { 3778 wc->vlan_id = vlan_id; 3779 wc->sl = sl; 3780 wc->wc_flags |= IB_WC_WITH_VLAN; 3781 } 3782 } 3783 wc->port_num = 1; 3784 wc->vendor_err = orig_cqe->status; 3785 3786 wc->opcode = IB_WC_RECV; 3787 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status); 3788 wc->wc_flags |= IB_WC_GRH; 3789 3790 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags, 3791 orig_cqe->raweth_qp1_flags2); 3792 if (nw_type >= 0) { 3793 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3794 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3795 } 3796 } 3797 3798 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp, 3799 struct ib_wc *wc, 3800 struct bnxt_qplib_cqe *cqe) 3801 { 3802 struct bnxt_re_dev *rdev; 3803 u16 vlan_id = 0; 3804 u8 nw_type; 3805 3806 rdev = qp->rdev; 3807 wc->opcode = IB_WC_RECV; 3808 wc->status = __rc_to_ib_wc_status(cqe->status); 3809 3810 if (cqe->flags & CQ_RES_UD_FLAGS_IMM) 3811 wc->wc_flags |= IB_WC_WITH_IMM; 3812 /* report only on GSI QP for Thor */ 3813 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) { 3814 wc->wc_flags |= IB_WC_GRH; 3815 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3816 wc->wc_flags |= IB_WC_WITH_SMAC; 3817 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) { 3818 vlan_id = (cqe->cfa_meta & 0xFFF); 3819 } 3820 /* Mark only if vlan_id is non zero */ 3821 if (vlan_id && bnxt_re_check_if_vlan_valid(rdev, vlan_id)) { 3822 wc->vlan_id = vlan_id; 3823 wc->wc_flags |= IB_WC_WITH_VLAN; 3824 } 3825 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >> 3826 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT; 3827 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3828 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3829 } 3830 3831 } 3832 3833 static int send_phantom_wqe(struct bnxt_re_qp *qp) 3834 { 3835 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp; 3836 unsigned long flags; 3837 int rc; 3838 3839 spin_lock_irqsave(&qp->sq_lock, flags); 3840 3841 rc = bnxt_re_bind_fence_mw(lib_qp); 3842 if (!rc) { 3843 lib_qp->sq.phantom_wqe_cnt++; 3844 ibdev_dbg(&qp->rdev->ibdev, 3845 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n", 3846 lib_qp->id, lib_qp->sq.hwq.prod, 3847 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq), 3848 lib_qp->sq.phantom_wqe_cnt); 3849 } 3850 3851 spin_unlock_irqrestore(&qp->sq_lock, flags); 3852 return rc; 3853 } 3854 3855 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc) 3856 { 3857 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3858 struct bnxt_re_qp *qp, *sh_qp; 3859 struct bnxt_qplib_cqe *cqe; 3860 int i, ncqe, budget; 3861 struct bnxt_qplib_q *sq; 3862 struct bnxt_qplib_qp *lib_qp; 3863 u32 tbl_idx; 3864 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3865 unsigned long flags; 3866 3867 /* User CQ; the only processing we do is to 3868 * complete any pending CQ resize operation. 3869 */ 3870 if (cq->umem) { 3871 if (cq->resize_umem) 3872 bnxt_re_resize_cq_complete(cq); 3873 return 0; 3874 } 3875 3876 spin_lock_irqsave(&cq->cq_lock, flags); 3877 budget = min_t(u32, num_entries, cq->max_cql); 3878 num_entries = budget; 3879 if (!cq->cql) { 3880 ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use"); 3881 goto exit; 3882 } 3883 cqe = &cq->cql[0]; 3884 while (budget) { 3885 lib_qp = NULL; 3886 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp); 3887 if (lib_qp) { 3888 sq = &lib_qp->sq; 3889 if (sq->send_phantom) { 3890 qp = container_of(lib_qp, 3891 struct bnxt_re_qp, qplib_qp); 3892 if (send_phantom_wqe(qp) == -ENOMEM) 3893 ibdev_err(&cq->rdev->ibdev, 3894 "Phantom failed! Scheduled to send again\n"); 3895 else 3896 sq->send_phantom = false; 3897 } 3898 } 3899 if (ncqe < budget) 3900 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq, 3901 cqe + ncqe, 3902 budget - ncqe); 3903 3904 if (!ncqe) 3905 break; 3906 3907 for (i = 0; i < ncqe; i++, cqe++) { 3908 /* Transcribe each qplib_wqe back to ib_wc */ 3909 memset(wc, 0, sizeof(*wc)); 3910 3911 wc->wr_id = cqe->wr_id; 3912 wc->byte_len = cqe->length; 3913 qp = container_of 3914 ((struct bnxt_qplib_qp *) 3915 (unsigned long)(cqe->qp_handle), 3916 struct bnxt_re_qp, qplib_qp); 3917 wc->qp = &qp->ib_qp; 3918 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 3919 wc->ex.imm_data = cpu_to_be32(cqe->immdata); 3920 else 3921 wc->ex.invalidate_rkey = cqe->invrkey; 3922 wc->src_qp = cqe->src_qp; 3923 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3924 wc->port_num = 1; 3925 wc->vendor_err = cqe->status; 3926 3927 switch (cqe->opcode) { 3928 case CQ_BASE_CQE_TYPE_REQ: 3929 sh_qp = qp->rdev->gsi_ctx.gsi_sqp; 3930 if (sh_qp && 3931 qp->qplib_qp.id == sh_qp->qplib_qp.id) { 3932 /* Handle this completion with 3933 * the stored completion 3934 */ 3935 memset(wc, 0, sizeof(*wc)); 3936 continue; 3937 } 3938 bnxt_re_process_req_wc(wc, cqe); 3939 break; 3940 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1: 3941 if (!cqe->status) { 3942 int rc = 0; 3943 3944 rc = bnxt_re_process_raw_qp_pkt_rx 3945 (qp, cqe); 3946 if (!rc) { 3947 memset(wc, 0, sizeof(*wc)); 3948 continue; 3949 } 3950 cqe->status = -1; 3951 } 3952 /* Errors need not be looped back. 3953 * But change the wr_id to the one 3954 * stored in the table 3955 */ 3956 tbl_idx = cqe->wr_id; 3957 sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3958 wc->wr_id = sqp_entry->wrid; 3959 bnxt_re_process_res_rawqp1_wc(wc, cqe); 3960 break; 3961 case CQ_BASE_CQE_TYPE_RES_RC: 3962 bnxt_re_process_res_rc_wc(wc, cqe); 3963 break; 3964 case CQ_BASE_CQE_TYPE_RES_UD: 3965 sh_qp = qp->rdev->gsi_ctx.gsi_sqp; 3966 if (sh_qp && 3967 qp->qplib_qp.id == sh_qp->qplib_qp.id) { 3968 /* Handle this completion with 3969 * the stored completion 3970 */ 3971 if (cqe->status) { 3972 continue; 3973 } else { 3974 bnxt_re_process_res_shadow_qp_wc 3975 (qp, wc, cqe); 3976 break; 3977 } 3978 } 3979 bnxt_re_process_res_ud_wc(qp, wc, cqe); 3980 break; 3981 default: 3982 ibdev_err(&cq->rdev->ibdev, 3983 "POLL CQ : type 0x%x not handled", 3984 cqe->opcode); 3985 continue; 3986 } 3987 wc++; 3988 budget--; 3989 } 3990 } 3991 exit: 3992 spin_unlock_irqrestore(&cq->cq_lock, flags); 3993 return num_entries - budget; 3994 } 3995 3996 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq, 3997 enum ib_cq_notify_flags ib_cqn_flags) 3998 { 3999 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 4000 int type = 0, rc = 0; 4001 unsigned long flags; 4002 4003 spin_lock_irqsave(&cq->cq_lock, flags); 4004 /* Trigger on the very next completion */ 4005 if (ib_cqn_flags & IB_CQ_NEXT_COMP) 4006 type = DBC_DBC_TYPE_CQ_ARMALL; 4007 /* Trigger on the next solicited completion */ 4008 else if (ib_cqn_flags & IB_CQ_SOLICITED) 4009 type = DBC_DBC_TYPE_CQ_ARMSE; 4010 4011 /* Poll to see if there are missed events */ 4012 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) && 4013 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) { 4014 rc = 1; 4015 goto exit; 4016 } 4017 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type); 4018 4019 exit: 4020 spin_unlock_irqrestore(&cq->cq_lock, flags); 4021 return rc; 4022 } 4023 4024 /* Memory Regions */ 4025 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags) 4026 { 4027 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4028 struct bnxt_re_dev *rdev = pd->rdev; 4029 struct bnxt_re_mr *mr; 4030 u32 active_mrs; 4031 int rc; 4032 4033 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 4034 if (!mr) 4035 return ERR_PTR(-ENOMEM); 4036 4037 mr->rdev = rdev; 4038 mr->qplib_mr.pd = &pd->qplib_pd; 4039 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags); 4040 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 4041 4042 if (mr_access_flags & IB_ACCESS_RELAXED_ORDERING) 4043 bnxt_re_check_and_set_relaxed_ordering(rdev, &mr->qplib_mr); 4044 4045 /* Allocate and register 0 as the address */ 4046 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 4047 if (rc) 4048 goto fail; 4049 4050 mr->qplib_mr.hwq.level = PBL_LVL_MAX; 4051 mr->qplib_mr.total_size = -1; /* Infinte length */ 4052 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 0, 4053 PAGE_SIZE, false); 4054 if (rc) 4055 goto fail_mr; 4056 4057 mr->ib_mr.lkey = mr->qplib_mr.lkey; 4058 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ | 4059 IB_ACCESS_REMOTE_ATOMIC)) 4060 mr->ib_mr.rkey = mr->ib_mr.lkey; 4061 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 4062 if (active_mrs > rdev->stats.res.mr_watermark) 4063 rdev->stats.res.mr_watermark = active_mrs; 4064 4065 return &mr->ib_mr; 4066 4067 fail_mr: 4068 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 4069 fail: 4070 kfree(mr); 4071 return ERR_PTR(rc); 4072 } 4073 4074 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata) 4075 { 4076 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 4077 struct bnxt_re_dev *rdev = mr->rdev; 4078 int rc; 4079 4080 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 4081 if (rc) { 4082 ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc); 4083 return rc; 4084 } 4085 4086 if (mr->pages) { 4087 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res, 4088 &mr->qplib_frpl); 4089 kfree(mr->pages); 4090 mr->npages = 0; 4091 mr->pages = NULL; 4092 } 4093 ib_umem_release(mr->ib_umem); 4094 4095 kfree(mr); 4096 atomic_dec(&rdev->stats.res.mr_count); 4097 return rc; 4098 } 4099 4100 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr) 4101 { 4102 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 4103 4104 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs)) 4105 return -ENOMEM; 4106 4107 mr->pages[mr->npages++] = addr; 4108 return 0; 4109 } 4110 4111 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents, 4112 unsigned int *sg_offset) 4113 { 4114 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 4115 4116 mr->npages = 0; 4117 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page); 4118 } 4119 4120 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type, 4121 u32 max_num_sg) 4122 { 4123 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4124 struct bnxt_re_dev *rdev = pd->rdev; 4125 struct bnxt_re_mr *mr = NULL; 4126 u32 active_mrs; 4127 int rc; 4128 4129 if (type != IB_MR_TYPE_MEM_REG) { 4130 ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type); 4131 return ERR_PTR(-EINVAL); 4132 } 4133 if (max_num_sg > MAX_PBL_LVL_1_PGS) 4134 return ERR_PTR(-EINVAL); 4135 4136 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 4137 if (!mr) 4138 return ERR_PTR(-ENOMEM); 4139 4140 mr->rdev = rdev; 4141 mr->qplib_mr.pd = &pd->qplib_pd; 4142 mr->qplib_mr.access_flags = BNXT_QPLIB_FR_PMR; 4143 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 4144 4145 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 4146 if (rc) 4147 goto bail; 4148 4149 mr->ib_mr.lkey = mr->qplib_mr.lkey; 4150 mr->ib_mr.rkey = mr->ib_mr.lkey; 4151 4152 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL); 4153 if (!mr->pages) { 4154 rc = -ENOMEM; 4155 goto fail; 4156 } 4157 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res, 4158 &mr->qplib_frpl, max_num_sg); 4159 if (rc) { 4160 ibdev_err(&rdev->ibdev, 4161 "Failed to allocate HW FR page list"); 4162 goto fail_mr; 4163 } 4164 4165 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 4166 if (active_mrs > rdev->stats.res.mr_watermark) 4167 rdev->stats.res.mr_watermark = active_mrs; 4168 return &mr->ib_mr; 4169 4170 fail_mr: 4171 kfree(mr->pages); 4172 fail: 4173 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 4174 bail: 4175 kfree(mr); 4176 return ERR_PTR(rc); 4177 } 4178 4179 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type, 4180 struct ib_udata *udata) 4181 { 4182 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4183 struct bnxt_re_dev *rdev = pd->rdev; 4184 struct bnxt_re_mw *mw; 4185 u32 active_mws; 4186 int rc; 4187 4188 mw = kzalloc(sizeof(*mw), GFP_KERNEL); 4189 if (!mw) 4190 return ERR_PTR(-ENOMEM); 4191 mw->rdev = rdev; 4192 mw->qplib_mw.pd = &pd->qplib_pd; 4193 4194 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ? 4195 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 : 4196 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B); 4197 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw); 4198 if (rc) { 4199 ibdev_err(&rdev->ibdev, "Allocate MW failed!"); 4200 goto fail; 4201 } 4202 mw->ib_mw.rkey = mw->qplib_mw.rkey; 4203 4204 active_mws = atomic_inc_return(&rdev->stats.res.mw_count); 4205 if (active_mws > rdev->stats.res.mw_watermark) 4206 rdev->stats.res.mw_watermark = active_mws; 4207 return &mw->ib_mw; 4208 4209 fail: 4210 kfree(mw); 4211 return ERR_PTR(rc); 4212 } 4213 4214 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw) 4215 { 4216 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw); 4217 struct bnxt_re_dev *rdev = mw->rdev; 4218 int rc; 4219 4220 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw); 4221 if (rc) { 4222 ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc); 4223 return rc; 4224 } 4225 4226 kfree(mw); 4227 atomic_dec(&rdev->stats.res.mw_count); 4228 return rc; 4229 } 4230 4231 static struct ib_mr *__bnxt_re_user_reg_mr(struct ib_pd *ib_pd, u64 length, u64 virt_addr, 4232 int mr_access_flags, struct ib_umem *umem) 4233 { 4234 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4235 struct bnxt_re_dev *rdev = pd->rdev; 4236 unsigned long page_size; 4237 struct bnxt_re_mr *mr; 4238 int umem_pgs, rc; 4239 u32 active_mrs; 4240 4241 if (length > BNXT_RE_MAX_MR_SIZE) { 4242 ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n", 4243 length, BNXT_RE_MAX_MR_SIZE); 4244 return ERR_PTR(-ENOMEM); 4245 } 4246 4247 page_size = ib_umem_find_best_pgsz(umem, BNXT_RE_PAGE_SIZE_SUPPORTED, virt_addr); 4248 if (!page_size) { 4249 ibdev_err(&rdev->ibdev, "umem page size unsupported!"); 4250 return ERR_PTR(-EINVAL); 4251 } 4252 4253 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 4254 if (!mr) 4255 return ERR_PTR(-ENOMEM); 4256 4257 mr->rdev = rdev; 4258 mr->qplib_mr.pd = &pd->qplib_pd; 4259 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags); 4260 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR; 4261 4262 if (!_is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags)) { 4263 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 4264 if (rc) { 4265 ibdev_err(&rdev->ibdev, "Failed to allocate MR rc = %d", rc); 4266 rc = -EIO; 4267 goto free_mr; 4268 } 4269 /* The fixed portion of the rkey is the same as the lkey */ 4270 mr->ib_mr.rkey = mr->qplib_mr.rkey; 4271 } else { 4272 mr->qplib_mr.flags = CMDQ_REGISTER_MR_FLAGS_ALLOC_MR; 4273 } 4274 mr->ib_umem = umem; 4275 mr->qplib_mr.va = virt_addr; 4276 mr->qplib_mr.total_size = length; 4277 4278 if (mr_access_flags & IB_ACCESS_RELAXED_ORDERING) 4279 bnxt_re_check_and_set_relaxed_ordering(rdev, &mr->qplib_mr); 4280 4281 umem_pgs = ib_umem_num_dma_blocks(umem, page_size); 4282 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, umem, 4283 umem_pgs, page_size, 4284 _is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags)); 4285 if (rc) { 4286 ibdev_err(&rdev->ibdev, "Failed to register user MR - rc = %d\n", rc); 4287 rc = -EIO; 4288 goto free_mrw; 4289 } 4290 4291 mr->ib_mr.lkey = mr->qplib_mr.lkey; 4292 mr->ib_mr.rkey = mr->qplib_mr.lkey; 4293 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 4294 if (active_mrs > rdev->stats.res.mr_watermark) 4295 rdev->stats.res.mr_watermark = active_mrs; 4296 4297 return &mr->ib_mr; 4298 4299 free_mrw: 4300 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 4301 free_mr: 4302 kfree(mr); 4303 return ERR_PTR(rc); 4304 } 4305 4306 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length, 4307 u64 virt_addr, int mr_access_flags, 4308 struct ib_dmah *dmah, 4309 struct ib_udata *udata) 4310 { 4311 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4312 struct bnxt_re_dev *rdev = pd->rdev; 4313 struct ib_umem *umem; 4314 struct ib_mr *ib_mr; 4315 4316 if (dmah) 4317 return ERR_PTR(-EOPNOTSUPP); 4318 4319 umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags); 4320 if (IS_ERR(umem)) 4321 return ERR_CAST(umem); 4322 4323 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem); 4324 if (IS_ERR(ib_mr)) 4325 ib_umem_release(umem); 4326 return ib_mr; 4327 } 4328 4329 struct ib_mr *bnxt_re_reg_user_mr_dmabuf(struct ib_pd *ib_pd, u64 start, 4330 u64 length, u64 virt_addr, int fd, 4331 int mr_access_flags, 4332 struct ib_dmah *dmah, 4333 struct uverbs_attr_bundle *attrs) 4334 { 4335 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4336 struct bnxt_re_dev *rdev = pd->rdev; 4337 struct ib_umem_dmabuf *umem_dmabuf; 4338 struct ib_umem *umem; 4339 struct ib_mr *ib_mr; 4340 4341 if (dmah) 4342 return ERR_PTR(-EOPNOTSUPP); 4343 4344 umem_dmabuf = ib_umem_dmabuf_get_pinned(&rdev->ibdev, start, length, 4345 fd, mr_access_flags); 4346 if (IS_ERR(umem_dmabuf)) 4347 return ERR_CAST(umem_dmabuf); 4348 4349 umem = &umem_dmabuf->umem; 4350 4351 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem); 4352 if (IS_ERR(ib_mr)) 4353 ib_umem_release(umem); 4354 return ib_mr; 4355 } 4356 4357 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata) 4358 { 4359 struct ib_device *ibdev = ctx->device; 4360 struct bnxt_re_ucontext *uctx = 4361 container_of(ctx, struct bnxt_re_ucontext, ib_uctx); 4362 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 4363 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 4364 struct bnxt_re_user_mmap_entry *entry; 4365 struct bnxt_re_uctx_resp resp = {}; 4366 struct bnxt_re_uctx_req ureq = {}; 4367 u32 chip_met_rev_num = 0; 4368 int rc; 4369 4370 ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver); 4371 4372 if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) { 4373 ibdev_dbg(ibdev, " is different from the device %d ", 4374 BNXT_RE_ABI_VERSION); 4375 return -EPERM; 4376 } 4377 4378 uctx->rdev = rdev; 4379 4380 uctx->shpg = (void *)__get_free_page(GFP_KERNEL); 4381 if (!uctx->shpg) { 4382 rc = -ENOMEM; 4383 goto fail; 4384 } 4385 spin_lock_init(&uctx->sh_lock); 4386 4387 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX; 4388 chip_met_rev_num = rdev->chip_ctx->chip_num; 4389 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) << 4390 BNXT_RE_CHIP_ID0_CHIP_REV_SFT; 4391 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) << 4392 BNXT_RE_CHIP_ID0_CHIP_MET_SFT; 4393 resp.chip_id0 = chip_met_rev_num; 4394 /*Temp, Use xa_alloc instead */ 4395 resp.dev_id = rdev->en_dev->pdev->devfn; 4396 resp.max_qp = rdev->qplib_ctx.qpc_count; 4397 resp.pg_size = PAGE_SIZE; 4398 resp.cqe_sz = sizeof(struct cq_base); 4399 resp.max_cqd = dev_attr->max_cq_wqes; 4400 4401 if (rdev->chip_ctx->modes.db_push) 4402 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_WC_DPI_ENABLED; 4403 4404 entry = bnxt_re_mmap_entry_insert(uctx, 0, BNXT_RE_MMAP_SH_PAGE, NULL); 4405 if (!entry) { 4406 rc = -ENOMEM; 4407 goto cfail; 4408 } 4409 uctx->shpage_mmap = &entry->rdma_entry; 4410 if (rdev->pacing.dbr_pacing) 4411 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED; 4412 4413 if (_is_host_msn_table(rdev->qplib_res.dattr->dev_cap_flags2)) 4414 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_MSN_TABLE_ENABLED; 4415 4416 if (_is_modify_qp_rate_limit_supported(dev_attr->dev_cap_flags2)) 4417 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_QP_RATE_LIMIT_ENABLED; 4418 4419 if (udata->inlen >= sizeof(ureq)) { 4420 rc = ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq))); 4421 if (rc) 4422 goto cfail; 4423 if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT) { 4424 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED; 4425 uctx->cmask |= BNXT_RE_UCNTX_CAP_POW2_DISABLED; 4426 } 4427 if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_VAR_WQE_SUPPORT) { 4428 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_HAVE_MODE; 4429 resp.mode = rdev->chip_ctx->modes.wqe_mode; 4430 if (resp.mode == BNXT_QPLIB_WQE_MODE_VARIABLE) 4431 uctx->cmask |= BNXT_RE_UCNTX_CAP_VAR_WQE_ENABLED; 4432 } 4433 } 4434 4435 rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 4436 if (rc) { 4437 ibdev_err(ibdev, "Failed to copy user context"); 4438 rc = -EFAULT; 4439 goto cfail; 4440 } 4441 4442 return 0; 4443 cfail: 4444 free_page((unsigned long)uctx->shpg); 4445 uctx->shpg = NULL; 4446 fail: 4447 return rc; 4448 } 4449 4450 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx) 4451 { 4452 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 4453 struct bnxt_re_ucontext, 4454 ib_uctx); 4455 4456 struct bnxt_re_dev *rdev = uctx->rdev; 4457 4458 rdma_user_mmap_entry_remove(uctx->shpage_mmap); 4459 uctx->shpage_mmap = NULL; 4460 if (uctx->shpg) 4461 free_page((unsigned long)uctx->shpg); 4462 4463 if (uctx->dpi.dbr) { 4464 /* Free DPI only if this is the first PD allocated by the 4465 * application and mark the context dpi as NULL 4466 */ 4467 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->dpi); 4468 uctx->dpi.dbr = NULL; 4469 } 4470 } 4471 4472 static int bnxt_re_setup_vnic(struct bnxt_re_dev *rdev, struct bnxt_re_qp *qp) 4473 { 4474 int rc; 4475 4476 rc = bnxt_re_hwrm_alloc_vnic(rdev); 4477 if (rc) 4478 return rc; 4479 4480 rc = bnxt_re_hwrm_cfg_vnic(rdev, qp->qplib_qp.id); 4481 if (rc) 4482 goto out_free_vnic; 4483 4484 return 0; 4485 out_free_vnic: 4486 bnxt_re_hwrm_free_vnic(rdev); 4487 return rc; 4488 } 4489 4490 struct ib_flow *bnxt_re_create_flow(struct ib_qp *ib_qp, 4491 struct ib_flow_attr *attr, 4492 struct ib_udata *udata) 4493 { 4494 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 4495 struct bnxt_re_dev *rdev = qp->rdev; 4496 struct bnxt_re_flow *flow; 4497 int rc; 4498 4499 if (attr->type != IB_FLOW_ATTR_SNIFFER || 4500 !rdev->rcfw.roce_mirror) 4501 return ERR_PTR(-EOPNOTSUPP); 4502 4503 mutex_lock(&rdev->qp_lock); 4504 if (rdev->sniffer_flow_created) { 4505 ibdev_err(&rdev->ibdev, "RoCE Mirroring is already Configured\n"); 4506 mutex_unlock(&rdev->qp_lock); 4507 return ERR_PTR(-EBUSY); 4508 } 4509 4510 flow = kzalloc(sizeof(*flow), GFP_KERNEL); 4511 if (!flow) { 4512 mutex_unlock(&rdev->qp_lock); 4513 return ERR_PTR(-ENOMEM); 4514 } 4515 4516 flow->rdev = rdev; 4517 4518 rc = bnxt_re_setup_vnic(rdev, qp); 4519 if (rc) 4520 goto out_free_flow; 4521 4522 rc = bnxt_qplib_create_flow(&rdev->qplib_res); 4523 if (rc) 4524 goto out_free_vnic; 4525 4526 rdev->sniffer_flow_created = 1; 4527 mutex_unlock(&rdev->qp_lock); 4528 4529 return &flow->ib_flow; 4530 4531 out_free_vnic: 4532 bnxt_re_hwrm_free_vnic(rdev); 4533 out_free_flow: 4534 mutex_unlock(&rdev->qp_lock); 4535 kfree(flow); 4536 return ERR_PTR(rc); 4537 } 4538 4539 int bnxt_re_destroy_flow(struct ib_flow *flow_id) 4540 { 4541 struct bnxt_re_flow *flow = 4542 container_of(flow_id, struct bnxt_re_flow, ib_flow); 4543 struct bnxt_re_dev *rdev = flow->rdev; 4544 int rc; 4545 4546 mutex_lock(&rdev->qp_lock); 4547 rc = bnxt_qplib_destroy_flow(&rdev->qplib_res); 4548 if (rc) 4549 ibdev_dbg(&rdev->ibdev, "failed to destroy_flow rc = %d\n", rc); 4550 rdev->sniffer_flow_created = 0; 4551 4552 bnxt_re_hwrm_free_vnic(rdev); 4553 mutex_unlock(&rdev->qp_lock); 4554 kfree(flow); 4555 4556 return rc; 4557 } 4558 4559 static struct bnxt_re_cq *bnxt_re_search_for_cq(struct bnxt_re_dev *rdev, u32 cq_id) 4560 { 4561 struct bnxt_re_cq *cq = NULL, *tmp_cq; 4562 4563 hash_for_each_possible(rdev->cq_hash, tmp_cq, hash_entry, cq_id) { 4564 if (tmp_cq->qplib_cq.id == cq_id) { 4565 cq = tmp_cq; 4566 break; 4567 } 4568 } 4569 return cq; 4570 } 4571 4572 static struct bnxt_re_srq *bnxt_re_search_for_srq(struct bnxt_re_dev *rdev, u32 srq_id) 4573 { 4574 struct bnxt_re_srq *srq = NULL, *tmp_srq; 4575 4576 hash_for_each_possible(rdev->srq_hash, tmp_srq, hash_entry, srq_id) { 4577 if (tmp_srq->qplib_srq.id == srq_id) { 4578 srq = tmp_srq; 4579 break; 4580 } 4581 } 4582 return srq; 4583 } 4584 4585 /* Helper function to mmap the virtual memory from user app */ 4586 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma) 4587 { 4588 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 4589 struct bnxt_re_ucontext, 4590 ib_uctx); 4591 struct bnxt_re_user_mmap_entry *bnxt_entry; 4592 struct rdma_user_mmap_entry *rdma_entry; 4593 int ret = 0; 4594 u64 pfn; 4595 4596 rdma_entry = rdma_user_mmap_entry_get(&uctx->ib_uctx, vma); 4597 if (!rdma_entry) 4598 return -EINVAL; 4599 4600 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry, 4601 rdma_entry); 4602 4603 switch (bnxt_entry->mmap_flag) { 4604 case BNXT_RE_MMAP_WC_DB: 4605 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4606 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4607 pgprot_writecombine(vma->vm_page_prot), 4608 rdma_entry); 4609 break; 4610 case BNXT_RE_MMAP_UC_DB: 4611 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4612 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4613 pgprot_noncached(vma->vm_page_prot), 4614 rdma_entry); 4615 break; 4616 case BNXT_RE_MMAP_SH_PAGE: 4617 ret = vm_insert_page(vma, vma->vm_start, virt_to_page(uctx->shpg)); 4618 break; 4619 case BNXT_RE_MMAP_DBR_BAR: 4620 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4621 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4622 pgprot_noncached(vma->vm_page_prot), 4623 rdma_entry); 4624 break; 4625 case BNXT_RE_MMAP_DBR_PAGE: 4626 case BNXT_RE_MMAP_TOGGLE_PAGE: 4627 /* Driver doesn't expect write access for user space */ 4628 if (vma->vm_flags & VM_WRITE) 4629 ret = -EFAULT; 4630 else 4631 ret = vm_insert_page(vma, vma->vm_start, 4632 virt_to_page((void *)bnxt_entry->mem_offset)); 4633 break; 4634 default: 4635 ret = -EINVAL; 4636 break; 4637 } 4638 4639 rdma_user_mmap_entry_put(rdma_entry); 4640 return ret; 4641 } 4642 4643 void bnxt_re_mmap_free(struct rdma_user_mmap_entry *rdma_entry) 4644 { 4645 struct bnxt_re_user_mmap_entry *bnxt_entry; 4646 4647 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry, 4648 rdma_entry); 4649 4650 kfree(bnxt_entry); 4651 } 4652 4653 int bnxt_re_process_mad(struct ib_device *ibdev, int mad_flags, 4654 u32 port_num, const struct ib_wc *in_wc, 4655 const struct ib_grh *in_grh, 4656 const struct ib_mad *in_mad, struct ib_mad *out_mad, 4657 size_t *out_mad_size, u16 *out_mad_pkey_index) 4658 { 4659 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 4660 struct ib_class_port_info cpi = {}; 4661 int ret = IB_MAD_RESULT_SUCCESS; 4662 int rc = 0; 4663 4664 if (in_mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_PERF_MGMT) 4665 return ret; 4666 4667 switch (in_mad->mad_hdr.attr_id) { 4668 case IB_PMA_CLASS_PORT_INFO: 4669 cpi.capability_mask = IB_PMA_CLASS_CAP_EXT_WIDTH; 4670 memcpy((out_mad->data + 40), &cpi, sizeof(cpi)); 4671 break; 4672 case IB_PMA_PORT_COUNTERS_EXT: 4673 rc = bnxt_re_assign_pma_port_ext_counters(rdev, out_mad); 4674 break; 4675 case IB_PMA_PORT_COUNTERS: 4676 rc = bnxt_re_assign_pma_port_counters(rdev, out_mad); 4677 break; 4678 default: 4679 rc = -EINVAL; 4680 break; 4681 } 4682 if (rc) 4683 return IB_MAD_RESULT_FAILURE; 4684 ret |= IB_MAD_RESULT_REPLY; 4685 return ret; 4686 } 4687 4688 static int UVERBS_HANDLER(BNXT_RE_METHOD_NOTIFY_DRV)(struct uverbs_attr_bundle *attrs) 4689 { 4690 struct bnxt_re_ucontext *uctx; 4691 4692 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx); 4693 bnxt_re_pacing_alert(uctx->rdev); 4694 return 0; 4695 } 4696 4697 static int UVERBS_HANDLER(BNXT_RE_METHOD_ALLOC_PAGE)(struct uverbs_attr_bundle *attrs) 4698 { 4699 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_ALLOC_PAGE_HANDLE); 4700 enum bnxt_re_alloc_page_type alloc_type; 4701 struct bnxt_re_user_mmap_entry *entry; 4702 enum bnxt_re_mmap_flag mmap_flag; 4703 struct bnxt_qplib_chip_ctx *cctx; 4704 struct bnxt_re_ucontext *uctx; 4705 struct bnxt_re_dev *rdev; 4706 u64 mmap_offset; 4707 u32 length; 4708 u32 dpi; 4709 u64 addr; 4710 int err; 4711 4712 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx); 4713 if (IS_ERR(uctx)) 4714 return PTR_ERR(uctx); 4715 4716 err = uverbs_get_const(&alloc_type, attrs, BNXT_RE_ALLOC_PAGE_TYPE); 4717 if (err) 4718 return err; 4719 4720 rdev = uctx->rdev; 4721 cctx = rdev->chip_ctx; 4722 4723 switch (alloc_type) { 4724 case BNXT_RE_ALLOC_WC_PAGE: 4725 if (cctx->modes.db_push) { 4726 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, &uctx->wcdpi, 4727 uctx, BNXT_QPLIB_DPI_TYPE_WC)) 4728 return -ENOMEM; 4729 length = PAGE_SIZE; 4730 dpi = uctx->wcdpi.dpi; 4731 addr = (u64)uctx->wcdpi.umdbr; 4732 mmap_flag = BNXT_RE_MMAP_WC_DB; 4733 } else { 4734 return -EINVAL; 4735 } 4736 4737 break; 4738 case BNXT_RE_ALLOC_DBR_BAR_PAGE: 4739 length = PAGE_SIZE; 4740 addr = (u64)rdev->pacing.dbr_bar_addr; 4741 mmap_flag = BNXT_RE_MMAP_DBR_BAR; 4742 break; 4743 4744 case BNXT_RE_ALLOC_DBR_PAGE: 4745 length = PAGE_SIZE; 4746 addr = (u64)rdev->pacing.dbr_page; 4747 mmap_flag = BNXT_RE_MMAP_DBR_PAGE; 4748 break; 4749 4750 default: 4751 return -EOPNOTSUPP; 4752 } 4753 4754 entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mmap_offset); 4755 if (!entry) 4756 return -ENOMEM; 4757 4758 uobj->object = entry; 4759 uverbs_finalize_uobj_create(attrs, BNXT_RE_ALLOC_PAGE_HANDLE); 4760 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_OFFSET, 4761 &mmap_offset, sizeof(mmap_offset)); 4762 if (err) 4763 return err; 4764 4765 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_LENGTH, 4766 &length, sizeof(length)); 4767 if (err) 4768 return err; 4769 4770 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_DPI, 4771 &dpi, sizeof(dpi)); 4772 if (err) 4773 return err; 4774 4775 return 0; 4776 } 4777 4778 static int alloc_page_obj_cleanup(struct ib_uobject *uobject, 4779 enum rdma_remove_reason why, 4780 struct uverbs_attr_bundle *attrs) 4781 { 4782 struct bnxt_re_user_mmap_entry *entry = uobject->object; 4783 struct bnxt_re_ucontext *uctx = entry->uctx; 4784 4785 switch (entry->mmap_flag) { 4786 case BNXT_RE_MMAP_WC_DB: 4787 if (uctx && uctx->wcdpi.dbr) { 4788 struct bnxt_re_dev *rdev = uctx->rdev; 4789 4790 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->wcdpi); 4791 uctx->wcdpi.dbr = NULL; 4792 } 4793 break; 4794 case BNXT_RE_MMAP_DBR_BAR: 4795 case BNXT_RE_MMAP_DBR_PAGE: 4796 break; 4797 default: 4798 goto exit; 4799 } 4800 rdma_user_mmap_entry_remove(&entry->rdma_entry); 4801 exit: 4802 return 0; 4803 } 4804 4805 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_ALLOC_PAGE, 4806 UVERBS_ATTR_IDR(BNXT_RE_ALLOC_PAGE_HANDLE, 4807 BNXT_RE_OBJECT_ALLOC_PAGE, 4808 UVERBS_ACCESS_NEW, 4809 UA_MANDATORY), 4810 UVERBS_ATTR_CONST_IN(BNXT_RE_ALLOC_PAGE_TYPE, 4811 enum bnxt_re_alloc_page_type, 4812 UA_MANDATORY), 4813 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_OFFSET, 4814 UVERBS_ATTR_TYPE(u64), 4815 UA_MANDATORY), 4816 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_LENGTH, 4817 UVERBS_ATTR_TYPE(u32), 4818 UA_MANDATORY), 4819 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_DPI, 4820 UVERBS_ATTR_TYPE(u32), 4821 UA_MANDATORY)); 4822 4823 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_DESTROY_PAGE, 4824 UVERBS_ATTR_IDR(BNXT_RE_DESTROY_PAGE_HANDLE, 4825 BNXT_RE_OBJECT_ALLOC_PAGE, 4826 UVERBS_ACCESS_DESTROY, 4827 UA_MANDATORY)); 4828 4829 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_ALLOC_PAGE, 4830 UVERBS_TYPE_ALLOC_IDR(alloc_page_obj_cleanup), 4831 &UVERBS_METHOD(BNXT_RE_METHOD_ALLOC_PAGE), 4832 &UVERBS_METHOD(BNXT_RE_METHOD_DESTROY_PAGE)); 4833 4834 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_NOTIFY_DRV); 4835 4836 DECLARE_UVERBS_GLOBAL_METHODS(BNXT_RE_OBJECT_NOTIFY_DRV, 4837 &UVERBS_METHOD(BNXT_RE_METHOD_NOTIFY_DRV)); 4838 4839 /* Toggle MEM */ 4840 static int UVERBS_HANDLER(BNXT_RE_METHOD_GET_TOGGLE_MEM)(struct uverbs_attr_bundle *attrs) 4841 { 4842 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_TOGGLE_MEM_HANDLE); 4843 enum bnxt_re_mmap_flag mmap_flag = BNXT_RE_MMAP_TOGGLE_PAGE; 4844 enum bnxt_re_get_toggle_mem_type res_type; 4845 struct bnxt_re_user_mmap_entry *entry; 4846 struct bnxt_re_ucontext *uctx; 4847 struct ib_ucontext *ib_uctx; 4848 struct bnxt_re_dev *rdev; 4849 struct bnxt_re_srq *srq; 4850 u32 length = PAGE_SIZE; 4851 struct bnxt_re_cq *cq; 4852 u64 mem_offset; 4853 u32 offset = 0; 4854 u64 addr = 0; 4855 u32 res_id; 4856 int err; 4857 4858 ib_uctx = ib_uverbs_get_ucontext(attrs); 4859 if (IS_ERR(ib_uctx)) 4860 return PTR_ERR(ib_uctx); 4861 4862 err = uverbs_get_const(&res_type, attrs, BNXT_RE_TOGGLE_MEM_TYPE); 4863 if (err) 4864 return err; 4865 4866 uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx); 4867 rdev = uctx->rdev; 4868 err = uverbs_copy_from(&res_id, attrs, BNXT_RE_TOGGLE_MEM_RES_ID); 4869 if (err) 4870 return err; 4871 4872 switch (res_type) { 4873 case BNXT_RE_CQ_TOGGLE_MEM: 4874 cq = bnxt_re_search_for_cq(rdev, res_id); 4875 if (!cq) 4876 return -EINVAL; 4877 4878 addr = (u64)cq->uctx_cq_page; 4879 break; 4880 case BNXT_RE_SRQ_TOGGLE_MEM: 4881 srq = bnxt_re_search_for_srq(rdev, res_id); 4882 if (!srq) 4883 return -EINVAL; 4884 4885 addr = (u64)srq->uctx_srq_page; 4886 break; 4887 4888 default: 4889 return -EOPNOTSUPP; 4890 } 4891 4892 entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mem_offset); 4893 if (!entry) 4894 return -ENOMEM; 4895 4896 uobj->object = entry; 4897 uverbs_finalize_uobj_create(attrs, BNXT_RE_TOGGLE_MEM_HANDLE); 4898 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_PAGE, 4899 &mem_offset, sizeof(mem_offset)); 4900 if (err) 4901 return err; 4902 4903 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_LENGTH, 4904 &length, sizeof(length)); 4905 if (err) 4906 return err; 4907 4908 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_OFFSET, 4909 &offset, sizeof(offset)); 4910 if (err) 4911 return err; 4912 4913 return 0; 4914 } 4915 4916 static int get_toggle_mem_obj_cleanup(struct ib_uobject *uobject, 4917 enum rdma_remove_reason why, 4918 struct uverbs_attr_bundle *attrs) 4919 { 4920 struct bnxt_re_user_mmap_entry *entry = uobject->object; 4921 4922 rdma_user_mmap_entry_remove(&entry->rdma_entry); 4923 return 0; 4924 } 4925 4926 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM, 4927 UVERBS_ATTR_IDR(BNXT_RE_TOGGLE_MEM_HANDLE, 4928 BNXT_RE_OBJECT_GET_TOGGLE_MEM, 4929 UVERBS_ACCESS_NEW, 4930 UA_MANDATORY), 4931 UVERBS_ATTR_CONST_IN(BNXT_RE_TOGGLE_MEM_TYPE, 4932 enum bnxt_re_get_toggle_mem_type, 4933 UA_MANDATORY), 4934 UVERBS_ATTR_PTR_IN(BNXT_RE_TOGGLE_MEM_RES_ID, 4935 UVERBS_ATTR_TYPE(u32), 4936 UA_MANDATORY), 4937 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_PAGE, 4938 UVERBS_ATTR_TYPE(u64), 4939 UA_MANDATORY), 4940 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_OFFSET, 4941 UVERBS_ATTR_TYPE(u32), 4942 UA_MANDATORY), 4943 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_LENGTH, 4944 UVERBS_ATTR_TYPE(u32), 4945 UA_MANDATORY)); 4946 4947 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM, 4948 UVERBS_ATTR_IDR(BNXT_RE_RELEASE_TOGGLE_MEM_HANDLE, 4949 BNXT_RE_OBJECT_GET_TOGGLE_MEM, 4950 UVERBS_ACCESS_DESTROY, 4951 UA_MANDATORY)); 4952 4953 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_GET_TOGGLE_MEM, 4954 UVERBS_TYPE_ALLOC_IDR(get_toggle_mem_obj_cleanup), 4955 &UVERBS_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM), 4956 &UVERBS_METHOD(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM)); 4957 4958 const struct uapi_definition bnxt_re_uapi_defs[] = { 4959 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_ALLOC_PAGE), 4960 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_NOTIFY_DRV), 4961 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_GET_TOGGLE_MEM), 4962 {} 4963 }; 4964