1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: IB Verbs interpreter
37 */
38
39 #include <linux/interrupt.h>
40 #include <linux/types.h>
41 #include <linux/pci.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_ether.h>
44 #include <net/addrconf.h>
45
46 #include <rdma/ib_verbs.h>
47 #include <rdma/ib_user_verbs.h>
48 #include <rdma/ib_umem.h>
49 #include <rdma/ib_addr.h>
50 #include <rdma/ib_mad.h>
51 #include <rdma/ib_cache.h>
52 #include <rdma/ib_pma.h>
53 #include <rdma/uverbs_ioctl.h>
54 #include <linux/hashtable.h>
55
56 #include "roce_hsi.h"
57 #include "qplib_res.h"
58 #include "qplib_sp.h"
59 #include "qplib_fp.h"
60 #include "qplib_rcfw.h"
61
62 #include "bnxt_re.h"
63 #include "ib_verbs.h"
64 #include "debugfs.h"
65
66 #include <rdma/uverbs_types.h>
67 #include <rdma/uverbs_std_types.h>
68
69 #include <rdma/ib_user_ioctl_cmds.h>
70
71 #define UVERBS_MODULE_NAME bnxt_re
72 #include <rdma/uverbs_named_ioctl.h>
73
74 #include <rdma/bnxt_re-abi.h>
75
__from_ib_access_flags(int iflags)76 static int __from_ib_access_flags(int iflags)
77 {
78 int qflags = 0;
79
80 if (iflags & IB_ACCESS_LOCAL_WRITE)
81 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
82 if (iflags & IB_ACCESS_REMOTE_READ)
83 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ;
84 if (iflags & IB_ACCESS_REMOTE_WRITE)
85 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
86 if (iflags & IB_ACCESS_REMOTE_ATOMIC)
87 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
88 if (iflags & IB_ACCESS_MW_BIND)
89 qflags |= BNXT_QPLIB_ACCESS_MW_BIND;
90 if (iflags & IB_ZERO_BASED)
91 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED;
92 if (iflags & IB_ACCESS_ON_DEMAND)
93 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND;
94 return qflags;
95 };
96
__to_ib_access_flags(int qflags)97 static int __to_ib_access_flags(int qflags)
98 {
99 int iflags = 0;
100
101 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
102 iflags |= IB_ACCESS_LOCAL_WRITE;
103 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
104 iflags |= IB_ACCESS_REMOTE_WRITE;
105 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
106 iflags |= IB_ACCESS_REMOTE_READ;
107 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
108 iflags |= IB_ACCESS_REMOTE_ATOMIC;
109 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
110 iflags |= IB_ACCESS_MW_BIND;
111 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
112 iflags |= IB_ZERO_BASED;
113 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
114 iflags |= IB_ACCESS_ON_DEMAND;
115 return iflags;
116 }
117
__qp_access_flags_from_ib(struct bnxt_qplib_chip_ctx * cctx,int iflags)118 static u8 __qp_access_flags_from_ib(struct bnxt_qplib_chip_ctx *cctx, int iflags)
119 {
120 u8 qflags = 0;
121
122 if (!bnxt_qplib_is_chip_gen_p5_p7(cctx))
123 /* For Wh+ */
124 return (u8)__from_ib_access_flags(iflags);
125
126 /* For P5, P7 and later chips */
127 if (iflags & IB_ACCESS_LOCAL_WRITE)
128 qflags |= CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE;
129 if (iflags & IB_ACCESS_REMOTE_WRITE)
130 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE;
131 if (iflags & IB_ACCESS_REMOTE_READ)
132 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ;
133 if (iflags & IB_ACCESS_REMOTE_ATOMIC)
134 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC;
135
136 return qflags;
137 }
138
__qp_access_flags_to_ib(struct bnxt_qplib_chip_ctx * cctx,u8 qflags)139 static int __qp_access_flags_to_ib(struct bnxt_qplib_chip_ctx *cctx, u8 qflags)
140 {
141 int iflags = 0;
142
143 if (!bnxt_qplib_is_chip_gen_p5_p7(cctx))
144 /* For Wh+ */
145 return __to_ib_access_flags(qflags);
146
147 /* For P5, P7 and later chips */
148 if (qflags & CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE)
149 iflags |= IB_ACCESS_LOCAL_WRITE;
150 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE)
151 iflags |= IB_ACCESS_REMOTE_WRITE;
152 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_READ)
153 iflags |= IB_ACCESS_REMOTE_READ;
154 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC)
155 iflags |= IB_ACCESS_REMOTE_ATOMIC;
156
157 return iflags;
158 }
159
bnxt_re_check_and_set_relaxed_ordering(struct bnxt_re_dev * rdev,struct bnxt_qplib_mrw * qplib_mr)160 static void bnxt_re_check_and_set_relaxed_ordering(struct bnxt_re_dev *rdev,
161 struct bnxt_qplib_mrw *qplib_mr)
162 {
163 if (_is_relaxed_ordering_supported(rdev->dev_attr->dev_cap_flags2) &&
164 pcie_relaxed_ordering_enabled(rdev->en_dev->pdev))
165 qplib_mr->flags |= CMDQ_REGISTER_MR_FLAGS_ENABLE_RO;
166 }
167
bnxt_re_build_sgl(struct ib_sge * ib_sg_list,struct bnxt_qplib_sge * sg_list,int num)168 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,
169 struct bnxt_qplib_sge *sg_list, int num)
170 {
171 int i, total = 0;
172
173 for (i = 0; i < num; i++) {
174 sg_list[i].addr = ib_sg_list[i].addr;
175 sg_list[i].lkey = ib_sg_list[i].lkey;
176 sg_list[i].size = ib_sg_list[i].length;
177 total += sg_list[i].size;
178 }
179 return total;
180 }
181
182 /* Device */
bnxt_re_query_device(struct ib_device * ibdev,struct ib_device_attr * ib_attr,struct ib_udata * udata)183 int bnxt_re_query_device(struct ib_device *ibdev,
184 struct ib_device_attr *ib_attr,
185 struct ib_udata *udata)
186 {
187 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
188 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr;
189 struct bnxt_re_query_device_ex_resp resp = {};
190 size_t outlen = (udata) ? udata->outlen : 0;
191 int rc = 0;
192
193 memset(ib_attr, 0, sizeof(*ib_attr));
194 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver,
195 min(sizeof(dev_attr->fw_ver),
196 sizeof(ib_attr->fw_ver)));
197 addrconf_addr_eui48((u8 *)&ib_attr->sys_image_guid,
198 rdev->netdev->dev_addr);
199 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE;
200 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_SUPPORTED;
201
202 ib_attr->vendor_id = rdev->en_dev->pdev->vendor;
203 ib_attr->vendor_part_id = rdev->en_dev->pdev->device;
204 ib_attr->hw_ver = rdev->en_dev->pdev->revision;
205 ib_attr->max_qp = dev_attr->max_qp;
206 ib_attr->max_qp_wr = dev_attr->max_qp_wqes;
207 ib_attr->device_cap_flags =
208 IB_DEVICE_CURR_QP_STATE_MOD
209 | IB_DEVICE_RC_RNR_NAK_GEN
210 | IB_DEVICE_SHUTDOWN_PORT
211 | IB_DEVICE_SYS_IMAGE_GUID
212 | IB_DEVICE_RESIZE_MAX_WR
213 | IB_DEVICE_PORT_ACTIVE_EVENT
214 | IB_DEVICE_N_NOTIFY_CQ
215 | IB_DEVICE_MEM_WINDOW
216 | IB_DEVICE_MEM_WINDOW_TYPE_2B
217 | IB_DEVICE_MEM_MGT_EXTENSIONS;
218 ib_attr->kernel_cap_flags = IBK_LOCAL_DMA_LKEY;
219 ib_attr->max_send_sge = dev_attr->max_qp_sges;
220 ib_attr->max_recv_sge = dev_attr->max_qp_sges;
221 ib_attr->max_sge_rd = dev_attr->max_qp_sges;
222 ib_attr->max_cq = dev_attr->max_cq;
223 ib_attr->max_cqe = dev_attr->max_cq_wqes;
224 ib_attr->max_mr = dev_attr->max_mr;
225 ib_attr->max_pd = dev_attr->max_pd;
226 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
227 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom;
228 ib_attr->atomic_cap = IB_ATOMIC_NONE;
229 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE;
230 if (dev_attr->is_atomic) {
231 ib_attr->atomic_cap = IB_ATOMIC_GLOB;
232 ib_attr->masked_atomic_cap = IB_ATOMIC_GLOB;
233 }
234
235 ib_attr->max_ee_rd_atom = 0;
236 ib_attr->max_res_rd_atom = 0;
237 ib_attr->max_ee_init_rd_atom = 0;
238 ib_attr->max_ee = 0;
239 ib_attr->max_rdd = 0;
240 ib_attr->max_mw = dev_attr->max_mw;
241 ib_attr->max_raw_ipv6_qp = 0;
242 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp;
243 ib_attr->max_mcast_grp = 0;
244 ib_attr->max_mcast_qp_attach = 0;
245 ib_attr->max_total_mcast_qp_attach = 0;
246 ib_attr->max_ah = dev_attr->max_ah;
247
248 ib_attr->max_srq = dev_attr->max_srq;
249 ib_attr->max_srq_wr = dev_attr->max_srq_wqes;
250 ib_attr->max_srq_sge = dev_attr->max_srq_sges;
251
252 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS;
253
254 ib_attr->max_pkeys = 1;
255 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY;
256
257 if ((offsetofend(typeof(resp), packet_pacing_caps) <= outlen) &&
258 _is_modify_qp_rate_limit_supported(dev_attr->dev_cap_flags2)) {
259 resp.packet_pacing_caps.qp_rate_limit_min =
260 dev_attr->rate_limit_min;
261 resp.packet_pacing_caps.qp_rate_limit_max =
262 dev_attr->rate_limit_max;
263 resp.packet_pacing_caps.supported_qpts =
264 1 << IB_QPT_RC;
265 }
266 if (outlen)
267 rc = ib_copy_to_udata(udata, &resp,
268 min(sizeof(resp), outlen));
269
270 return rc;
271 }
272
bnxt_re_modify_device(struct ib_device * ibdev,int device_modify_mask,struct ib_device_modify * device_modify)273 int bnxt_re_modify_device(struct ib_device *ibdev,
274 int device_modify_mask,
275 struct ib_device_modify *device_modify)
276 {
277 ibdev_dbg(ibdev, "Modify device with mask 0x%x", device_modify_mask);
278
279 if (device_modify_mask & ~IB_DEVICE_MODIFY_NODE_DESC)
280 return -EOPNOTSUPP;
281
282 if (!(device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC))
283 return 0;
284
285 memcpy(ibdev->node_desc, device_modify->node_desc, IB_DEVICE_NODE_DESC_MAX);
286 return 0;
287 }
288
289 /* Port */
bnxt_re_query_port(struct ib_device * ibdev,u32 port_num,struct ib_port_attr * port_attr)290 int bnxt_re_query_port(struct ib_device *ibdev, u32 port_num,
291 struct ib_port_attr *port_attr)
292 {
293 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
294 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr;
295 int rc;
296
297 memset(port_attr, 0, sizeof(*port_attr));
298
299 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) {
300 port_attr->state = IB_PORT_ACTIVE;
301 port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
302 } else {
303 port_attr->state = IB_PORT_DOWN;
304 port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED;
305 }
306 port_attr->max_mtu = IB_MTU_4096;
307 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu);
308 /* One GID is reserved for RawEth QP. Report one less */
309 port_attr->gid_tbl_len = (rdev->rcfw.roce_mirror ? (dev_attr->max_sgid - 1) :
310 dev_attr->max_sgid);
311 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
312 IB_PORT_DEVICE_MGMT_SUP |
313 IB_PORT_VENDOR_CLASS_SUP;
314 port_attr->ip_gids = true;
315
316 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW;
317 port_attr->bad_pkey_cntr = 0;
318 port_attr->qkey_viol_cntr = 0;
319 port_attr->pkey_tbl_len = dev_attr->max_pkey;
320 port_attr->lid = 0;
321 port_attr->sm_lid = 0;
322 port_attr->lmc = 0;
323 port_attr->max_vl_num = 4;
324 port_attr->sm_sl = 0;
325 port_attr->subnet_timeout = 0;
326 port_attr->init_type_reply = 0;
327 rc = ib_get_eth_speed(&rdev->ibdev, port_num, &port_attr->active_speed,
328 &port_attr->active_width);
329
330 return rc;
331 }
332
bnxt_re_get_port_immutable(struct ib_device * ibdev,u32 port_num,struct ib_port_immutable * immutable)333 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u32 port_num,
334 struct ib_port_immutable *immutable)
335 {
336 struct ib_port_attr port_attr;
337
338 if (bnxt_re_query_port(ibdev, port_num, &port_attr))
339 return -EINVAL;
340
341 immutable->pkey_tbl_len = port_attr.pkey_tbl_len;
342 immutable->gid_tbl_len = port_attr.gid_tbl_len;
343 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
344 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP;
345 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
346 return 0;
347 }
348
bnxt_re_query_fw_str(struct ib_device * ibdev,char * str)349 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str)
350 {
351 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
352
353 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
354 rdev->dev_attr->fw_ver[0], rdev->dev_attr->fw_ver[1],
355 rdev->dev_attr->fw_ver[2], rdev->dev_attr->fw_ver[3]);
356 }
357
bnxt_re_query_pkey(struct ib_device * ibdev,u32 port_num,u16 index,u16 * pkey)358 int bnxt_re_query_pkey(struct ib_device *ibdev, u32 port_num,
359 u16 index, u16 *pkey)
360 {
361 if (index > 0)
362 return -EINVAL;
363
364 *pkey = IB_DEFAULT_PKEY_FULL;
365
366 return 0;
367 }
368
bnxt_re_query_gid(struct ib_device * ibdev,u32 port_num,int index,union ib_gid * gid)369 int bnxt_re_query_gid(struct ib_device *ibdev, u32 port_num,
370 int index, union ib_gid *gid)
371 {
372 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
373 int rc;
374
375 /* Ignore port_num */
376 memset(gid, 0, sizeof(*gid));
377 rc = bnxt_qplib_get_sgid(&rdev->qplib_res,
378 &rdev->qplib_res.sgid_tbl, index,
379 (struct bnxt_qplib_gid *)gid);
380 return rc;
381 }
382
bnxt_re_del_gid(const struct ib_gid_attr * attr,void ** context)383 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context)
384 {
385 int rc = 0;
386 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
387 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
388 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
389 struct bnxt_qplib_gid *gid_to_del;
390 u16 vlan_id = 0xFFFF;
391
392 /* Delete the entry from the hardware */
393 ctx = *context;
394 if (!ctx)
395 return -EINVAL;
396
397 if (sgid_tbl->active) {
398 if (ctx->idx >= sgid_tbl->max)
399 return -EINVAL;
400 gid_to_del = &sgid_tbl->tbl[ctx->idx].gid;
401 vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id;
402 /* DEL_GID is called in WQ context(netdevice_event_work_handler)
403 * or via the ib_unregister_device path. In the former case QP1
404 * may not be destroyed yet, in which case just return as FW
405 * needs that entry to be present and will fail it's deletion.
406 * We could get invoked again after QP1 is destroyed OR get an
407 * ADD_GID call with a different GID value for the same index
408 * where we issue MODIFY_GID cmd to update the GID entry -- TBD
409 */
410 if (ctx->idx == 0 &&
411 rdma_link_local_addr((struct in6_addr *)gid_to_del) &&
412 ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) {
413 ibdev_dbg(&rdev->ibdev,
414 "Trying to delete GID0 while QP1 is alive\n");
415 return -EFAULT;
416 }
417 ctx->refcnt--;
418 if (!ctx->refcnt) {
419 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del,
420 vlan_id, true);
421 if (rc) {
422 ibdev_err(&rdev->ibdev,
423 "Failed to remove GID: %#x", rc);
424 } else {
425 ctx_tbl = sgid_tbl->ctx;
426 ctx_tbl[ctx->idx] = NULL;
427 kfree(ctx);
428 }
429 }
430 } else {
431 return -EINVAL;
432 }
433 return rc;
434 }
435
bnxt_re_add_gid(const struct ib_gid_attr * attr,void ** context)436 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context)
437 {
438 int rc;
439 u32 tbl_idx = 0;
440 u16 vlan_id = 0xFFFF;
441 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
442 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
443 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
444
445 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL);
446 if (rc)
447 return rc;
448
449 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid,
450 rdev->qplib_res.netdev->dev_addr,
451 vlan_id, true, &tbl_idx, false, 0);
452 if (rc == -EALREADY) {
453 ctx_tbl = sgid_tbl->ctx;
454 ctx_tbl[tbl_idx]->refcnt++;
455 *context = ctx_tbl[tbl_idx];
456 return 0;
457 }
458
459 if (rc < 0) {
460 ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc);
461 return rc;
462 }
463
464 ctx = kmalloc_obj(*ctx);
465 if (!ctx)
466 return -ENOMEM;
467 ctx_tbl = sgid_tbl->ctx;
468 ctx->idx = tbl_idx;
469 ctx->refcnt = 1;
470 ctx_tbl[tbl_idx] = ctx;
471 *context = ctx;
472
473 return rc;
474 }
475
bnxt_re_get_link_layer(struct ib_device * ibdev,u32 port_num)476 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev,
477 u32 port_num)
478 {
479 return IB_LINK_LAYER_ETHERNET;
480 }
481
482 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE)
483
bnxt_re_create_fence_wqe(struct bnxt_re_pd * pd)484 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd)
485 {
486 struct bnxt_re_fence_data *fence = &pd->fence;
487 struct ib_mr *ib_mr = &fence->mr->ib_mr;
488 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe;
489 struct bnxt_re_dev *rdev = pd->rdev;
490
491 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
492 return;
493
494 memset(wqe, 0, sizeof(*wqe));
495 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW;
496 wqe->wr_id = BNXT_QPLIB_FENCE_WRID;
497 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
498 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
499 wqe->bind.zero_based = false;
500 wqe->bind.parent_l_key = ib_mr->lkey;
501 wqe->bind.va = (u64)(unsigned long)fence->va;
502 wqe->bind.length = fence->size;
503 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ);
504 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1;
505
506 /* Save the initial rkey in fence structure for now;
507 * wqe->bind.r_key will be set at (re)bind time.
508 */
509 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey);
510 }
511
bnxt_re_bind_fence_mw(struct bnxt_qplib_qp * qplib_qp)512 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp)
513 {
514 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp,
515 qplib_qp);
516 struct ib_pd *ib_pd = qp->ib_qp.pd;
517 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
518 struct bnxt_re_fence_data *fence = &pd->fence;
519 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe;
520 struct bnxt_qplib_swqe wqe;
521 int rc;
522
523 memcpy(&wqe, fence_wqe, sizeof(wqe));
524 wqe.bind.r_key = fence->bind_rkey;
525 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey);
526
527 ibdev_dbg(&qp->rdev->ibdev,
528 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n",
529 wqe.bind.r_key, qp->qplib_qp.id, pd);
530 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
531 if (rc) {
532 ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n");
533 return rc;
534 }
535 bnxt_qplib_post_send_db(&qp->qplib_qp);
536
537 return rc;
538 }
539
bnxt_re_destroy_fence_mr(struct bnxt_re_pd * pd)540 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd)
541 {
542 struct bnxt_re_fence_data *fence = &pd->fence;
543 struct bnxt_re_dev *rdev = pd->rdev;
544 struct device *dev = &rdev->en_dev->pdev->dev;
545 struct bnxt_re_mr *mr = fence->mr;
546
547 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
548 return;
549
550 if (fence->mw) {
551 bnxt_re_dealloc_mw(fence->mw);
552 fence->mw = NULL;
553 }
554 if (mr) {
555 if (mr->ib_mr.rkey)
556 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr,
557 true);
558 if (mr->ib_mr.lkey)
559 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
560 kfree(mr);
561 fence->mr = NULL;
562 }
563 if (fence->dma_addr) {
564 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES,
565 DMA_BIDIRECTIONAL);
566 fence->dma_addr = 0;
567 }
568 }
569
bnxt_re_create_fence_mr(struct bnxt_re_pd * pd)570 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd)
571 {
572 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND;
573 struct bnxt_re_fence_data *fence = &pd->fence;
574 struct bnxt_re_dev *rdev = pd->rdev;
575 struct device *dev = &rdev->en_dev->pdev->dev;
576 struct bnxt_re_mr *mr = NULL;
577 dma_addr_t dma_addr = 0;
578 struct ib_mw *mw;
579 int rc;
580
581 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
582 return 0;
583
584 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES,
585 DMA_BIDIRECTIONAL);
586 rc = dma_mapping_error(dev, dma_addr);
587 if (rc) {
588 ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n");
589 rc = -EIO;
590 fence->dma_addr = 0;
591 goto fail;
592 }
593 fence->dma_addr = dma_addr;
594
595 /* Allocate a MR */
596 mr = kzalloc_obj(*mr);
597 if (!mr) {
598 rc = -ENOMEM;
599 goto fail;
600 }
601 fence->mr = mr;
602 mr->rdev = rdev;
603 mr->qplib_mr.pd = &pd->qplib_pd;
604 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
605 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags);
606 if (!_is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags)) {
607 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
608 if (rc) {
609 ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n");
610 goto fail;
611 }
612
613 /* Register MR */
614 mr->ib_mr.lkey = mr->qplib_mr.lkey;
615 } else {
616 mr->qplib_mr.flags = CMDQ_REGISTER_MR_FLAGS_ALLOC_MR;
617 }
618 mr->qplib_mr.va = (u64)(unsigned long)fence->va;
619 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES;
620 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL,
621 BNXT_RE_FENCE_PBL_SIZE, PAGE_SIZE,
622 _is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags));
623 if (rc) {
624 ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n");
625 goto fail;
626 }
627 mr->ib_mr.rkey = mr->qplib_mr.rkey;
628
629 /* Create a fence MW only for kernel consumers */
630 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL);
631 if (IS_ERR(mw)) {
632 ibdev_err(&rdev->ibdev,
633 "Failed to create fence-MW for PD: %p\n", pd);
634 rc = PTR_ERR(mw);
635 goto fail;
636 }
637 fence->mw = mw;
638
639 bnxt_re_create_fence_wqe(pd);
640 return 0;
641
642 fail:
643 bnxt_re_destroy_fence_mr(pd);
644 return rc;
645 }
646
647 static struct bnxt_re_user_mmap_entry*
bnxt_re_mmap_entry_insert(struct bnxt_re_ucontext * uctx,u64 mem_offset,enum bnxt_re_mmap_flag mmap_flag,u64 * offset)648 bnxt_re_mmap_entry_insert(struct bnxt_re_ucontext *uctx, u64 mem_offset,
649 enum bnxt_re_mmap_flag mmap_flag, u64 *offset)
650 {
651 struct bnxt_re_user_mmap_entry *entry;
652 int ret;
653
654 entry = kzalloc_obj(*entry);
655 if (!entry)
656 return NULL;
657
658 entry->mem_offset = mem_offset;
659 entry->mmap_flag = mmap_flag;
660 entry->uctx = uctx;
661
662 switch (mmap_flag) {
663 case BNXT_RE_MMAP_SH_PAGE:
664 ret = rdma_user_mmap_entry_insert_exact(&uctx->ib_uctx,
665 &entry->rdma_entry, PAGE_SIZE, 0);
666 break;
667 case BNXT_RE_MMAP_UC_DB:
668 case BNXT_RE_MMAP_WC_DB:
669 case BNXT_RE_MMAP_DBR_BAR:
670 case BNXT_RE_MMAP_DBR_PAGE:
671 case BNXT_RE_MMAP_TOGGLE_PAGE:
672 ret = rdma_user_mmap_entry_insert(&uctx->ib_uctx,
673 &entry->rdma_entry, PAGE_SIZE);
674 break;
675 default:
676 ret = -EINVAL;
677 break;
678 }
679
680 if (ret) {
681 kfree(entry);
682 return NULL;
683 }
684 if (offset)
685 *offset = rdma_user_mmap_get_offset(&entry->rdma_entry);
686
687 return entry;
688 }
689
690 /* Protection Domains */
bnxt_re_dealloc_pd(struct ib_pd * ib_pd,struct ib_udata * udata)691 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata)
692 {
693 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
694 struct bnxt_re_dev *rdev = pd->rdev;
695
696 if (udata) {
697 rdma_user_mmap_entry_remove(pd->pd_db_mmap);
698 pd->pd_db_mmap = NULL;
699 }
700
701 bnxt_re_destroy_fence_mr(pd);
702
703 if (pd->qplib_pd.id) {
704 if (!bnxt_qplib_dealloc_pd(&rdev->qplib_res,
705 &rdev->qplib_res.pd_tbl,
706 &pd->qplib_pd))
707 atomic_dec(&rdev->stats.res.pd_count);
708 }
709 return 0;
710 }
711
bnxt_re_alloc_pd(struct ib_pd * ibpd,struct ib_udata * udata)712 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
713 {
714 struct ib_device *ibdev = ibpd->device;
715 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
716 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context(
717 udata, struct bnxt_re_ucontext, ib_uctx);
718 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd);
719 struct bnxt_re_user_mmap_entry *entry = NULL;
720 u32 active_pds;
721 int rc = 0;
722
723 pd->rdev = rdev;
724 if (bnxt_qplib_alloc_pd(&rdev->qplib_res, &pd->qplib_pd)) {
725 ibdev_err(&rdev->ibdev, "Failed to allocate HW PD");
726 rc = -ENOMEM;
727 goto fail;
728 }
729
730 if (udata) {
731 struct bnxt_re_pd_resp resp = {};
732
733 if (!ucntx->dpi.dbr) {
734 /* Allocate DPI in alloc_pd to avoid failing of
735 * ibv_devinfo and family of application when DPIs
736 * are depleted.
737 */
738 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res,
739 &ucntx->dpi, ucntx, BNXT_QPLIB_DPI_TYPE_UC)) {
740 rc = -ENOMEM;
741 goto dbfail;
742 }
743 }
744
745 resp.pdid = pd->qplib_pd.id;
746 /* Still allow mapping this DBR to the new user PD. */
747 resp.dpi = ucntx->dpi.dpi;
748
749 entry = bnxt_re_mmap_entry_insert(ucntx, (u64)ucntx->dpi.umdbr,
750 BNXT_RE_MMAP_UC_DB, &resp.dbr);
751
752 if (!entry) {
753 rc = -ENOMEM;
754 goto dbfail;
755 }
756
757 pd->pd_db_mmap = &entry->rdma_entry;
758
759 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen));
760 if (rc) {
761 rdma_user_mmap_entry_remove(pd->pd_db_mmap);
762 rc = -EFAULT;
763 goto dbfail;
764 }
765 }
766
767 if (!udata)
768 if (bnxt_re_create_fence_mr(pd))
769 ibdev_warn(&rdev->ibdev,
770 "Failed to create Fence-MR\n");
771 active_pds = atomic_inc_return(&rdev->stats.res.pd_count);
772 if (active_pds > rdev->stats.res.pd_watermark)
773 rdev->stats.res.pd_watermark = active_pds;
774
775 return 0;
776 dbfail:
777 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
778 &pd->qplib_pd);
779 fail:
780 return rc;
781 }
782
783 /* Address Handles */
bnxt_re_destroy_ah(struct ib_ah * ib_ah,u32 flags)784 int bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags)
785 {
786 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
787 struct bnxt_re_dev *rdev = ah->rdev;
788 bool block = true;
789 int rc;
790
791 block = !(flags & RDMA_DESTROY_AH_SLEEPABLE);
792 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah, block);
793 if (BNXT_RE_CHECK_RC(rc)) {
794 if (rc == -ETIMEDOUT)
795 rc = 0;
796 else
797 goto fail;
798 }
799 atomic_dec(&rdev->stats.res.ah_count);
800 fail:
801 return rc;
802 }
803
bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype)804 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype)
805 {
806 u8 nw_type;
807
808 switch (ntype) {
809 case RDMA_NETWORK_IPV4:
810 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
811 break;
812 case RDMA_NETWORK_IPV6:
813 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
814 break;
815 default:
816 nw_type = CMDQ_CREATE_AH_TYPE_V1;
817 break;
818 }
819 return nw_type;
820 }
821
bnxt_re_create_ah(struct ib_ah * ib_ah,struct rdma_ah_init_attr * init_attr,struct ib_udata * udata)822 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_init_attr *init_attr,
823 struct ib_udata *udata)
824 {
825 struct ib_pd *ib_pd = ib_ah->pd;
826 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
827 struct rdma_ah_attr *ah_attr = init_attr->ah_attr;
828 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
829 struct bnxt_re_dev *rdev = pd->rdev;
830 const struct ib_gid_attr *sgid_attr;
831 struct bnxt_re_gid_ctx *ctx;
832 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
833 u32 active_ahs;
834 u8 nw_type;
835 int rc;
836
837 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) {
838 ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set");
839 return -EINVAL;
840 }
841
842 ah->rdev = rdev;
843 ah->qplib_ah.pd = &pd->qplib_pd;
844
845 /* Supply the configuration for the HW */
846 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw,
847 sizeof(union ib_gid));
848 sgid_attr = grh->sgid_attr;
849 /* Get the HW context of the GID. The reference
850 * of GID table entry is already taken by the caller.
851 */
852 ctx = rdma_read_gid_hw_context(sgid_attr);
853 ah->qplib_ah.sgid_index = ctx->idx;
854 ah->qplib_ah.host_sgid_index = grh->sgid_index;
855 ah->qplib_ah.traffic_class = grh->traffic_class;
856 ah->qplib_ah.flow_label = grh->flow_label;
857 ah->qplib_ah.hop_limit = grh->hop_limit;
858 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr);
859
860 /* Get network header type for this GID */
861 nw_type = rdma_gid_attr_network_type(sgid_attr);
862 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type);
863
864 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
865 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah,
866 !(init_attr->flags &
867 RDMA_CREATE_AH_SLEEPABLE));
868 if (rc) {
869 ibdev_err(&rdev->ibdev, "Failed to allocate HW AH");
870 return rc;
871 }
872
873 /* Write AVID to shared page. */
874 if (udata) {
875 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(
876 udata, struct bnxt_re_ucontext, ib_uctx);
877 unsigned long flag;
878 u32 *wrptr;
879
880 spin_lock_irqsave(&uctx->sh_lock, flag);
881 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT);
882 *wrptr = ah->qplib_ah.id;
883 wmb(); /* make sure cache is updated. */
884 spin_unlock_irqrestore(&uctx->sh_lock, flag);
885 }
886 active_ahs = atomic_inc_return(&rdev->stats.res.ah_count);
887 if (active_ahs > rdev->stats.res.ah_watermark)
888 rdev->stats.res.ah_watermark = active_ahs;
889
890 return 0;
891 }
892
bnxt_re_query_ah(struct ib_ah * ib_ah,struct rdma_ah_attr * ah_attr)893 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
894 {
895 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
896
897 ah_attr->type = ib_ah->type;
898 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl);
899 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN);
900 rdma_ah_set_grh(ah_attr, NULL, 0,
901 ah->qplib_ah.host_sgid_index,
902 0, ah->qplib_ah.traffic_class);
903 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data);
904 rdma_ah_set_port_num(ah_attr, 1);
905 rdma_ah_set_static_rate(ah_attr, 0);
906 return 0;
907 }
908
bnxt_re_lock_cqs(struct bnxt_re_qp * qp)909 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp)
910 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock)
911 {
912 unsigned long flags;
913
914 spin_lock_irqsave(&qp->scq->cq_lock, flags);
915 if (qp->rcq != qp->scq)
916 spin_lock(&qp->rcq->cq_lock);
917 else
918 __acquire(&qp->rcq->cq_lock);
919
920 return flags;
921 }
922
bnxt_re_unlock_cqs(struct bnxt_re_qp * qp,unsigned long flags)923 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp,
924 unsigned long flags)
925 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock)
926 {
927 if (qp->rcq != qp->scq)
928 spin_unlock(&qp->rcq->cq_lock);
929 else
930 __release(&qp->rcq->cq_lock);
931 spin_unlock_irqrestore(&qp->scq->cq_lock, flags);
932 }
933
bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp * qp)934 static void bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp)
935 {
936 struct bnxt_re_qp *gsi_sqp;
937 struct bnxt_re_ah *gsi_sah;
938 struct bnxt_re_dev *rdev;
939 int rc;
940
941 rdev = qp->rdev;
942 gsi_sqp = rdev->gsi_ctx.gsi_sqp;
943 gsi_sah = rdev->gsi_ctx.gsi_sah;
944
945 ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n");
946 bnxt_qplib_destroy_ah(&rdev->qplib_res,
947 &gsi_sah->qplib_ah,
948 true);
949 atomic_dec(&rdev->stats.res.ah_count);
950 bnxt_qplib_clean_qp(&qp->qplib_qp);
951
952 ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n");
953 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp);
954 if (rc)
955 ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed");
956
957 bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp);
958
959 /* remove from active qp list */
960 mutex_lock(&rdev->qp_lock);
961 list_del(&gsi_sqp->list);
962 mutex_unlock(&rdev->qp_lock);
963 atomic_dec(&rdev->stats.res.qp_count);
964
965 kfree(rdev->gsi_ctx.sqp_tbl);
966 kfree(gsi_sah);
967 kfree(gsi_sqp);
968 rdev->gsi_ctx.gsi_sqp = NULL;
969 rdev->gsi_ctx.gsi_sah = NULL;
970 rdev->gsi_ctx.sqp_tbl = NULL;
971 }
972
bnxt_re_del_unique_gid(struct bnxt_re_dev * rdev)973 static void bnxt_re_del_unique_gid(struct bnxt_re_dev *rdev)
974 {
975 int rc;
976
977 if (!rdev->rcfw.roce_mirror)
978 return;
979
980 rc = bnxt_qplib_del_sgid(&rdev->qplib_res.sgid_tbl,
981 (struct bnxt_qplib_gid *)&rdev->ugid,
982 0xFFFF, true);
983 if (rc)
984 dev_err(rdev_to_dev(rdev), "Failed to delete unique GID, rc: %d\n", rc);
985 }
986
987 /* Queue Pairs */
bnxt_re_destroy_qp(struct ib_qp * ib_qp,struct ib_udata * udata)988 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata)
989 {
990 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
991 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp;
992 struct bnxt_re_dev *rdev = qp->rdev;
993 struct bnxt_qplib_nq *scq_nq = NULL;
994 struct bnxt_qplib_nq *rcq_nq = NULL;
995 unsigned int flags;
996 int rc;
997
998 bnxt_re_debug_rem_qpinfo(rdev, qp);
999
1000 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp);
1001
1002 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
1003 if (rc)
1004 ibdev_err(&rdev->ibdev, "Failed to destroy HW QP");
1005
1006 if (rdma_is_kernel_res(&qp->ib_qp.res)) {
1007 flags = bnxt_re_lock_cqs(qp);
1008 bnxt_qplib_clean_qp(&qp->qplib_qp);
1009 bnxt_re_unlock_cqs(qp, flags);
1010 }
1011
1012 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp);
1013
1014 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp)
1015 bnxt_re_destroy_gsi_sqp(qp);
1016
1017 mutex_lock(&rdev->qp_lock);
1018 list_del(&qp->list);
1019 mutex_unlock(&rdev->qp_lock);
1020 atomic_dec(&rdev->stats.res.qp_count);
1021 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_RC)
1022 atomic_dec(&rdev->stats.res.rc_qp_count);
1023 else if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD)
1024 atomic_dec(&rdev->stats.res.ud_qp_count);
1025
1026 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE)
1027 bnxt_re_del_unique_gid(rdev);
1028
1029 ib_umem_release(qp->rumem);
1030 ib_umem_release(qp->sumem);
1031
1032 /* Flush all the entries of notification queue associated with
1033 * given qp.
1034 */
1035 scq_nq = qplib_qp->scq->nq;
1036 rcq_nq = qplib_qp->rcq->nq;
1037 bnxt_re_synchronize_nq(scq_nq);
1038 if (scq_nq != rcq_nq)
1039 bnxt_re_synchronize_nq(rcq_nq);
1040
1041 return 0;
1042 }
1043
__from_ib_qp_type(enum ib_qp_type type)1044 static u8 __from_ib_qp_type(enum ib_qp_type type)
1045 {
1046 switch (type) {
1047 case IB_QPT_GSI:
1048 return CMDQ_CREATE_QP1_TYPE_GSI;
1049 case IB_QPT_RC:
1050 return CMDQ_CREATE_QP_TYPE_RC;
1051 case IB_QPT_UD:
1052 return CMDQ_CREATE_QP_TYPE_UD;
1053 case IB_QPT_RAW_PACKET:
1054 return CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE;
1055 default:
1056 return IB_QPT_MAX;
1057 }
1058 }
1059
bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp * qplqp,int rsge,int max)1060 static u16 bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp *qplqp,
1061 int rsge, int max)
1062 {
1063 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC)
1064 rsge = max;
1065 return bnxt_re_get_rwqe_size(rsge);
1066 }
1067
bnxt_re_get_wqe_size(int ilsize,int nsge)1068 static u16 bnxt_re_get_wqe_size(int ilsize, int nsge)
1069 {
1070 u16 wqe_size, calc_ils;
1071
1072 wqe_size = bnxt_re_get_swqe_size(nsge);
1073 if (ilsize) {
1074 calc_ils = sizeof(struct sq_send_hdr) + ilsize;
1075 wqe_size = max_t(u16, calc_ils, wqe_size);
1076 wqe_size = ALIGN(wqe_size, sizeof(struct sq_send_hdr));
1077 }
1078 return wqe_size;
1079 }
1080
bnxt_re_setup_swqe_size(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr)1081 static int bnxt_re_setup_swqe_size(struct bnxt_re_qp *qp,
1082 struct ib_qp_init_attr *init_attr)
1083 {
1084 struct bnxt_qplib_dev_attr *dev_attr;
1085 struct bnxt_qplib_qp *qplqp;
1086 struct bnxt_re_dev *rdev;
1087 struct bnxt_qplib_q *sq;
1088 int align, ilsize;
1089
1090 rdev = qp->rdev;
1091 qplqp = &qp->qplib_qp;
1092 sq = &qplqp->sq;
1093 dev_attr = rdev->dev_attr;
1094
1095 align = sizeof(struct sq_send_hdr);
1096 ilsize = ALIGN(init_attr->cap.max_inline_data, align);
1097
1098 /* For gen p4 and gen p5 fixed wqe compatibility mode
1099 * wqe size is fixed to 128 bytes - ie 6 SGEs
1100 */
1101 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) {
1102 sq->wqe_size = bnxt_re_get_swqe_size(BNXT_STATIC_MAX_SGE);
1103 sq->max_sge = BNXT_STATIC_MAX_SGE;
1104 } else {
1105 sq->wqe_size = bnxt_re_get_wqe_size(ilsize, sq->max_sge);
1106 if (sq->wqe_size > bnxt_re_get_swqe_size(dev_attr->max_qp_sges))
1107 return -EINVAL;
1108 }
1109
1110 if (init_attr->cap.max_inline_data) {
1111 qplqp->max_inline_data = sq->wqe_size -
1112 sizeof(struct sq_send_hdr);
1113 init_attr->cap.max_inline_data = qplqp->max_inline_data;
1114 }
1115
1116 return 0;
1117 }
1118
bnxt_re_init_user_qp(struct bnxt_re_dev * rdev,struct bnxt_re_pd * pd,struct bnxt_re_qp * qp,struct bnxt_re_ucontext * cntx,struct bnxt_re_qp_req * ureq)1119 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd,
1120 struct bnxt_re_qp *qp, struct bnxt_re_ucontext *cntx,
1121 struct bnxt_re_qp_req *ureq)
1122 {
1123 struct bnxt_qplib_qp *qplib_qp;
1124 int bytes = 0, psn_sz;
1125 struct ib_umem *umem;
1126 int psn_nume;
1127
1128 qplib_qp = &qp->qplib_qp;
1129
1130 bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size);
1131 /* Consider mapping PSN search memory only for RC QPs. */
1132 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) {
1133 psn_sz = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ?
1134 sizeof(struct sq_psn_search_ext) :
1135 sizeof(struct sq_psn_search);
1136 if (cntx && bnxt_re_is_var_size_supported(rdev, cntx)) {
1137 psn_nume = ureq->sq_slots;
1138 } else {
1139 psn_nume = (qplib_qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ?
1140 qplib_qp->sq.max_wqe : ((qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size) /
1141 sizeof(struct bnxt_qplib_sge));
1142 }
1143 if (_is_host_msn_table(rdev->qplib_res.dattr->dev_cap_flags2))
1144 psn_nume = roundup_pow_of_two(psn_nume);
1145 bytes += (psn_nume * psn_sz);
1146 }
1147
1148 bytes = PAGE_ALIGN(bytes);
1149 umem = ib_umem_get(&rdev->ibdev, ureq->qpsva, bytes,
1150 IB_ACCESS_LOCAL_WRITE);
1151 if (IS_ERR(umem))
1152 return PTR_ERR(umem);
1153
1154 qp->sumem = umem;
1155 qplib_qp->sq.sg_info.umem = umem;
1156 qplib_qp->sq.sg_info.pgsize = PAGE_SIZE;
1157 qplib_qp->sq.sg_info.pgshft = PAGE_SHIFT;
1158 qplib_qp->qp_handle = ureq->qp_handle;
1159
1160 if (!qp->qplib_qp.srq) {
1161 bytes = (qplib_qp->rq.max_wqe * qplib_qp->rq.wqe_size);
1162 bytes = PAGE_ALIGN(bytes);
1163 umem = ib_umem_get(&rdev->ibdev, ureq->qprva, bytes,
1164 IB_ACCESS_LOCAL_WRITE);
1165 if (IS_ERR(umem))
1166 goto rqfail;
1167 qp->rumem = umem;
1168 qplib_qp->rq.sg_info.umem = umem;
1169 qplib_qp->rq.sg_info.pgsize = PAGE_SIZE;
1170 qplib_qp->rq.sg_info.pgshft = PAGE_SHIFT;
1171 }
1172
1173 qplib_qp->dpi = &cntx->dpi;
1174 return 0;
1175 rqfail:
1176 ib_umem_release(qp->sumem);
1177 qp->sumem = NULL;
1178 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info));
1179
1180 return PTR_ERR(umem);
1181 }
1182
bnxt_re_create_shadow_qp_ah(struct bnxt_re_pd * pd,struct bnxt_qplib_res * qp1_res,struct bnxt_qplib_qp * qp1_qp)1183 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah
1184 (struct bnxt_re_pd *pd,
1185 struct bnxt_qplib_res *qp1_res,
1186 struct bnxt_qplib_qp *qp1_qp)
1187 {
1188 struct bnxt_re_dev *rdev = pd->rdev;
1189 struct bnxt_re_ah *ah;
1190 union ib_gid sgid;
1191 int rc;
1192
1193 ah = kzalloc_obj(*ah);
1194 if (!ah)
1195 return NULL;
1196
1197 ah->rdev = rdev;
1198 ah->qplib_ah.pd = &pd->qplib_pd;
1199
1200 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid);
1201 if (rc)
1202 goto fail;
1203
1204 /* supply the dgid data same as sgid */
1205 memcpy(ah->qplib_ah.dgid.data, &sgid.raw,
1206 sizeof(union ib_gid));
1207 ah->qplib_ah.sgid_index = 0;
1208
1209 ah->qplib_ah.traffic_class = 0;
1210 ah->qplib_ah.flow_label = 0;
1211 ah->qplib_ah.hop_limit = 1;
1212 ah->qplib_ah.sl = 0;
1213 /* Have DMAC same as SMAC */
1214 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr);
1215
1216 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false);
1217 if (rc) {
1218 ibdev_err(&rdev->ibdev,
1219 "Failed to allocate HW AH for Shadow QP");
1220 goto fail;
1221 }
1222 atomic_inc(&rdev->stats.res.ah_count);
1223
1224 return ah;
1225
1226 fail:
1227 kfree(ah);
1228 return NULL;
1229 }
1230
bnxt_re_create_shadow_qp(struct bnxt_re_pd * pd,struct bnxt_qplib_res * qp1_res,struct bnxt_qplib_qp * qp1_qp)1231 static struct bnxt_re_qp *bnxt_re_create_shadow_qp
1232 (struct bnxt_re_pd *pd,
1233 struct bnxt_qplib_res *qp1_res,
1234 struct bnxt_qplib_qp *qp1_qp)
1235 {
1236 struct bnxt_re_dev *rdev = pd->rdev;
1237 struct bnxt_re_qp *qp;
1238 int rc;
1239
1240 qp = kzalloc_obj(*qp);
1241 if (!qp)
1242 return NULL;
1243
1244 qp->rdev = rdev;
1245
1246 /* Initialize the shadow QP structure from the QP1 values */
1247 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
1248
1249 qp->qplib_qp.pd = &pd->qplib_pd;
1250 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
1251 qp->qplib_qp.type = IB_QPT_UD;
1252
1253 qp->qplib_qp.max_inline_data = 0;
1254 qp->qplib_qp.sig_type = true;
1255
1256 /* Shadow QP SQ depth should be same as QP1 RQ depth */
1257 qp->qplib_qp.sq.wqe_size = bnxt_re_get_wqe_size(0, 6);
1258 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;
1259 qp->qplib_qp.sq.max_sw_wqe = qp1_qp->rq.max_wqe;
1260 qp->qplib_qp.sq.max_sge = 2;
1261 /* Q full delta can be 1 since it is internal QP */
1262 qp->qplib_qp.sq.q_full_delta = 1;
1263 qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE;
1264 qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT;
1265
1266 qp->qplib_qp.scq = qp1_qp->scq;
1267 qp->qplib_qp.rcq = qp1_qp->rcq;
1268
1269 qp->qplib_qp.rq.wqe_size = bnxt_re_get_rwqe_size(6);
1270 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;
1271 qp->qplib_qp.rq.max_sw_wqe = qp1_qp->rq.max_wqe;
1272 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;
1273 /* Q full delta can be 1 since it is internal QP */
1274 qp->qplib_qp.rq.q_full_delta = 1;
1275 qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE;
1276 qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT;
1277
1278 qp->qplib_qp.mtu = qp1_qp->mtu;
1279
1280 qp->qplib_qp.sq_hdr_buf_size = 0;
1281 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
1282 qp->qplib_qp.dpi = &rdev->dpi_privileged;
1283
1284 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp);
1285 if (rc)
1286 goto fail;
1287
1288 spin_lock_init(&qp->sq_lock);
1289 INIT_LIST_HEAD(&qp->list);
1290 mutex_lock(&rdev->qp_lock);
1291 list_add_tail(&qp->list, &rdev->qp_list);
1292 atomic_inc(&rdev->stats.res.qp_count);
1293 mutex_unlock(&rdev->qp_lock);
1294 return qp;
1295 fail:
1296 kfree(qp);
1297 return NULL;
1298 }
1299
bnxt_re_init_rq_attr(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr,struct bnxt_re_ucontext * uctx)1300 static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp,
1301 struct ib_qp_init_attr *init_attr,
1302 struct bnxt_re_ucontext *uctx)
1303 {
1304 struct bnxt_qplib_dev_attr *dev_attr;
1305 struct bnxt_qplib_qp *qplqp;
1306 struct bnxt_re_dev *rdev;
1307 struct bnxt_qplib_q *rq;
1308 int entries;
1309
1310 rdev = qp->rdev;
1311 qplqp = &qp->qplib_qp;
1312 rq = &qplqp->rq;
1313 dev_attr = rdev->dev_attr;
1314
1315 if (init_attr->srq) {
1316 struct bnxt_re_srq *srq;
1317
1318 srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq);
1319 qplqp->srq = &srq->qplib_srq;
1320 rq->max_wqe = 0;
1321 } else {
1322 rq->max_sge = init_attr->cap.max_recv_sge;
1323 if (rq->max_sge > dev_attr->max_qp_sges)
1324 rq->max_sge = dev_attr->max_qp_sges;
1325 init_attr->cap.max_recv_sge = rq->max_sge;
1326 rq->wqe_size = bnxt_re_setup_rwqe_size(qplqp, rq->max_sge,
1327 dev_attr->max_qp_sges);
1328 /* Allocate 1 more than what's provided so posting max doesn't
1329 * mean empty.
1330 */
1331 entries = bnxt_re_init_depth(init_attr->cap.max_recv_wr + 1, uctx);
1332 rq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1);
1333 rq->max_sw_wqe = rq->max_wqe;
1334 rq->q_full_delta = 0;
1335 rq->sg_info.pgsize = PAGE_SIZE;
1336 rq->sg_info.pgshft = PAGE_SHIFT;
1337 }
1338
1339 return 0;
1340 }
1341
bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp * qp)1342 static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp)
1343 {
1344 struct bnxt_qplib_dev_attr *dev_attr;
1345 struct bnxt_qplib_qp *qplqp;
1346 struct bnxt_re_dev *rdev;
1347
1348 rdev = qp->rdev;
1349 qplqp = &qp->qplib_qp;
1350 dev_attr = rdev->dev_attr;
1351
1352 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) {
1353 qplqp->rq.max_sge = dev_attr->max_qp_sges;
1354 if (qplqp->rq.max_sge > dev_attr->max_qp_sges)
1355 qplqp->rq.max_sge = dev_attr->max_qp_sges;
1356 qplqp->rq.max_sge = 6;
1357 }
1358 }
1359
bnxt_re_init_sq_attr(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr,struct bnxt_re_ucontext * uctx,struct bnxt_re_qp_req * ureq)1360 static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp,
1361 struct ib_qp_init_attr *init_attr,
1362 struct bnxt_re_ucontext *uctx,
1363 struct bnxt_re_qp_req *ureq)
1364 {
1365 struct bnxt_qplib_dev_attr *dev_attr;
1366 struct bnxt_qplib_qp *qplqp;
1367 struct bnxt_re_dev *rdev;
1368 struct bnxt_qplib_q *sq;
1369 int diff = 0;
1370 int entries;
1371 int rc;
1372
1373 rdev = qp->rdev;
1374 qplqp = &qp->qplib_qp;
1375 sq = &qplqp->sq;
1376 dev_attr = rdev->dev_attr;
1377
1378 sq->max_sge = init_attr->cap.max_send_sge;
1379 entries = init_attr->cap.max_send_wr;
1380 if (uctx && qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) {
1381 sq->max_wqe = ureq->sq_slots;
1382 sq->max_sw_wqe = ureq->sq_slots;
1383 sq->wqe_size = sizeof(struct sq_sge);
1384 } else {
1385 if (sq->max_sge > dev_attr->max_qp_sges) {
1386 sq->max_sge = dev_attr->max_qp_sges;
1387 init_attr->cap.max_send_sge = sq->max_sge;
1388 }
1389
1390 rc = bnxt_re_setup_swqe_size(qp, init_attr);
1391 if (rc)
1392 return rc;
1393
1394 /* Allocate 128 + 1 more than what's provided */
1395 diff = (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) ?
1396 0 : BNXT_QPLIB_RESERVED_QP_WRS;
1397 entries = bnxt_re_init_depth(entries + diff + 1, uctx);
1398 sq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + diff + 1);
1399 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE)
1400 sq->max_sw_wqe = bnxt_qplib_get_depth(sq, qplqp->wqe_mode, true);
1401 else
1402 sq->max_sw_wqe = sq->max_wqe;
1403
1404 }
1405 sq->q_full_delta = diff + 1;
1406 /*
1407 * Reserving one slot for Phantom WQE. Application can
1408 * post one extra entry in this case. But allowing this to avoid
1409 * unexpected Queue full condition
1410 */
1411 qplqp->sq.q_full_delta -= 1;
1412 qplqp->sq.sg_info.pgsize = PAGE_SIZE;
1413 qplqp->sq.sg_info.pgshft = PAGE_SHIFT;
1414
1415 return 0;
1416 }
1417
bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr,struct bnxt_re_ucontext * uctx)1418 static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp,
1419 struct ib_qp_init_attr *init_attr,
1420 struct bnxt_re_ucontext *uctx)
1421 {
1422 struct bnxt_qplib_dev_attr *dev_attr;
1423 struct bnxt_qplib_qp *qplqp;
1424 struct bnxt_re_dev *rdev;
1425 int entries;
1426
1427 rdev = qp->rdev;
1428 qplqp = &qp->qplib_qp;
1429 dev_attr = rdev->dev_attr;
1430
1431 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) {
1432 entries = bnxt_re_init_depth(init_attr->cap.max_send_wr + 1, uctx);
1433 qplqp->sq.max_wqe = min_t(u32, entries,
1434 dev_attr->max_qp_wqes + 1);
1435 qplqp->sq.q_full_delta = qplqp->sq.max_wqe -
1436 init_attr->cap.max_send_wr;
1437 qplqp->sq.max_sge++; /* Need one extra sge to put UD header */
1438 if (qplqp->sq.max_sge > dev_attr->max_qp_sges)
1439 qplqp->sq.max_sge = dev_attr->max_qp_sges;
1440 }
1441 }
1442
bnxt_re_init_qp_type(struct bnxt_re_dev * rdev,struct ib_qp_init_attr * init_attr)1443 static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev,
1444 struct ib_qp_init_attr *init_attr)
1445 {
1446 struct bnxt_qplib_chip_ctx *chip_ctx;
1447 int qptype;
1448
1449 chip_ctx = rdev->chip_ctx;
1450
1451 qptype = __from_ib_qp_type(init_attr->qp_type);
1452 if (qptype == IB_QPT_MAX) {
1453 ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype);
1454 qptype = -EOPNOTSUPP;
1455 goto out;
1456 }
1457
1458 if (bnxt_qplib_is_chip_gen_p5_p7(chip_ctx) &&
1459 init_attr->qp_type == IB_QPT_GSI)
1460 qptype = CMDQ_CREATE_QP_TYPE_GSI;
1461 out:
1462 return qptype;
1463 }
1464
bnxt_re_init_qp_attr(struct bnxt_re_qp * qp,struct bnxt_re_pd * pd,struct ib_qp_init_attr * init_attr,struct bnxt_re_ucontext * uctx,struct bnxt_re_qp_req * ureq)1465 static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1466 struct ib_qp_init_attr *init_attr,
1467 struct bnxt_re_ucontext *uctx,
1468 struct bnxt_re_qp_req *ureq)
1469 {
1470 struct bnxt_qplib_dev_attr *dev_attr;
1471 struct bnxt_qplib_qp *qplqp;
1472 struct bnxt_re_dev *rdev;
1473 struct bnxt_re_cq *cq;
1474 int rc = 0, qptype;
1475
1476 rdev = qp->rdev;
1477 qplqp = &qp->qplib_qp;
1478 dev_attr = rdev->dev_attr;
1479
1480 /* Setup misc params */
1481 ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr);
1482 qplqp->pd = &pd->qplib_pd;
1483 qplqp->qp_handle = (u64)qplqp;
1484 qplqp->max_inline_data = init_attr->cap.max_inline_data;
1485 qplqp->sig_type = init_attr->sq_sig_type == IB_SIGNAL_ALL_WR;
1486 qptype = bnxt_re_init_qp_type(rdev, init_attr);
1487 if (qptype < 0) {
1488 rc = qptype;
1489 goto out;
1490 }
1491 qplqp->type = (u8)qptype;
1492 qplqp->wqe_mode = bnxt_re_is_var_size_supported(rdev, uctx);
1493 if (init_attr->qp_type == IB_QPT_RC) {
1494 qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom;
1495 qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;
1496 }
1497 qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1498 qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */
1499 if (init_attr->create_flags) {
1500 ibdev_dbg(&rdev->ibdev,
1501 "QP create flags 0x%x not supported",
1502 init_attr->create_flags);
1503 return -EOPNOTSUPP;
1504 }
1505
1506 /* Setup CQs */
1507 if (init_attr->send_cq) {
1508 cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq);
1509 qplqp->scq = &cq->qplib_cq;
1510 qp->scq = cq;
1511 }
1512
1513 if (init_attr->recv_cq) {
1514 cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq);
1515 qplqp->rcq = &cq->qplib_cq;
1516 qp->rcq = cq;
1517 }
1518
1519 /* Setup RQ/SRQ */
1520 rc = bnxt_re_init_rq_attr(qp, init_attr, uctx);
1521 if (rc)
1522 goto out;
1523 if (init_attr->qp_type == IB_QPT_GSI)
1524 bnxt_re_adjust_gsi_rq_attr(qp);
1525
1526 /* Setup SQ */
1527 rc = bnxt_re_init_sq_attr(qp, init_attr, uctx, ureq);
1528 if (rc)
1529 goto out;
1530 if (init_attr->qp_type == IB_QPT_GSI)
1531 bnxt_re_adjust_gsi_sq_attr(qp, init_attr, uctx);
1532
1533 if (uctx) /* This will update DPI and qp_handle */
1534 rc = bnxt_re_init_user_qp(rdev, pd, qp, uctx, ureq);
1535 out:
1536 return rc;
1537 }
1538
bnxt_re_create_shadow_gsi(struct bnxt_re_qp * qp,struct bnxt_re_pd * pd)1539 static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp,
1540 struct bnxt_re_pd *pd)
1541 {
1542 struct bnxt_re_sqp_entries *sqp_tbl;
1543 struct bnxt_re_dev *rdev;
1544 struct bnxt_re_qp *sqp;
1545 struct bnxt_re_ah *sah;
1546 int rc = 0;
1547
1548 rdev = qp->rdev;
1549 /* Create a shadow QP to handle the QP1 traffic */
1550 sqp_tbl = kzalloc_objs(*sqp_tbl, BNXT_RE_MAX_GSI_SQP_ENTRIES);
1551 if (!sqp_tbl)
1552 return -ENOMEM;
1553 rdev->gsi_ctx.sqp_tbl = sqp_tbl;
1554
1555 sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp);
1556 if (!sqp) {
1557 rc = -ENODEV;
1558 ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1");
1559 goto out;
1560 }
1561 rdev->gsi_ctx.gsi_sqp = sqp;
1562
1563 sqp->rcq = qp->rcq;
1564 sqp->scq = qp->scq;
1565 sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res,
1566 &qp->qplib_qp);
1567 if (!sah) {
1568 bnxt_qplib_destroy_qp(&rdev->qplib_res,
1569 &sqp->qplib_qp);
1570 rc = -ENODEV;
1571 ibdev_err(&rdev->ibdev,
1572 "Failed to create AH entry for ShadowQP");
1573 goto out;
1574 }
1575 rdev->gsi_ctx.gsi_sah = sah;
1576
1577 return 0;
1578 out:
1579 kfree(sqp_tbl);
1580 return rc;
1581 }
1582
bnxt_re_create_gsi_qp(struct bnxt_re_qp * qp,struct bnxt_re_pd * pd,struct ib_qp_init_attr * init_attr)1583 static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1584 struct ib_qp_init_attr *init_attr)
1585 {
1586 struct bnxt_re_dev *rdev;
1587 struct bnxt_qplib_qp *qplqp;
1588 int rc;
1589
1590 rdev = qp->rdev;
1591 qplqp = &qp->qplib_qp;
1592
1593 qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
1594 qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2;
1595
1596 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp);
1597 if (rc) {
1598 ibdev_err(&rdev->ibdev, "create HW QP1 failed!");
1599 goto out;
1600 }
1601
1602 rc = bnxt_re_create_shadow_gsi(qp, pd);
1603 out:
1604 return rc;
1605 }
1606
bnxt_re_test_qp_limits(struct bnxt_re_dev * rdev,struct ib_qp_init_attr * init_attr,struct bnxt_qplib_dev_attr * dev_attr)1607 static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev,
1608 struct ib_qp_init_attr *init_attr,
1609 struct bnxt_qplib_dev_attr *dev_attr)
1610 {
1611 bool rc = true;
1612
1613 if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes ||
1614 init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes ||
1615 init_attr->cap.max_send_sge > dev_attr->max_qp_sges ||
1616 init_attr->cap.max_recv_sge > dev_attr->max_qp_sges ||
1617 init_attr->cap.max_inline_data > dev_attr->max_inline_data) {
1618 ibdev_err(&rdev->ibdev,
1619 "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x",
1620 init_attr->cap.max_send_wr, dev_attr->max_qp_wqes,
1621 init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes,
1622 init_attr->cap.max_send_sge, dev_attr->max_qp_sges,
1623 init_attr->cap.max_recv_sge, dev_attr->max_qp_sges,
1624 init_attr->cap.max_inline_data,
1625 dev_attr->max_inline_data);
1626 rc = false;
1627 }
1628 return rc;
1629 }
1630
bnxt_re_add_unique_gid(struct bnxt_re_dev * rdev)1631 static int bnxt_re_add_unique_gid(struct bnxt_re_dev *rdev)
1632 {
1633 struct bnxt_qplib_ctx *hctx = &rdev->qplib_ctx;
1634 struct bnxt_qplib_res *res = &rdev->qplib_res;
1635 int rc;
1636
1637 if (!rdev->rcfw.roce_mirror)
1638 return 0;
1639
1640 rdev->ugid.global.subnet_prefix = cpu_to_be64(0xfe8000000000abcdLL);
1641 addrconf_ifid_eui48(&rdev->ugid.raw[8], rdev->netdev);
1642
1643 rc = bnxt_qplib_add_sgid(&res->sgid_tbl,
1644 (struct bnxt_qplib_gid *)&rdev->ugid,
1645 rdev->qplib_res.netdev->dev_addr,
1646 0xFFFF, true, &rdev->ugid_index, true,
1647 hctx->stats3.fw_id);
1648 if (rc)
1649 dev_err(rdev_to_dev(rdev), "Failed to add unique GID. rc = %d\n", rc);
1650
1651 return rc;
1652 }
1653
bnxt_re_create_qp(struct ib_qp * ib_qp,struct ib_qp_init_attr * qp_init_attr,struct ib_udata * udata)1654 int bnxt_re_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *qp_init_attr,
1655 struct ib_udata *udata)
1656 {
1657 struct bnxt_qplib_dev_attr *dev_attr;
1658 struct bnxt_re_ucontext *uctx;
1659 struct bnxt_re_qp_req ureq;
1660 struct bnxt_re_dev *rdev;
1661 struct bnxt_re_pd *pd;
1662 struct bnxt_re_qp *qp;
1663 struct ib_pd *ib_pd;
1664 u32 active_qps;
1665 int rc;
1666
1667 ib_pd = ib_qp->pd;
1668 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1669 rdev = pd->rdev;
1670 dev_attr = rdev->dev_attr;
1671 qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1672
1673 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
1674 if (udata)
1675 if (ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq))))
1676 return -EFAULT;
1677
1678 rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr);
1679 if (!rc) {
1680 rc = -EINVAL;
1681 goto fail;
1682 }
1683
1684 qp->rdev = rdev;
1685 rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, uctx, &ureq);
1686 if (rc)
1687 goto fail;
1688
1689 if (qp_init_attr->qp_type == IB_QPT_GSI &&
1690 !(bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))) {
1691 rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr);
1692 if (rc == -ENODEV)
1693 goto qp_destroy;
1694 if (rc)
1695 goto fail;
1696 } else {
1697 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp);
1698 if (rc) {
1699 ibdev_err(&rdev->ibdev, "Failed to create HW QP");
1700 goto free_umem;
1701 }
1702 if (udata) {
1703 struct bnxt_re_qp_resp resp;
1704
1705 resp.qpid = qp->qplib_qp.id;
1706 resp.rsvd = 0;
1707 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1708 if (rc) {
1709 ibdev_err(&rdev->ibdev, "Failed to copy QP udata");
1710 goto qp_destroy;
1711 }
1712 }
1713 }
1714
1715 /* Support for RawEth QP is added to capture TCP pkt dump.
1716 * So unique SGID is used to avoid incorrect statistics on per
1717 * function stats_ctx
1718 */
1719 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE) {
1720 rc = bnxt_re_add_unique_gid(rdev);
1721 if (rc)
1722 goto qp_destroy;
1723 qp->qplib_qp.ugid_index = rdev->ugid_index;
1724 }
1725
1726 qp->ib_qp.qp_num = qp->qplib_qp.id;
1727 if (qp_init_attr->qp_type == IB_QPT_GSI)
1728 rdev->gsi_ctx.gsi_qp = qp;
1729 spin_lock_init(&qp->sq_lock);
1730 spin_lock_init(&qp->rq_lock);
1731 INIT_LIST_HEAD(&qp->list);
1732 mutex_lock(&rdev->qp_lock);
1733 list_add_tail(&qp->list, &rdev->qp_list);
1734 mutex_unlock(&rdev->qp_lock);
1735 active_qps = atomic_inc_return(&rdev->stats.res.qp_count);
1736 if (active_qps > rdev->stats.res.qp_watermark)
1737 rdev->stats.res.qp_watermark = active_qps;
1738 if (qp_init_attr->qp_type == IB_QPT_RC) {
1739 active_qps = atomic_inc_return(&rdev->stats.res.rc_qp_count);
1740 if (active_qps > rdev->stats.res.rc_qp_watermark)
1741 rdev->stats.res.rc_qp_watermark = active_qps;
1742 } else if (qp_init_attr->qp_type == IB_QPT_UD) {
1743 active_qps = atomic_inc_return(&rdev->stats.res.ud_qp_count);
1744 if (active_qps > rdev->stats.res.ud_qp_watermark)
1745 rdev->stats.res.ud_qp_watermark = active_qps;
1746 }
1747 bnxt_re_debug_add_qpinfo(rdev, qp);
1748
1749 return 0;
1750 qp_destroy:
1751 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
1752 free_umem:
1753 ib_umem_release(qp->rumem);
1754 ib_umem_release(qp->sumem);
1755 fail:
1756 return rc;
1757 }
1758
__from_ib_qp_state(enum ib_qp_state state)1759 static u8 __from_ib_qp_state(enum ib_qp_state state)
1760 {
1761 switch (state) {
1762 case IB_QPS_RESET:
1763 return CMDQ_MODIFY_QP_NEW_STATE_RESET;
1764 case IB_QPS_INIT:
1765 return CMDQ_MODIFY_QP_NEW_STATE_INIT;
1766 case IB_QPS_RTR:
1767 return CMDQ_MODIFY_QP_NEW_STATE_RTR;
1768 case IB_QPS_RTS:
1769 return CMDQ_MODIFY_QP_NEW_STATE_RTS;
1770 case IB_QPS_SQD:
1771 return CMDQ_MODIFY_QP_NEW_STATE_SQD;
1772 case IB_QPS_SQE:
1773 return CMDQ_MODIFY_QP_NEW_STATE_SQE;
1774 case IB_QPS_ERR:
1775 default:
1776 return CMDQ_MODIFY_QP_NEW_STATE_ERR;
1777 }
1778 }
1779
__to_ib_qp_state(u8 state)1780 static enum ib_qp_state __to_ib_qp_state(u8 state)
1781 {
1782 switch (state) {
1783 case CMDQ_MODIFY_QP_NEW_STATE_RESET:
1784 return IB_QPS_RESET;
1785 case CMDQ_MODIFY_QP_NEW_STATE_INIT:
1786 return IB_QPS_INIT;
1787 case CMDQ_MODIFY_QP_NEW_STATE_RTR:
1788 return IB_QPS_RTR;
1789 case CMDQ_MODIFY_QP_NEW_STATE_RTS:
1790 return IB_QPS_RTS;
1791 case CMDQ_MODIFY_QP_NEW_STATE_SQD:
1792 return IB_QPS_SQD;
1793 case CMDQ_MODIFY_QP_NEW_STATE_SQE:
1794 return IB_QPS_SQE;
1795 case CMDQ_MODIFY_QP_NEW_STATE_ERR:
1796 default:
1797 return IB_QPS_ERR;
1798 }
1799 }
1800
__from_ib_mtu(enum ib_mtu mtu)1801 static u32 __from_ib_mtu(enum ib_mtu mtu)
1802 {
1803 switch (mtu) {
1804 case IB_MTU_256:
1805 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256;
1806 case IB_MTU_512:
1807 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512;
1808 case IB_MTU_1024:
1809 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024;
1810 case IB_MTU_2048:
1811 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1812 case IB_MTU_4096:
1813 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096;
1814 default:
1815 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1816 }
1817 }
1818
__to_ib_mtu(u32 mtu)1819 static enum ib_mtu __to_ib_mtu(u32 mtu)
1820 {
1821 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) {
1822 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256:
1823 return IB_MTU_256;
1824 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512:
1825 return IB_MTU_512;
1826 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024:
1827 return IB_MTU_1024;
1828 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048:
1829 return IB_MTU_2048;
1830 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096:
1831 return IB_MTU_4096;
1832 default:
1833 return IB_MTU_2048;
1834 }
1835 }
1836
1837 /* Shared Receive Queues */
bnxt_re_destroy_srq(struct ib_srq * ib_srq,struct ib_udata * udata)1838 int bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata)
1839 {
1840 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1841 ib_srq);
1842 struct bnxt_re_dev *rdev = srq->rdev;
1843 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1844
1845 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) {
1846 free_page((unsigned long)srq->uctx_srq_page);
1847 hash_del(&srq->hash_entry);
1848 }
1849 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq);
1850 ib_umem_release(srq->umem);
1851 atomic_dec(&rdev->stats.res.srq_count);
1852 return 0;
1853 }
1854
bnxt_re_init_user_srq(struct bnxt_re_dev * rdev,struct bnxt_re_pd * pd,struct bnxt_re_srq * srq,struct ib_udata * udata)1855 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev,
1856 struct bnxt_re_pd *pd,
1857 struct bnxt_re_srq *srq,
1858 struct ib_udata *udata)
1859 {
1860 struct bnxt_re_srq_req ureq;
1861 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1862 struct ib_umem *umem;
1863 int bytes = 0;
1864 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context(
1865 udata, struct bnxt_re_ucontext, ib_uctx);
1866
1867 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
1868 return -EFAULT;
1869
1870 bytes = (qplib_srq->max_wqe * qplib_srq->wqe_size);
1871 bytes = PAGE_ALIGN(bytes);
1872 umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes,
1873 IB_ACCESS_LOCAL_WRITE);
1874 if (IS_ERR(umem))
1875 return PTR_ERR(umem);
1876
1877 srq->umem = umem;
1878 qplib_srq->sg_info.umem = umem;
1879 qplib_srq->sg_info.pgsize = PAGE_SIZE;
1880 qplib_srq->sg_info.pgshft = PAGE_SHIFT;
1881 qplib_srq->srq_handle = ureq.srq_handle;
1882 qplib_srq->dpi = &cntx->dpi;
1883
1884 return 0;
1885 }
1886
bnxt_re_create_srq(struct ib_srq * ib_srq,struct ib_srq_init_attr * srq_init_attr,struct ib_udata * udata)1887 int bnxt_re_create_srq(struct ib_srq *ib_srq,
1888 struct ib_srq_init_attr *srq_init_attr,
1889 struct ib_udata *udata)
1890 {
1891 struct bnxt_qplib_dev_attr *dev_attr;
1892 struct bnxt_re_ucontext *uctx;
1893 struct bnxt_re_dev *rdev;
1894 struct bnxt_re_srq *srq;
1895 struct bnxt_re_pd *pd;
1896 struct ib_pd *ib_pd;
1897 u32 active_srqs;
1898 int rc, entries;
1899
1900 ib_pd = ib_srq->pd;
1901 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1902 rdev = pd->rdev;
1903 dev_attr = rdev->dev_attr;
1904 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq);
1905
1906 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) {
1907 ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded");
1908 rc = -EINVAL;
1909 goto exit;
1910 }
1911
1912 if (srq_init_attr->srq_type != IB_SRQT_BASIC) {
1913 rc = -EOPNOTSUPP;
1914 goto exit;
1915 }
1916
1917 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
1918 srq->rdev = rdev;
1919 srq->qplib_srq.pd = &pd->qplib_pd;
1920 srq->qplib_srq.dpi = &rdev->dpi_privileged;
1921 /* Allocate 1 more than what's provided so posting max doesn't
1922 * mean empty
1923 */
1924 entries = bnxt_re_init_depth(srq_init_attr->attr.max_wr + 1, uctx);
1925 if (entries > dev_attr->max_srq_wqes + 1)
1926 entries = dev_attr->max_srq_wqes + 1;
1927 srq->qplib_srq.max_wqe = entries;
1928
1929 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge;
1930 /* 128 byte wqe size for SRQ . So use max sges */
1931 srq->qplib_srq.wqe_size = bnxt_re_get_rwqe_size(dev_attr->max_srq_sges);
1932 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit;
1933 srq->srq_limit = srq_init_attr->attr.srq_limit;
1934 srq->qplib_srq.eventq_hw_ring_id = rdev->nqr->nq[0].ring_id;
1935 srq->qplib_srq.sg_info.pgsize = PAGE_SIZE;
1936 srq->qplib_srq.sg_info.pgshft = PAGE_SHIFT;
1937
1938 if (udata) {
1939 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata);
1940 if (rc)
1941 goto fail;
1942 }
1943
1944 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq);
1945 if (rc) {
1946 ibdev_err(&rdev->ibdev, "Create HW SRQ failed!");
1947 goto fail;
1948 }
1949
1950 if (udata) {
1951 struct bnxt_re_srq_resp resp = {};
1952
1953 resp.srqid = srq->qplib_srq.id;
1954 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) {
1955 hash_add(rdev->srq_hash, &srq->hash_entry, srq->qplib_srq.id);
1956 srq->uctx_srq_page = (void *)get_zeroed_page(GFP_KERNEL);
1957 if (!srq->uctx_srq_page) {
1958 rc = -ENOMEM;
1959 goto fail;
1960 }
1961 resp.comp_mask |= BNXT_RE_SRQ_TOGGLE_PAGE_SUPPORT;
1962 }
1963 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1964 if (rc) {
1965 ibdev_err(&rdev->ibdev, "SRQ copy to udata failed!");
1966 bnxt_qplib_destroy_srq(&rdev->qplib_res,
1967 &srq->qplib_srq);
1968 goto fail;
1969 }
1970 }
1971 active_srqs = atomic_inc_return(&rdev->stats.res.srq_count);
1972 if (active_srqs > rdev->stats.res.srq_watermark)
1973 rdev->stats.res.srq_watermark = active_srqs;
1974 spin_lock_init(&srq->lock);
1975
1976 return 0;
1977
1978 fail:
1979 ib_umem_release(srq->umem);
1980 exit:
1981 return rc;
1982 }
1983
bnxt_re_modify_srq(struct ib_srq * ib_srq,struct ib_srq_attr * srq_attr,enum ib_srq_attr_mask srq_attr_mask,struct ib_udata * udata)1984 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr,
1985 enum ib_srq_attr_mask srq_attr_mask,
1986 struct ib_udata *udata)
1987 {
1988 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1989 ib_srq);
1990 struct bnxt_re_dev *rdev = srq->rdev;
1991
1992 switch (srq_attr_mask) {
1993 case IB_SRQ_MAX_WR:
1994 /* SRQ resize is not supported */
1995 return -EINVAL;
1996 case IB_SRQ_LIMIT:
1997 /* Change the SRQ threshold */
1998 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe)
1999 return -EINVAL;
2000
2001 srq->qplib_srq.threshold = srq_attr->srq_limit;
2002 bnxt_qplib_srq_arm_db(&srq->qplib_srq.dbinfo, srq->qplib_srq.threshold);
2003
2004 /* On success, update the shadow */
2005 srq->srq_limit = srq_attr->srq_limit;
2006 /* No need to Build and send response back to udata */
2007 return 0;
2008 default:
2009 ibdev_err(&rdev->ibdev,
2010 "Unsupported srq_attr_mask 0x%x", srq_attr_mask);
2011 return -EINVAL;
2012 }
2013 }
2014
bnxt_re_query_srq(struct ib_srq * ib_srq,struct ib_srq_attr * srq_attr)2015 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr)
2016 {
2017 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
2018 ib_srq);
2019 struct bnxt_re_srq tsrq;
2020 struct bnxt_re_dev *rdev = srq->rdev;
2021 int rc;
2022
2023 /* Get live SRQ attr */
2024 tsrq.qplib_srq.id = srq->qplib_srq.id;
2025 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq);
2026 if (rc) {
2027 ibdev_err(&rdev->ibdev, "Query HW SRQ failed!");
2028 return rc;
2029 }
2030 srq_attr->max_wr = srq->qplib_srq.max_wqe;
2031 srq_attr->max_sge = srq->qplib_srq.max_sge;
2032 srq_attr->srq_limit = tsrq.qplib_srq.threshold;
2033
2034 return 0;
2035 }
2036
bnxt_re_post_srq_recv(struct ib_srq * ib_srq,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)2037 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr,
2038 const struct ib_recv_wr **bad_wr)
2039 {
2040 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
2041 ib_srq);
2042 struct bnxt_qplib_swqe wqe;
2043 unsigned long flags;
2044 int rc = 0;
2045
2046 spin_lock_irqsave(&srq->lock, flags);
2047 while (wr) {
2048 /* Transcribe each ib_recv_wr to qplib_swqe */
2049 wqe.num_sge = wr->num_sge;
2050 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
2051 wqe.wr_id = wr->wr_id;
2052 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2053
2054 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe);
2055 if (rc) {
2056 *bad_wr = wr;
2057 break;
2058 }
2059 wr = wr->next;
2060 }
2061 spin_unlock_irqrestore(&srq->lock, flags);
2062
2063 return rc;
2064 }
bnxt_re_modify_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp1_qp,int qp_attr_mask)2065 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,
2066 struct bnxt_re_qp *qp1_qp,
2067 int qp_attr_mask)
2068 {
2069 struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp;
2070 int rc;
2071
2072 if (qp_attr_mask & IB_QP_STATE) {
2073 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
2074 qp->qplib_qp.state = qp1_qp->qplib_qp.state;
2075 }
2076 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
2077 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
2078 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index;
2079 }
2080
2081 if (qp_attr_mask & IB_QP_QKEY) {
2082 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
2083 /* Using a Random QKEY */
2084 qp->qplib_qp.qkey = 0x81818181;
2085 }
2086 if (qp_attr_mask & IB_QP_SQ_PSN) {
2087 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
2088 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn;
2089 }
2090
2091 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
2092 if (rc)
2093 ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1");
2094 return rc;
2095 }
2096
bnxt_re_modify_qp(struct ib_qp * ib_qp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_udata * udata)2097 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
2098 int qp_attr_mask, struct ib_udata *udata)
2099 {
2100 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2101 struct bnxt_re_dev *rdev = qp->rdev;
2102 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr;
2103 enum ib_qp_state curr_qp_state, new_qp_state;
2104 int rc, entries;
2105 unsigned int flags;
2106 u8 nw_type;
2107
2108 if (qp_attr_mask & ~(IB_QP_ATTR_STANDARD_BITS | IB_QP_RATE_LIMIT))
2109 return -EOPNOTSUPP;
2110
2111 qp->qplib_qp.modify_flags = 0;
2112 qp->qplib_qp.ext_modify_flags = 0;
2113 if (qp_attr_mask & IB_QP_STATE) {
2114 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state);
2115 new_qp_state = qp_attr->qp_state;
2116 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state,
2117 ib_qp->qp_type, qp_attr_mask)) {
2118 ibdev_err(&rdev->ibdev,
2119 "Invalid attribute mask: %#x specified ",
2120 qp_attr_mask);
2121 ibdev_err(&rdev->ibdev,
2122 "for qpn: %#x type: %#x",
2123 ib_qp->qp_num, ib_qp->qp_type);
2124 ibdev_err(&rdev->ibdev,
2125 "curr_qp_state=0x%x, new_qp_state=0x%x\n",
2126 curr_qp_state, new_qp_state);
2127 return -EINVAL;
2128 }
2129 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
2130 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state);
2131
2132 if (!qp->sumem &&
2133 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {
2134 ibdev_dbg(&rdev->ibdev,
2135 "Move QP = %p to flush list\n", qp);
2136 flags = bnxt_re_lock_cqs(qp);
2137 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
2138 bnxt_re_unlock_cqs(qp, flags);
2139 }
2140 if (!qp->sumem &&
2141 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) {
2142 ibdev_dbg(&rdev->ibdev,
2143 "Move QP = %p out of flush list\n", qp);
2144 flags = bnxt_re_lock_cqs(qp);
2145 bnxt_qplib_clean_qp(&qp->qplib_qp);
2146 bnxt_re_unlock_cqs(qp, flags);
2147 }
2148 }
2149
2150 if (qp_attr_mask & IB_QP_RATE_LIMIT) {
2151 if (qp->qplib_qp.type != IB_QPT_RC ||
2152 !_is_modify_qp_rate_limit_supported(dev_attr->dev_cap_flags2))
2153 return -EOPNOTSUPP;
2154 qp->qplib_qp.ext_modify_flags |=
2155 CMDQ_MODIFY_QP_EXT_MODIFY_MASK_RATE_LIMIT_VALID;
2156 qp->qplib_qp.rate_limit = qp_attr->rate_limit;
2157 }
2158 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
2159 qp->qplib_qp.modify_flags |=
2160 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY;
2161 qp->qplib_qp.en_sqd_async_notify = true;
2162 }
2163 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
2164 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS;
2165 qp->qplib_qp.access =
2166 __qp_access_flags_from_ib(qp->qplib_qp.cctx,
2167 qp_attr->qp_access_flags);
2168 /* LOCAL_WRITE access must be set to allow RC receive */
2169 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE;
2170 }
2171 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
2172 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
2173 qp->qplib_qp.pkey_index = qp_attr->pkey_index;
2174 }
2175 if (qp_attr_mask & IB_QP_QKEY) {
2176 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
2177 qp->qplib_qp.qkey = qp_attr->qkey;
2178 }
2179 if (qp_attr_mask & IB_QP_AV) {
2180 const struct ib_global_route *grh =
2181 rdma_ah_read_grh(&qp_attr->ah_attr);
2182 const struct ib_gid_attr *sgid_attr;
2183 struct bnxt_re_gid_ctx *ctx;
2184
2185 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID |
2186 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL |
2187 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX |
2188 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT |
2189 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS |
2190 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC |
2191 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID;
2192 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw,
2193 sizeof(qp->qplib_qp.ah.dgid.data));
2194 qp->qplib_qp.ah.flow_label = grh->flow_label;
2195 sgid_attr = grh->sgid_attr;
2196 /* Get the HW context of the GID. The reference
2197 * of GID table entry is already taken by the caller.
2198 */
2199 ctx = rdma_read_gid_hw_context(sgid_attr);
2200 qp->qplib_qp.ah.sgid_index = ctx->idx;
2201 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index;
2202 qp->qplib_qp.ah.hop_limit = grh->hop_limit;
2203 qp->qplib_qp.ah.traffic_class = grh->traffic_class >> 2;
2204 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr);
2205 ether_addr_copy(qp->qplib_qp.ah.dmac,
2206 qp_attr->ah_attr.roce.dmac);
2207
2208 rc = rdma_read_gid_l2_fields(sgid_attr, NULL,
2209 &qp->qplib_qp.smac[0]);
2210 if (rc)
2211 return rc;
2212
2213 nw_type = rdma_gid_attr_network_type(sgid_attr);
2214 switch (nw_type) {
2215 case RDMA_NETWORK_IPV4:
2216 qp->qplib_qp.nw_type =
2217 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4;
2218 break;
2219 case RDMA_NETWORK_IPV6:
2220 qp->qplib_qp.nw_type =
2221 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6;
2222 break;
2223 default:
2224 qp->qplib_qp.nw_type =
2225 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1;
2226 break;
2227 }
2228 }
2229
2230 if (qp_attr->qp_state == IB_QPS_RTR) {
2231 enum ib_mtu qpmtu;
2232
2233 qpmtu = iboe_get_mtu(rdev->netdev->mtu);
2234 if (qp_attr_mask & IB_QP_PATH_MTU) {
2235 if (ib_mtu_enum_to_int(qp_attr->path_mtu) >
2236 ib_mtu_enum_to_int(qpmtu))
2237 return -EINVAL;
2238 qpmtu = qp_attr->path_mtu;
2239 }
2240
2241 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
2242 qp->qplib_qp.path_mtu = __from_ib_mtu(qpmtu);
2243 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qpmtu);
2244 }
2245
2246 if (qp_attr_mask & IB_QP_TIMEOUT) {
2247 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT;
2248 qp->qplib_qp.timeout = qp_attr->timeout;
2249 }
2250 if (qp_attr_mask & IB_QP_RETRY_CNT) {
2251 qp->qplib_qp.modify_flags |=
2252 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT;
2253 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt;
2254 }
2255 if (qp_attr_mask & IB_QP_RNR_RETRY) {
2256 qp->qplib_qp.modify_flags |=
2257 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY;
2258 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry;
2259 }
2260 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) {
2261 qp->qplib_qp.modify_flags |=
2262 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER;
2263 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer;
2264 }
2265 if (qp_attr_mask & IB_QP_RQ_PSN) {
2266 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN;
2267 qp->qplib_qp.rq.psn = qp_attr->rq_psn;
2268 }
2269 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2270 qp->qplib_qp.modify_flags |=
2271 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC;
2272 /* Cap the max_rd_atomic to device max */
2273 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic,
2274 dev_attr->max_qp_rd_atom);
2275 }
2276 if (qp_attr_mask & IB_QP_SQ_PSN) {
2277 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
2278 qp->qplib_qp.sq.psn = qp_attr->sq_psn;
2279 }
2280 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2281 if (qp_attr->max_dest_rd_atomic >
2282 dev_attr->max_qp_init_rd_atom) {
2283 ibdev_err(&rdev->ibdev,
2284 "max_dest_rd_atomic requested%d is > dev_max%d",
2285 qp_attr->max_dest_rd_atomic,
2286 dev_attr->max_qp_init_rd_atom);
2287 return -EINVAL;
2288 }
2289
2290 qp->qplib_qp.modify_flags |=
2291 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC;
2292 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic;
2293 }
2294 if (qp_attr_mask & IB_QP_CAP) {
2295 struct bnxt_re_ucontext *uctx =
2296 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
2297
2298 qp->qplib_qp.modify_flags |=
2299 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |
2300 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |
2301 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE |
2302 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE |
2303 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA;
2304 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) ||
2305 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) ||
2306 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) ||
2307 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) ||
2308 (qp_attr->cap.max_inline_data >=
2309 dev_attr->max_inline_data)) {
2310 ibdev_err(&rdev->ibdev,
2311 "Create QP failed - max exceeded");
2312 return -EINVAL;
2313 }
2314 entries = bnxt_re_init_depth(qp_attr->cap.max_send_wr, uctx);
2315 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
2316 dev_attr->max_qp_wqes + 1);
2317 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
2318 qp_attr->cap.max_send_wr;
2319 /*
2320 * Reserving one slot for Phantom WQE. Some application can
2321 * post one extra entry in this case. Allowing this to avoid
2322 * unexpected Queue full condition
2323 */
2324 qp->qplib_qp.sq.q_full_delta -= 1;
2325 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;
2326 if (qp->qplib_qp.rq.max_wqe) {
2327 entries = bnxt_re_init_depth(qp_attr->cap.max_recv_wr, uctx);
2328 qp->qplib_qp.rq.max_wqe =
2329 min_t(u32, entries, dev_attr->max_qp_wqes + 1);
2330 qp->qplib_qp.rq.max_sw_wqe = qp->qplib_qp.rq.max_wqe;
2331 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
2332 qp_attr->cap.max_recv_wr;
2333 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;
2334 } else {
2335 /* SRQ was used prior, just ignore the RQ caps */
2336 }
2337 }
2338 if (qp_attr_mask & IB_QP_DEST_QPN) {
2339 qp->qplib_qp.modify_flags |=
2340 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID;
2341 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num;
2342 }
2343 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
2344 if (rc) {
2345 ibdev_err(&rdev->ibdev, "Failed to modify HW QP");
2346 return rc;
2347 }
2348 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp)
2349 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask);
2350 return rc;
2351 }
2352
bnxt_re_query_qp(struct ib_qp * ib_qp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)2353 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
2354 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
2355 {
2356 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2357 struct bnxt_re_dev *rdev = qp->rdev;
2358 struct bnxt_qplib_qp *qplib_qp;
2359 int rc;
2360
2361 qplib_qp = kzalloc_obj(*qplib_qp);
2362 if (!qplib_qp)
2363 return -ENOMEM;
2364
2365 qplib_qp->id = qp->qplib_qp.id;
2366 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;
2367
2368 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp);
2369 if (rc) {
2370 ibdev_err(&rdev->ibdev, "Failed to query HW QP");
2371 goto out;
2372 }
2373 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state);
2374 qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state);
2375 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0;
2376 qp_attr->qp_access_flags = __qp_access_flags_to_ib(qp->qplib_qp.cctx,
2377 qplib_qp->access);
2378 qp_attr->pkey_index = qplib_qp->pkey_index;
2379 qp_attr->qkey = qplib_qp->qkey;
2380 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2381 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->udp_sport,
2382 qplib_qp->ah.host_sgid_index,
2383 qplib_qp->ah.hop_limit,
2384 qplib_qp->ah.traffic_class);
2385 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data);
2386 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl);
2387 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac);
2388 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu);
2389 qp_attr->timeout = qplib_qp->timeout;
2390 qp_attr->retry_cnt = qplib_qp->retry_cnt;
2391 qp_attr->rnr_retry = qplib_qp->rnr_retry;
2392 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer;
2393 qp_attr->port_num = __to_ib_port_num(qplib_qp->port_id);
2394 qp_attr->rq_psn = qplib_qp->rq.psn;
2395 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic;
2396 qp_attr->sq_psn = qplib_qp->sq.psn;
2397 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic;
2398 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR :
2399 IB_SIGNAL_REQ_WR;
2400 qp_attr->dest_qp_num = qplib_qp->dest_qpn;
2401
2402 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;
2403 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;
2404 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe;
2405 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge;
2406 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;
2407 qp_init_attr->cap = qp_attr->cap;
2408
2409 out:
2410 kfree(qplib_qp);
2411 return rc;
2412 }
2413
2414 /* Routine for sending QP1 packets for RoCE V1 an V2
2415 */
bnxt_re_build_qp1_send_v2(struct bnxt_re_qp * qp,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe,int payload_size)2416 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
2417 const struct ib_send_wr *wr,
2418 struct bnxt_qplib_swqe *wqe,
2419 int payload_size)
2420 {
2421 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah,
2422 ib_ah);
2423 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah;
2424 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr;
2425 struct bnxt_qplib_sge sge;
2426 u8 nw_type;
2427 u16 ether_type;
2428 union ib_gid dgid;
2429 bool is_eth = false;
2430 bool is_vlan = false;
2431 bool is_grh = false;
2432 bool is_udp = false;
2433 u8 ip_version = 0;
2434 u16 vlan_id = 0xFFFF;
2435 void *buf;
2436 int i, rc;
2437
2438 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr));
2439
2440 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL);
2441 if (rc)
2442 return rc;
2443
2444 /* Get network header type for this GID */
2445 nw_type = rdma_gid_attr_network_type(sgid_attr);
2446 switch (nw_type) {
2447 case RDMA_NETWORK_IPV4:
2448 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET;
2449 break;
2450 case RDMA_NETWORK_IPV6:
2451 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET;
2452 break;
2453 default:
2454 nw_type = BNXT_RE_ROCE_V1_PACKET;
2455 break;
2456 }
2457 memcpy(&dgid.raw, &qplib_ah->dgid, 16);
2458 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2459 if (is_udp) {
2460 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) {
2461 ip_version = 4;
2462 ether_type = ETH_P_IP;
2463 } else {
2464 ip_version = 6;
2465 ether_type = ETH_P_IPV6;
2466 }
2467 is_grh = false;
2468 } else {
2469 ether_type = ETH_P_IBOE;
2470 is_grh = true;
2471 }
2472
2473 is_eth = true;
2474 is_vlan = vlan_id && (vlan_id < 0x1000);
2475
2476 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh,
2477 ip_version, is_udp, 0, &qp->qp1_hdr);
2478
2479 /* ETH */
2480 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac);
2481 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac);
2482
2483 /* For vlan, check the sgid for vlan existence */
2484
2485 if (!is_vlan) {
2486 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type);
2487 } else {
2488 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type);
2489 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id);
2490 }
2491
2492 if (is_grh || (ip_version == 6)) {
2493 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw,
2494 sizeof(sgid_attr->gid));
2495 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data,
2496 sizeof(sgid_attr->gid));
2497 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit;
2498 }
2499
2500 if (ip_version == 4) {
2501 qp->qp1_hdr.ip4.tos = 0;
2502 qp->qp1_hdr.ip4.id = 0;
2503 qp->qp1_hdr.ip4.frag_off = htons(IP_DF);
2504 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit;
2505
2506 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4);
2507 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4);
2508 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr);
2509 }
2510
2511 if (is_udp) {
2512 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT);
2513 qp->qp1_hdr.udp.sport = htons(0x8CD1);
2514 qp->qp1_hdr.udp.csum = 0;
2515 }
2516
2517 /* BTH */
2518 if (wr->opcode == IB_WR_SEND_WITH_IMM) {
2519 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2520 qp->qp1_hdr.immediate_present = 1;
2521 } else {
2522 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2523 }
2524 if (wr->send_flags & IB_SEND_SOLICITED)
2525 qp->qp1_hdr.bth.solicited_event = 1;
2526 /* pad_count */
2527 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3;
2528
2529 /* P_key for QP1 is for all members */
2530 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF);
2531 qp->qp1_hdr.bth.destination_qpn = IB_QP1;
2532 qp->qp1_hdr.bth.ack_req = 0;
2533 qp->send_psn++;
2534 qp->send_psn &= BTH_PSN_MASK;
2535 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn);
2536 /* DETH */
2537 /* Use the priviledged Q_Key for QP1 */
2538 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY);
2539 qp->qp1_hdr.deth.source_qpn = IB_QP1;
2540
2541 /* Pack the QP1 to the transmit buffer */
2542 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge);
2543 if (buf) {
2544 ib_ud_header_pack(&qp->qp1_hdr, buf);
2545 for (i = wqe->num_sge; i; i--) {
2546 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr;
2547 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey;
2548 wqe->sg_list[i].size = wqe->sg_list[i - 1].size;
2549 }
2550
2551 /*
2552 * Max Header buf size for IPV6 RoCE V2 is 86,
2553 * which is same as the QP1 SQ header buffer.
2554 * Header buf size for IPV4 RoCE V2 can be 66.
2555 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20).
2556 * Subtract 20 bytes from QP1 SQ header buf size
2557 */
2558 if (is_udp && ip_version == 4)
2559 sge.size -= 20;
2560 /*
2561 * Max Header buf size for RoCE V1 is 78.
2562 * ETH(14) + VLAN(4) + GRH(40) + BTH(20).
2563 * Subtract 8 bytes from QP1 SQ header buf size
2564 */
2565 if (!is_udp)
2566 sge.size -= 8;
2567
2568 /* Subtract 4 bytes for non vlan packets */
2569 if (!is_vlan)
2570 sge.size -= 4;
2571
2572 wqe->sg_list[0].addr = sge.addr;
2573 wqe->sg_list[0].lkey = sge.lkey;
2574 wqe->sg_list[0].size = sge.size;
2575 wqe->num_sge++;
2576
2577 } else {
2578 ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!");
2579 rc = -ENOMEM;
2580 }
2581 return rc;
2582 }
2583
2584 /* For the MAD layer, it only provides the recv SGE the size of
2585 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH,
2586 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire
2587 * receive packet (334 bytes) with no VLAN and then copy the GRH
2588 * and the MAD datagram out to the provided SGE.
2589 */
bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp * qp,const struct ib_recv_wr * wr,struct bnxt_qplib_swqe * wqe,int payload_size)2590 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp,
2591 const struct ib_recv_wr *wr,
2592 struct bnxt_qplib_swqe *wqe,
2593 int payload_size)
2594 {
2595 struct bnxt_re_sqp_entries *sqp_entry;
2596 struct bnxt_qplib_sge ref, sge;
2597 struct bnxt_re_dev *rdev;
2598 u32 rq_prod_index;
2599
2600 rdev = qp->rdev;
2601
2602 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp);
2603
2604 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge))
2605 return -ENOMEM;
2606
2607 /* Create 1 SGE to receive the entire
2608 * ethernet packet
2609 */
2610 /* Save the reference from ULP */
2611 ref.addr = wqe->sg_list[0].addr;
2612 ref.lkey = wqe->sg_list[0].lkey;
2613 ref.size = wqe->sg_list[0].size;
2614
2615 sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index];
2616
2617 /* SGE 1 */
2618 wqe->sg_list[0].addr = sge.addr;
2619 wqe->sg_list[0].lkey = sge.lkey;
2620 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
2621 sge.size -= wqe->sg_list[0].size;
2622
2623 sqp_entry->sge.addr = ref.addr;
2624 sqp_entry->sge.lkey = ref.lkey;
2625 sqp_entry->sge.size = ref.size;
2626 /* Store the wrid for reporting completion */
2627 sqp_entry->wrid = wqe->wr_id;
2628 /* change the wqe->wrid to table index */
2629 wqe->wr_id = rq_prod_index;
2630 return 0;
2631 }
2632
is_ud_qp(struct bnxt_re_qp * qp)2633 static int is_ud_qp(struct bnxt_re_qp *qp)
2634 {
2635 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD ||
2636 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI);
2637 }
2638
bnxt_re_build_send_wqe(struct bnxt_re_qp * qp,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2639 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp,
2640 const struct ib_send_wr *wr,
2641 struct bnxt_qplib_swqe *wqe)
2642 {
2643 struct bnxt_re_ah *ah = NULL;
2644
2645 if (is_ud_qp(qp)) {
2646 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah);
2647 wqe->send.q_key = ud_wr(wr)->remote_qkey;
2648 wqe->send.dst_qp = ud_wr(wr)->remote_qpn;
2649 wqe->send.avid = ah->qplib_ah.id;
2650 }
2651 switch (wr->opcode) {
2652 case IB_WR_SEND:
2653 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND;
2654 break;
2655 case IB_WR_SEND_WITH_IMM:
2656 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM;
2657 wqe->send.imm_data = be32_to_cpu(wr->ex.imm_data);
2658 break;
2659 case IB_WR_SEND_WITH_INV:
2660 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV;
2661 wqe->send.inv_key = wr->ex.invalidate_rkey;
2662 break;
2663 default:
2664 return -EINVAL;
2665 }
2666 if (wr->send_flags & IB_SEND_SIGNALED)
2667 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2668 if (wr->send_flags & IB_SEND_FENCE)
2669 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2670 if (wr->send_flags & IB_SEND_SOLICITED)
2671 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2672 if (wr->send_flags & IB_SEND_INLINE)
2673 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2674
2675 return 0;
2676 }
2677
bnxt_re_build_rdma_wqe(const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2678 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr,
2679 struct bnxt_qplib_swqe *wqe)
2680 {
2681 switch (wr->opcode) {
2682 case IB_WR_RDMA_WRITE:
2683 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE;
2684 break;
2685 case IB_WR_RDMA_WRITE_WITH_IMM:
2686 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM;
2687 wqe->rdma.imm_data = be32_to_cpu(wr->ex.imm_data);
2688 break;
2689 case IB_WR_RDMA_READ:
2690 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ;
2691 wqe->rdma.inv_key = wr->ex.invalidate_rkey;
2692 break;
2693 default:
2694 return -EINVAL;
2695 }
2696 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr;
2697 wqe->rdma.r_key = rdma_wr(wr)->rkey;
2698 if (wr->send_flags & IB_SEND_SIGNALED)
2699 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2700 if (wr->send_flags & IB_SEND_FENCE)
2701 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2702 if (wr->send_flags & IB_SEND_SOLICITED)
2703 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2704 if (wr->send_flags & IB_SEND_INLINE)
2705 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2706
2707 return 0;
2708 }
2709
bnxt_re_build_atomic_wqe(const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2710 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr,
2711 struct bnxt_qplib_swqe *wqe)
2712 {
2713 switch (wr->opcode) {
2714 case IB_WR_ATOMIC_CMP_AND_SWP:
2715 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;
2716 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2717 wqe->atomic.swap_data = atomic_wr(wr)->swap;
2718 break;
2719 case IB_WR_ATOMIC_FETCH_AND_ADD:
2720 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD;
2721 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2722 break;
2723 default:
2724 return -EINVAL;
2725 }
2726 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr;
2727 wqe->atomic.r_key = atomic_wr(wr)->rkey;
2728 if (wr->send_flags & IB_SEND_SIGNALED)
2729 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2730 if (wr->send_flags & IB_SEND_FENCE)
2731 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2732 if (wr->send_flags & IB_SEND_SOLICITED)
2733 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2734 return 0;
2735 }
2736
bnxt_re_build_inv_wqe(const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2737 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr,
2738 struct bnxt_qplib_swqe *wqe)
2739 {
2740 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV;
2741 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey;
2742
2743 if (wr->send_flags & IB_SEND_SIGNALED)
2744 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2745 if (wr->send_flags & IB_SEND_SOLICITED)
2746 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2747
2748 return 0;
2749 }
2750
bnxt_re_build_reg_wqe(const struct ib_reg_wr * wr,struct bnxt_qplib_swqe * wqe)2751 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr,
2752 struct bnxt_qplib_swqe *wqe)
2753 {
2754 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr);
2755 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl;
2756 int access = wr->access;
2757
2758 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0];
2759 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0];
2760 wqe->frmr.page_list = mr->pages;
2761 wqe->frmr.page_list_len = mr->npages;
2762 wqe->frmr.levels = qplib_frpl->hwq.level;
2763 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR;
2764
2765 if (wr->wr.send_flags & IB_SEND_SIGNALED)
2766 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2767
2768 if (access & IB_ACCESS_LOCAL_WRITE)
2769 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE;
2770 if (access & IB_ACCESS_REMOTE_READ)
2771 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ;
2772 if (access & IB_ACCESS_REMOTE_WRITE)
2773 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE;
2774 if (access & IB_ACCESS_REMOTE_ATOMIC)
2775 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC;
2776 if (access & IB_ACCESS_MW_BIND)
2777 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND;
2778
2779 wqe->frmr.l_key = wr->key;
2780 wqe->frmr.length = wr->mr->length;
2781 wqe->frmr.pbl_pg_sz_log = ilog2(PAGE_SIZE >> PAGE_SHIFT_4K);
2782 wqe->frmr.pg_sz_log = ilog2(wr->mr->page_size >> PAGE_SHIFT_4K);
2783 wqe->frmr.va = wr->mr->iova;
2784 return 0;
2785 }
2786
bnxt_re_copy_inline_data(struct bnxt_re_dev * rdev,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2787 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev,
2788 const struct ib_send_wr *wr,
2789 struct bnxt_qplib_swqe *wqe)
2790 {
2791 /* Copy the inline data to the data field */
2792 u8 *in_data;
2793 u32 i, sge_len;
2794 void *sge_addr;
2795
2796 in_data = wqe->inline_data;
2797 for (i = 0; i < wr->num_sge; i++) {
2798 sge_addr = (void *)(unsigned long)
2799 wr->sg_list[i].addr;
2800 sge_len = wr->sg_list[i].length;
2801
2802 if ((sge_len + wqe->inline_len) >
2803 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) {
2804 ibdev_err(&rdev->ibdev,
2805 "Inline data size requested > supported value");
2806 return -EINVAL;
2807 }
2808 sge_len = wr->sg_list[i].length;
2809
2810 memcpy(in_data, sge_addr, sge_len);
2811 in_data += wr->sg_list[i].length;
2812 wqe->inline_len += wr->sg_list[i].length;
2813 }
2814 return wqe->inline_len;
2815 }
2816
bnxt_re_copy_wr_payload(struct bnxt_re_dev * rdev,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2817 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev,
2818 const struct ib_send_wr *wr,
2819 struct bnxt_qplib_swqe *wqe)
2820 {
2821 int payload_sz = 0;
2822
2823 if (wr->send_flags & IB_SEND_INLINE)
2824 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe);
2825 else
2826 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list,
2827 wqe->num_sge);
2828
2829 return payload_sz;
2830 }
2831
bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp * qp)2832 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp)
2833 {
2834 if ((qp->ib_qp.qp_type == IB_QPT_UD ||
2835 qp->ib_qp.qp_type == IB_QPT_GSI ||
2836 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) &&
2837 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) {
2838 int qp_attr_mask;
2839 struct ib_qp_attr qp_attr;
2840
2841 qp_attr_mask = IB_QP_STATE;
2842 qp_attr.qp_state = IB_QPS_RTS;
2843 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL);
2844 qp->qplib_qp.wqe_cnt = 0;
2845 }
2846 }
2847
bnxt_re_post_send_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp,const struct ib_send_wr * wr)2848 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,
2849 struct bnxt_re_qp *qp,
2850 const struct ib_send_wr *wr)
2851 {
2852 int rc = 0, payload_sz = 0;
2853 unsigned long flags;
2854
2855 spin_lock_irqsave(&qp->sq_lock, flags);
2856 while (wr) {
2857 struct bnxt_qplib_swqe wqe = {};
2858
2859 /* Common */
2860 wqe.num_sge = wr->num_sge;
2861 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2862 ibdev_err(&rdev->ibdev,
2863 "Limit exceeded for Send SGEs");
2864 rc = -EINVAL;
2865 goto bad;
2866 }
2867
2868 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2869 if (payload_sz < 0) {
2870 rc = -EINVAL;
2871 goto bad;
2872 }
2873 wqe.wr_id = wr->wr_id;
2874
2875 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND;
2876
2877 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2878 if (!rc)
2879 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2880 bad:
2881 if (rc) {
2882 ibdev_err(&rdev->ibdev,
2883 "Post send failed opcode = %#x rc = %d",
2884 wr->opcode, rc);
2885 break;
2886 }
2887 wr = wr->next;
2888 }
2889 bnxt_qplib_post_send_db(&qp->qplib_qp);
2890 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx))
2891 bnxt_ud_qp_hw_stall_workaround(qp);
2892 spin_unlock_irqrestore(&qp->sq_lock, flags);
2893 return rc;
2894 }
2895
bnxt_re_legacy_set_uc_fence(struct bnxt_qplib_swqe * wqe)2896 static void bnxt_re_legacy_set_uc_fence(struct bnxt_qplib_swqe *wqe)
2897 {
2898 /* Need unconditional fence for non-wire memory opcode
2899 * to work as expected.
2900 */
2901 if (wqe->type == BNXT_QPLIB_SWQE_TYPE_LOCAL_INV ||
2902 wqe->type == BNXT_QPLIB_SWQE_TYPE_FAST_REG_MR ||
2903 wqe->type == BNXT_QPLIB_SWQE_TYPE_REG_MR ||
2904 wqe->type == BNXT_QPLIB_SWQE_TYPE_BIND_MW)
2905 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2906 }
2907
bnxt_re_post_send(struct ib_qp * ib_qp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)2908 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr,
2909 const struct ib_send_wr **bad_wr)
2910 {
2911 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2912 struct bnxt_qplib_swqe wqe;
2913 int rc = 0, payload_sz = 0;
2914 unsigned long flags;
2915
2916 spin_lock_irqsave(&qp->sq_lock, flags);
2917 while (wr) {
2918 /* House keeping */
2919 memset(&wqe, 0, sizeof(wqe));
2920
2921 /* Common */
2922 wqe.num_sge = wr->num_sge;
2923 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2924 ibdev_err(&qp->rdev->ibdev,
2925 "Limit exceeded for Send SGEs");
2926 rc = -EINVAL;
2927 goto bad;
2928 }
2929
2930 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2931 if (payload_sz < 0) {
2932 rc = -EINVAL;
2933 goto bad;
2934 }
2935 wqe.wr_id = wr->wr_id;
2936
2937 switch (wr->opcode) {
2938 case IB_WR_SEND:
2939 case IB_WR_SEND_WITH_IMM:
2940 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) {
2941 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe,
2942 payload_sz);
2943 if (rc)
2944 goto bad;
2945 wqe.rawqp1.lflags |=
2946 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC;
2947 }
2948 if (wr->send_flags & IB_SEND_IP_CSUM)
2949 wqe.rawqp1.lflags |=
2950 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM;
2951 fallthrough;
2952 case IB_WR_SEND_WITH_INV:
2953 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2954 break;
2955 case IB_WR_RDMA_WRITE:
2956 case IB_WR_RDMA_WRITE_WITH_IMM:
2957 case IB_WR_RDMA_READ:
2958 rc = bnxt_re_build_rdma_wqe(wr, &wqe);
2959 break;
2960 case IB_WR_ATOMIC_CMP_AND_SWP:
2961 case IB_WR_ATOMIC_FETCH_AND_ADD:
2962 rc = bnxt_re_build_atomic_wqe(wr, &wqe);
2963 break;
2964 case IB_WR_RDMA_READ_WITH_INV:
2965 ibdev_err(&qp->rdev->ibdev,
2966 "RDMA Read with Invalidate is not supported");
2967 rc = -EINVAL;
2968 goto bad;
2969 case IB_WR_LOCAL_INV:
2970 rc = bnxt_re_build_inv_wqe(wr, &wqe);
2971 break;
2972 case IB_WR_REG_MR:
2973 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
2974 break;
2975 default:
2976 /* Unsupported WRs */
2977 ibdev_err(&qp->rdev->ibdev,
2978 "WR (%#x) is not supported", wr->opcode);
2979 rc = -EINVAL;
2980 goto bad;
2981 }
2982 if (!rc) {
2983 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx))
2984 bnxt_re_legacy_set_uc_fence(&wqe);
2985 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2986 }
2987 bad:
2988 if (rc) {
2989 ibdev_err(&qp->rdev->ibdev,
2990 "post_send failed op:%#x qps = %#x rc = %d\n",
2991 wr->opcode, qp->qplib_qp.state, rc);
2992 *bad_wr = wr;
2993 break;
2994 }
2995 wr = wr->next;
2996 }
2997 bnxt_qplib_post_send_db(&qp->qplib_qp);
2998 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx))
2999 bnxt_ud_qp_hw_stall_workaround(qp);
3000 spin_unlock_irqrestore(&qp->sq_lock, flags);
3001
3002 return rc;
3003 }
3004
bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp,const struct ib_recv_wr * wr)3005 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
3006 struct bnxt_re_qp *qp,
3007 const struct ib_recv_wr *wr)
3008 {
3009 struct bnxt_qplib_swqe wqe;
3010 int rc = 0;
3011
3012 while (wr) {
3013 /* House keeping */
3014 memset(&wqe, 0, sizeof(wqe));
3015
3016 /* Common */
3017 wqe.num_sge = wr->num_sge;
3018 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
3019 ibdev_err(&rdev->ibdev,
3020 "Limit exceeded for Receive SGEs");
3021 rc = -EINVAL;
3022 break;
3023 }
3024 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
3025 wqe.wr_id = wr->wr_id;
3026 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
3027
3028 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
3029 if (rc)
3030 break;
3031
3032 wr = wr->next;
3033 }
3034 if (!rc)
3035 bnxt_qplib_post_recv_db(&qp->qplib_qp);
3036 return rc;
3037 }
3038
bnxt_re_post_recv(struct ib_qp * ib_qp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)3039 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr,
3040 const struct ib_recv_wr **bad_wr)
3041 {
3042 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
3043 struct bnxt_qplib_swqe wqe;
3044 int rc = 0, payload_sz = 0;
3045 unsigned long flags;
3046 u32 count = 0;
3047
3048 spin_lock_irqsave(&qp->rq_lock, flags);
3049 while (wr) {
3050 /* House keeping */
3051 memset(&wqe, 0, sizeof(wqe));
3052
3053 /* Common */
3054 wqe.num_sge = wr->num_sge;
3055 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
3056 ibdev_err(&qp->rdev->ibdev,
3057 "Limit exceeded for Receive SGEs");
3058 rc = -EINVAL;
3059 *bad_wr = wr;
3060 break;
3061 }
3062
3063 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
3064 wr->num_sge);
3065 wqe.wr_id = wr->wr_id;
3066 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
3067
3068 if (ib_qp->qp_type == IB_QPT_GSI &&
3069 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI)
3070 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe,
3071 payload_sz);
3072 if (!rc)
3073 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
3074 if (rc) {
3075 *bad_wr = wr;
3076 break;
3077 }
3078
3079 /* Ring DB if the RQEs posted reaches a threshold value */
3080 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) {
3081 bnxt_qplib_post_recv_db(&qp->qplib_qp);
3082 count = 0;
3083 }
3084
3085 wr = wr->next;
3086 }
3087
3088 if (count)
3089 bnxt_qplib_post_recv_db(&qp->qplib_qp);
3090
3091 spin_unlock_irqrestore(&qp->rq_lock, flags);
3092
3093 return rc;
3094 }
3095
bnxt_re_get_nq(struct bnxt_re_dev * rdev)3096 static struct bnxt_qplib_nq *bnxt_re_get_nq(struct bnxt_re_dev *rdev)
3097 {
3098 int min, indx;
3099
3100 mutex_lock(&rdev->nqr->load_lock);
3101 for (indx = 0, min = 0; indx < (rdev->nqr->num_msix - 1); indx++) {
3102 if (rdev->nqr->nq[min].load > rdev->nqr->nq[indx].load)
3103 min = indx;
3104 }
3105 rdev->nqr->nq[min].load++;
3106 mutex_unlock(&rdev->nqr->load_lock);
3107
3108 return &rdev->nqr->nq[min];
3109 }
3110
bnxt_re_put_nq(struct bnxt_re_dev * rdev,struct bnxt_qplib_nq * nq)3111 static void bnxt_re_put_nq(struct bnxt_re_dev *rdev, struct bnxt_qplib_nq *nq)
3112 {
3113 mutex_lock(&rdev->nqr->load_lock);
3114 nq->load--;
3115 mutex_unlock(&rdev->nqr->load_lock);
3116 }
3117
3118 /* Completion Queues */
bnxt_re_destroy_cq(struct ib_cq * ib_cq,struct ib_udata * udata)3119 int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
3120 {
3121 struct bnxt_qplib_chip_ctx *cctx;
3122 struct bnxt_qplib_nq *nq;
3123 struct bnxt_re_dev *rdev;
3124 struct bnxt_re_cq *cq;
3125
3126 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3127 rdev = cq->rdev;
3128 nq = cq->qplib_cq.nq;
3129 cctx = rdev->chip_ctx;
3130
3131 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) {
3132 free_page((unsigned long)cq->uctx_cq_page);
3133 hash_del(&cq->hash_entry);
3134 }
3135 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
3136
3137 bnxt_re_put_nq(rdev, nq);
3138 ib_umem_release(cq->umem);
3139
3140 atomic_dec(&rdev->stats.res.cq_count);
3141 kfree(cq->cql);
3142 return 0;
3143 }
3144
bnxt_re_create_cq(struct ib_cq * ibcq,const struct ib_cq_init_attr * attr,struct uverbs_attr_bundle * attrs)3145 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
3146 struct uverbs_attr_bundle *attrs)
3147 {
3148 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);
3149 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev);
3150 struct ib_udata *udata = &attrs->driver_udata;
3151 struct bnxt_re_ucontext *uctx =
3152 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
3153 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr;
3154 struct bnxt_qplib_chip_ctx *cctx;
3155 int cqe = attr->cqe;
3156 int rc, entries;
3157 u32 active_cqs;
3158
3159 if (attr->flags)
3160 return -EOPNOTSUPP;
3161
3162 /* Validate CQ fields */
3163 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
3164 ibdev_err(&rdev->ibdev, "Failed to create CQ -max exceeded");
3165 return -EINVAL;
3166 }
3167
3168 cq->rdev = rdev;
3169 cctx = rdev->chip_ctx;
3170 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq);
3171
3172 entries = bnxt_re_init_depth(cqe + 1, uctx);
3173 if (entries > dev_attr->max_cq_wqes + 1)
3174 entries = dev_attr->max_cq_wqes + 1;
3175
3176 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE;
3177 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT;
3178 if (udata) {
3179 struct bnxt_re_cq_req req;
3180 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
3181 rc = -EFAULT;
3182 goto fail;
3183 }
3184
3185 cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va,
3186 entries * sizeof(struct cq_base),
3187 IB_ACCESS_LOCAL_WRITE);
3188 if (IS_ERR(cq->umem)) {
3189 rc = PTR_ERR(cq->umem);
3190 goto fail;
3191 }
3192 cq->qplib_cq.sg_info.umem = cq->umem;
3193 cq->qplib_cq.dpi = &uctx->dpi;
3194 } else {
3195 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL);
3196 cq->cql = kzalloc_objs(struct bnxt_qplib_cqe, cq->max_cql);
3197 if (!cq->cql) {
3198 rc = -ENOMEM;
3199 goto fail;
3200 }
3201
3202 cq->qplib_cq.dpi = &rdev->dpi_privileged;
3203 }
3204 cq->qplib_cq.max_wqe = entries;
3205 cq->qplib_cq.coalescing = &rdev->cq_coalescing;
3206 cq->qplib_cq.nq = bnxt_re_get_nq(rdev);
3207 cq->qplib_cq.cnq_hw_ring_id = cq->qplib_cq.nq->ring_id;
3208
3209 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq);
3210 if (rc) {
3211 ibdev_err(&rdev->ibdev, "Failed to create HW CQ");
3212 goto fail;
3213 }
3214
3215 cq->ib_cq.cqe = entries;
3216 cq->cq_period = cq->qplib_cq.period;
3217
3218 active_cqs = atomic_inc_return(&rdev->stats.res.cq_count);
3219 if (active_cqs > rdev->stats.res.cq_watermark)
3220 rdev->stats.res.cq_watermark = active_cqs;
3221 spin_lock_init(&cq->cq_lock);
3222
3223 if (udata) {
3224 struct bnxt_re_cq_resp resp = {};
3225
3226 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) {
3227 hash_add(rdev->cq_hash, &cq->hash_entry, cq->qplib_cq.id);
3228 /* Allocate a page */
3229 cq->uctx_cq_page = (void *)get_zeroed_page(GFP_KERNEL);
3230 if (!cq->uctx_cq_page) {
3231 rc = -ENOMEM;
3232 goto c2fail;
3233 }
3234 resp.comp_mask |= BNXT_RE_CQ_TOGGLE_PAGE_SUPPORT;
3235 }
3236 resp.cqid = cq->qplib_cq.id;
3237 resp.tail = cq->qplib_cq.hwq.cons;
3238 resp.phase = cq->qplib_cq.period;
3239 resp.rsvd = 0;
3240 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen));
3241 if (rc) {
3242 ibdev_err(&rdev->ibdev, "Failed to copy CQ udata");
3243 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
3244 goto free_mem;
3245 }
3246 }
3247
3248 return 0;
3249
3250 free_mem:
3251 free_page((unsigned long)cq->uctx_cq_page);
3252 c2fail:
3253 ib_umem_release(cq->umem);
3254 fail:
3255 kfree(cq->cql);
3256 return rc;
3257 }
3258
bnxt_re_resize_cq_complete(struct bnxt_re_cq * cq)3259 static void bnxt_re_resize_cq_complete(struct bnxt_re_cq *cq)
3260 {
3261 struct bnxt_re_dev *rdev = cq->rdev;
3262
3263 bnxt_qplib_resize_cq_complete(&rdev->qplib_res, &cq->qplib_cq);
3264
3265 cq->qplib_cq.max_wqe = cq->resize_cqe;
3266 if (cq->resize_umem) {
3267 ib_umem_release(cq->umem);
3268 cq->umem = cq->resize_umem;
3269 cq->resize_umem = NULL;
3270 cq->resize_cqe = 0;
3271 }
3272 }
3273
bnxt_re_resize_cq(struct ib_cq * ibcq,int cqe,struct ib_udata * udata)3274 int bnxt_re_resize_cq(struct ib_cq *ibcq, int cqe, struct ib_udata *udata)
3275 {
3276 struct bnxt_qplib_sg_info sg_info = {};
3277 struct bnxt_qplib_dpi *orig_dpi = NULL;
3278 struct bnxt_qplib_dev_attr *dev_attr;
3279 struct bnxt_re_ucontext *uctx = NULL;
3280 struct bnxt_re_resize_cq_req req;
3281 struct bnxt_re_dev *rdev;
3282 struct bnxt_re_cq *cq;
3283 int rc, entries;
3284
3285 cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);
3286 rdev = cq->rdev;
3287 dev_attr = rdev->dev_attr;
3288 if (!ibcq->uobject) {
3289 ibdev_err(&rdev->ibdev, "Kernel CQ Resize not supported");
3290 return -EOPNOTSUPP;
3291 }
3292
3293 if (cq->resize_umem) {
3294 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - Busy",
3295 cq->qplib_cq.id);
3296 return -EBUSY;
3297 }
3298
3299 /* Check the requested cq depth out of supported depth */
3300 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
3301 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - out of range cqe %d",
3302 cq->qplib_cq.id, cqe);
3303 return -EINVAL;
3304 }
3305
3306 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
3307 entries = bnxt_re_init_depth(cqe + 1, uctx);
3308 if (entries > dev_attr->max_cq_wqes + 1)
3309 entries = dev_attr->max_cq_wqes + 1;
3310
3311 /* uverbs consumer */
3312 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
3313 rc = -EFAULT;
3314 goto fail;
3315 }
3316
3317 cq->resize_umem = ib_umem_get(&rdev->ibdev, req.cq_va,
3318 entries * sizeof(struct cq_base),
3319 IB_ACCESS_LOCAL_WRITE);
3320 if (IS_ERR(cq->resize_umem)) {
3321 rc = PTR_ERR(cq->resize_umem);
3322 ibdev_err(&rdev->ibdev, "%s: ib_umem_get failed! rc = %pe\n",
3323 __func__, cq->resize_umem);
3324 cq->resize_umem = NULL;
3325 goto fail;
3326 }
3327 cq->resize_cqe = entries;
3328 memcpy(&sg_info, &cq->qplib_cq.sg_info, sizeof(sg_info));
3329 orig_dpi = cq->qplib_cq.dpi;
3330
3331 cq->qplib_cq.sg_info.umem = cq->resize_umem;
3332 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE;
3333 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT;
3334 cq->qplib_cq.dpi = &uctx->dpi;
3335
3336 rc = bnxt_qplib_resize_cq(&rdev->qplib_res, &cq->qplib_cq, entries);
3337 if (rc) {
3338 ibdev_err(&rdev->ibdev, "Resize HW CQ %#x failed!",
3339 cq->qplib_cq.id);
3340 goto fail;
3341 }
3342
3343 cq->ib_cq.cqe = cq->resize_cqe;
3344 atomic_inc(&rdev->stats.res.resize_count);
3345
3346 return 0;
3347
3348 fail:
3349 if (cq->resize_umem) {
3350 ib_umem_release(cq->resize_umem);
3351 cq->resize_umem = NULL;
3352 cq->resize_cqe = 0;
3353 memcpy(&cq->qplib_cq.sg_info, &sg_info, sizeof(sg_info));
3354 cq->qplib_cq.dpi = orig_dpi;
3355 }
3356 return rc;
3357 }
3358
__req_to_ib_wc_status(u8 qstatus)3359 static u8 __req_to_ib_wc_status(u8 qstatus)
3360 {
3361 switch (qstatus) {
3362 case CQ_REQ_STATUS_OK:
3363 return IB_WC_SUCCESS;
3364 case CQ_REQ_STATUS_BAD_RESPONSE_ERR:
3365 return IB_WC_BAD_RESP_ERR;
3366 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR:
3367 return IB_WC_LOC_LEN_ERR;
3368 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR:
3369 return IB_WC_LOC_QP_OP_ERR;
3370 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR:
3371 return IB_WC_LOC_PROT_ERR;
3372 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR:
3373 return IB_WC_GENERAL_ERR;
3374 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR:
3375 return IB_WC_REM_INV_REQ_ERR;
3376 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR:
3377 return IB_WC_REM_ACCESS_ERR;
3378 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR:
3379 return IB_WC_REM_OP_ERR;
3380 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR:
3381 return IB_WC_RNR_RETRY_EXC_ERR;
3382 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR:
3383 return IB_WC_RETRY_EXC_ERR;
3384 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR:
3385 return IB_WC_WR_FLUSH_ERR;
3386 default:
3387 return IB_WC_GENERAL_ERR;
3388 }
3389 return 0;
3390 }
3391
__rawqp1_to_ib_wc_status(u8 qstatus)3392 static u8 __rawqp1_to_ib_wc_status(u8 qstatus)
3393 {
3394 switch (qstatus) {
3395 case CQ_RES_RAWETH_QP1_STATUS_OK:
3396 return IB_WC_SUCCESS;
3397 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR:
3398 return IB_WC_LOC_ACCESS_ERR;
3399 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR:
3400 return IB_WC_LOC_LEN_ERR;
3401 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR:
3402 return IB_WC_LOC_PROT_ERR;
3403 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR:
3404 return IB_WC_LOC_QP_OP_ERR;
3405 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR:
3406 return IB_WC_GENERAL_ERR;
3407 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR:
3408 return IB_WC_WR_FLUSH_ERR;
3409 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR:
3410 return IB_WC_WR_FLUSH_ERR;
3411 default:
3412 return IB_WC_GENERAL_ERR;
3413 }
3414 }
3415
__rc_to_ib_wc_status(u8 qstatus)3416 static u8 __rc_to_ib_wc_status(u8 qstatus)
3417 {
3418 switch (qstatus) {
3419 case CQ_RES_RC_STATUS_OK:
3420 return IB_WC_SUCCESS;
3421 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR:
3422 return IB_WC_LOC_ACCESS_ERR;
3423 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR:
3424 return IB_WC_LOC_LEN_ERR;
3425 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR:
3426 return IB_WC_LOC_PROT_ERR;
3427 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR:
3428 return IB_WC_LOC_QP_OP_ERR;
3429 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR:
3430 return IB_WC_GENERAL_ERR;
3431 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR:
3432 return IB_WC_REM_INV_REQ_ERR;
3433 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR:
3434 return IB_WC_WR_FLUSH_ERR;
3435 case CQ_RES_RC_STATUS_HW_FLUSH_ERR:
3436 return IB_WC_WR_FLUSH_ERR;
3437 default:
3438 return IB_WC_GENERAL_ERR;
3439 }
3440 }
3441
bnxt_re_process_req_wc(struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3442 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe)
3443 {
3444 switch (cqe->type) {
3445 case BNXT_QPLIB_SWQE_TYPE_SEND:
3446 wc->opcode = IB_WC_SEND;
3447 break;
3448 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
3449 wc->opcode = IB_WC_SEND;
3450 wc->wc_flags |= IB_WC_WITH_IMM;
3451 break;
3452 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
3453 wc->opcode = IB_WC_SEND;
3454 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3455 break;
3456 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE:
3457 wc->opcode = IB_WC_RDMA_WRITE;
3458 break;
3459 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM:
3460 wc->opcode = IB_WC_RDMA_WRITE;
3461 wc->wc_flags |= IB_WC_WITH_IMM;
3462 break;
3463 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ:
3464 wc->opcode = IB_WC_RDMA_READ;
3465 break;
3466 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP:
3467 wc->opcode = IB_WC_COMP_SWAP;
3468 break;
3469 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD:
3470 wc->opcode = IB_WC_FETCH_ADD;
3471 break;
3472 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV:
3473 wc->opcode = IB_WC_LOCAL_INV;
3474 break;
3475 case BNXT_QPLIB_SWQE_TYPE_REG_MR:
3476 wc->opcode = IB_WC_REG_MR;
3477 break;
3478 default:
3479 wc->opcode = IB_WC_SEND;
3480 break;
3481 }
3482
3483 wc->status = __req_to_ib_wc_status(cqe->status);
3484 }
3485
bnxt_re_check_packet_type(u16 raweth_qp1_flags,u16 raweth_qp1_flags2)3486 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
3487 u16 raweth_qp1_flags2)
3488 {
3489 bool is_ipv6 = false, is_ipv4 = false;
3490
3491 /* raweth_qp1_flags Bit 9-6 indicates itype */
3492 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
3493 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
3494 return -1;
3495
3496 if (raweth_qp1_flags2 &
3497 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC &&
3498 raweth_qp1_flags2 &
3499 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) {
3500 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */
3501 (raweth_qp1_flags2 &
3502 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ?
3503 (is_ipv6 = true) : (is_ipv4 = true);
3504 return ((is_ipv6) ?
3505 BNXT_RE_ROCEV2_IPV6_PACKET :
3506 BNXT_RE_ROCEV2_IPV4_PACKET);
3507 } else {
3508 return BNXT_RE_ROCE_V1_PACKET;
3509 }
3510 }
3511
bnxt_re_to_ib_nw_type(int nw_type)3512 static int bnxt_re_to_ib_nw_type(int nw_type)
3513 {
3514 u8 nw_hdr_type = 0xFF;
3515
3516 switch (nw_type) {
3517 case BNXT_RE_ROCE_V1_PACKET:
3518 nw_hdr_type = RDMA_NETWORK_ROCE_V1;
3519 break;
3520 case BNXT_RE_ROCEV2_IPV4_PACKET:
3521 nw_hdr_type = RDMA_NETWORK_IPV4;
3522 break;
3523 case BNXT_RE_ROCEV2_IPV6_PACKET:
3524 nw_hdr_type = RDMA_NETWORK_IPV6;
3525 break;
3526 }
3527 return nw_hdr_type;
3528 }
3529
bnxt_re_is_loopback_packet(struct bnxt_re_dev * rdev,void * rq_hdr_buf)3530 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev,
3531 void *rq_hdr_buf)
3532 {
3533 u8 *tmp_buf = NULL;
3534 struct ethhdr *eth_hdr;
3535 u16 eth_type;
3536 bool rc = false;
3537
3538 tmp_buf = (u8 *)rq_hdr_buf;
3539 /*
3540 * If dest mac is not same as I/F mac, this could be a
3541 * loopback address or multicast address, check whether
3542 * it is a loopback packet
3543 */
3544 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) {
3545 tmp_buf += 4;
3546 /* Check the ether type */
3547 eth_hdr = (struct ethhdr *)tmp_buf;
3548 eth_type = ntohs(eth_hdr->h_proto);
3549 switch (eth_type) {
3550 case ETH_P_IBOE:
3551 rc = true;
3552 break;
3553 case ETH_P_IP:
3554 case ETH_P_IPV6: {
3555 u32 len;
3556 struct udphdr *udp_hdr;
3557
3558 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) :
3559 sizeof(struct ipv6hdr));
3560 tmp_buf += sizeof(struct ethhdr) + len;
3561 udp_hdr = (struct udphdr *)tmp_buf;
3562 if (ntohs(udp_hdr->dest) ==
3563 ROCE_V2_UDP_DPORT)
3564 rc = true;
3565 break;
3566 }
3567 default:
3568 break;
3569 }
3570 }
3571
3572 return rc;
3573 }
3574
bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp * gsi_qp,struct bnxt_qplib_cqe * cqe)3575 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp,
3576 struct bnxt_qplib_cqe *cqe)
3577 {
3578 struct bnxt_re_dev *rdev = gsi_qp->rdev;
3579 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3580 struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp;
3581 dma_addr_t shrq_hdr_buf_map;
3582 struct ib_sge s_sge[2] = {};
3583 struct ib_sge r_sge[2] = {};
3584 struct bnxt_re_ah *gsi_sah;
3585 struct ib_recv_wr rwr = {};
3586 dma_addr_t rq_hdr_buf_map;
3587 struct ib_ud_wr udwr = {};
3588 struct ib_send_wr *swr;
3589 u32 skip_bytes = 0;
3590 int pkt_type = 0;
3591 void *rq_hdr_buf;
3592 u32 offset = 0;
3593 u32 tbl_idx;
3594 int rc;
3595
3596 swr = &udwr.wr;
3597 tbl_idx = cqe->wr_id;
3598
3599 rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf +
3600 (tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size);
3601 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3602 tbl_idx);
3603
3604 /* Shadow QP header buffer */
3605 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3606 tbl_idx);
3607 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3608
3609 /* Store this cqe */
3610 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe));
3611 sqp_entry->qp1_qp = gsi_qp;
3612
3613 /* Find packet type from the cqe */
3614
3615 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags,
3616 cqe->raweth_qp1_flags2);
3617 if (pkt_type < 0) {
3618 ibdev_err(&rdev->ibdev, "Invalid packet\n");
3619 return -EINVAL;
3620 }
3621
3622 /* Adjust the offset for the user buffer and post in the rq */
3623
3624 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET)
3625 offset = 20;
3626
3627 /*
3628 * QP1 loopback packet has 4 bytes of internal header before
3629 * ether header. Skip these four bytes.
3630 */
3631 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf))
3632 skip_bytes = 4;
3633
3634 /* First send SGE . Skip the ether header*/
3635 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE
3636 + skip_bytes;
3637 s_sge[0].lkey = 0xFFFFFFFF;
3638 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 :
3639 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
3640
3641 /* Second Send SGE */
3642 s_sge[1].addr = s_sge[0].addr + s_sge[0].length +
3643 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE;
3644 if (pkt_type != BNXT_RE_ROCE_V1_PACKET)
3645 s_sge[1].addr += 8;
3646 s_sge[1].lkey = 0xFFFFFFFF;
3647 s_sge[1].length = 256;
3648
3649 /* First recv SGE */
3650
3651 r_sge[0].addr = shrq_hdr_buf_map;
3652 r_sge[0].lkey = 0xFFFFFFFF;
3653 r_sge[0].length = 40;
3654
3655 r_sge[1].addr = sqp_entry->sge.addr + offset;
3656 r_sge[1].lkey = sqp_entry->sge.lkey;
3657 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset;
3658
3659 /* Create receive work request */
3660 rwr.num_sge = 2;
3661 rwr.sg_list = r_sge;
3662 rwr.wr_id = tbl_idx;
3663 rwr.next = NULL;
3664
3665 rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr);
3666 if (rc) {
3667 ibdev_err(&rdev->ibdev,
3668 "Failed to post Rx buffers to shadow QP");
3669 return -ENOMEM;
3670 }
3671
3672 swr->num_sge = 2;
3673 swr->sg_list = s_sge;
3674 swr->wr_id = tbl_idx;
3675 swr->opcode = IB_WR_SEND;
3676 swr->next = NULL;
3677 gsi_sah = rdev->gsi_ctx.gsi_sah;
3678 udwr.ah = &gsi_sah->ib_ah;
3679 udwr.remote_qpn = gsi_sqp->qplib_qp.id;
3680 udwr.remote_qkey = gsi_sqp->qplib_qp.qkey;
3681
3682 /* post data received in the send queue */
3683 return bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr);
3684 }
3685
bnxt_re_process_res_rawqp1_wc(struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3686 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc,
3687 struct bnxt_qplib_cqe *cqe)
3688 {
3689 wc->opcode = IB_WC_RECV;
3690 wc->status = __rawqp1_to_ib_wc_status(cqe->status);
3691 wc->wc_flags |= IB_WC_GRH;
3692 }
3693
bnxt_re_check_if_vlan_valid(struct bnxt_re_dev * rdev,u16 vlan_id)3694 static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev,
3695 u16 vlan_id)
3696 {
3697 /*
3698 * Check if the vlan is configured in the host. If not configured, it
3699 * can be a transparent VLAN. So dont report the vlan id.
3700 */
3701 if (!__vlan_find_dev_deep_rcu(rdev->netdev,
3702 htons(ETH_P_8021Q), vlan_id))
3703 return false;
3704 return true;
3705 }
3706
bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe * orig_cqe,u16 * vid,u8 * sl)3707 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe,
3708 u16 *vid, u8 *sl)
3709 {
3710 bool ret = false;
3711 u32 metadata;
3712 u16 tpid;
3713
3714 metadata = orig_cqe->raweth_qp1_metadata;
3715 if (orig_cqe->raweth_qp1_flags2 &
3716 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) {
3717 tpid = ((metadata &
3718 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >>
3719 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT);
3720 if (tpid == ETH_P_8021Q) {
3721 *vid = metadata &
3722 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK;
3723 *sl = (metadata &
3724 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >>
3725 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT;
3726 ret = true;
3727 }
3728 }
3729
3730 return ret;
3731 }
3732
bnxt_re_process_res_rc_wc(struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3733 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc,
3734 struct bnxt_qplib_cqe *cqe)
3735 {
3736 wc->opcode = IB_WC_RECV;
3737 wc->status = __rc_to_ib_wc_status(cqe->status);
3738
3739 if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
3740 wc->wc_flags |= IB_WC_WITH_IMM;
3741 if (cqe->flags & CQ_RES_RC_FLAGS_INV)
3742 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3743 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
3744 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
3745 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
3746 }
3747
bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp * gsi_sqp,struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3748 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp,
3749 struct ib_wc *wc,
3750 struct bnxt_qplib_cqe *cqe)
3751 {
3752 struct bnxt_re_dev *rdev = gsi_sqp->rdev;
3753 struct bnxt_re_qp *gsi_qp = NULL;
3754 struct bnxt_qplib_cqe *orig_cqe = NULL;
3755 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3756 int nw_type;
3757 u32 tbl_idx;
3758 u16 vlan_id;
3759 u8 sl;
3760
3761 tbl_idx = cqe->wr_id;
3762
3763 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3764 gsi_qp = sqp_entry->qp1_qp;
3765 orig_cqe = &sqp_entry->cqe;
3766
3767 wc->wr_id = sqp_entry->wrid;
3768 wc->byte_len = orig_cqe->length;
3769 wc->qp = &gsi_qp->ib_qp;
3770
3771 wc->ex.imm_data = cpu_to_be32(orig_cqe->immdata);
3772 wc->src_qp = orig_cqe->src_qp;
3773 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
3774 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) {
3775 if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) {
3776 wc->vlan_id = vlan_id;
3777 wc->sl = sl;
3778 wc->wc_flags |= IB_WC_WITH_VLAN;
3779 }
3780 }
3781 wc->port_num = 1;
3782 wc->vendor_err = orig_cqe->status;
3783
3784 wc->opcode = IB_WC_RECV;
3785 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status);
3786 wc->wc_flags |= IB_WC_GRH;
3787
3788 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags,
3789 orig_cqe->raweth_qp1_flags2);
3790 if (nw_type >= 0) {
3791 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3792 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3793 }
3794 }
3795
bnxt_re_process_res_ud_wc(struct bnxt_re_qp * qp,struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3796 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp,
3797 struct ib_wc *wc,
3798 struct bnxt_qplib_cqe *cqe)
3799 {
3800 struct bnxt_re_dev *rdev;
3801 u16 vlan_id = 0;
3802 u8 nw_type;
3803
3804 rdev = qp->rdev;
3805 wc->opcode = IB_WC_RECV;
3806 wc->status = __rc_to_ib_wc_status(cqe->status);
3807
3808 if (cqe->flags & CQ_RES_UD_FLAGS_IMM)
3809 wc->wc_flags |= IB_WC_WITH_IMM;
3810 /* report only on GSI QP for Thor */
3811 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) {
3812 wc->wc_flags |= IB_WC_GRH;
3813 memcpy(wc->smac, cqe->smac, ETH_ALEN);
3814 wc->wc_flags |= IB_WC_WITH_SMAC;
3815 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) {
3816 vlan_id = (cqe->cfa_meta & 0xFFF);
3817 }
3818 /* Mark only if vlan_id is non zero */
3819 if (vlan_id && bnxt_re_check_if_vlan_valid(rdev, vlan_id)) {
3820 wc->vlan_id = vlan_id;
3821 wc->wc_flags |= IB_WC_WITH_VLAN;
3822 }
3823 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >>
3824 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT;
3825 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3826 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3827 }
3828
3829 }
3830
send_phantom_wqe(struct bnxt_re_qp * qp)3831 static int send_phantom_wqe(struct bnxt_re_qp *qp)
3832 {
3833 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp;
3834 unsigned long flags;
3835 int rc;
3836
3837 spin_lock_irqsave(&qp->sq_lock, flags);
3838
3839 rc = bnxt_re_bind_fence_mw(lib_qp);
3840 if (!rc) {
3841 lib_qp->sq.phantom_wqe_cnt++;
3842 ibdev_dbg(&qp->rdev->ibdev,
3843 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n",
3844 lib_qp->id, lib_qp->sq.hwq.prod,
3845 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq),
3846 lib_qp->sq.phantom_wqe_cnt);
3847 }
3848
3849 spin_unlock_irqrestore(&qp->sq_lock, flags);
3850 return rc;
3851 }
3852
bnxt_re_poll_cq(struct ib_cq * ib_cq,int num_entries,struct ib_wc * wc)3853 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc)
3854 {
3855 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3856 struct bnxt_re_qp *qp, *sh_qp;
3857 struct bnxt_qplib_cqe *cqe;
3858 int i, ncqe, budget;
3859 struct bnxt_qplib_q *sq;
3860 struct bnxt_qplib_qp *lib_qp;
3861 u32 tbl_idx;
3862 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3863 unsigned long flags;
3864
3865 /* User CQ; the only processing we do is to
3866 * complete any pending CQ resize operation.
3867 */
3868 if (cq->umem) {
3869 if (cq->resize_umem)
3870 bnxt_re_resize_cq_complete(cq);
3871 return 0;
3872 }
3873
3874 spin_lock_irqsave(&cq->cq_lock, flags);
3875 budget = min_t(u32, num_entries, cq->max_cql);
3876 num_entries = budget;
3877 if (!cq->cql) {
3878 ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use");
3879 goto exit;
3880 }
3881 cqe = &cq->cql[0];
3882 while (budget) {
3883 lib_qp = NULL;
3884 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp);
3885 if (lib_qp) {
3886 sq = &lib_qp->sq;
3887 if (sq->send_phantom) {
3888 qp = container_of(lib_qp,
3889 struct bnxt_re_qp, qplib_qp);
3890 if (send_phantom_wqe(qp) == -ENOMEM)
3891 ibdev_err(&cq->rdev->ibdev,
3892 "Phantom failed! Scheduled to send again\n");
3893 else
3894 sq->send_phantom = false;
3895 }
3896 }
3897 if (ncqe < budget)
3898 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq,
3899 cqe + ncqe,
3900 budget - ncqe);
3901
3902 if (!ncqe)
3903 break;
3904
3905 for (i = 0; i < ncqe; i++, cqe++) {
3906 /* Transcribe each qplib_wqe back to ib_wc */
3907 memset(wc, 0, sizeof(*wc));
3908
3909 wc->wr_id = cqe->wr_id;
3910 wc->byte_len = cqe->length;
3911 qp = container_of
3912 ((struct bnxt_qplib_qp *)
3913 (unsigned long)(cqe->qp_handle),
3914 struct bnxt_re_qp, qplib_qp);
3915 wc->qp = &qp->ib_qp;
3916 if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
3917 wc->ex.imm_data = cpu_to_be32(cqe->immdata);
3918 else
3919 wc->ex.invalidate_rkey = cqe->invrkey;
3920 wc->src_qp = cqe->src_qp;
3921 memcpy(wc->smac, cqe->smac, ETH_ALEN);
3922 wc->port_num = 1;
3923 wc->vendor_err = cqe->status;
3924
3925 switch (cqe->opcode) {
3926 case CQ_BASE_CQE_TYPE_REQ:
3927 sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3928 if (sh_qp &&
3929 qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3930 /* Handle this completion with
3931 * the stored completion
3932 */
3933 memset(wc, 0, sizeof(*wc));
3934 continue;
3935 }
3936 bnxt_re_process_req_wc(wc, cqe);
3937 break;
3938 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
3939 if (!cqe->status) {
3940 int rc = 0;
3941
3942 rc = bnxt_re_process_raw_qp_pkt_rx
3943 (qp, cqe);
3944 if (!rc) {
3945 memset(wc, 0, sizeof(*wc));
3946 continue;
3947 }
3948 cqe->status = -1;
3949 }
3950 /* Errors need not be looped back.
3951 * But change the wr_id to the one
3952 * stored in the table
3953 */
3954 tbl_idx = cqe->wr_id;
3955 sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx];
3956 wc->wr_id = sqp_entry->wrid;
3957 bnxt_re_process_res_rawqp1_wc(wc, cqe);
3958 break;
3959 case CQ_BASE_CQE_TYPE_RES_RC:
3960 bnxt_re_process_res_rc_wc(wc, cqe);
3961 break;
3962 case CQ_BASE_CQE_TYPE_RES_UD:
3963 sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3964 if (sh_qp &&
3965 qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3966 /* Handle this completion with
3967 * the stored completion
3968 */
3969 if (cqe->status) {
3970 continue;
3971 } else {
3972 bnxt_re_process_res_shadow_qp_wc
3973 (qp, wc, cqe);
3974 break;
3975 }
3976 }
3977 bnxt_re_process_res_ud_wc(qp, wc, cqe);
3978 break;
3979 default:
3980 ibdev_err(&cq->rdev->ibdev,
3981 "POLL CQ : type 0x%x not handled",
3982 cqe->opcode);
3983 continue;
3984 }
3985 wc++;
3986 budget--;
3987 }
3988 }
3989 exit:
3990 spin_unlock_irqrestore(&cq->cq_lock, flags);
3991 return num_entries - budget;
3992 }
3993
bnxt_re_req_notify_cq(struct ib_cq * ib_cq,enum ib_cq_notify_flags ib_cqn_flags)3994 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
3995 enum ib_cq_notify_flags ib_cqn_flags)
3996 {
3997 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3998 int type = 0, rc = 0;
3999 unsigned long flags;
4000
4001 spin_lock_irqsave(&cq->cq_lock, flags);
4002 /* Trigger on the very next completion */
4003 if (ib_cqn_flags & IB_CQ_NEXT_COMP)
4004 type = DBC_DBC_TYPE_CQ_ARMALL;
4005 /* Trigger on the next solicited completion */
4006 else if (ib_cqn_flags & IB_CQ_SOLICITED)
4007 type = DBC_DBC_TYPE_CQ_ARMSE;
4008
4009 /* Poll to see if there are missed events */
4010 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
4011 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) {
4012 rc = 1;
4013 goto exit;
4014 }
4015 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type);
4016
4017 exit:
4018 spin_unlock_irqrestore(&cq->cq_lock, flags);
4019 return rc;
4020 }
4021
4022 /* Memory Regions */
bnxt_re_get_dma_mr(struct ib_pd * ib_pd,int mr_access_flags)4023 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags)
4024 {
4025 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4026 struct bnxt_re_dev *rdev = pd->rdev;
4027 struct bnxt_re_mr *mr;
4028 u32 active_mrs;
4029 int rc;
4030
4031 mr = kzalloc_obj(*mr);
4032 if (!mr)
4033 return ERR_PTR(-ENOMEM);
4034
4035 mr->rdev = rdev;
4036 mr->qplib_mr.pd = &pd->qplib_pd;
4037 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags);
4038 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
4039
4040 if (mr_access_flags & IB_ACCESS_RELAXED_ORDERING)
4041 bnxt_re_check_and_set_relaxed_ordering(rdev, &mr->qplib_mr);
4042
4043 /* Allocate and register 0 as the address */
4044 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
4045 if (rc)
4046 goto fail;
4047
4048 mr->qplib_mr.hwq.level = PBL_LVL_MAX;
4049 mr->qplib_mr.total_size = -1; /* Infinte length */
4050 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 0,
4051 PAGE_SIZE, false);
4052 if (rc)
4053 goto fail_mr;
4054
4055 mr->ib_mr.lkey = mr->qplib_mr.lkey;
4056 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ |
4057 IB_ACCESS_REMOTE_ATOMIC))
4058 mr->ib_mr.rkey = mr->ib_mr.lkey;
4059 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count);
4060 if (active_mrs > rdev->stats.res.mr_watermark)
4061 rdev->stats.res.mr_watermark = active_mrs;
4062
4063 return &mr->ib_mr;
4064
4065 fail_mr:
4066 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
4067 fail:
4068 kfree(mr);
4069 return ERR_PTR(rc);
4070 }
4071
bnxt_re_dereg_mr(struct ib_mr * ib_mr,struct ib_udata * udata)4072 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
4073 {
4074 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
4075 struct bnxt_re_dev *rdev = mr->rdev;
4076 int rc;
4077
4078 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
4079 if (rc) {
4080 ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc);
4081 return rc;
4082 }
4083
4084 if (mr->pages) {
4085 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
4086 &mr->qplib_frpl);
4087 kfree(mr->pages);
4088 mr->npages = 0;
4089 mr->pages = NULL;
4090 }
4091 ib_umem_release(mr->ib_umem);
4092
4093 kfree(mr);
4094 atomic_dec(&rdev->stats.res.mr_count);
4095 return rc;
4096 }
4097
bnxt_re_set_page(struct ib_mr * ib_mr,u64 addr)4098 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr)
4099 {
4100 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
4101
4102 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs))
4103 return -ENOMEM;
4104
4105 mr->pages[mr->npages++] = addr;
4106 return 0;
4107 }
4108
bnxt_re_map_mr_sg(struct ib_mr * ib_mr,struct scatterlist * sg,int sg_nents,unsigned int * sg_offset)4109 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents,
4110 unsigned int *sg_offset)
4111 {
4112 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
4113
4114 mr->npages = 0;
4115 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page);
4116 }
4117
bnxt_re_alloc_mr(struct ib_pd * ib_pd,enum ib_mr_type type,u32 max_num_sg)4118 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type,
4119 u32 max_num_sg)
4120 {
4121 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4122 struct bnxt_re_dev *rdev = pd->rdev;
4123 struct bnxt_re_mr *mr = NULL;
4124 u32 active_mrs;
4125 int rc;
4126
4127 if (type != IB_MR_TYPE_MEM_REG) {
4128 ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type);
4129 return ERR_PTR(-EINVAL);
4130 }
4131 if (max_num_sg > MAX_PBL_LVL_1_PGS)
4132 return ERR_PTR(-EINVAL);
4133
4134 mr = kzalloc_obj(*mr);
4135 if (!mr)
4136 return ERR_PTR(-ENOMEM);
4137
4138 mr->rdev = rdev;
4139 mr->qplib_mr.pd = &pd->qplib_pd;
4140 mr->qplib_mr.access_flags = BNXT_QPLIB_FR_PMR;
4141 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
4142
4143 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
4144 if (rc)
4145 goto bail;
4146
4147 mr->ib_mr.lkey = mr->qplib_mr.lkey;
4148 mr->ib_mr.rkey = mr->ib_mr.lkey;
4149
4150 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
4151 if (!mr->pages) {
4152 rc = -ENOMEM;
4153 goto fail;
4154 }
4155 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res,
4156 &mr->qplib_frpl, max_num_sg);
4157 if (rc) {
4158 ibdev_err(&rdev->ibdev,
4159 "Failed to allocate HW FR page list");
4160 goto fail_mr;
4161 }
4162
4163 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count);
4164 if (active_mrs > rdev->stats.res.mr_watermark)
4165 rdev->stats.res.mr_watermark = active_mrs;
4166 return &mr->ib_mr;
4167
4168 fail_mr:
4169 kfree(mr->pages);
4170 fail:
4171 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
4172 bail:
4173 kfree(mr);
4174 return ERR_PTR(rc);
4175 }
4176
bnxt_re_alloc_mw(struct ib_pd * ib_pd,enum ib_mw_type type,struct ib_udata * udata)4177 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type,
4178 struct ib_udata *udata)
4179 {
4180 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4181 struct bnxt_re_dev *rdev = pd->rdev;
4182 struct bnxt_re_mw *mw;
4183 u32 active_mws;
4184 int rc;
4185
4186 mw = kzalloc_obj(*mw);
4187 if (!mw)
4188 return ERR_PTR(-ENOMEM);
4189 mw->rdev = rdev;
4190 mw->qplib_mw.pd = &pd->qplib_pd;
4191
4192 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ?
4193 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 :
4194 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B);
4195 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw);
4196 if (rc) {
4197 ibdev_err(&rdev->ibdev, "Allocate MW failed!");
4198 goto fail;
4199 }
4200 mw->ib_mw.rkey = mw->qplib_mw.rkey;
4201
4202 active_mws = atomic_inc_return(&rdev->stats.res.mw_count);
4203 if (active_mws > rdev->stats.res.mw_watermark)
4204 rdev->stats.res.mw_watermark = active_mws;
4205 return &mw->ib_mw;
4206
4207 fail:
4208 kfree(mw);
4209 return ERR_PTR(rc);
4210 }
4211
bnxt_re_dealloc_mw(struct ib_mw * ib_mw)4212 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw)
4213 {
4214 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw);
4215 struct bnxt_re_dev *rdev = mw->rdev;
4216 int rc;
4217
4218 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw);
4219 if (rc) {
4220 ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc);
4221 return rc;
4222 }
4223
4224 kfree(mw);
4225 atomic_dec(&rdev->stats.res.mw_count);
4226 return rc;
4227 }
4228
__bnxt_re_user_reg_mr(struct ib_pd * ib_pd,u64 length,u64 virt_addr,int mr_access_flags,struct ib_umem * umem)4229 static struct ib_mr *__bnxt_re_user_reg_mr(struct ib_pd *ib_pd, u64 length, u64 virt_addr,
4230 int mr_access_flags, struct ib_umem *umem)
4231 {
4232 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4233 struct bnxt_re_dev *rdev = pd->rdev;
4234 unsigned long page_size;
4235 struct bnxt_re_mr *mr;
4236 int umem_pgs, rc;
4237 u32 active_mrs;
4238
4239 if (length > BNXT_RE_MAX_MR_SIZE) {
4240 ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n",
4241 length, BNXT_RE_MAX_MR_SIZE);
4242 return ERR_PTR(-ENOMEM);
4243 }
4244
4245 page_size = ib_umem_find_best_pgsz(umem, BNXT_RE_PAGE_SIZE_SUPPORTED, virt_addr);
4246 if (!page_size) {
4247 ibdev_err(&rdev->ibdev, "umem page size unsupported!");
4248 return ERR_PTR(-EINVAL);
4249 }
4250
4251 mr = kzalloc_obj(*mr);
4252 if (!mr)
4253 return ERR_PTR(-ENOMEM);
4254
4255 mr->rdev = rdev;
4256 mr->qplib_mr.pd = &pd->qplib_pd;
4257 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags);
4258 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR;
4259
4260 if (!_is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags)) {
4261 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
4262 if (rc) {
4263 ibdev_err(&rdev->ibdev, "Failed to allocate MR rc = %d", rc);
4264 rc = -EIO;
4265 goto free_mr;
4266 }
4267 /* The fixed portion of the rkey is the same as the lkey */
4268 mr->ib_mr.rkey = mr->qplib_mr.rkey;
4269 } else {
4270 mr->qplib_mr.flags = CMDQ_REGISTER_MR_FLAGS_ALLOC_MR;
4271 }
4272 mr->ib_umem = umem;
4273 mr->qplib_mr.va = virt_addr;
4274 mr->qplib_mr.total_size = length;
4275
4276 if (mr_access_flags & IB_ACCESS_RELAXED_ORDERING)
4277 bnxt_re_check_and_set_relaxed_ordering(rdev, &mr->qplib_mr);
4278
4279 umem_pgs = ib_umem_num_dma_blocks(umem, page_size);
4280 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, umem,
4281 umem_pgs, page_size,
4282 _is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags));
4283 if (rc) {
4284 ibdev_err(&rdev->ibdev, "Failed to register user MR - rc = %d\n", rc);
4285 rc = -EIO;
4286 goto free_mrw;
4287 }
4288
4289 mr->ib_mr.lkey = mr->qplib_mr.lkey;
4290 mr->ib_mr.rkey = mr->qplib_mr.lkey;
4291 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count);
4292 if (active_mrs > rdev->stats.res.mr_watermark)
4293 rdev->stats.res.mr_watermark = active_mrs;
4294
4295 return &mr->ib_mr;
4296
4297 free_mrw:
4298 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
4299 free_mr:
4300 kfree(mr);
4301 return ERR_PTR(rc);
4302 }
4303
bnxt_re_reg_user_mr(struct ib_pd * ib_pd,u64 start,u64 length,u64 virt_addr,int mr_access_flags,struct ib_dmah * dmah,struct ib_udata * udata)4304 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length,
4305 u64 virt_addr, int mr_access_flags,
4306 struct ib_dmah *dmah,
4307 struct ib_udata *udata)
4308 {
4309 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4310 struct bnxt_re_dev *rdev = pd->rdev;
4311 struct ib_umem *umem;
4312 struct ib_mr *ib_mr;
4313
4314 if (dmah)
4315 return ERR_PTR(-EOPNOTSUPP);
4316
4317 umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags);
4318 if (IS_ERR(umem))
4319 return ERR_CAST(umem);
4320
4321 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem);
4322 if (IS_ERR(ib_mr))
4323 ib_umem_release(umem);
4324 return ib_mr;
4325 }
4326
bnxt_re_reg_user_mr_dmabuf(struct ib_pd * ib_pd,u64 start,u64 length,u64 virt_addr,int fd,int mr_access_flags,struct ib_dmah * dmah,struct uverbs_attr_bundle * attrs)4327 struct ib_mr *bnxt_re_reg_user_mr_dmabuf(struct ib_pd *ib_pd, u64 start,
4328 u64 length, u64 virt_addr, int fd,
4329 int mr_access_flags,
4330 struct ib_dmah *dmah,
4331 struct uverbs_attr_bundle *attrs)
4332 {
4333 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4334 struct bnxt_re_dev *rdev = pd->rdev;
4335 struct ib_umem_dmabuf *umem_dmabuf;
4336 struct ib_umem *umem;
4337 struct ib_mr *ib_mr;
4338
4339 if (dmah)
4340 return ERR_PTR(-EOPNOTSUPP);
4341
4342 umem_dmabuf = ib_umem_dmabuf_get_pinned(&rdev->ibdev, start, length,
4343 fd, mr_access_flags);
4344 if (IS_ERR(umem_dmabuf))
4345 return ERR_CAST(umem_dmabuf);
4346
4347 umem = &umem_dmabuf->umem;
4348
4349 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem);
4350 if (IS_ERR(ib_mr))
4351 ib_umem_release(umem);
4352 return ib_mr;
4353 }
4354
bnxt_re_alloc_ucontext(struct ib_ucontext * ctx,struct ib_udata * udata)4355 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata)
4356 {
4357 struct ib_device *ibdev = ctx->device;
4358 struct bnxt_re_ucontext *uctx =
4359 container_of(ctx, struct bnxt_re_ucontext, ib_uctx);
4360 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
4361 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr;
4362 struct bnxt_re_user_mmap_entry *entry;
4363 struct bnxt_re_uctx_resp resp = {};
4364 struct bnxt_re_uctx_req ureq = {};
4365 u32 chip_met_rev_num = 0;
4366 int rc;
4367
4368 ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver);
4369
4370 if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) {
4371 ibdev_dbg(ibdev, " is different from the device %d ",
4372 BNXT_RE_ABI_VERSION);
4373 return -EPERM;
4374 }
4375
4376 uctx->rdev = rdev;
4377
4378 uctx->shpg = (void *)__get_free_page(GFP_KERNEL);
4379 if (!uctx->shpg) {
4380 rc = -ENOMEM;
4381 goto fail;
4382 }
4383 spin_lock_init(&uctx->sh_lock);
4384
4385 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX;
4386 chip_met_rev_num = rdev->chip_ctx->chip_num;
4387 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) <<
4388 BNXT_RE_CHIP_ID0_CHIP_REV_SFT;
4389 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) <<
4390 BNXT_RE_CHIP_ID0_CHIP_MET_SFT;
4391 resp.chip_id0 = chip_met_rev_num;
4392 /*Temp, Use xa_alloc instead */
4393 resp.dev_id = rdev->en_dev->pdev->devfn;
4394 resp.max_qp = rdev->qplib_ctx.qpc_count;
4395 resp.pg_size = PAGE_SIZE;
4396 resp.cqe_sz = sizeof(struct cq_base);
4397 resp.max_cqd = dev_attr->max_cq_wqes;
4398
4399 if (rdev->chip_ctx->modes.db_push)
4400 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_WC_DPI_ENABLED;
4401
4402 entry = bnxt_re_mmap_entry_insert(uctx, 0, BNXT_RE_MMAP_SH_PAGE, NULL);
4403 if (!entry) {
4404 rc = -ENOMEM;
4405 goto cfail;
4406 }
4407 uctx->shpage_mmap = &entry->rdma_entry;
4408 if (rdev->pacing.dbr_pacing)
4409 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED;
4410
4411 if (_is_host_msn_table(rdev->qplib_res.dattr->dev_cap_flags2))
4412 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_MSN_TABLE_ENABLED;
4413
4414 if (_is_modify_qp_rate_limit_supported(dev_attr->dev_cap_flags2))
4415 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_QP_RATE_LIMIT_ENABLED;
4416
4417 if (udata->inlen >= sizeof(ureq)) {
4418 rc = ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq)));
4419 if (rc)
4420 goto cfail;
4421 if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT) {
4422 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED;
4423 uctx->cmask |= BNXT_RE_UCNTX_CAP_POW2_DISABLED;
4424 }
4425 if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_VAR_WQE_SUPPORT) {
4426 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_HAVE_MODE;
4427 resp.mode = rdev->chip_ctx->modes.wqe_mode;
4428 if (resp.mode == BNXT_QPLIB_WQE_MODE_VARIABLE)
4429 uctx->cmask |= BNXT_RE_UCNTX_CAP_VAR_WQE_ENABLED;
4430 }
4431 }
4432
4433 rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
4434 if (rc) {
4435 ibdev_err(ibdev, "Failed to copy user context");
4436 rc = -EFAULT;
4437 goto cfail;
4438 }
4439
4440 return 0;
4441 cfail:
4442 free_page((unsigned long)uctx->shpg);
4443 uctx->shpg = NULL;
4444 fail:
4445 return rc;
4446 }
4447
bnxt_re_dealloc_ucontext(struct ib_ucontext * ib_uctx)4448 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx)
4449 {
4450 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
4451 struct bnxt_re_ucontext,
4452 ib_uctx);
4453
4454 struct bnxt_re_dev *rdev = uctx->rdev;
4455
4456 rdma_user_mmap_entry_remove(uctx->shpage_mmap);
4457 uctx->shpage_mmap = NULL;
4458 if (uctx->shpg)
4459 free_page((unsigned long)uctx->shpg);
4460
4461 if (uctx->dpi.dbr) {
4462 /* Free DPI only if this is the first PD allocated by the
4463 * application and mark the context dpi as NULL
4464 */
4465 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->dpi);
4466 uctx->dpi.dbr = NULL;
4467 }
4468 }
4469
bnxt_re_setup_vnic(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp)4470 static int bnxt_re_setup_vnic(struct bnxt_re_dev *rdev, struct bnxt_re_qp *qp)
4471 {
4472 int rc;
4473
4474 rc = bnxt_re_hwrm_alloc_vnic(rdev);
4475 if (rc)
4476 return rc;
4477
4478 rc = bnxt_re_hwrm_cfg_vnic(rdev, qp->qplib_qp.id);
4479 if (rc)
4480 goto out_free_vnic;
4481
4482 return 0;
4483 out_free_vnic:
4484 bnxt_re_hwrm_free_vnic(rdev);
4485 return rc;
4486 }
4487
bnxt_re_create_flow(struct ib_qp * ib_qp,struct ib_flow_attr * attr,struct ib_udata * udata)4488 struct ib_flow *bnxt_re_create_flow(struct ib_qp *ib_qp,
4489 struct ib_flow_attr *attr,
4490 struct ib_udata *udata)
4491 {
4492 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
4493 struct bnxt_re_dev *rdev = qp->rdev;
4494 struct bnxt_re_flow *flow;
4495 int rc;
4496
4497 if (attr->type != IB_FLOW_ATTR_SNIFFER ||
4498 !rdev->rcfw.roce_mirror)
4499 return ERR_PTR(-EOPNOTSUPP);
4500
4501 mutex_lock(&rdev->qp_lock);
4502 if (rdev->sniffer_flow_created) {
4503 ibdev_err(&rdev->ibdev, "RoCE Mirroring is already Configured\n");
4504 mutex_unlock(&rdev->qp_lock);
4505 return ERR_PTR(-EBUSY);
4506 }
4507
4508 flow = kzalloc_obj(*flow);
4509 if (!flow) {
4510 mutex_unlock(&rdev->qp_lock);
4511 return ERR_PTR(-ENOMEM);
4512 }
4513
4514 flow->rdev = rdev;
4515
4516 rc = bnxt_re_setup_vnic(rdev, qp);
4517 if (rc)
4518 goto out_free_flow;
4519
4520 rc = bnxt_qplib_create_flow(&rdev->qplib_res);
4521 if (rc)
4522 goto out_free_vnic;
4523
4524 rdev->sniffer_flow_created = 1;
4525 mutex_unlock(&rdev->qp_lock);
4526
4527 return &flow->ib_flow;
4528
4529 out_free_vnic:
4530 bnxt_re_hwrm_free_vnic(rdev);
4531 out_free_flow:
4532 mutex_unlock(&rdev->qp_lock);
4533 kfree(flow);
4534 return ERR_PTR(rc);
4535 }
4536
bnxt_re_destroy_flow(struct ib_flow * flow_id)4537 int bnxt_re_destroy_flow(struct ib_flow *flow_id)
4538 {
4539 struct bnxt_re_flow *flow =
4540 container_of(flow_id, struct bnxt_re_flow, ib_flow);
4541 struct bnxt_re_dev *rdev = flow->rdev;
4542 int rc;
4543
4544 mutex_lock(&rdev->qp_lock);
4545 rc = bnxt_qplib_destroy_flow(&rdev->qplib_res);
4546 if (rc)
4547 ibdev_dbg(&rdev->ibdev, "failed to destroy_flow rc = %d\n", rc);
4548 rdev->sniffer_flow_created = 0;
4549
4550 bnxt_re_hwrm_free_vnic(rdev);
4551 mutex_unlock(&rdev->qp_lock);
4552 kfree(flow);
4553
4554 return rc;
4555 }
4556
bnxt_re_search_for_cq(struct bnxt_re_dev * rdev,u32 cq_id)4557 static struct bnxt_re_cq *bnxt_re_search_for_cq(struct bnxt_re_dev *rdev, u32 cq_id)
4558 {
4559 struct bnxt_re_cq *cq = NULL, *tmp_cq;
4560
4561 hash_for_each_possible(rdev->cq_hash, tmp_cq, hash_entry, cq_id) {
4562 if (tmp_cq->qplib_cq.id == cq_id) {
4563 cq = tmp_cq;
4564 break;
4565 }
4566 }
4567 return cq;
4568 }
4569
bnxt_re_search_for_srq(struct bnxt_re_dev * rdev,u32 srq_id)4570 static struct bnxt_re_srq *bnxt_re_search_for_srq(struct bnxt_re_dev *rdev, u32 srq_id)
4571 {
4572 struct bnxt_re_srq *srq = NULL, *tmp_srq;
4573
4574 hash_for_each_possible(rdev->srq_hash, tmp_srq, hash_entry, srq_id) {
4575 if (tmp_srq->qplib_srq.id == srq_id) {
4576 srq = tmp_srq;
4577 break;
4578 }
4579 }
4580 return srq;
4581 }
4582
4583 /* Helper function to mmap the virtual memory from user app */
bnxt_re_mmap(struct ib_ucontext * ib_uctx,struct vm_area_struct * vma)4584 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)
4585 {
4586 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
4587 struct bnxt_re_ucontext,
4588 ib_uctx);
4589 struct bnxt_re_user_mmap_entry *bnxt_entry;
4590 struct rdma_user_mmap_entry *rdma_entry;
4591 int ret = 0;
4592 u64 pfn;
4593
4594 rdma_entry = rdma_user_mmap_entry_get(&uctx->ib_uctx, vma);
4595 if (!rdma_entry)
4596 return -EINVAL;
4597
4598 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry,
4599 rdma_entry);
4600
4601 switch (bnxt_entry->mmap_flag) {
4602 case BNXT_RE_MMAP_WC_DB:
4603 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT;
4604 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE,
4605 pgprot_writecombine(vma->vm_page_prot),
4606 rdma_entry);
4607 break;
4608 case BNXT_RE_MMAP_UC_DB:
4609 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT;
4610 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE,
4611 pgprot_noncached(vma->vm_page_prot),
4612 rdma_entry);
4613 break;
4614 case BNXT_RE_MMAP_SH_PAGE:
4615 ret = vm_insert_page(vma, vma->vm_start, virt_to_page(uctx->shpg));
4616 break;
4617 case BNXT_RE_MMAP_DBR_BAR:
4618 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT;
4619 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE,
4620 pgprot_noncached(vma->vm_page_prot),
4621 rdma_entry);
4622 break;
4623 case BNXT_RE_MMAP_DBR_PAGE:
4624 case BNXT_RE_MMAP_TOGGLE_PAGE:
4625 /* Driver doesn't expect write access for user space */
4626 if (vma->vm_flags & VM_WRITE)
4627 ret = -EFAULT;
4628 else
4629 ret = vm_insert_page(vma, vma->vm_start,
4630 virt_to_page((void *)bnxt_entry->mem_offset));
4631 break;
4632 default:
4633 ret = -EINVAL;
4634 break;
4635 }
4636
4637 rdma_user_mmap_entry_put(rdma_entry);
4638 return ret;
4639 }
4640
bnxt_re_mmap_free(struct rdma_user_mmap_entry * rdma_entry)4641 void bnxt_re_mmap_free(struct rdma_user_mmap_entry *rdma_entry)
4642 {
4643 struct bnxt_re_user_mmap_entry *bnxt_entry;
4644
4645 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry,
4646 rdma_entry);
4647
4648 kfree(bnxt_entry);
4649 }
4650
bnxt_re_process_mad(struct ib_device * ibdev,int mad_flags,u32 port_num,const struct ib_wc * in_wc,const struct ib_grh * in_grh,const struct ib_mad * in_mad,struct ib_mad * out_mad,size_t * out_mad_size,u16 * out_mad_pkey_index)4651 int bnxt_re_process_mad(struct ib_device *ibdev, int mad_flags,
4652 u32 port_num, const struct ib_wc *in_wc,
4653 const struct ib_grh *in_grh,
4654 const struct ib_mad *in_mad, struct ib_mad *out_mad,
4655 size_t *out_mad_size, u16 *out_mad_pkey_index)
4656 {
4657 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
4658 struct ib_class_port_info cpi = {};
4659 int ret = IB_MAD_RESULT_SUCCESS;
4660 int rc = 0;
4661
4662 if (in_mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_PERF_MGMT)
4663 return ret;
4664
4665 switch (in_mad->mad_hdr.attr_id) {
4666 case IB_PMA_CLASS_PORT_INFO:
4667 cpi.capability_mask = IB_PMA_CLASS_CAP_EXT_WIDTH;
4668 memcpy((out_mad->data + 40), &cpi, sizeof(cpi));
4669 break;
4670 case IB_PMA_PORT_COUNTERS_EXT:
4671 rc = bnxt_re_assign_pma_port_ext_counters(rdev, out_mad);
4672 break;
4673 case IB_PMA_PORT_COUNTERS:
4674 rc = bnxt_re_assign_pma_port_counters(rdev, out_mad);
4675 break;
4676 default:
4677 rc = -EINVAL;
4678 break;
4679 }
4680 if (rc)
4681 return IB_MAD_RESULT_FAILURE;
4682 ret |= IB_MAD_RESULT_REPLY;
4683 return ret;
4684 }
4685
UVERBS_HANDLER(BNXT_RE_METHOD_NOTIFY_DRV)4686 static int UVERBS_HANDLER(BNXT_RE_METHOD_NOTIFY_DRV)(struct uverbs_attr_bundle *attrs)
4687 {
4688 struct bnxt_re_ucontext *uctx;
4689
4690 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx);
4691 bnxt_re_pacing_alert(uctx->rdev);
4692 return 0;
4693 }
4694
UVERBS_HANDLER(BNXT_RE_METHOD_ALLOC_PAGE)4695 static int UVERBS_HANDLER(BNXT_RE_METHOD_ALLOC_PAGE)(struct uverbs_attr_bundle *attrs)
4696 {
4697 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_ALLOC_PAGE_HANDLE);
4698 enum bnxt_re_alloc_page_type alloc_type;
4699 struct bnxt_re_user_mmap_entry *entry;
4700 enum bnxt_re_mmap_flag mmap_flag;
4701 struct bnxt_qplib_chip_ctx *cctx;
4702 struct bnxt_re_ucontext *uctx;
4703 struct bnxt_re_dev *rdev;
4704 u64 mmap_offset;
4705 u32 length;
4706 u32 dpi;
4707 u64 addr;
4708 int err;
4709
4710 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx);
4711 if (IS_ERR(uctx))
4712 return PTR_ERR(uctx);
4713
4714 err = uverbs_get_const(&alloc_type, attrs, BNXT_RE_ALLOC_PAGE_TYPE);
4715 if (err)
4716 return err;
4717
4718 rdev = uctx->rdev;
4719 cctx = rdev->chip_ctx;
4720
4721 switch (alloc_type) {
4722 case BNXT_RE_ALLOC_WC_PAGE:
4723 if (cctx->modes.db_push) {
4724 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, &uctx->wcdpi,
4725 uctx, BNXT_QPLIB_DPI_TYPE_WC))
4726 return -ENOMEM;
4727 length = PAGE_SIZE;
4728 dpi = uctx->wcdpi.dpi;
4729 addr = (u64)uctx->wcdpi.umdbr;
4730 mmap_flag = BNXT_RE_MMAP_WC_DB;
4731 } else {
4732 return -EINVAL;
4733 }
4734
4735 break;
4736 case BNXT_RE_ALLOC_DBR_BAR_PAGE:
4737 length = PAGE_SIZE;
4738 addr = (u64)rdev->pacing.dbr_bar_addr;
4739 mmap_flag = BNXT_RE_MMAP_DBR_BAR;
4740 break;
4741
4742 case BNXT_RE_ALLOC_DBR_PAGE:
4743 length = PAGE_SIZE;
4744 addr = (u64)rdev->pacing.dbr_page;
4745 mmap_flag = BNXT_RE_MMAP_DBR_PAGE;
4746 break;
4747
4748 default:
4749 return -EOPNOTSUPP;
4750 }
4751
4752 entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mmap_offset);
4753 if (!entry)
4754 return -ENOMEM;
4755
4756 uobj->object = entry;
4757 uverbs_finalize_uobj_create(attrs, BNXT_RE_ALLOC_PAGE_HANDLE);
4758 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_OFFSET,
4759 &mmap_offset, sizeof(mmap_offset));
4760 if (err)
4761 return err;
4762
4763 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_LENGTH,
4764 &length, sizeof(length));
4765 if (err)
4766 return err;
4767
4768 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_DPI,
4769 &dpi, sizeof(dpi));
4770 if (err)
4771 return err;
4772
4773 return 0;
4774 }
4775
alloc_page_obj_cleanup(struct ib_uobject * uobject,enum rdma_remove_reason why,struct uverbs_attr_bundle * attrs)4776 static int alloc_page_obj_cleanup(struct ib_uobject *uobject,
4777 enum rdma_remove_reason why,
4778 struct uverbs_attr_bundle *attrs)
4779 {
4780 struct bnxt_re_user_mmap_entry *entry = uobject->object;
4781 struct bnxt_re_ucontext *uctx = entry->uctx;
4782
4783 switch (entry->mmap_flag) {
4784 case BNXT_RE_MMAP_WC_DB:
4785 if (uctx && uctx->wcdpi.dbr) {
4786 struct bnxt_re_dev *rdev = uctx->rdev;
4787
4788 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->wcdpi);
4789 uctx->wcdpi.dbr = NULL;
4790 }
4791 break;
4792 case BNXT_RE_MMAP_DBR_BAR:
4793 case BNXT_RE_MMAP_DBR_PAGE:
4794 break;
4795 default:
4796 goto exit;
4797 }
4798 rdma_user_mmap_entry_remove(&entry->rdma_entry);
4799 exit:
4800 return 0;
4801 }
4802
4803 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_ALLOC_PAGE,
4804 UVERBS_ATTR_IDR(BNXT_RE_ALLOC_PAGE_HANDLE,
4805 BNXT_RE_OBJECT_ALLOC_PAGE,
4806 UVERBS_ACCESS_NEW,
4807 UA_MANDATORY),
4808 UVERBS_ATTR_CONST_IN(BNXT_RE_ALLOC_PAGE_TYPE,
4809 enum bnxt_re_alloc_page_type,
4810 UA_MANDATORY),
4811 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_OFFSET,
4812 UVERBS_ATTR_TYPE(u64),
4813 UA_MANDATORY),
4814 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_LENGTH,
4815 UVERBS_ATTR_TYPE(u32),
4816 UA_MANDATORY),
4817 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_DPI,
4818 UVERBS_ATTR_TYPE(u32),
4819 UA_MANDATORY));
4820
4821 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_DESTROY_PAGE,
4822 UVERBS_ATTR_IDR(BNXT_RE_DESTROY_PAGE_HANDLE,
4823 BNXT_RE_OBJECT_ALLOC_PAGE,
4824 UVERBS_ACCESS_DESTROY,
4825 UA_MANDATORY));
4826
4827 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_ALLOC_PAGE,
4828 UVERBS_TYPE_ALLOC_IDR(alloc_page_obj_cleanup),
4829 &UVERBS_METHOD(BNXT_RE_METHOD_ALLOC_PAGE),
4830 &UVERBS_METHOD(BNXT_RE_METHOD_DESTROY_PAGE));
4831
4832 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_NOTIFY_DRV);
4833
4834 DECLARE_UVERBS_GLOBAL_METHODS(BNXT_RE_OBJECT_NOTIFY_DRV,
4835 &UVERBS_METHOD(BNXT_RE_METHOD_NOTIFY_DRV));
4836
4837 /* Toggle MEM */
UVERBS_HANDLER(BNXT_RE_METHOD_GET_TOGGLE_MEM)4838 static int UVERBS_HANDLER(BNXT_RE_METHOD_GET_TOGGLE_MEM)(struct uverbs_attr_bundle *attrs)
4839 {
4840 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_TOGGLE_MEM_HANDLE);
4841 enum bnxt_re_mmap_flag mmap_flag = BNXT_RE_MMAP_TOGGLE_PAGE;
4842 enum bnxt_re_get_toggle_mem_type res_type;
4843 struct bnxt_re_user_mmap_entry *entry;
4844 struct bnxt_re_ucontext *uctx;
4845 struct ib_ucontext *ib_uctx;
4846 struct bnxt_re_dev *rdev;
4847 struct bnxt_re_srq *srq;
4848 u32 length = PAGE_SIZE;
4849 struct bnxt_re_cq *cq;
4850 u64 mem_offset;
4851 u32 offset = 0;
4852 u64 addr = 0;
4853 u32 res_id;
4854 int err;
4855
4856 ib_uctx = ib_uverbs_get_ucontext(attrs);
4857 if (IS_ERR(ib_uctx))
4858 return PTR_ERR(ib_uctx);
4859
4860 err = uverbs_get_const(&res_type, attrs, BNXT_RE_TOGGLE_MEM_TYPE);
4861 if (err)
4862 return err;
4863
4864 uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx);
4865 rdev = uctx->rdev;
4866 err = uverbs_copy_from(&res_id, attrs, BNXT_RE_TOGGLE_MEM_RES_ID);
4867 if (err)
4868 return err;
4869
4870 switch (res_type) {
4871 case BNXT_RE_CQ_TOGGLE_MEM:
4872 cq = bnxt_re_search_for_cq(rdev, res_id);
4873 if (!cq)
4874 return -EINVAL;
4875
4876 addr = (u64)cq->uctx_cq_page;
4877 break;
4878 case BNXT_RE_SRQ_TOGGLE_MEM:
4879 srq = bnxt_re_search_for_srq(rdev, res_id);
4880 if (!srq)
4881 return -EINVAL;
4882
4883 addr = (u64)srq->uctx_srq_page;
4884 break;
4885
4886 default:
4887 return -EOPNOTSUPP;
4888 }
4889
4890 entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mem_offset);
4891 if (!entry)
4892 return -ENOMEM;
4893
4894 uobj->object = entry;
4895 uverbs_finalize_uobj_create(attrs, BNXT_RE_TOGGLE_MEM_HANDLE);
4896 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_PAGE,
4897 &mem_offset, sizeof(mem_offset));
4898 if (err)
4899 return err;
4900
4901 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_LENGTH,
4902 &length, sizeof(length));
4903 if (err)
4904 return err;
4905
4906 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_OFFSET,
4907 &offset, sizeof(offset));
4908 if (err)
4909 return err;
4910
4911 return 0;
4912 }
4913
get_toggle_mem_obj_cleanup(struct ib_uobject * uobject,enum rdma_remove_reason why,struct uverbs_attr_bundle * attrs)4914 static int get_toggle_mem_obj_cleanup(struct ib_uobject *uobject,
4915 enum rdma_remove_reason why,
4916 struct uverbs_attr_bundle *attrs)
4917 {
4918 struct bnxt_re_user_mmap_entry *entry = uobject->object;
4919
4920 rdma_user_mmap_entry_remove(&entry->rdma_entry);
4921 return 0;
4922 }
4923
4924 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM,
4925 UVERBS_ATTR_IDR(BNXT_RE_TOGGLE_MEM_HANDLE,
4926 BNXT_RE_OBJECT_GET_TOGGLE_MEM,
4927 UVERBS_ACCESS_NEW,
4928 UA_MANDATORY),
4929 UVERBS_ATTR_CONST_IN(BNXT_RE_TOGGLE_MEM_TYPE,
4930 enum bnxt_re_get_toggle_mem_type,
4931 UA_MANDATORY),
4932 UVERBS_ATTR_PTR_IN(BNXT_RE_TOGGLE_MEM_RES_ID,
4933 UVERBS_ATTR_TYPE(u32),
4934 UA_MANDATORY),
4935 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_PAGE,
4936 UVERBS_ATTR_TYPE(u64),
4937 UA_MANDATORY),
4938 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_OFFSET,
4939 UVERBS_ATTR_TYPE(u32),
4940 UA_MANDATORY),
4941 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_LENGTH,
4942 UVERBS_ATTR_TYPE(u32),
4943 UA_MANDATORY));
4944
4945 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM,
4946 UVERBS_ATTR_IDR(BNXT_RE_RELEASE_TOGGLE_MEM_HANDLE,
4947 BNXT_RE_OBJECT_GET_TOGGLE_MEM,
4948 UVERBS_ACCESS_DESTROY,
4949 UA_MANDATORY));
4950
4951 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_GET_TOGGLE_MEM,
4952 UVERBS_TYPE_ALLOC_IDR(get_toggle_mem_obj_cleanup),
4953 &UVERBS_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM),
4954 &UVERBS_METHOD(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM));
4955
4956 const struct uapi_definition bnxt_re_uapi_defs[] = {
4957 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_ALLOC_PAGE),
4958 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_NOTIFY_DRV),
4959 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_GET_TOGGLE_MEM),
4960 {}
4961 };
4962