1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: IB Verbs interpreter
37 */
38
39 #include <linux/interrupt.h>
40 #include <linux/types.h>
41 #include <linux/pci.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_ether.h>
44 #include <net/addrconf.h>
45
46 #include <rdma/ib_verbs.h>
47 #include <rdma/ib_user_verbs.h>
48 #include <rdma/ib_umem.h>
49 #include <rdma/ib_addr.h>
50 #include <rdma/ib_mad.h>
51 #include <rdma/ib_cache.h>
52 #include <rdma/ib_pma.h>
53 #include <rdma/uverbs_ioctl.h>
54 #include <linux/hashtable.h>
55
56 #include "roce_hsi.h"
57 #include "qplib_res.h"
58 #include "qplib_sp.h"
59 #include "qplib_fp.h"
60 #include "qplib_rcfw.h"
61
62 #include "bnxt_re.h"
63 #include "ib_verbs.h"
64 #include "debugfs.h"
65
66 #include <rdma/uverbs_types.h>
67 #include <rdma/uverbs_std_types.h>
68
69 #include <rdma/ib_user_ioctl_cmds.h>
70
71 #define UVERBS_MODULE_NAME bnxt_re
72 #include <rdma/uverbs_named_ioctl.h>
73
74 #include <rdma/bnxt_re-abi.h>
75
__from_ib_access_flags(int iflags)76 static int __from_ib_access_flags(int iflags)
77 {
78 int qflags = 0;
79
80 if (iflags & IB_ACCESS_LOCAL_WRITE)
81 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
82 if (iflags & IB_ACCESS_REMOTE_READ)
83 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ;
84 if (iflags & IB_ACCESS_REMOTE_WRITE)
85 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
86 if (iflags & IB_ACCESS_REMOTE_ATOMIC)
87 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
88 if (iflags & IB_ACCESS_MW_BIND)
89 qflags |= BNXT_QPLIB_ACCESS_MW_BIND;
90 if (iflags & IB_ZERO_BASED)
91 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED;
92 if (iflags & IB_ACCESS_ON_DEMAND)
93 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND;
94 return qflags;
95 };
96
__to_ib_access_flags(int qflags)97 static int __to_ib_access_flags(int qflags)
98 {
99 int iflags = 0;
100
101 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
102 iflags |= IB_ACCESS_LOCAL_WRITE;
103 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
104 iflags |= IB_ACCESS_REMOTE_WRITE;
105 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
106 iflags |= IB_ACCESS_REMOTE_READ;
107 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
108 iflags |= IB_ACCESS_REMOTE_ATOMIC;
109 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
110 iflags |= IB_ACCESS_MW_BIND;
111 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
112 iflags |= IB_ZERO_BASED;
113 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
114 iflags |= IB_ACCESS_ON_DEMAND;
115 return iflags;
116 }
117
__qp_access_flags_from_ib(struct bnxt_qplib_chip_ctx * cctx,int iflags)118 static u8 __qp_access_flags_from_ib(struct bnxt_qplib_chip_ctx *cctx, int iflags)
119 {
120 u8 qflags = 0;
121
122 if (!bnxt_qplib_is_chip_gen_p5_p7(cctx))
123 /* For Wh+ */
124 return (u8)__from_ib_access_flags(iflags);
125
126 /* For P5, P7 and later chips */
127 if (iflags & IB_ACCESS_LOCAL_WRITE)
128 qflags |= CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE;
129 if (iflags & IB_ACCESS_REMOTE_WRITE)
130 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE;
131 if (iflags & IB_ACCESS_REMOTE_READ)
132 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ;
133 if (iflags & IB_ACCESS_REMOTE_ATOMIC)
134 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC;
135
136 return qflags;
137 }
138
__qp_access_flags_to_ib(struct bnxt_qplib_chip_ctx * cctx,u8 qflags)139 static int __qp_access_flags_to_ib(struct bnxt_qplib_chip_ctx *cctx, u8 qflags)
140 {
141 int iflags = 0;
142
143 if (!bnxt_qplib_is_chip_gen_p5_p7(cctx))
144 /* For Wh+ */
145 return __to_ib_access_flags(qflags);
146
147 /* For P5, P7 and later chips */
148 if (qflags & CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE)
149 iflags |= IB_ACCESS_LOCAL_WRITE;
150 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE)
151 iflags |= IB_ACCESS_REMOTE_WRITE;
152 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_READ)
153 iflags |= IB_ACCESS_REMOTE_READ;
154 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC)
155 iflags |= IB_ACCESS_REMOTE_ATOMIC;
156
157 return iflags;
158 }
159
bnxt_re_check_and_set_relaxed_ordering(struct bnxt_re_dev * rdev,struct bnxt_qplib_mrw * qplib_mr)160 static void bnxt_re_check_and_set_relaxed_ordering(struct bnxt_re_dev *rdev,
161 struct bnxt_qplib_mrw *qplib_mr)
162 {
163 if (_is_relaxed_ordering_supported(rdev->dev_attr->dev_cap_flags2) &&
164 pcie_relaxed_ordering_enabled(rdev->en_dev->pdev))
165 qplib_mr->flags |= CMDQ_REGISTER_MR_FLAGS_ENABLE_RO;
166 }
167
bnxt_re_build_sgl(struct ib_sge * ib_sg_list,struct bnxt_qplib_sge * sg_list,int num)168 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,
169 struct bnxt_qplib_sge *sg_list, int num)
170 {
171 int i, total = 0;
172
173 for (i = 0; i < num; i++) {
174 sg_list[i].addr = ib_sg_list[i].addr;
175 sg_list[i].lkey = ib_sg_list[i].lkey;
176 sg_list[i].size = ib_sg_list[i].length;
177 total += sg_list[i].size;
178 }
179 return total;
180 }
181
182 /* Device */
bnxt_re_query_device(struct ib_device * ibdev,struct ib_device_attr * ib_attr,struct ib_udata * udata)183 int bnxt_re_query_device(struct ib_device *ibdev,
184 struct ib_device_attr *ib_attr,
185 struct ib_udata *udata)
186 {
187 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
188 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr;
189
190 memset(ib_attr, 0, sizeof(*ib_attr));
191 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver,
192 min(sizeof(dev_attr->fw_ver),
193 sizeof(ib_attr->fw_ver)));
194 addrconf_addr_eui48((u8 *)&ib_attr->sys_image_guid,
195 rdev->netdev->dev_addr);
196 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE;
197 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_SUPPORTED;
198
199 ib_attr->vendor_id = rdev->en_dev->pdev->vendor;
200 ib_attr->vendor_part_id = rdev->en_dev->pdev->device;
201 ib_attr->hw_ver = rdev->en_dev->pdev->revision;
202 ib_attr->max_qp = dev_attr->max_qp;
203 ib_attr->max_qp_wr = dev_attr->max_qp_wqes;
204 ib_attr->device_cap_flags =
205 IB_DEVICE_CURR_QP_STATE_MOD
206 | IB_DEVICE_RC_RNR_NAK_GEN
207 | IB_DEVICE_SHUTDOWN_PORT
208 | IB_DEVICE_SYS_IMAGE_GUID
209 | IB_DEVICE_RESIZE_MAX_WR
210 | IB_DEVICE_PORT_ACTIVE_EVENT
211 | IB_DEVICE_N_NOTIFY_CQ
212 | IB_DEVICE_MEM_WINDOW
213 | IB_DEVICE_MEM_WINDOW_TYPE_2B
214 | IB_DEVICE_MEM_MGT_EXTENSIONS;
215 ib_attr->kernel_cap_flags = IBK_LOCAL_DMA_LKEY;
216 ib_attr->max_send_sge = dev_attr->max_qp_sges;
217 ib_attr->max_recv_sge = dev_attr->max_qp_sges;
218 ib_attr->max_sge_rd = dev_attr->max_qp_sges;
219 ib_attr->max_cq = dev_attr->max_cq;
220 ib_attr->max_cqe = dev_attr->max_cq_wqes;
221 ib_attr->max_mr = dev_attr->max_mr;
222 ib_attr->max_pd = dev_attr->max_pd;
223 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
224 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom;
225 ib_attr->atomic_cap = IB_ATOMIC_NONE;
226 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE;
227 if (dev_attr->is_atomic) {
228 ib_attr->atomic_cap = IB_ATOMIC_GLOB;
229 ib_attr->masked_atomic_cap = IB_ATOMIC_GLOB;
230 }
231
232 ib_attr->max_ee_rd_atom = 0;
233 ib_attr->max_res_rd_atom = 0;
234 ib_attr->max_ee_init_rd_atom = 0;
235 ib_attr->max_ee = 0;
236 ib_attr->max_rdd = 0;
237 ib_attr->max_mw = dev_attr->max_mw;
238 ib_attr->max_raw_ipv6_qp = 0;
239 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp;
240 ib_attr->max_mcast_grp = 0;
241 ib_attr->max_mcast_qp_attach = 0;
242 ib_attr->max_total_mcast_qp_attach = 0;
243 ib_attr->max_ah = dev_attr->max_ah;
244
245 ib_attr->max_srq = dev_attr->max_srq;
246 ib_attr->max_srq_wr = dev_attr->max_srq_wqes;
247 ib_attr->max_srq_sge = dev_attr->max_srq_sges;
248
249 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS;
250
251 ib_attr->max_pkeys = 1;
252 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY;
253 return 0;
254 }
255
bnxt_re_modify_device(struct ib_device * ibdev,int device_modify_mask,struct ib_device_modify * device_modify)256 int bnxt_re_modify_device(struct ib_device *ibdev,
257 int device_modify_mask,
258 struct ib_device_modify *device_modify)
259 {
260 ibdev_dbg(ibdev, "Modify device with mask 0x%x", device_modify_mask);
261
262 if (device_modify_mask & ~IB_DEVICE_MODIFY_NODE_DESC)
263 return -EOPNOTSUPP;
264
265 if (!(device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC))
266 return 0;
267
268 memcpy(ibdev->node_desc, device_modify->node_desc, IB_DEVICE_NODE_DESC_MAX);
269 return 0;
270 }
271
272 /* Port */
bnxt_re_query_port(struct ib_device * ibdev,u32 port_num,struct ib_port_attr * port_attr)273 int bnxt_re_query_port(struct ib_device *ibdev, u32 port_num,
274 struct ib_port_attr *port_attr)
275 {
276 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
277 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr;
278 int rc;
279
280 memset(port_attr, 0, sizeof(*port_attr));
281
282 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) {
283 port_attr->state = IB_PORT_ACTIVE;
284 port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
285 } else {
286 port_attr->state = IB_PORT_DOWN;
287 port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED;
288 }
289 port_attr->max_mtu = IB_MTU_4096;
290 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu);
291 port_attr->gid_tbl_len = dev_attr->max_sgid;
292 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
293 IB_PORT_DEVICE_MGMT_SUP |
294 IB_PORT_VENDOR_CLASS_SUP;
295 port_attr->ip_gids = true;
296
297 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW;
298 port_attr->bad_pkey_cntr = 0;
299 port_attr->qkey_viol_cntr = 0;
300 port_attr->pkey_tbl_len = dev_attr->max_pkey;
301 port_attr->lid = 0;
302 port_attr->sm_lid = 0;
303 port_attr->lmc = 0;
304 port_attr->max_vl_num = 4;
305 port_attr->sm_sl = 0;
306 port_attr->subnet_timeout = 0;
307 port_attr->init_type_reply = 0;
308 rc = ib_get_eth_speed(&rdev->ibdev, port_num, &port_attr->active_speed,
309 &port_attr->active_width);
310
311 return rc;
312 }
313
bnxt_re_get_port_immutable(struct ib_device * ibdev,u32 port_num,struct ib_port_immutable * immutable)314 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u32 port_num,
315 struct ib_port_immutable *immutable)
316 {
317 struct ib_port_attr port_attr;
318
319 if (bnxt_re_query_port(ibdev, port_num, &port_attr))
320 return -EINVAL;
321
322 immutable->pkey_tbl_len = port_attr.pkey_tbl_len;
323 immutable->gid_tbl_len = port_attr.gid_tbl_len;
324 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
325 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP;
326 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
327 return 0;
328 }
329
bnxt_re_query_fw_str(struct ib_device * ibdev,char * str)330 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str)
331 {
332 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
333
334 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
335 rdev->dev_attr->fw_ver[0], rdev->dev_attr->fw_ver[1],
336 rdev->dev_attr->fw_ver[2], rdev->dev_attr->fw_ver[3]);
337 }
338
bnxt_re_query_pkey(struct ib_device * ibdev,u32 port_num,u16 index,u16 * pkey)339 int bnxt_re_query_pkey(struct ib_device *ibdev, u32 port_num,
340 u16 index, u16 *pkey)
341 {
342 if (index > 0)
343 return -EINVAL;
344
345 *pkey = IB_DEFAULT_PKEY_FULL;
346
347 return 0;
348 }
349
bnxt_re_query_gid(struct ib_device * ibdev,u32 port_num,int index,union ib_gid * gid)350 int bnxt_re_query_gid(struct ib_device *ibdev, u32 port_num,
351 int index, union ib_gid *gid)
352 {
353 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
354 int rc;
355
356 /* Ignore port_num */
357 memset(gid, 0, sizeof(*gid));
358 rc = bnxt_qplib_get_sgid(&rdev->qplib_res,
359 &rdev->qplib_res.sgid_tbl, index,
360 (struct bnxt_qplib_gid *)gid);
361 return rc;
362 }
363
bnxt_re_del_gid(const struct ib_gid_attr * attr,void ** context)364 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context)
365 {
366 int rc = 0;
367 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
368 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
369 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
370 struct bnxt_qplib_gid *gid_to_del;
371 u16 vlan_id = 0xFFFF;
372
373 /* Delete the entry from the hardware */
374 ctx = *context;
375 if (!ctx)
376 return -EINVAL;
377
378 if (sgid_tbl && sgid_tbl->active) {
379 if (ctx->idx >= sgid_tbl->max)
380 return -EINVAL;
381 gid_to_del = &sgid_tbl->tbl[ctx->idx].gid;
382 vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id;
383 /* DEL_GID is called in WQ context(netdevice_event_work_handler)
384 * or via the ib_unregister_device path. In the former case QP1
385 * may not be destroyed yet, in which case just return as FW
386 * needs that entry to be present and will fail it's deletion.
387 * We could get invoked again after QP1 is destroyed OR get an
388 * ADD_GID call with a different GID value for the same index
389 * where we issue MODIFY_GID cmd to update the GID entry -- TBD
390 */
391 if (ctx->idx == 0 &&
392 rdma_link_local_addr((struct in6_addr *)gid_to_del) &&
393 ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) {
394 ibdev_dbg(&rdev->ibdev,
395 "Trying to delete GID0 while QP1 is alive\n");
396 return -EFAULT;
397 }
398 ctx->refcnt--;
399 if (!ctx->refcnt) {
400 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del,
401 vlan_id, true);
402 if (rc) {
403 ibdev_err(&rdev->ibdev,
404 "Failed to remove GID: %#x", rc);
405 } else {
406 ctx_tbl = sgid_tbl->ctx;
407 ctx_tbl[ctx->idx] = NULL;
408 kfree(ctx);
409 }
410 }
411 } else {
412 return -EINVAL;
413 }
414 return rc;
415 }
416
bnxt_re_add_gid(const struct ib_gid_attr * attr,void ** context)417 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context)
418 {
419 int rc;
420 u32 tbl_idx = 0;
421 u16 vlan_id = 0xFFFF;
422 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
423 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
424 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
425
426 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL);
427 if (rc)
428 return rc;
429
430 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid,
431 rdev->qplib_res.netdev->dev_addr,
432 vlan_id, true, &tbl_idx);
433 if (rc == -EALREADY) {
434 ctx_tbl = sgid_tbl->ctx;
435 ctx_tbl[tbl_idx]->refcnt++;
436 *context = ctx_tbl[tbl_idx];
437 return 0;
438 }
439
440 if (rc < 0) {
441 ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc);
442 return rc;
443 }
444
445 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
446 if (!ctx)
447 return -ENOMEM;
448 ctx_tbl = sgid_tbl->ctx;
449 ctx->idx = tbl_idx;
450 ctx->refcnt = 1;
451 ctx_tbl[tbl_idx] = ctx;
452 *context = ctx;
453
454 return rc;
455 }
456
bnxt_re_get_link_layer(struct ib_device * ibdev,u32 port_num)457 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev,
458 u32 port_num)
459 {
460 return IB_LINK_LAYER_ETHERNET;
461 }
462
463 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE)
464
bnxt_re_create_fence_wqe(struct bnxt_re_pd * pd)465 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd)
466 {
467 struct bnxt_re_fence_data *fence = &pd->fence;
468 struct ib_mr *ib_mr = &fence->mr->ib_mr;
469 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe;
470 struct bnxt_re_dev *rdev = pd->rdev;
471
472 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
473 return;
474
475 memset(wqe, 0, sizeof(*wqe));
476 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW;
477 wqe->wr_id = BNXT_QPLIB_FENCE_WRID;
478 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
479 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
480 wqe->bind.zero_based = false;
481 wqe->bind.parent_l_key = ib_mr->lkey;
482 wqe->bind.va = (u64)(unsigned long)fence->va;
483 wqe->bind.length = fence->size;
484 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ);
485 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1;
486
487 /* Save the initial rkey in fence structure for now;
488 * wqe->bind.r_key will be set at (re)bind time.
489 */
490 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey);
491 }
492
bnxt_re_bind_fence_mw(struct bnxt_qplib_qp * qplib_qp)493 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp)
494 {
495 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp,
496 qplib_qp);
497 struct ib_pd *ib_pd = qp->ib_qp.pd;
498 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
499 struct bnxt_re_fence_data *fence = &pd->fence;
500 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe;
501 struct bnxt_qplib_swqe wqe;
502 int rc;
503
504 memcpy(&wqe, fence_wqe, sizeof(wqe));
505 wqe.bind.r_key = fence->bind_rkey;
506 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey);
507
508 ibdev_dbg(&qp->rdev->ibdev,
509 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n",
510 wqe.bind.r_key, qp->qplib_qp.id, pd);
511 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
512 if (rc) {
513 ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n");
514 return rc;
515 }
516 bnxt_qplib_post_send_db(&qp->qplib_qp);
517
518 return rc;
519 }
520
bnxt_re_destroy_fence_mr(struct bnxt_re_pd * pd)521 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd)
522 {
523 struct bnxt_re_fence_data *fence = &pd->fence;
524 struct bnxt_re_dev *rdev = pd->rdev;
525 struct device *dev = &rdev->en_dev->pdev->dev;
526 struct bnxt_re_mr *mr = fence->mr;
527
528 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
529 return;
530
531 if (fence->mw) {
532 bnxt_re_dealloc_mw(fence->mw);
533 fence->mw = NULL;
534 }
535 if (mr) {
536 if (mr->ib_mr.rkey)
537 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr,
538 true);
539 if (mr->ib_mr.lkey)
540 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
541 kfree(mr);
542 fence->mr = NULL;
543 }
544 if (fence->dma_addr) {
545 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES,
546 DMA_BIDIRECTIONAL);
547 fence->dma_addr = 0;
548 }
549 }
550
bnxt_re_create_fence_mr(struct bnxt_re_pd * pd)551 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd)
552 {
553 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND;
554 struct bnxt_re_fence_data *fence = &pd->fence;
555 struct bnxt_re_dev *rdev = pd->rdev;
556 struct device *dev = &rdev->en_dev->pdev->dev;
557 struct bnxt_re_mr *mr = NULL;
558 dma_addr_t dma_addr = 0;
559 struct ib_mw *mw;
560 int rc;
561
562 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
563 return 0;
564
565 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES,
566 DMA_BIDIRECTIONAL);
567 rc = dma_mapping_error(dev, dma_addr);
568 if (rc) {
569 ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n");
570 rc = -EIO;
571 fence->dma_addr = 0;
572 goto fail;
573 }
574 fence->dma_addr = dma_addr;
575
576 /* Allocate a MR */
577 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
578 if (!mr) {
579 rc = -ENOMEM;
580 goto fail;
581 }
582 fence->mr = mr;
583 mr->rdev = rdev;
584 mr->qplib_mr.pd = &pd->qplib_pd;
585 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
586 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags);
587 if (!_is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags)) {
588 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
589 if (rc) {
590 ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n");
591 goto fail;
592 }
593
594 /* Register MR */
595 mr->ib_mr.lkey = mr->qplib_mr.lkey;
596 } else {
597 mr->qplib_mr.flags = CMDQ_REGISTER_MR_FLAGS_ALLOC_MR;
598 }
599 mr->qplib_mr.va = (u64)(unsigned long)fence->va;
600 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES;
601 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL,
602 BNXT_RE_FENCE_PBL_SIZE, PAGE_SIZE);
603 if (rc) {
604 ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n");
605 goto fail;
606 }
607 mr->ib_mr.rkey = mr->qplib_mr.rkey;
608
609 /* Create a fence MW only for kernel consumers */
610 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL);
611 if (IS_ERR(mw)) {
612 ibdev_err(&rdev->ibdev,
613 "Failed to create fence-MW for PD: %p\n", pd);
614 rc = PTR_ERR(mw);
615 goto fail;
616 }
617 fence->mw = mw;
618
619 bnxt_re_create_fence_wqe(pd);
620 return 0;
621
622 fail:
623 bnxt_re_destroy_fence_mr(pd);
624 return rc;
625 }
626
627 static struct bnxt_re_user_mmap_entry*
bnxt_re_mmap_entry_insert(struct bnxt_re_ucontext * uctx,u64 mem_offset,enum bnxt_re_mmap_flag mmap_flag,u64 * offset)628 bnxt_re_mmap_entry_insert(struct bnxt_re_ucontext *uctx, u64 mem_offset,
629 enum bnxt_re_mmap_flag mmap_flag, u64 *offset)
630 {
631 struct bnxt_re_user_mmap_entry *entry;
632 int ret;
633
634 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
635 if (!entry)
636 return NULL;
637
638 entry->mem_offset = mem_offset;
639 entry->mmap_flag = mmap_flag;
640 entry->uctx = uctx;
641
642 switch (mmap_flag) {
643 case BNXT_RE_MMAP_SH_PAGE:
644 ret = rdma_user_mmap_entry_insert_exact(&uctx->ib_uctx,
645 &entry->rdma_entry, PAGE_SIZE, 0);
646 break;
647 case BNXT_RE_MMAP_UC_DB:
648 case BNXT_RE_MMAP_WC_DB:
649 case BNXT_RE_MMAP_DBR_BAR:
650 case BNXT_RE_MMAP_DBR_PAGE:
651 case BNXT_RE_MMAP_TOGGLE_PAGE:
652 ret = rdma_user_mmap_entry_insert(&uctx->ib_uctx,
653 &entry->rdma_entry, PAGE_SIZE);
654 break;
655 default:
656 ret = -EINVAL;
657 break;
658 }
659
660 if (ret) {
661 kfree(entry);
662 return NULL;
663 }
664 if (offset)
665 *offset = rdma_user_mmap_get_offset(&entry->rdma_entry);
666
667 return entry;
668 }
669
670 /* Protection Domains */
bnxt_re_dealloc_pd(struct ib_pd * ib_pd,struct ib_udata * udata)671 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata)
672 {
673 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
674 struct bnxt_re_dev *rdev = pd->rdev;
675
676 if (udata) {
677 rdma_user_mmap_entry_remove(pd->pd_db_mmap);
678 pd->pd_db_mmap = NULL;
679 }
680
681 bnxt_re_destroy_fence_mr(pd);
682
683 if (pd->qplib_pd.id) {
684 if (!bnxt_qplib_dealloc_pd(&rdev->qplib_res,
685 &rdev->qplib_res.pd_tbl,
686 &pd->qplib_pd))
687 atomic_dec(&rdev->stats.res.pd_count);
688 }
689 return 0;
690 }
691
bnxt_re_alloc_pd(struct ib_pd * ibpd,struct ib_udata * udata)692 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
693 {
694 struct ib_device *ibdev = ibpd->device;
695 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
696 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context(
697 udata, struct bnxt_re_ucontext, ib_uctx);
698 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd);
699 struct bnxt_re_user_mmap_entry *entry = NULL;
700 u32 active_pds;
701 int rc = 0;
702
703 pd->rdev = rdev;
704 if (bnxt_qplib_alloc_pd(&rdev->qplib_res, &pd->qplib_pd)) {
705 ibdev_err(&rdev->ibdev, "Failed to allocate HW PD");
706 rc = -ENOMEM;
707 goto fail;
708 }
709
710 if (udata) {
711 struct bnxt_re_pd_resp resp = {};
712
713 if (!ucntx->dpi.dbr) {
714 /* Allocate DPI in alloc_pd to avoid failing of
715 * ibv_devinfo and family of application when DPIs
716 * are depleted.
717 */
718 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res,
719 &ucntx->dpi, ucntx, BNXT_QPLIB_DPI_TYPE_UC)) {
720 rc = -ENOMEM;
721 goto dbfail;
722 }
723 }
724
725 resp.pdid = pd->qplib_pd.id;
726 /* Still allow mapping this DBR to the new user PD. */
727 resp.dpi = ucntx->dpi.dpi;
728
729 entry = bnxt_re_mmap_entry_insert(ucntx, (u64)ucntx->dpi.umdbr,
730 BNXT_RE_MMAP_UC_DB, &resp.dbr);
731
732 if (!entry) {
733 rc = -ENOMEM;
734 goto dbfail;
735 }
736
737 pd->pd_db_mmap = &entry->rdma_entry;
738
739 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen));
740 if (rc) {
741 rdma_user_mmap_entry_remove(pd->pd_db_mmap);
742 rc = -EFAULT;
743 goto dbfail;
744 }
745 }
746
747 if (!udata)
748 if (bnxt_re_create_fence_mr(pd))
749 ibdev_warn(&rdev->ibdev,
750 "Failed to create Fence-MR\n");
751 active_pds = atomic_inc_return(&rdev->stats.res.pd_count);
752 if (active_pds > rdev->stats.res.pd_watermark)
753 rdev->stats.res.pd_watermark = active_pds;
754
755 return 0;
756 dbfail:
757 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
758 &pd->qplib_pd);
759 fail:
760 return rc;
761 }
762
763 /* Address Handles */
bnxt_re_destroy_ah(struct ib_ah * ib_ah,u32 flags)764 int bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags)
765 {
766 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
767 struct bnxt_re_dev *rdev = ah->rdev;
768 bool block = true;
769 int rc;
770
771 block = !(flags & RDMA_DESTROY_AH_SLEEPABLE);
772 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah, block);
773 if (BNXT_RE_CHECK_RC(rc)) {
774 if (rc == -ETIMEDOUT)
775 rc = 0;
776 else
777 goto fail;
778 }
779 atomic_dec(&rdev->stats.res.ah_count);
780 fail:
781 return rc;
782 }
783
bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype)784 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype)
785 {
786 u8 nw_type;
787
788 switch (ntype) {
789 case RDMA_NETWORK_IPV4:
790 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
791 break;
792 case RDMA_NETWORK_IPV6:
793 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
794 break;
795 default:
796 nw_type = CMDQ_CREATE_AH_TYPE_V1;
797 break;
798 }
799 return nw_type;
800 }
801
bnxt_re_create_ah(struct ib_ah * ib_ah,struct rdma_ah_init_attr * init_attr,struct ib_udata * udata)802 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_init_attr *init_attr,
803 struct ib_udata *udata)
804 {
805 struct ib_pd *ib_pd = ib_ah->pd;
806 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
807 struct rdma_ah_attr *ah_attr = init_attr->ah_attr;
808 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
809 struct bnxt_re_dev *rdev = pd->rdev;
810 const struct ib_gid_attr *sgid_attr;
811 struct bnxt_re_gid_ctx *ctx;
812 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
813 u32 active_ahs;
814 u8 nw_type;
815 int rc;
816
817 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) {
818 ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set");
819 return -EINVAL;
820 }
821
822 ah->rdev = rdev;
823 ah->qplib_ah.pd = &pd->qplib_pd;
824
825 /* Supply the configuration for the HW */
826 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw,
827 sizeof(union ib_gid));
828 sgid_attr = grh->sgid_attr;
829 /* Get the HW context of the GID. The reference
830 * of GID table entry is already taken by the caller.
831 */
832 ctx = rdma_read_gid_hw_context(sgid_attr);
833 ah->qplib_ah.sgid_index = ctx->idx;
834 ah->qplib_ah.host_sgid_index = grh->sgid_index;
835 ah->qplib_ah.traffic_class = grh->traffic_class;
836 ah->qplib_ah.flow_label = grh->flow_label;
837 ah->qplib_ah.hop_limit = grh->hop_limit;
838 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr);
839
840 /* Get network header type for this GID */
841 nw_type = rdma_gid_attr_network_type(sgid_attr);
842 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type);
843
844 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
845 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah,
846 !(init_attr->flags &
847 RDMA_CREATE_AH_SLEEPABLE));
848 if (rc) {
849 ibdev_err(&rdev->ibdev, "Failed to allocate HW AH");
850 return rc;
851 }
852
853 /* Write AVID to shared page. */
854 if (udata) {
855 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(
856 udata, struct bnxt_re_ucontext, ib_uctx);
857 unsigned long flag;
858 u32 *wrptr;
859
860 spin_lock_irqsave(&uctx->sh_lock, flag);
861 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT);
862 *wrptr = ah->qplib_ah.id;
863 wmb(); /* make sure cache is updated. */
864 spin_unlock_irqrestore(&uctx->sh_lock, flag);
865 }
866 active_ahs = atomic_inc_return(&rdev->stats.res.ah_count);
867 if (active_ahs > rdev->stats.res.ah_watermark)
868 rdev->stats.res.ah_watermark = active_ahs;
869
870 return 0;
871 }
872
bnxt_re_query_ah(struct ib_ah * ib_ah,struct rdma_ah_attr * ah_attr)873 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
874 {
875 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
876
877 ah_attr->type = ib_ah->type;
878 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl);
879 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN);
880 rdma_ah_set_grh(ah_attr, NULL, 0,
881 ah->qplib_ah.host_sgid_index,
882 0, ah->qplib_ah.traffic_class);
883 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data);
884 rdma_ah_set_port_num(ah_attr, 1);
885 rdma_ah_set_static_rate(ah_attr, 0);
886 return 0;
887 }
888
bnxt_re_lock_cqs(struct bnxt_re_qp * qp)889 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp)
890 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock)
891 {
892 unsigned long flags;
893
894 spin_lock_irqsave(&qp->scq->cq_lock, flags);
895 if (qp->rcq != qp->scq)
896 spin_lock(&qp->rcq->cq_lock);
897 else
898 __acquire(&qp->rcq->cq_lock);
899
900 return flags;
901 }
902
bnxt_re_unlock_cqs(struct bnxt_re_qp * qp,unsigned long flags)903 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp,
904 unsigned long flags)
905 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock)
906 {
907 if (qp->rcq != qp->scq)
908 spin_unlock(&qp->rcq->cq_lock);
909 else
910 __release(&qp->rcq->cq_lock);
911 spin_unlock_irqrestore(&qp->scq->cq_lock, flags);
912 }
913
bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp * qp)914 static int bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp)
915 {
916 struct bnxt_re_qp *gsi_sqp;
917 struct bnxt_re_ah *gsi_sah;
918 struct bnxt_re_dev *rdev;
919 int rc;
920
921 rdev = qp->rdev;
922 gsi_sqp = rdev->gsi_ctx.gsi_sqp;
923 gsi_sah = rdev->gsi_ctx.gsi_sah;
924
925 ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n");
926 bnxt_qplib_destroy_ah(&rdev->qplib_res,
927 &gsi_sah->qplib_ah,
928 true);
929 atomic_dec(&rdev->stats.res.ah_count);
930 bnxt_qplib_clean_qp(&qp->qplib_qp);
931
932 ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n");
933 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp);
934 if (rc) {
935 ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed");
936 goto fail;
937 }
938 bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp);
939
940 /* remove from active qp list */
941 mutex_lock(&rdev->qp_lock);
942 list_del(&gsi_sqp->list);
943 mutex_unlock(&rdev->qp_lock);
944 atomic_dec(&rdev->stats.res.qp_count);
945
946 kfree(rdev->gsi_ctx.sqp_tbl);
947 kfree(gsi_sah);
948 kfree(gsi_sqp);
949 rdev->gsi_ctx.gsi_sqp = NULL;
950 rdev->gsi_ctx.gsi_sah = NULL;
951 rdev->gsi_ctx.sqp_tbl = NULL;
952
953 return 0;
954 fail:
955 return rc;
956 }
957
958 /* Queue Pairs */
bnxt_re_destroy_qp(struct ib_qp * ib_qp,struct ib_udata * udata)959 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata)
960 {
961 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
962 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp;
963 struct bnxt_re_dev *rdev = qp->rdev;
964 struct bnxt_qplib_nq *scq_nq = NULL;
965 struct bnxt_qplib_nq *rcq_nq = NULL;
966 unsigned int flags;
967 int rc;
968
969 bnxt_re_debug_rem_qpinfo(rdev, qp);
970
971 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp);
972
973 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
974 if (rc)
975 ibdev_err(&rdev->ibdev, "Failed to destroy HW QP");
976
977 if (rdma_is_kernel_res(&qp->ib_qp.res)) {
978 flags = bnxt_re_lock_cqs(qp);
979 bnxt_qplib_clean_qp(&qp->qplib_qp);
980 bnxt_re_unlock_cqs(qp, flags);
981 }
982
983 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp);
984
985 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp)
986 bnxt_re_destroy_gsi_sqp(qp);
987
988 mutex_lock(&rdev->qp_lock);
989 list_del(&qp->list);
990 mutex_unlock(&rdev->qp_lock);
991 atomic_dec(&rdev->stats.res.qp_count);
992 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_RC)
993 atomic_dec(&rdev->stats.res.rc_qp_count);
994 else if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD)
995 atomic_dec(&rdev->stats.res.ud_qp_count);
996
997 ib_umem_release(qp->rumem);
998 ib_umem_release(qp->sumem);
999
1000 /* Flush all the entries of notification queue associated with
1001 * given qp.
1002 */
1003 scq_nq = qplib_qp->scq->nq;
1004 rcq_nq = qplib_qp->rcq->nq;
1005 bnxt_re_synchronize_nq(scq_nq);
1006 if (scq_nq != rcq_nq)
1007 bnxt_re_synchronize_nq(rcq_nq);
1008
1009 return 0;
1010 }
1011
__from_ib_qp_type(enum ib_qp_type type)1012 static u8 __from_ib_qp_type(enum ib_qp_type type)
1013 {
1014 switch (type) {
1015 case IB_QPT_GSI:
1016 return CMDQ_CREATE_QP1_TYPE_GSI;
1017 case IB_QPT_RC:
1018 return CMDQ_CREATE_QP_TYPE_RC;
1019 case IB_QPT_UD:
1020 return CMDQ_CREATE_QP_TYPE_UD;
1021 default:
1022 return IB_QPT_MAX;
1023 }
1024 }
1025
bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp * qplqp,int rsge,int max)1026 static u16 bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp *qplqp,
1027 int rsge, int max)
1028 {
1029 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC)
1030 rsge = max;
1031 return bnxt_re_get_rwqe_size(rsge);
1032 }
1033
bnxt_re_get_wqe_size(int ilsize,int nsge)1034 static u16 bnxt_re_get_wqe_size(int ilsize, int nsge)
1035 {
1036 u16 wqe_size, calc_ils;
1037
1038 wqe_size = bnxt_re_get_swqe_size(nsge);
1039 if (ilsize) {
1040 calc_ils = sizeof(struct sq_send_hdr) + ilsize;
1041 wqe_size = max_t(u16, calc_ils, wqe_size);
1042 wqe_size = ALIGN(wqe_size, sizeof(struct sq_send_hdr));
1043 }
1044 return wqe_size;
1045 }
1046
bnxt_re_setup_swqe_size(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr)1047 static int bnxt_re_setup_swqe_size(struct bnxt_re_qp *qp,
1048 struct ib_qp_init_attr *init_attr)
1049 {
1050 struct bnxt_qplib_dev_attr *dev_attr;
1051 struct bnxt_qplib_qp *qplqp;
1052 struct bnxt_re_dev *rdev;
1053 struct bnxt_qplib_q *sq;
1054 int align, ilsize;
1055
1056 rdev = qp->rdev;
1057 qplqp = &qp->qplib_qp;
1058 sq = &qplqp->sq;
1059 dev_attr = rdev->dev_attr;
1060
1061 align = sizeof(struct sq_send_hdr);
1062 ilsize = ALIGN(init_attr->cap.max_inline_data, align);
1063
1064 /* For gen p4 and gen p5 fixed wqe compatibility mode
1065 * wqe size is fixed to 128 bytes - ie 6 SGEs
1066 */
1067 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) {
1068 sq->wqe_size = bnxt_re_get_swqe_size(BNXT_STATIC_MAX_SGE);
1069 sq->max_sge = BNXT_STATIC_MAX_SGE;
1070 } else {
1071 sq->wqe_size = bnxt_re_get_wqe_size(ilsize, sq->max_sge);
1072 if (sq->wqe_size > bnxt_re_get_swqe_size(dev_attr->max_qp_sges))
1073 return -EINVAL;
1074 }
1075
1076 if (init_attr->cap.max_inline_data) {
1077 qplqp->max_inline_data = sq->wqe_size -
1078 sizeof(struct sq_send_hdr);
1079 init_attr->cap.max_inline_data = qplqp->max_inline_data;
1080 }
1081
1082 return 0;
1083 }
1084
bnxt_re_init_user_qp(struct bnxt_re_dev * rdev,struct bnxt_re_pd * pd,struct bnxt_re_qp * qp,struct bnxt_re_ucontext * cntx,struct bnxt_re_qp_req * ureq)1085 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd,
1086 struct bnxt_re_qp *qp, struct bnxt_re_ucontext *cntx,
1087 struct bnxt_re_qp_req *ureq)
1088 {
1089 struct bnxt_qplib_qp *qplib_qp;
1090 int bytes = 0, psn_sz;
1091 struct ib_umem *umem;
1092 int psn_nume;
1093
1094 qplib_qp = &qp->qplib_qp;
1095
1096 bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size);
1097 /* Consider mapping PSN search memory only for RC QPs. */
1098 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) {
1099 psn_sz = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ?
1100 sizeof(struct sq_psn_search_ext) :
1101 sizeof(struct sq_psn_search);
1102 if (cntx && bnxt_re_is_var_size_supported(rdev, cntx)) {
1103 psn_nume = ureq->sq_slots;
1104 } else {
1105 psn_nume = (qplib_qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ?
1106 qplib_qp->sq.max_wqe : ((qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size) /
1107 sizeof(struct bnxt_qplib_sge));
1108 }
1109 if (_is_host_msn_table(rdev->qplib_res.dattr->dev_cap_flags2))
1110 psn_nume = roundup_pow_of_two(psn_nume);
1111 bytes += (psn_nume * psn_sz);
1112 }
1113
1114 bytes = PAGE_ALIGN(bytes);
1115 umem = ib_umem_get(&rdev->ibdev, ureq->qpsva, bytes,
1116 IB_ACCESS_LOCAL_WRITE);
1117 if (IS_ERR(umem))
1118 return PTR_ERR(umem);
1119
1120 qp->sumem = umem;
1121 qplib_qp->sq.sg_info.umem = umem;
1122 qplib_qp->sq.sg_info.pgsize = PAGE_SIZE;
1123 qplib_qp->sq.sg_info.pgshft = PAGE_SHIFT;
1124 qplib_qp->qp_handle = ureq->qp_handle;
1125
1126 if (!qp->qplib_qp.srq) {
1127 bytes = (qplib_qp->rq.max_wqe * qplib_qp->rq.wqe_size);
1128 bytes = PAGE_ALIGN(bytes);
1129 umem = ib_umem_get(&rdev->ibdev, ureq->qprva, bytes,
1130 IB_ACCESS_LOCAL_WRITE);
1131 if (IS_ERR(umem))
1132 goto rqfail;
1133 qp->rumem = umem;
1134 qplib_qp->rq.sg_info.umem = umem;
1135 qplib_qp->rq.sg_info.pgsize = PAGE_SIZE;
1136 qplib_qp->rq.sg_info.pgshft = PAGE_SHIFT;
1137 }
1138
1139 qplib_qp->dpi = &cntx->dpi;
1140 return 0;
1141 rqfail:
1142 ib_umem_release(qp->sumem);
1143 qp->sumem = NULL;
1144 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info));
1145
1146 return PTR_ERR(umem);
1147 }
1148
bnxt_re_create_shadow_qp_ah(struct bnxt_re_pd * pd,struct bnxt_qplib_res * qp1_res,struct bnxt_qplib_qp * qp1_qp)1149 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah
1150 (struct bnxt_re_pd *pd,
1151 struct bnxt_qplib_res *qp1_res,
1152 struct bnxt_qplib_qp *qp1_qp)
1153 {
1154 struct bnxt_re_dev *rdev = pd->rdev;
1155 struct bnxt_re_ah *ah;
1156 union ib_gid sgid;
1157 int rc;
1158
1159 ah = kzalloc(sizeof(*ah), GFP_KERNEL);
1160 if (!ah)
1161 return NULL;
1162
1163 ah->rdev = rdev;
1164 ah->qplib_ah.pd = &pd->qplib_pd;
1165
1166 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid);
1167 if (rc)
1168 goto fail;
1169
1170 /* supply the dgid data same as sgid */
1171 memcpy(ah->qplib_ah.dgid.data, &sgid.raw,
1172 sizeof(union ib_gid));
1173 ah->qplib_ah.sgid_index = 0;
1174
1175 ah->qplib_ah.traffic_class = 0;
1176 ah->qplib_ah.flow_label = 0;
1177 ah->qplib_ah.hop_limit = 1;
1178 ah->qplib_ah.sl = 0;
1179 /* Have DMAC same as SMAC */
1180 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr);
1181
1182 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false);
1183 if (rc) {
1184 ibdev_err(&rdev->ibdev,
1185 "Failed to allocate HW AH for Shadow QP");
1186 goto fail;
1187 }
1188 atomic_inc(&rdev->stats.res.ah_count);
1189
1190 return ah;
1191
1192 fail:
1193 kfree(ah);
1194 return NULL;
1195 }
1196
bnxt_re_create_shadow_qp(struct bnxt_re_pd * pd,struct bnxt_qplib_res * qp1_res,struct bnxt_qplib_qp * qp1_qp)1197 static struct bnxt_re_qp *bnxt_re_create_shadow_qp
1198 (struct bnxt_re_pd *pd,
1199 struct bnxt_qplib_res *qp1_res,
1200 struct bnxt_qplib_qp *qp1_qp)
1201 {
1202 struct bnxt_re_dev *rdev = pd->rdev;
1203 struct bnxt_re_qp *qp;
1204 int rc;
1205
1206 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1207 if (!qp)
1208 return NULL;
1209
1210 qp->rdev = rdev;
1211
1212 /* Initialize the shadow QP structure from the QP1 values */
1213 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
1214
1215 qp->qplib_qp.pd = &pd->qplib_pd;
1216 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
1217 qp->qplib_qp.type = IB_QPT_UD;
1218
1219 qp->qplib_qp.max_inline_data = 0;
1220 qp->qplib_qp.sig_type = true;
1221
1222 /* Shadow QP SQ depth should be same as QP1 RQ depth */
1223 qp->qplib_qp.sq.wqe_size = bnxt_re_get_wqe_size(0, 6);
1224 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;
1225 qp->qplib_qp.sq.max_sw_wqe = qp1_qp->rq.max_wqe;
1226 qp->qplib_qp.sq.max_sge = 2;
1227 /* Q full delta can be 1 since it is internal QP */
1228 qp->qplib_qp.sq.q_full_delta = 1;
1229 qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE;
1230 qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT;
1231
1232 qp->qplib_qp.scq = qp1_qp->scq;
1233 qp->qplib_qp.rcq = qp1_qp->rcq;
1234
1235 qp->qplib_qp.rq.wqe_size = bnxt_re_get_rwqe_size(6);
1236 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;
1237 qp->qplib_qp.rq.max_sw_wqe = qp1_qp->rq.max_wqe;
1238 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;
1239 /* Q full delta can be 1 since it is internal QP */
1240 qp->qplib_qp.rq.q_full_delta = 1;
1241 qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE;
1242 qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT;
1243
1244 qp->qplib_qp.mtu = qp1_qp->mtu;
1245
1246 qp->qplib_qp.sq_hdr_buf_size = 0;
1247 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
1248 qp->qplib_qp.dpi = &rdev->dpi_privileged;
1249
1250 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp);
1251 if (rc)
1252 goto fail;
1253
1254 spin_lock_init(&qp->sq_lock);
1255 INIT_LIST_HEAD(&qp->list);
1256 mutex_lock(&rdev->qp_lock);
1257 list_add_tail(&qp->list, &rdev->qp_list);
1258 atomic_inc(&rdev->stats.res.qp_count);
1259 mutex_unlock(&rdev->qp_lock);
1260 return qp;
1261 fail:
1262 kfree(qp);
1263 return NULL;
1264 }
1265
bnxt_re_init_rq_attr(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr,struct bnxt_re_ucontext * uctx)1266 static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp,
1267 struct ib_qp_init_attr *init_attr,
1268 struct bnxt_re_ucontext *uctx)
1269 {
1270 struct bnxt_qplib_dev_attr *dev_attr;
1271 struct bnxt_qplib_qp *qplqp;
1272 struct bnxt_re_dev *rdev;
1273 struct bnxt_qplib_q *rq;
1274 int entries;
1275
1276 rdev = qp->rdev;
1277 qplqp = &qp->qplib_qp;
1278 rq = &qplqp->rq;
1279 dev_attr = rdev->dev_attr;
1280
1281 if (init_attr->srq) {
1282 struct bnxt_re_srq *srq;
1283
1284 srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq);
1285 qplqp->srq = &srq->qplib_srq;
1286 rq->max_wqe = 0;
1287 } else {
1288 rq->max_sge = init_attr->cap.max_recv_sge;
1289 if (rq->max_sge > dev_attr->max_qp_sges)
1290 rq->max_sge = dev_attr->max_qp_sges;
1291 init_attr->cap.max_recv_sge = rq->max_sge;
1292 rq->wqe_size = bnxt_re_setup_rwqe_size(qplqp, rq->max_sge,
1293 dev_attr->max_qp_sges);
1294 /* Allocate 1 more than what's provided so posting max doesn't
1295 * mean empty.
1296 */
1297 entries = bnxt_re_init_depth(init_attr->cap.max_recv_wr + 1, uctx);
1298 rq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1);
1299 rq->max_sw_wqe = rq->max_wqe;
1300 rq->q_full_delta = 0;
1301 rq->sg_info.pgsize = PAGE_SIZE;
1302 rq->sg_info.pgshft = PAGE_SHIFT;
1303 }
1304
1305 return 0;
1306 }
1307
bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp * qp)1308 static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp)
1309 {
1310 struct bnxt_qplib_dev_attr *dev_attr;
1311 struct bnxt_qplib_qp *qplqp;
1312 struct bnxt_re_dev *rdev;
1313
1314 rdev = qp->rdev;
1315 qplqp = &qp->qplib_qp;
1316 dev_attr = rdev->dev_attr;
1317
1318 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) {
1319 qplqp->rq.max_sge = dev_attr->max_qp_sges;
1320 if (qplqp->rq.max_sge > dev_attr->max_qp_sges)
1321 qplqp->rq.max_sge = dev_attr->max_qp_sges;
1322 qplqp->rq.max_sge = 6;
1323 }
1324 }
1325
bnxt_re_init_sq_attr(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr,struct bnxt_re_ucontext * uctx,struct bnxt_re_qp_req * ureq)1326 static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp,
1327 struct ib_qp_init_attr *init_attr,
1328 struct bnxt_re_ucontext *uctx,
1329 struct bnxt_re_qp_req *ureq)
1330 {
1331 struct bnxt_qplib_dev_attr *dev_attr;
1332 struct bnxt_qplib_qp *qplqp;
1333 struct bnxt_re_dev *rdev;
1334 struct bnxt_qplib_q *sq;
1335 int diff = 0;
1336 int entries;
1337 int rc;
1338
1339 rdev = qp->rdev;
1340 qplqp = &qp->qplib_qp;
1341 sq = &qplqp->sq;
1342 dev_attr = rdev->dev_attr;
1343
1344 sq->max_sge = init_attr->cap.max_send_sge;
1345 entries = init_attr->cap.max_send_wr;
1346 if (uctx && qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) {
1347 sq->max_wqe = ureq->sq_slots;
1348 sq->max_sw_wqe = ureq->sq_slots;
1349 sq->wqe_size = sizeof(struct sq_sge);
1350 } else {
1351 if (sq->max_sge > dev_attr->max_qp_sges) {
1352 sq->max_sge = dev_attr->max_qp_sges;
1353 init_attr->cap.max_send_sge = sq->max_sge;
1354 }
1355
1356 rc = bnxt_re_setup_swqe_size(qp, init_attr);
1357 if (rc)
1358 return rc;
1359
1360 /* Allocate 128 + 1 more than what's provided */
1361 diff = (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) ?
1362 0 : BNXT_QPLIB_RESERVED_QP_WRS;
1363 entries = bnxt_re_init_depth(entries + diff + 1, uctx);
1364 sq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + diff + 1);
1365 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE)
1366 sq->max_sw_wqe = bnxt_qplib_get_depth(sq, qplqp->wqe_mode, true);
1367 else
1368 sq->max_sw_wqe = sq->max_wqe;
1369
1370 }
1371 sq->q_full_delta = diff + 1;
1372 /*
1373 * Reserving one slot for Phantom WQE. Application can
1374 * post one extra entry in this case. But allowing this to avoid
1375 * unexpected Queue full condition
1376 */
1377 qplqp->sq.q_full_delta -= 1;
1378 qplqp->sq.sg_info.pgsize = PAGE_SIZE;
1379 qplqp->sq.sg_info.pgshft = PAGE_SHIFT;
1380
1381 return 0;
1382 }
1383
bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr,struct bnxt_re_ucontext * uctx)1384 static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp,
1385 struct ib_qp_init_attr *init_attr,
1386 struct bnxt_re_ucontext *uctx)
1387 {
1388 struct bnxt_qplib_dev_attr *dev_attr;
1389 struct bnxt_qplib_qp *qplqp;
1390 struct bnxt_re_dev *rdev;
1391 int entries;
1392
1393 rdev = qp->rdev;
1394 qplqp = &qp->qplib_qp;
1395 dev_attr = rdev->dev_attr;
1396
1397 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) {
1398 entries = bnxt_re_init_depth(init_attr->cap.max_send_wr + 1, uctx);
1399 qplqp->sq.max_wqe = min_t(u32, entries,
1400 dev_attr->max_qp_wqes + 1);
1401 qplqp->sq.q_full_delta = qplqp->sq.max_wqe -
1402 init_attr->cap.max_send_wr;
1403 qplqp->sq.max_sge++; /* Need one extra sge to put UD header */
1404 if (qplqp->sq.max_sge > dev_attr->max_qp_sges)
1405 qplqp->sq.max_sge = dev_attr->max_qp_sges;
1406 }
1407 }
1408
bnxt_re_init_qp_type(struct bnxt_re_dev * rdev,struct ib_qp_init_attr * init_attr)1409 static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev,
1410 struct ib_qp_init_attr *init_attr)
1411 {
1412 struct bnxt_qplib_chip_ctx *chip_ctx;
1413 int qptype;
1414
1415 chip_ctx = rdev->chip_ctx;
1416
1417 qptype = __from_ib_qp_type(init_attr->qp_type);
1418 if (qptype == IB_QPT_MAX) {
1419 ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype);
1420 qptype = -EOPNOTSUPP;
1421 goto out;
1422 }
1423
1424 if (bnxt_qplib_is_chip_gen_p5_p7(chip_ctx) &&
1425 init_attr->qp_type == IB_QPT_GSI)
1426 qptype = CMDQ_CREATE_QP_TYPE_GSI;
1427 out:
1428 return qptype;
1429 }
1430
bnxt_re_init_qp_attr(struct bnxt_re_qp * qp,struct bnxt_re_pd * pd,struct ib_qp_init_attr * init_attr,struct bnxt_re_ucontext * uctx,struct bnxt_re_qp_req * ureq)1431 static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1432 struct ib_qp_init_attr *init_attr,
1433 struct bnxt_re_ucontext *uctx,
1434 struct bnxt_re_qp_req *ureq)
1435 {
1436 struct bnxt_qplib_dev_attr *dev_attr;
1437 struct bnxt_qplib_qp *qplqp;
1438 struct bnxt_re_dev *rdev;
1439 struct bnxt_re_cq *cq;
1440 int rc = 0, qptype;
1441
1442 rdev = qp->rdev;
1443 qplqp = &qp->qplib_qp;
1444 dev_attr = rdev->dev_attr;
1445
1446 /* Setup misc params */
1447 ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr);
1448 qplqp->pd = &pd->qplib_pd;
1449 qplqp->qp_handle = (u64)qplqp;
1450 qplqp->max_inline_data = init_attr->cap.max_inline_data;
1451 qplqp->sig_type = init_attr->sq_sig_type == IB_SIGNAL_ALL_WR;
1452 qptype = bnxt_re_init_qp_type(rdev, init_attr);
1453 if (qptype < 0) {
1454 rc = qptype;
1455 goto out;
1456 }
1457 qplqp->type = (u8)qptype;
1458 qplqp->wqe_mode = bnxt_re_is_var_size_supported(rdev, uctx);
1459 if (init_attr->qp_type == IB_QPT_RC) {
1460 qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom;
1461 qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;
1462 }
1463 qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1464 qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */
1465 if (init_attr->create_flags) {
1466 ibdev_dbg(&rdev->ibdev,
1467 "QP create flags 0x%x not supported",
1468 init_attr->create_flags);
1469 return -EOPNOTSUPP;
1470 }
1471
1472 /* Setup CQs */
1473 if (init_attr->send_cq) {
1474 cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq);
1475 qplqp->scq = &cq->qplib_cq;
1476 qp->scq = cq;
1477 }
1478
1479 if (init_attr->recv_cq) {
1480 cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq);
1481 qplqp->rcq = &cq->qplib_cq;
1482 qp->rcq = cq;
1483 }
1484
1485 /* Setup RQ/SRQ */
1486 rc = bnxt_re_init_rq_attr(qp, init_attr, uctx);
1487 if (rc)
1488 goto out;
1489 if (init_attr->qp_type == IB_QPT_GSI)
1490 bnxt_re_adjust_gsi_rq_attr(qp);
1491
1492 /* Setup SQ */
1493 rc = bnxt_re_init_sq_attr(qp, init_attr, uctx, ureq);
1494 if (rc)
1495 goto out;
1496 if (init_attr->qp_type == IB_QPT_GSI)
1497 bnxt_re_adjust_gsi_sq_attr(qp, init_attr, uctx);
1498
1499 if (uctx) /* This will update DPI and qp_handle */
1500 rc = bnxt_re_init_user_qp(rdev, pd, qp, uctx, ureq);
1501 out:
1502 return rc;
1503 }
1504
bnxt_re_create_shadow_gsi(struct bnxt_re_qp * qp,struct bnxt_re_pd * pd)1505 static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp,
1506 struct bnxt_re_pd *pd)
1507 {
1508 struct bnxt_re_sqp_entries *sqp_tbl;
1509 struct bnxt_re_dev *rdev;
1510 struct bnxt_re_qp *sqp;
1511 struct bnxt_re_ah *sah;
1512 int rc = 0;
1513
1514 rdev = qp->rdev;
1515 /* Create a shadow QP to handle the QP1 traffic */
1516 sqp_tbl = kcalloc(BNXT_RE_MAX_GSI_SQP_ENTRIES, sizeof(*sqp_tbl),
1517 GFP_KERNEL);
1518 if (!sqp_tbl)
1519 return -ENOMEM;
1520 rdev->gsi_ctx.sqp_tbl = sqp_tbl;
1521
1522 sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp);
1523 if (!sqp) {
1524 rc = -ENODEV;
1525 ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1");
1526 goto out;
1527 }
1528 rdev->gsi_ctx.gsi_sqp = sqp;
1529
1530 sqp->rcq = qp->rcq;
1531 sqp->scq = qp->scq;
1532 sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res,
1533 &qp->qplib_qp);
1534 if (!sah) {
1535 bnxt_qplib_destroy_qp(&rdev->qplib_res,
1536 &sqp->qplib_qp);
1537 rc = -ENODEV;
1538 ibdev_err(&rdev->ibdev,
1539 "Failed to create AH entry for ShadowQP");
1540 goto out;
1541 }
1542 rdev->gsi_ctx.gsi_sah = sah;
1543
1544 return 0;
1545 out:
1546 kfree(sqp_tbl);
1547 return rc;
1548 }
1549
bnxt_re_create_gsi_qp(struct bnxt_re_qp * qp,struct bnxt_re_pd * pd,struct ib_qp_init_attr * init_attr)1550 static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1551 struct ib_qp_init_attr *init_attr)
1552 {
1553 struct bnxt_re_dev *rdev;
1554 struct bnxt_qplib_qp *qplqp;
1555 int rc;
1556
1557 rdev = qp->rdev;
1558 qplqp = &qp->qplib_qp;
1559
1560 qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
1561 qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2;
1562
1563 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp);
1564 if (rc) {
1565 ibdev_err(&rdev->ibdev, "create HW QP1 failed!");
1566 goto out;
1567 }
1568
1569 rc = bnxt_re_create_shadow_gsi(qp, pd);
1570 out:
1571 return rc;
1572 }
1573
bnxt_re_test_qp_limits(struct bnxt_re_dev * rdev,struct ib_qp_init_attr * init_attr,struct bnxt_qplib_dev_attr * dev_attr)1574 static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev,
1575 struct ib_qp_init_attr *init_attr,
1576 struct bnxt_qplib_dev_attr *dev_attr)
1577 {
1578 bool rc = true;
1579
1580 if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes ||
1581 init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes ||
1582 init_attr->cap.max_send_sge > dev_attr->max_qp_sges ||
1583 init_attr->cap.max_recv_sge > dev_attr->max_qp_sges ||
1584 init_attr->cap.max_inline_data > dev_attr->max_inline_data) {
1585 ibdev_err(&rdev->ibdev,
1586 "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x",
1587 init_attr->cap.max_send_wr, dev_attr->max_qp_wqes,
1588 init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes,
1589 init_attr->cap.max_send_sge, dev_attr->max_qp_sges,
1590 init_attr->cap.max_recv_sge, dev_attr->max_qp_sges,
1591 init_attr->cap.max_inline_data,
1592 dev_attr->max_inline_data);
1593 rc = false;
1594 }
1595 return rc;
1596 }
1597
bnxt_re_create_qp(struct ib_qp * ib_qp,struct ib_qp_init_attr * qp_init_attr,struct ib_udata * udata)1598 int bnxt_re_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *qp_init_attr,
1599 struct ib_udata *udata)
1600 {
1601 struct bnxt_qplib_dev_attr *dev_attr;
1602 struct bnxt_re_ucontext *uctx;
1603 struct bnxt_re_qp_req ureq;
1604 struct bnxt_re_dev *rdev;
1605 struct bnxt_re_pd *pd;
1606 struct bnxt_re_qp *qp;
1607 struct ib_pd *ib_pd;
1608 u32 active_qps;
1609 int rc;
1610
1611 ib_pd = ib_qp->pd;
1612 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1613 rdev = pd->rdev;
1614 dev_attr = rdev->dev_attr;
1615 qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1616
1617 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
1618 if (udata)
1619 if (ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq))))
1620 return -EFAULT;
1621
1622 rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr);
1623 if (!rc) {
1624 rc = -EINVAL;
1625 goto fail;
1626 }
1627
1628 qp->rdev = rdev;
1629 rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, uctx, &ureq);
1630 if (rc)
1631 goto fail;
1632
1633 if (qp_init_attr->qp_type == IB_QPT_GSI &&
1634 !(bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))) {
1635 rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr);
1636 if (rc == -ENODEV)
1637 goto qp_destroy;
1638 if (rc)
1639 goto fail;
1640 } else {
1641 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp);
1642 if (rc) {
1643 ibdev_err(&rdev->ibdev, "Failed to create HW QP");
1644 goto free_umem;
1645 }
1646 if (udata) {
1647 struct bnxt_re_qp_resp resp;
1648
1649 resp.qpid = qp->qplib_qp.id;
1650 resp.rsvd = 0;
1651 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1652 if (rc) {
1653 ibdev_err(&rdev->ibdev, "Failed to copy QP udata");
1654 goto qp_destroy;
1655 }
1656 }
1657 }
1658
1659 qp->ib_qp.qp_num = qp->qplib_qp.id;
1660 if (qp_init_attr->qp_type == IB_QPT_GSI)
1661 rdev->gsi_ctx.gsi_qp = qp;
1662 spin_lock_init(&qp->sq_lock);
1663 spin_lock_init(&qp->rq_lock);
1664 INIT_LIST_HEAD(&qp->list);
1665 mutex_lock(&rdev->qp_lock);
1666 list_add_tail(&qp->list, &rdev->qp_list);
1667 mutex_unlock(&rdev->qp_lock);
1668 active_qps = atomic_inc_return(&rdev->stats.res.qp_count);
1669 if (active_qps > rdev->stats.res.qp_watermark)
1670 rdev->stats.res.qp_watermark = active_qps;
1671 if (qp_init_attr->qp_type == IB_QPT_RC) {
1672 active_qps = atomic_inc_return(&rdev->stats.res.rc_qp_count);
1673 if (active_qps > rdev->stats.res.rc_qp_watermark)
1674 rdev->stats.res.rc_qp_watermark = active_qps;
1675 } else if (qp_init_attr->qp_type == IB_QPT_UD) {
1676 active_qps = atomic_inc_return(&rdev->stats.res.ud_qp_count);
1677 if (active_qps > rdev->stats.res.ud_qp_watermark)
1678 rdev->stats.res.ud_qp_watermark = active_qps;
1679 }
1680 bnxt_re_debug_add_qpinfo(rdev, qp);
1681
1682 return 0;
1683 qp_destroy:
1684 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
1685 free_umem:
1686 ib_umem_release(qp->rumem);
1687 ib_umem_release(qp->sumem);
1688 fail:
1689 return rc;
1690 }
1691
__from_ib_qp_state(enum ib_qp_state state)1692 static u8 __from_ib_qp_state(enum ib_qp_state state)
1693 {
1694 switch (state) {
1695 case IB_QPS_RESET:
1696 return CMDQ_MODIFY_QP_NEW_STATE_RESET;
1697 case IB_QPS_INIT:
1698 return CMDQ_MODIFY_QP_NEW_STATE_INIT;
1699 case IB_QPS_RTR:
1700 return CMDQ_MODIFY_QP_NEW_STATE_RTR;
1701 case IB_QPS_RTS:
1702 return CMDQ_MODIFY_QP_NEW_STATE_RTS;
1703 case IB_QPS_SQD:
1704 return CMDQ_MODIFY_QP_NEW_STATE_SQD;
1705 case IB_QPS_SQE:
1706 return CMDQ_MODIFY_QP_NEW_STATE_SQE;
1707 case IB_QPS_ERR:
1708 default:
1709 return CMDQ_MODIFY_QP_NEW_STATE_ERR;
1710 }
1711 }
1712
__to_ib_qp_state(u8 state)1713 static enum ib_qp_state __to_ib_qp_state(u8 state)
1714 {
1715 switch (state) {
1716 case CMDQ_MODIFY_QP_NEW_STATE_RESET:
1717 return IB_QPS_RESET;
1718 case CMDQ_MODIFY_QP_NEW_STATE_INIT:
1719 return IB_QPS_INIT;
1720 case CMDQ_MODIFY_QP_NEW_STATE_RTR:
1721 return IB_QPS_RTR;
1722 case CMDQ_MODIFY_QP_NEW_STATE_RTS:
1723 return IB_QPS_RTS;
1724 case CMDQ_MODIFY_QP_NEW_STATE_SQD:
1725 return IB_QPS_SQD;
1726 case CMDQ_MODIFY_QP_NEW_STATE_SQE:
1727 return IB_QPS_SQE;
1728 case CMDQ_MODIFY_QP_NEW_STATE_ERR:
1729 default:
1730 return IB_QPS_ERR;
1731 }
1732 }
1733
__from_ib_mtu(enum ib_mtu mtu)1734 static u32 __from_ib_mtu(enum ib_mtu mtu)
1735 {
1736 switch (mtu) {
1737 case IB_MTU_256:
1738 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256;
1739 case IB_MTU_512:
1740 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512;
1741 case IB_MTU_1024:
1742 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024;
1743 case IB_MTU_2048:
1744 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1745 case IB_MTU_4096:
1746 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096;
1747 default:
1748 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1749 }
1750 }
1751
__to_ib_mtu(u32 mtu)1752 static enum ib_mtu __to_ib_mtu(u32 mtu)
1753 {
1754 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) {
1755 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256:
1756 return IB_MTU_256;
1757 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512:
1758 return IB_MTU_512;
1759 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024:
1760 return IB_MTU_1024;
1761 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048:
1762 return IB_MTU_2048;
1763 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096:
1764 return IB_MTU_4096;
1765 default:
1766 return IB_MTU_2048;
1767 }
1768 }
1769
1770 /* Shared Receive Queues */
bnxt_re_destroy_srq(struct ib_srq * ib_srq,struct ib_udata * udata)1771 int bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata)
1772 {
1773 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1774 ib_srq);
1775 struct bnxt_re_dev *rdev = srq->rdev;
1776 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1777
1778 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) {
1779 free_page((unsigned long)srq->uctx_srq_page);
1780 hash_del(&srq->hash_entry);
1781 }
1782 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq);
1783 ib_umem_release(srq->umem);
1784 atomic_dec(&rdev->stats.res.srq_count);
1785 return 0;
1786 }
1787
bnxt_re_init_user_srq(struct bnxt_re_dev * rdev,struct bnxt_re_pd * pd,struct bnxt_re_srq * srq,struct ib_udata * udata)1788 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev,
1789 struct bnxt_re_pd *pd,
1790 struct bnxt_re_srq *srq,
1791 struct ib_udata *udata)
1792 {
1793 struct bnxt_re_srq_req ureq;
1794 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1795 struct ib_umem *umem;
1796 int bytes = 0;
1797 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context(
1798 udata, struct bnxt_re_ucontext, ib_uctx);
1799
1800 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
1801 return -EFAULT;
1802
1803 bytes = (qplib_srq->max_wqe * qplib_srq->wqe_size);
1804 bytes = PAGE_ALIGN(bytes);
1805 umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes,
1806 IB_ACCESS_LOCAL_WRITE);
1807 if (IS_ERR(umem))
1808 return PTR_ERR(umem);
1809
1810 srq->umem = umem;
1811 qplib_srq->sg_info.umem = umem;
1812 qplib_srq->sg_info.pgsize = PAGE_SIZE;
1813 qplib_srq->sg_info.pgshft = PAGE_SHIFT;
1814 qplib_srq->srq_handle = ureq.srq_handle;
1815 qplib_srq->dpi = &cntx->dpi;
1816
1817 return 0;
1818 }
1819
bnxt_re_create_srq(struct ib_srq * ib_srq,struct ib_srq_init_attr * srq_init_attr,struct ib_udata * udata)1820 int bnxt_re_create_srq(struct ib_srq *ib_srq,
1821 struct ib_srq_init_attr *srq_init_attr,
1822 struct ib_udata *udata)
1823 {
1824 struct bnxt_qplib_dev_attr *dev_attr;
1825 struct bnxt_re_ucontext *uctx;
1826 struct bnxt_re_dev *rdev;
1827 struct bnxt_re_srq *srq;
1828 struct bnxt_re_pd *pd;
1829 struct ib_pd *ib_pd;
1830 u32 active_srqs;
1831 int rc, entries;
1832
1833 ib_pd = ib_srq->pd;
1834 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1835 rdev = pd->rdev;
1836 dev_attr = rdev->dev_attr;
1837 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq);
1838
1839 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) {
1840 ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded");
1841 rc = -EINVAL;
1842 goto exit;
1843 }
1844
1845 if (srq_init_attr->srq_type != IB_SRQT_BASIC) {
1846 rc = -EOPNOTSUPP;
1847 goto exit;
1848 }
1849
1850 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
1851 srq->rdev = rdev;
1852 srq->qplib_srq.pd = &pd->qplib_pd;
1853 srq->qplib_srq.dpi = &rdev->dpi_privileged;
1854 /* Allocate 1 more than what's provided so posting max doesn't
1855 * mean empty
1856 */
1857 entries = bnxt_re_init_depth(srq_init_attr->attr.max_wr + 1, uctx);
1858 if (entries > dev_attr->max_srq_wqes + 1)
1859 entries = dev_attr->max_srq_wqes + 1;
1860 srq->qplib_srq.max_wqe = entries;
1861
1862 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge;
1863 /* 128 byte wqe size for SRQ . So use max sges */
1864 srq->qplib_srq.wqe_size = bnxt_re_get_rwqe_size(dev_attr->max_srq_sges);
1865 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit;
1866 srq->srq_limit = srq_init_attr->attr.srq_limit;
1867 srq->qplib_srq.eventq_hw_ring_id = rdev->nqr->nq[0].ring_id;
1868 srq->qplib_srq.sg_info.pgsize = PAGE_SIZE;
1869 srq->qplib_srq.sg_info.pgshft = PAGE_SHIFT;
1870
1871 if (udata) {
1872 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata);
1873 if (rc)
1874 goto fail;
1875 }
1876
1877 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq);
1878 if (rc) {
1879 ibdev_err(&rdev->ibdev, "Create HW SRQ failed!");
1880 goto fail;
1881 }
1882
1883 if (udata) {
1884 struct bnxt_re_srq_resp resp = {};
1885
1886 resp.srqid = srq->qplib_srq.id;
1887 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) {
1888 hash_add(rdev->srq_hash, &srq->hash_entry, srq->qplib_srq.id);
1889 srq->uctx_srq_page = (void *)get_zeroed_page(GFP_KERNEL);
1890 if (!srq->uctx_srq_page) {
1891 rc = -ENOMEM;
1892 goto fail;
1893 }
1894 resp.comp_mask |= BNXT_RE_SRQ_TOGGLE_PAGE_SUPPORT;
1895 }
1896 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1897 if (rc) {
1898 ibdev_err(&rdev->ibdev, "SRQ copy to udata failed!");
1899 bnxt_qplib_destroy_srq(&rdev->qplib_res,
1900 &srq->qplib_srq);
1901 goto fail;
1902 }
1903 }
1904 active_srqs = atomic_inc_return(&rdev->stats.res.srq_count);
1905 if (active_srqs > rdev->stats.res.srq_watermark)
1906 rdev->stats.res.srq_watermark = active_srqs;
1907 spin_lock_init(&srq->lock);
1908
1909 return 0;
1910
1911 fail:
1912 ib_umem_release(srq->umem);
1913 exit:
1914 return rc;
1915 }
1916
bnxt_re_modify_srq(struct ib_srq * ib_srq,struct ib_srq_attr * srq_attr,enum ib_srq_attr_mask srq_attr_mask,struct ib_udata * udata)1917 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr,
1918 enum ib_srq_attr_mask srq_attr_mask,
1919 struct ib_udata *udata)
1920 {
1921 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1922 ib_srq);
1923 struct bnxt_re_dev *rdev = srq->rdev;
1924
1925 switch (srq_attr_mask) {
1926 case IB_SRQ_MAX_WR:
1927 /* SRQ resize is not supported */
1928 return -EINVAL;
1929 case IB_SRQ_LIMIT:
1930 /* Change the SRQ threshold */
1931 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe)
1932 return -EINVAL;
1933
1934 srq->qplib_srq.threshold = srq_attr->srq_limit;
1935 bnxt_qplib_srq_arm_db(&srq->qplib_srq.dbinfo, srq->qplib_srq.threshold);
1936
1937 /* On success, update the shadow */
1938 srq->srq_limit = srq_attr->srq_limit;
1939 /* No need to Build and send response back to udata */
1940 return 0;
1941 default:
1942 ibdev_err(&rdev->ibdev,
1943 "Unsupported srq_attr_mask 0x%x", srq_attr_mask);
1944 return -EINVAL;
1945 }
1946 }
1947
bnxt_re_query_srq(struct ib_srq * ib_srq,struct ib_srq_attr * srq_attr)1948 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr)
1949 {
1950 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1951 ib_srq);
1952 struct bnxt_re_srq tsrq;
1953 struct bnxt_re_dev *rdev = srq->rdev;
1954 int rc;
1955
1956 /* Get live SRQ attr */
1957 tsrq.qplib_srq.id = srq->qplib_srq.id;
1958 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq);
1959 if (rc) {
1960 ibdev_err(&rdev->ibdev, "Query HW SRQ failed!");
1961 return rc;
1962 }
1963 srq_attr->max_wr = srq->qplib_srq.max_wqe;
1964 srq_attr->max_sge = srq->qplib_srq.max_sge;
1965 srq_attr->srq_limit = tsrq.qplib_srq.threshold;
1966
1967 return 0;
1968 }
1969
bnxt_re_post_srq_recv(struct ib_srq * ib_srq,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)1970 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr,
1971 const struct ib_recv_wr **bad_wr)
1972 {
1973 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1974 ib_srq);
1975 struct bnxt_qplib_swqe wqe;
1976 unsigned long flags;
1977 int rc = 0;
1978
1979 spin_lock_irqsave(&srq->lock, flags);
1980 while (wr) {
1981 /* Transcribe each ib_recv_wr to qplib_swqe */
1982 wqe.num_sge = wr->num_sge;
1983 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
1984 wqe.wr_id = wr->wr_id;
1985 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
1986
1987 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe);
1988 if (rc) {
1989 *bad_wr = wr;
1990 break;
1991 }
1992 wr = wr->next;
1993 }
1994 spin_unlock_irqrestore(&srq->lock, flags);
1995
1996 return rc;
1997 }
bnxt_re_modify_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp1_qp,int qp_attr_mask)1998 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,
1999 struct bnxt_re_qp *qp1_qp,
2000 int qp_attr_mask)
2001 {
2002 struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp;
2003 int rc;
2004
2005 if (qp_attr_mask & IB_QP_STATE) {
2006 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
2007 qp->qplib_qp.state = qp1_qp->qplib_qp.state;
2008 }
2009 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
2010 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
2011 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index;
2012 }
2013
2014 if (qp_attr_mask & IB_QP_QKEY) {
2015 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
2016 /* Using a Random QKEY */
2017 qp->qplib_qp.qkey = 0x81818181;
2018 }
2019 if (qp_attr_mask & IB_QP_SQ_PSN) {
2020 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
2021 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn;
2022 }
2023
2024 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
2025 if (rc)
2026 ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1");
2027 return rc;
2028 }
2029
bnxt_re_modify_qp(struct ib_qp * ib_qp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_udata * udata)2030 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
2031 int qp_attr_mask, struct ib_udata *udata)
2032 {
2033 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2034 struct bnxt_re_dev *rdev = qp->rdev;
2035 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr;
2036 enum ib_qp_state curr_qp_state, new_qp_state;
2037 int rc, entries;
2038 unsigned int flags;
2039 u8 nw_type;
2040
2041 if (qp_attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
2042 return -EOPNOTSUPP;
2043
2044 qp->qplib_qp.modify_flags = 0;
2045 if (qp_attr_mask & IB_QP_STATE) {
2046 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state);
2047 new_qp_state = qp_attr->qp_state;
2048 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state,
2049 ib_qp->qp_type, qp_attr_mask)) {
2050 ibdev_err(&rdev->ibdev,
2051 "Invalid attribute mask: %#x specified ",
2052 qp_attr_mask);
2053 ibdev_err(&rdev->ibdev,
2054 "for qpn: %#x type: %#x",
2055 ib_qp->qp_num, ib_qp->qp_type);
2056 ibdev_err(&rdev->ibdev,
2057 "curr_qp_state=0x%x, new_qp_state=0x%x\n",
2058 curr_qp_state, new_qp_state);
2059 return -EINVAL;
2060 }
2061 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
2062 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state);
2063
2064 if (!qp->sumem &&
2065 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {
2066 ibdev_dbg(&rdev->ibdev,
2067 "Move QP = %p to flush list\n", qp);
2068 flags = bnxt_re_lock_cqs(qp);
2069 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
2070 bnxt_re_unlock_cqs(qp, flags);
2071 }
2072 if (!qp->sumem &&
2073 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) {
2074 ibdev_dbg(&rdev->ibdev,
2075 "Move QP = %p out of flush list\n", qp);
2076 flags = bnxt_re_lock_cqs(qp);
2077 bnxt_qplib_clean_qp(&qp->qplib_qp);
2078 bnxt_re_unlock_cqs(qp, flags);
2079 }
2080 }
2081 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
2082 qp->qplib_qp.modify_flags |=
2083 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY;
2084 qp->qplib_qp.en_sqd_async_notify = true;
2085 }
2086 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
2087 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS;
2088 qp->qplib_qp.access =
2089 __qp_access_flags_from_ib(qp->qplib_qp.cctx,
2090 qp_attr->qp_access_flags);
2091 /* LOCAL_WRITE access must be set to allow RC receive */
2092 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE;
2093 }
2094 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
2095 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
2096 qp->qplib_qp.pkey_index = qp_attr->pkey_index;
2097 }
2098 if (qp_attr_mask & IB_QP_QKEY) {
2099 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
2100 qp->qplib_qp.qkey = qp_attr->qkey;
2101 }
2102 if (qp_attr_mask & IB_QP_AV) {
2103 const struct ib_global_route *grh =
2104 rdma_ah_read_grh(&qp_attr->ah_attr);
2105 const struct ib_gid_attr *sgid_attr;
2106 struct bnxt_re_gid_ctx *ctx;
2107
2108 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID |
2109 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL |
2110 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX |
2111 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT |
2112 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS |
2113 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC |
2114 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID;
2115 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw,
2116 sizeof(qp->qplib_qp.ah.dgid.data));
2117 qp->qplib_qp.ah.flow_label = grh->flow_label;
2118 sgid_attr = grh->sgid_attr;
2119 /* Get the HW context of the GID. The reference
2120 * of GID table entry is already taken by the caller.
2121 */
2122 ctx = rdma_read_gid_hw_context(sgid_attr);
2123 qp->qplib_qp.ah.sgid_index = ctx->idx;
2124 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index;
2125 qp->qplib_qp.ah.hop_limit = grh->hop_limit;
2126 qp->qplib_qp.ah.traffic_class = grh->traffic_class >> 2;
2127 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr);
2128 ether_addr_copy(qp->qplib_qp.ah.dmac,
2129 qp_attr->ah_attr.roce.dmac);
2130
2131 rc = rdma_read_gid_l2_fields(sgid_attr, NULL,
2132 &qp->qplib_qp.smac[0]);
2133 if (rc)
2134 return rc;
2135
2136 nw_type = rdma_gid_attr_network_type(sgid_attr);
2137 switch (nw_type) {
2138 case RDMA_NETWORK_IPV4:
2139 qp->qplib_qp.nw_type =
2140 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4;
2141 break;
2142 case RDMA_NETWORK_IPV6:
2143 qp->qplib_qp.nw_type =
2144 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6;
2145 break;
2146 default:
2147 qp->qplib_qp.nw_type =
2148 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1;
2149 break;
2150 }
2151 }
2152
2153 if (qp_attr->qp_state == IB_QPS_RTR) {
2154 enum ib_mtu qpmtu;
2155
2156 qpmtu = iboe_get_mtu(rdev->netdev->mtu);
2157 if (qp_attr_mask & IB_QP_PATH_MTU) {
2158 if (ib_mtu_enum_to_int(qp_attr->path_mtu) >
2159 ib_mtu_enum_to_int(qpmtu))
2160 return -EINVAL;
2161 qpmtu = qp_attr->path_mtu;
2162 }
2163
2164 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
2165 qp->qplib_qp.path_mtu = __from_ib_mtu(qpmtu);
2166 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qpmtu);
2167 }
2168
2169 if (qp_attr_mask & IB_QP_TIMEOUT) {
2170 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT;
2171 qp->qplib_qp.timeout = qp_attr->timeout;
2172 }
2173 if (qp_attr_mask & IB_QP_RETRY_CNT) {
2174 qp->qplib_qp.modify_flags |=
2175 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT;
2176 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt;
2177 }
2178 if (qp_attr_mask & IB_QP_RNR_RETRY) {
2179 qp->qplib_qp.modify_flags |=
2180 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY;
2181 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry;
2182 }
2183 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) {
2184 qp->qplib_qp.modify_flags |=
2185 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER;
2186 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer;
2187 }
2188 if (qp_attr_mask & IB_QP_RQ_PSN) {
2189 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN;
2190 qp->qplib_qp.rq.psn = qp_attr->rq_psn;
2191 }
2192 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2193 qp->qplib_qp.modify_flags |=
2194 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC;
2195 /* Cap the max_rd_atomic to device max */
2196 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic,
2197 dev_attr->max_qp_rd_atom);
2198 }
2199 if (qp_attr_mask & IB_QP_SQ_PSN) {
2200 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
2201 qp->qplib_qp.sq.psn = qp_attr->sq_psn;
2202 }
2203 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2204 if (qp_attr->max_dest_rd_atomic >
2205 dev_attr->max_qp_init_rd_atom) {
2206 ibdev_err(&rdev->ibdev,
2207 "max_dest_rd_atomic requested%d is > dev_max%d",
2208 qp_attr->max_dest_rd_atomic,
2209 dev_attr->max_qp_init_rd_atom);
2210 return -EINVAL;
2211 }
2212
2213 qp->qplib_qp.modify_flags |=
2214 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC;
2215 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic;
2216 }
2217 if (qp_attr_mask & IB_QP_CAP) {
2218 struct bnxt_re_ucontext *uctx =
2219 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
2220
2221 qp->qplib_qp.modify_flags |=
2222 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |
2223 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |
2224 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE |
2225 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE |
2226 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA;
2227 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) ||
2228 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) ||
2229 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) ||
2230 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) ||
2231 (qp_attr->cap.max_inline_data >=
2232 dev_attr->max_inline_data)) {
2233 ibdev_err(&rdev->ibdev,
2234 "Create QP failed - max exceeded");
2235 return -EINVAL;
2236 }
2237 entries = bnxt_re_init_depth(qp_attr->cap.max_send_wr, uctx);
2238 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
2239 dev_attr->max_qp_wqes + 1);
2240 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
2241 qp_attr->cap.max_send_wr;
2242 /*
2243 * Reserving one slot for Phantom WQE. Some application can
2244 * post one extra entry in this case. Allowing this to avoid
2245 * unexpected Queue full condition
2246 */
2247 qp->qplib_qp.sq.q_full_delta -= 1;
2248 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;
2249 if (qp->qplib_qp.rq.max_wqe) {
2250 entries = bnxt_re_init_depth(qp_attr->cap.max_recv_wr, uctx);
2251 qp->qplib_qp.rq.max_wqe =
2252 min_t(u32, entries, dev_attr->max_qp_wqes + 1);
2253 qp->qplib_qp.rq.max_sw_wqe = qp->qplib_qp.rq.max_wqe;
2254 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
2255 qp_attr->cap.max_recv_wr;
2256 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;
2257 } else {
2258 /* SRQ was used prior, just ignore the RQ caps */
2259 }
2260 }
2261 if (qp_attr_mask & IB_QP_DEST_QPN) {
2262 qp->qplib_qp.modify_flags |=
2263 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID;
2264 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num;
2265 }
2266 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
2267 if (rc) {
2268 ibdev_err(&rdev->ibdev, "Failed to modify HW QP");
2269 return rc;
2270 }
2271 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp)
2272 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask);
2273 return rc;
2274 }
2275
bnxt_re_query_qp(struct ib_qp * ib_qp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)2276 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
2277 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
2278 {
2279 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2280 struct bnxt_re_dev *rdev = qp->rdev;
2281 struct bnxt_qplib_qp *qplib_qp;
2282 int rc;
2283
2284 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL);
2285 if (!qplib_qp)
2286 return -ENOMEM;
2287
2288 qplib_qp->id = qp->qplib_qp.id;
2289 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;
2290
2291 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp);
2292 if (rc) {
2293 ibdev_err(&rdev->ibdev, "Failed to query HW QP");
2294 goto out;
2295 }
2296 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state);
2297 qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state);
2298 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0;
2299 qp_attr->qp_access_flags = __qp_access_flags_to_ib(qp->qplib_qp.cctx,
2300 qplib_qp->access);
2301 qp_attr->pkey_index = qplib_qp->pkey_index;
2302 qp_attr->qkey = qplib_qp->qkey;
2303 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2304 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label,
2305 qplib_qp->ah.host_sgid_index,
2306 qplib_qp->ah.hop_limit,
2307 qplib_qp->ah.traffic_class);
2308 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data);
2309 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl);
2310 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac);
2311 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu);
2312 qp_attr->timeout = qplib_qp->timeout;
2313 qp_attr->retry_cnt = qplib_qp->retry_cnt;
2314 qp_attr->rnr_retry = qplib_qp->rnr_retry;
2315 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer;
2316 qp_attr->port_num = __to_ib_port_num(qplib_qp->port_id);
2317 qp_attr->rq_psn = qplib_qp->rq.psn;
2318 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic;
2319 qp_attr->sq_psn = qplib_qp->sq.psn;
2320 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic;
2321 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR :
2322 IB_SIGNAL_REQ_WR;
2323 qp_attr->dest_qp_num = qplib_qp->dest_qpn;
2324
2325 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;
2326 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;
2327 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe;
2328 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge;
2329 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;
2330 qp_init_attr->cap = qp_attr->cap;
2331
2332 out:
2333 kfree(qplib_qp);
2334 return rc;
2335 }
2336
2337 /* Routine for sending QP1 packets for RoCE V1 an V2
2338 */
bnxt_re_build_qp1_send_v2(struct bnxt_re_qp * qp,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe,int payload_size)2339 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
2340 const struct ib_send_wr *wr,
2341 struct bnxt_qplib_swqe *wqe,
2342 int payload_size)
2343 {
2344 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah,
2345 ib_ah);
2346 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah;
2347 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr;
2348 struct bnxt_qplib_sge sge;
2349 u8 nw_type;
2350 u16 ether_type;
2351 union ib_gid dgid;
2352 bool is_eth = false;
2353 bool is_vlan = false;
2354 bool is_grh = false;
2355 bool is_udp = false;
2356 u8 ip_version = 0;
2357 u16 vlan_id = 0xFFFF;
2358 void *buf;
2359 int i, rc;
2360
2361 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr));
2362
2363 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL);
2364 if (rc)
2365 return rc;
2366
2367 /* Get network header type for this GID */
2368 nw_type = rdma_gid_attr_network_type(sgid_attr);
2369 switch (nw_type) {
2370 case RDMA_NETWORK_IPV4:
2371 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET;
2372 break;
2373 case RDMA_NETWORK_IPV6:
2374 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET;
2375 break;
2376 default:
2377 nw_type = BNXT_RE_ROCE_V1_PACKET;
2378 break;
2379 }
2380 memcpy(&dgid.raw, &qplib_ah->dgid, 16);
2381 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2382 if (is_udp) {
2383 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) {
2384 ip_version = 4;
2385 ether_type = ETH_P_IP;
2386 } else {
2387 ip_version = 6;
2388 ether_type = ETH_P_IPV6;
2389 }
2390 is_grh = false;
2391 } else {
2392 ether_type = ETH_P_IBOE;
2393 is_grh = true;
2394 }
2395
2396 is_eth = true;
2397 is_vlan = vlan_id && (vlan_id < 0x1000);
2398
2399 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh,
2400 ip_version, is_udp, 0, &qp->qp1_hdr);
2401
2402 /* ETH */
2403 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac);
2404 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac);
2405
2406 /* For vlan, check the sgid for vlan existence */
2407
2408 if (!is_vlan) {
2409 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type);
2410 } else {
2411 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type);
2412 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id);
2413 }
2414
2415 if (is_grh || (ip_version == 6)) {
2416 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw,
2417 sizeof(sgid_attr->gid));
2418 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data,
2419 sizeof(sgid_attr->gid));
2420 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit;
2421 }
2422
2423 if (ip_version == 4) {
2424 qp->qp1_hdr.ip4.tos = 0;
2425 qp->qp1_hdr.ip4.id = 0;
2426 qp->qp1_hdr.ip4.frag_off = htons(IP_DF);
2427 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit;
2428
2429 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4);
2430 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4);
2431 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr);
2432 }
2433
2434 if (is_udp) {
2435 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT);
2436 qp->qp1_hdr.udp.sport = htons(0x8CD1);
2437 qp->qp1_hdr.udp.csum = 0;
2438 }
2439
2440 /* BTH */
2441 if (wr->opcode == IB_WR_SEND_WITH_IMM) {
2442 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2443 qp->qp1_hdr.immediate_present = 1;
2444 } else {
2445 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2446 }
2447 if (wr->send_flags & IB_SEND_SOLICITED)
2448 qp->qp1_hdr.bth.solicited_event = 1;
2449 /* pad_count */
2450 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3;
2451
2452 /* P_key for QP1 is for all members */
2453 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF);
2454 qp->qp1_hdr.bth.destination_qpn = IB_QP1;
2455 qp->qp1_hdr.bth.ack_req = 0;
2456 qp->send_psn++;
2457 qp->send_psn &= BTH_PSN_MASK;
2458 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn);
2459 /* DETH */
2460 /* Use the priviledged Q_Key for QP1 */
2461 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY);
2462 qp->qp1_hdr.deth.source_qpn = IB_QP1;
2463
2464 /* Pack the QP1 to the transmit buffer */
2465 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge);
2466 if (buf) {
2467 ib_ud_header_pack(&qp->qp1_hdr, buf);
2468 for (i = wqe->num_sge; i; i--) {
2469 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr;
2470 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey;
2471 wqe->sg_list[i].size = wqe->sg_list[i - 1].size;
2472 }
2473
2474 /*
2475 * Max Header buf size for IPV6 RoCE V2 is 86,
2476 * which is same as the QP1 SQ header buffer.
2477 * Header buf size for IPV4 RoCE V2 can be 66.
2478 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20).
2479 * Subtract 20 bytes from QP1 SQ header buf size
2480 */
2481 if (is_udp && ip_version == 4)
2482 sge.size -= 20;
2483 /*
2484 * Max Header buf size for RoCE V1 is 78.
2485 * ETH(14) + VLAN(4) + GRH(40) + BTH(20).
2486 * Subtract 8 bytes from QP1 SQ header buf size
2487 */
2488 if (!is_udp)
2489 sge.size -= 8;
2490
2491 /* Subtract 4 bytes for non vlan packets */
2492 if (!is_vlan)
2493 sge.size -= 4;
2494
2495 wqe->sg_list[0].addr = sge.addr;
2496 wqe->sg_list[0].lkey = sge.lkey;
2497 wqe->sg_list[0].size = sge.size;
2498 wqe->num_sge++;
2499
2500 } else {
2501 ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!");
2502 rc = -ENOMEM;
2503 }
2504 return rc;
2505 }
2506
2507 /* For the MAD layer, it only provides the recv SGE the size of
2508 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH,
2509 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire
2510 * receive packet (334 bytes) with no VLAN and then copy the GRH
2511 * and the MAD datagram out to the provided SGE.
2512 */
bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp * qp,const struct ib_recv_wr * wr,struct bnxt_qplib_swqe * wqe,int payload_size)2513 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp,
2514 const struct ib_recv_wr *wr,
2515 struct bnxt_qplib_swqe *wqe,
2516 int payload_size)
2517 {
2518 struct bnxt_re_sqp_entries *sqp_entry;
2519 struct bnxt_qplib_sge ref, sge;
2520 struct bnxt_re_dev *rdev;
2521 u32 rq_prod_index;
2522
2523 rdev = qp->rdev;
2524
2525 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp);
2526
2527 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge))
2528 return -ENOMEM;
2529
2530 /* Create 1 SGE to receive the entire
2531 * ethernet packet
2532 */
2533 /* Save the reference from ULP */
2534 ref.addr = wqe->sg_list[0].addr;
2535 ref.lkey = wqe->sg_list[0].lkey;
2536 ref.size = wqe->sg_list[0].size;
2537
2538 sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index];
2539
2540 /* SGE 1 */
2541 wqe->sg_list[0].addr = sge.addr;
2542 wqe->sg_list[0].lkey = sge.lkey;
2543 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
2544 sge.size -= wqe->sg_list[0].size;
2545
2546 sqp_entry->sge.addr = ref.addr;
2547 sqp_entry->sge.lkey = ref.lkey;
2548 sqp_entry->sge.size = ref.size;
2549 /* Store the wrid for reporting completion */
2550 sqp_entry->wrid = wqe->wr_id;
2551 /* change the wqe->wrid to table index */
2552 wqe->wr_id = rq_prod_index;
2553 return 0;
2554 }
2555
is_ud_qp(struct bnxt_re_qp * qp)2556 static int is_ud_qp(struct bnxt_re_qp *qp)
2557 {
2558 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD ||
2559 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI);
2560 }
2561
bnxt_re_build_send_wqe(struct bnxt_re_qp * qp,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2562 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp,
2563 const struct ib_send_wr *wr,
2564 struct bnxt_qplib_swqe *wqe)
2565 {
2566 struct bnxt_re_ah *ah = NULL;
2567
2568 if (is_ud_qp(qp)) {
2569 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah);
2570 wqe->send.q_key = ud_wr(wr)->remote_qkey;
2571 wqe->send.dst_qp = ud_wr(wr)->remote_qpn;
2572 wqe->send.avid = ah->qplib_ah.id;
2573 }
2574 switch (wr->opcode) {
2575 case IB_WR_SEND:
2576 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND;
2577 break;
2578 case IB_WR_SEND_WITH_IMM:
2579 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM;
2580 wqe->send.imm_data = be32_to_cpu(wr->ex.imm_data);
2581 break;
2582 case IB_WR_SEND_WITH_INV:
2583 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV;
2584 wqe->send.inv_key = wr->ex.invalidate_rkey;
2585 break;
2586 default:
2587 return -EINVAL;
2588 }
2589 if (wr->send_flags & IB_SEND_SIGNALED)
2590 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2591 if (wr->send_flags & IB_SEND_FENCE)
2592 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2593 if (wr->send_flags & IB_SEND_SOLICITED)
2594 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2595 if (wr->send_flags & IB_SEND_INLINE)
2596 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2597
2598 return 0;
2599 }
2600
bnxt_re_build_rdma_wqe(const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2601 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr,
2602 struct bnxt_qplib_swqe *wqe)
2603 {
2604 switch (wr->opcode) {
2605 case IB_WR_RDMA_WRITE:
2606 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE;
2607 break;
2608 case IB_WR_RDMA_WRITE_WITH_IMM:
2609 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM;
2610 wqe->rdma.imm_data = be32_to_cpu(wr->ex.imm_data);
2611 break;
2612 case IB_WR_RDMA_READ:
2613 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ;
2614 wqe->rdma.inv_key = wr->ex.invalidate_rkey;
2615 break;
2616 default:
2617 return -EINVAL;
2618 }
2619 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr;
2620 wqe->rdma.r_key = rdma_wr(wr)->rkey;
2621 if (wr->send_flags & IB_SEND_SIGNALED)
2622 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2623 if (wr->send_flags & IB_SEND_FENCE)
2624 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2625 if (wr->send_flags & IB_SEND_SOLICITED)
2626 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2627 if (wr->send_flags & IB_SEND_INLINE)
2628 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2629
2630 return 0;
2631 }
2632
bnxt_re_build_atomic_wqe(const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2633 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr,
2634 struct bnxt_qplib_swqe *wqe)
2635 {
2636 switch (wr->opcode) {
2637 case IB_WR_ATOMIC_CMP_AND_SWP:
2638 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;
2639 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2640 wqe->atomic.swap_data = atomic_wr(wr)->swap;
2641 break;
2642 case IB_WR_ATOMIC_FETCH_AND_ADD:
2643 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD;
2644 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2645 break;
2646 default:
2647 return -EINVAL;
2648 }
2649 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr;
2650 wqe->atomic.r_key = atomic_wr(wr)->rkey;
2651 if (wr->send_flags & IB_SEND_SIGNALED)
2652 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2653 if (wr->send_flags & IB_SEND_FENCE)
2654 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2655 if (wr->send_flags & IB_SEND_SOLICITED)
2656 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2657 return 0;
2658 }
2659
bnxt_re_build_inv_wqe(const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2660 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr,
2661 struct bnxt_qplib_swqe *wqe)
2662 {
2663 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV;
2664 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey;
2665
2666 if (wr->send_flags & IB_SEND_SIGNALED)
2667 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2668 if (wr->send_flags & IB_SEND_SOLICITED)
2669 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2670
2671 return 0;
2672 }
2673
bnxt_re_build_reg_wqe(const struct ib_reg_wr * wr,struct bnxt_qplib_swqe * wqe)2674 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr,
2675 struct bnxt_qplib_swqe *wqe)
2676 {
2677 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr);
2678 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl;
2679 int access = wr->access;
2680
2681 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0];
2682 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0];
2683 wqe->frmr.page_list = mr->pages;
2684 wqe->frmr.page_list_len = mr->npages;
2685 wqe->frmr.levels = qplib_frpl->hwq.level;
2686 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR;
2687
2688 if (wr->wr.send_flags & IB_SEND_SIGNALED)
2689 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2690
2691 if (access & IB_ACCESS_LOCAL_WRITE)
2692 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE;
2693 if (access & IB_ACCESS_REMOTE_READ)
2694 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ;
2695 if (access & IB_ACCESS_REMOTE_WRITE)
2696 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE;
2697 if (access & IB_ACCESS_REMOTE_ATOMIC)
2698 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC;
2699 if (access & IB_ACCESS_MW_BIND)
2700 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND;
2701
2702 wqe->frmr.l_key = wr->key;
2703 wqe->frmr.length = wr->mr->length;
2704 wqe->frmr.pbl_pg_sz_log = ilog2(PAGE_SIZE >> PAGE_SHIFT_4K);
2705 wqe->frmr.pg_sz_log = ilog2(wr->mr->page_size >> PAGE_SHIFT_4K);
2706 wqe->frmr.va = wr->mr->iova;
2707 return 0;
2708 }
2709
bnxt_re_copy_inline_data(struct bnxt_re_dev * rdev,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2710 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev,
2711 const struct ib_send_wr *wr,
2712 struct bnxt_qplib_swqe *wqe)
2713 {
2714 /* Copy the inline data to the data field */
2715 u8 *in_data;
2716 u32 i, sge_len;
2717 void *sge_addr;
2718
2719 in_data = wqe->inline_data;
2720 for (i = 0; i < wr->num_sge; i++) {
2721 sge_addr = (void *)(unsigned long)
2722 wr->sg_list[i].addr;
2723 sge_len = wr->sg_list[i].length;
2724
2725 if ((sge_len + wqe->inline_len) >
2726 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) {
2727 ibdev_err(&rdev->ibdev,
2728 "Inline data size requested > supported value");
2729 return -EINVAL;
2730 }
2731 sge_len = wr->sg_list[i].length;
2732
2733 memcpy(in_data, sge_addr, sge_len);
2734 in_data += wr->sg_list[i].length;
2735 wqe->inline_len += wr->sg_list[i].length;
2736 }
2737 return wqe->inline_len;
2738 }
2739
bnxt_re_copy_wr_payload(struct bnxt_re_dev * rdev,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2740 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev,
2741 const struct ib_send_wr *wr,
2742 struct bnxt_qplib_swqe *wqe)
2743 {
2744 int payload_sz = 0;
2745
2746 if (wr->send_flags & IB_SEND_INLINE)
2747 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe);
2748 else
2749 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list,
2750 wqe->num_sge);
2751
2752 return payload_sz;
2753 }
2754
bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp * qp)2755 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp)
2756 {
2757 if ((qp->ib_qp.qp_type == IB_QPT_UD ||
2758 qp->ib_qp.qp_type == IB_QPT_GSI ||
2759 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) &&
2760 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) {
2761 int qp_attr_mask;
2762 struct ib_qp_attr qp_attr;
2763
2764 qp_attr_mask = IB_QP_STATE;
2765 qp_attr.qp_state = IB_QPS_RTS;
2766 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL);
2767 qp->qplib_qp.wqe_cnt = 0;
2768 }
2769 }
2770
bnxt_re_post_send_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp,const struct ib_send_wr * wr)2771 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,
2772 struct bnxt_re_qp *qp,
2773 const struct ib_send_wr *wr)
2774 {
2775 int rc = 0, payload_sz = 0;
2776 unsigned long flags;
2777
2778 spin_lock_irqsave(&qp->sq_lock, flags);
2779 while (wr) {
2780 struct bnxt_qplib_swqe wqe = {};
2781
2782 /* Common */
2783 wqe.num_sge = wr->num_sge;
2784 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2785 ibdev_err(&rdev->ibdev,
2786 "Limit exceeded for Send SGEs");
2787 rc = -EINVAL;
2788 goto bad;
2789 }
2790
2791 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2792 if (payload_sz < 0) {
2793 rc = -EINVAL;
2794 goto bad;
2795 }
2796 wqe.wr_id = wr->wr_id;
2797
2798 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND;
2799
2800 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2801 if (!rc)
2802 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2803 bad:
2804 if (rc) {
2805 ibdev_err(&rdev->ibdev,
2806 "Post send failed opcode = %#x rc = %d",
2807 wr->opcode, rc);
2808 break;
2809 }
2810 wr = wr->next;
2811 }
2812 bnxt_qplib_post_send_db(&qp->qplib_qp);
2813 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx))
2814 bnxt_ud_qp_hw_stall_workaround(qp);
2815 spin_unlock_irqrestore(&qp->sq_lock, flags);
2816 return rc;
2817 }
2818
bnxt_re_legacy_set_uc_fence(struct bnxt_qplib_swqe * wqe)2819 static void bnxt_re_legacy_set_uc_fence(struct bnxt_qplib_swqe *wqe)
2820 {
2821 /* Need unconditional fence for non-wire memory opcode
2822 * to work as expected.
2823 */
2824 if (wqe->type == BNXT_QPLIB_SWQE_TYPE_LOCAL_INV ||
2825 wqe->type == BNXT_QPLIB_SWQE_TYPE_FAST_REG_MR ||
2826 wqe->type == BNXT_QPLIB_SWQE_TYPE_REG_MR ||
2827 wqe->type == BNXT_QPLIB_SWQE_TYPE_BIND_MW)
2828 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2829 }
2830
bnxt_re_post_send(struct ib_qp * ib_qp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)2831 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr,
2832 const struct ib_send_wr **bad_wr)
2833 {
2834 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2835 struct bnxt_qplib_swqe wqe;
2836 int rc = 0, payload_sz = 0;
2837 unsigned long flags;
2838
2839 spin_lock_irqsave(&qp->sq_lock, flags);
2840 while (wr) {
2841 /* House keeping */
2842 memset(&wqe, 0, sizeof(wqe));
2843
2844 /* Common */
2845 wqe.num_sge = wr->num_sge;
2846 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2847 ibdev_err(&qp->rdev->ibdev,
2848 "Limit exceeded for Send SGEs");
2849 rc = -EINVAL;
2850 goto bad;
2851 }
2852
2853 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2854 if (payload_sz < 0) {
2855 rc = -EINVAL;
2856 goto bad;
2857 }
2858 wqe.wr_id = wr->wr_id;
2859
2860 switch (wr->opcode) {
2861 case IB_WR_SEND:
2862 case IB_WR_SEND_WITH_IMM:
2863 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) {
2864 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe,
2865 payload_sz);
2866 if (rc)
2867 goto bad;
2868 wqe.rawqp1.lflags |=
2869 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC;
2870 }
2871 switch (wr->send_flags) {
2872 case IB_SEND_IP_CSUM:
2873 wqe.rawqp1.lflags |=
2874 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM;
2875 break;
2876 default:
2877 break;
2878 }
2879 fallthrough;
2880 case IB_WR_SEND_WITH_INV:
2881 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2882 break;
2883 case IB_WR_RDMA_WRITE:
2884 case IB_WR_RDMA_WRITE_WITH_IMM:
2885 case IB_WR_RDMA_READ:
2886 rc = bnxt_re_build_rdma_wqe(wr, &wqe);
2887 break;
2888 case IB_WR_ATOMIC_CMP_AND_SWP:
2889 case IB_WR_ATOMIC_FETCH_AND_ADD:
2890 rc = bnxt_re_build_atomic_wqe(wr, &wqe);
2891 break;
2892 case IB_WR_RDMA_READ_WITH_INV:
2893 ibdev_err(&qp->rdev->ibdev,
2894 "RDMA Read with Invalidate is not supported");
2895 rc = -EINVAL;
2896 goto bad;
2897 case IB_WR_LOCAL_INV:
2898 rc = bnxt_re_build_inv_wqe(wr, &wqe);
2899 break;
2900 case IB_WR_REG_MR:
2901 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
2902 break;
2903 default:
2904 /* Unsupported WRs */
2905 ibdev_err(&qp->rdev->ibdev,
2906 "WR (%#x) is not supported", wr->opcode);
2907 rc = -EINVAL;
2908 goto bad;
2909 }
2910 if (!rc) {
2911 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx))
2912 bnxt_re_legacy_set_uc_fence(&wqe);
2913 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2914 }
2915 bad:
2916 if (rc) {
2917 ibdev_err(&qp->rdev->ibdev,
2918 "post_send failed op:%#x qps = %#x rc = %d\n",
2919 wr->opcode, qp->qplib_qp.state, rc);
2920 *bad_wr = wr;
2921 break;
2922 }
2923 wr = wr->next;
2924 }
2925 bnxt_qplib_post_send_db(&qp->qplib_qp);
2926 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx))
2927 bnxt_ud_qp_hw_stall_workaround(qp);
2928 spin_unlock_irqrestore(&qp->sq_lock, flags);
2929
2930 return rc;
2931 }
2932
bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp,const struct ib_recv_wr * wr)2933 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
2934 struct bnxt_re_qp *qp,
2935 const struct ib_recv_wr *wr)
2936 {
2937 struct bnxt_qplib_swqe wqe;
2938 int rc = 0;
2939
2940 while (wr) {
2941 /* House keeping */
2942 memset(&wqe, 0, sizeof(wqe));
2943
2944 /* Common */
2945 wqe.num_sge = wr->num_sge;
2946 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2947 ibdev_err(&rdev->ibdev,
2948 "Limit exceeded for Receive SGEs");
2949 rc = -EINVAL;
2950 break;
2951 }
2952 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
2953 wqe.wr_id = wr->wr_id;
2954 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2955
2956 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2957 if (rc)
2958 break;
2959
2960 wr = wr->next;
2961 }
2962 if (!rc)
2963 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2964 return rc;
2965 }
2966
bnxt_re_post_recv(struct ib_qp * ib_qp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)2967 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr,
2968 const struct ib_recv_wr **bad_wr)
2969 {
2970 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2971 struct bnxt_qplib_swqe wqe;
2972 int rc = 0, payload_sz = 0;
2973 unsigned long flags;
2974 u32 count = 0;
2975
2976 spin_lock_irqsave(&qp->rq_lock, flags);
2977 while (wr) {
2978 /* House keeping */
2979 memset(&wqe, 0, sizeof(wqe));
2980
2981 /* Common */
2982 wqe.num_sge = wr->num_sge;
2983 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2984 ibdev_err(&qp->rdev->ibdev,
2985 "Limit exceeded for Receive SGEs");
2986 rc = -EINVAL;
2987 *bad_wr = wr;
2988 break;
2989 }
2990
2991 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
2992 wr->num_sge);
2993 wqe.wr_id = wr->wr_id;
2994 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2995
2996 if (ib_qp->qp_type == IB_QPT_GSI &&
2997 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI)
2998 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe,
2999 payload_sz);
3000 if (!rc)
3001 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
3002 if (rc) {
3003 *bad_wr = wr;
3004 break;
3005 }
3006
3007 /* Ring DB if the RQEs posted reaches a threshold value */
3008 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) {
3009 bnxt_qplib_post_recv_db(&qp->qplib_qp);
3010 count = 0;
3011 }
3012
3013 wr = wr->next;
3014 }
3015
3016 if (count)
3017 bnxt_qplib_post_recv_db(&qp->qplib_qp);
3018
3019 spin_unlock_irqrestore(&qp->rq_lock, flags);
3020
3021 return rc;
3022 }
3023
bnxt_re_get_nq(struct bnxt_re_dev * rdev)3024 static struct bnxt_qplib_nq *bnxt_re_get_nq(struct bnxt_re_dev *rdev)
3025 {
3026 int min, indx;
3027
3028 mutex_lock(&rdev->nqr->load_lock);
3029 for (indx = 0, min = 0; indx < (rdev->nqr->num_msix - 1); indx++) {
3030 if (rdev->nqr->nq[min].load > rdev->nqr->nq[indx].load)
3031 min = indx;
3032 }
3033 rdev->nqr->nq[min].load++;
3034 mutex_unlock(&rdev->nqr->load_lock);
3035
3036 return &rdev->nqr->nq[min];
3037 }
3038
bnxt_re_put_nq(struct bnxt_re_dev * rdev,struct bnxt_qplib_nq * nq)3039 static void bnxt_re_put_nq(struct bnxt_re_dev *rdev, struct bnxt_qplib_nq *nq)
3040 {
3041 mutex_lock(&rdev->nqr->load_lock);
3042 nq->load--;
3043 mutex_unlock(&rdev->nqr->load_lock);
3044 }
3045
3046 /* Completion Queues */
bnxt_re_destroy_cq(struct ib_cq * ib_cq,struct ib_udata * udata)3047 int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
3048 {
3049 struct bnxt_qplib_chip_ctx *cctx;
3050 struct bnxt_qplib_nq *nq;
3051 struct bnxt_re_dev *rdev;
3052 struct bnxt_re_cq *cq;
3053
3054 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3055 rdev = cq->rdev;
3056 nq = cq->qplib_cq.nq;
3057 cctx = rdev->chip_ctx;
3058
3059 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) {
3060 free_page((unsigned long)cq->uctx_cq_page);
3061 hash_del(&cq->hash_entry);
3062 }
3063 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
3064
3065 bnxt_re_put_nq(rdev, nq);
3066 ib_umem_release(cq->umem);
3067
3068 atomic_dec(&rdev->stats.res.cq_count);
3069 kfree(cq->cql);
3070 return 0;
3071 }
3072
bnxt_re_create_cq(struct ib_cq * ibcq,const struct ib_cq_init_attr * attr,struct uverbs_attr_bundle * attrs)3073 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
3074 struct uverbs_attr_bundle *attrs)
3075 {
3076 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);
3077 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev);
3078 struct ib_udata *udata = &attrs->driver_udata;
3079 struct bnxt_re_ucontext *uctx =
3080 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
3081 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr;
3082 struct bnxt_qplib_chip_ctx *cctx;
3083 int cqe = attr->cqe;
3084 int rc, entries;
3085 u32 active_cqs;
3086
3087 if (attr->flags)
3088 return -EOPNOTSUPP;
3089
3090 /* Validate CQ fields */
3091 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
3092 ibdev_err(&rdev->ibdev, "Failed to create CQ -max exceeded");
3093 return -EINVAL;
3094 }
3095
3096 cq->rdev = rdev;
3097 cctx = rdev->chip_ctx;
3098 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq);
3099
3100 entries = bnxt_re_init_depth(cqe + 1, uctx);
3101 if (entries > dev_attr->max_cq_wqes + 1)
3102 entries = dev_attr->max_cq_wqes + 1;
3103
3104 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE;
3105 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT;
3106 if (udata) {
3107 struct bnxt_re_cq_req req;
3108 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
3109 rc = -EFAULT;
3110 goto fail;
3111 }
3112
3113 cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va,
3114 entries * sizeof(struct cq_base),
3115 IB_ACCESS_LOCAL_WRITE);
3116 if (IS_ERR(cq->umem)) {
3117 rc = PTR_ERR(cq->umem);
3118 goto fail;
3119 }
3120 cq->qplib_cq.sg_info.umem = cq->umem;
3121 cq->qplib_cq.dpi = &uctx->dpi;
3122 } else {
3123 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL);
3124 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe),
3125 GFP_KERNEL);
3126 if (!cq->cql) {
3127 rc = -ENOMEM;
3128 goto fail;
3129 }
3130
3131 cq->qplib_cq.dpi = &rdev->dpi_privileged;
3132 }
3133 cq->qplib_cq.max_wqe = entries;
3134 cq->qplib_cq.coalescing = &rdev->cq_coalescing;
3135 cq->qplib_cq.nq = bnxt_re_get_nq(rdev);
3136 cq->qplib_cq.cnq_hw_ring_id = cq->qplib_cq.nq->ring_id;
3137
3138 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq);
3139 if (rc) {
3140 ibdev_err(&rdev->ibdev, "Failed to create HW CQ");
3141 goto fail;
3142 }
3143
3144 cq->ib_cq.cqe = entries;
3145 cq->cq_period = cq->qplib_cq.period;
3146
3147 active_cqs = atomic_inc_return(&rdev->stats.res.cq_count);
3148 if (active_cqs > rdev->stats.res.cq_watermark)
3149 rdev->stats.res.cq_watermark = active_cqs;
3150 spin_lock_init(&cq->cq_lock);
3151
3152 if (udata) {
3153 struct bnxt_re_cq_resp resp = {};
3154
3155 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) {
3156 hash_add(rdev->cq_hash, &cq->hash_entry, cq->qplib_cq.id);
3157 /* Allocate a page */
3158 cq->uctx_cq_page = (void *)get_zeroed_page(GFP_KERNEL);
3159 if (!cq->uctx_cq_page) {
3160 rc = -ENOMEM;
3161 goto c2fail;
3162 }
3163 resp.comp_mask |= BNXT_RE_CQ_TOGGLE_PAGE_SUPPORT;
3164 }
3165 resp.cqid = cq->qplib_cq.id;
3166 resp.tail = cq->qplib_cq.hwq.cons;
3167 resp.phase = cq->qplib_cq.period;
3168 resp.rsvd = 0;
3169 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen));
3170 if (rc) {
3171 ibdev_err(&rdev->ibdev, "Failed to copy CQ udata");
3172 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
3173 goto free_mem;
3174 }
3175 }
3176
3177 return 0;
3178
3179 free_mem:
3180 free_page((unsigned long)cq->uctx_cq_page);
3181 c2fail:
3182 ib_umem_release(cq->umem);
3183 fail:
3184 kfree(cq->cql);
3185 return rc;
3186 }
3187
bnxt_re_resize_cq_complete(struct bnxt_re_cq * cq)3188 static void bnxt_re_resize_cq_complete(struct bnxt_re_cq *cq)
3189 {
3190 struct bnxt_re_dev *rdev = cq->rdev;
3191
3192 bnxt_qplib_resize_cq_complete(&rdev->qplib_res, &cq->qplib_cq);
3193
3194 cq->qplib_cq.max_wqe = cq->resize_cqe;
3195 if (cq->resize_umem) {
3196 ib_umem_release(cq->umem);
3197 cq->umem = cq->resize_umem;
3198 cq->resize_umem = NULL;
3199 cq->resize_cqe = 0;
3200 }
3201 }
3202
bnxt_re_resize_cq(struct ib_cq * ibcq,int cqe,struct ib_udata * udata)3203 int bnxt_re_resize_cq(struct ib_cq *ibcq, int cqe, struct ib_udata *udata)
3204 {
3205 struct bnxt_qplib_sg_info sg_info = {};
3206 struct bnxt_qplib_dpi *orig_dpi = NULL;
3207 struct bnxt_qplib_dev_attr *dev_attr;
3208 struct bnxt_re_ucontext *uctx = NULL;
3209 struct bnxt_re_resize_cq_req req;
3210 struct bnxt_re_dev *rdev;
3211 struct bnxt_re_cq *cq;
3212 int rc, entries;
3213
3214 cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);
3215 rdev = cq->rdev;
3216 dev_attr = rdev->dev_attr;
3217 if (!ibcq->uobject) {
3218 ibdev_err(&rdev->ibdev, "Kernel CQ Resize not supported");
3219 return -EOPNOTSUPP;
3220 }
3221
3222 if (cq->resize_umem) {
3223 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - Busy",
3224 cq->qplib_cq.id);
3225 return -EBUSY;
3226 }
3227
3228 /* Check the requested cq depth out of supported depth */
3229 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
3230 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - out of range cqe %d",
3231 cq->qplib_cq.id, cqe);
3232 return -EINVAL;
3233 }
3234
3235 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
3236 entries = bnxt_re_init_depth(cqe + 1, uctx);
3237 if (entries > dev_attr->max_cq_wqes + 1)
3238 entries = dev_attr->max_cq_wqes + 1;
3239
3240 /* uverbs consumer */
3241 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
3242 rc = -EFAULT;
3243 goto fail;
3244 }
3245
3246 cq->resize_umem = ib_umem_get(&rdev->ibdev, req.cq_va,
3247 entries * sizeof(struct cq_base),
3248 IB_ACCESS_LOCAL_WRITE);
3249 if (IS_ERR(cq->resize_umem)) {
3250 rc = PTR_ERR(cq->resize_umem);
3251 cq->resize_umem = NULL;
3252 ibdev_err(&rdev->ibdev, "%s: ib_umem_get failed! rc = %d\n",
3253 __func__, rc);
3254 goto fail;
3255 }
3256 cq->resize_cqe = entries;
3257 memcpy(&sg_info, &cq->qplib_cq.sg_info, sizeof(sg_info));
3258 orig_dpi = cq->qplib_cq.dpi;
3259
3260 cq->qplib_cq.sg_info.umem = cq->resize_umem;
3261 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE;
3262 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT;
3263 cq->qplib_cq.dpi = &uctx->dpi;
3264
3265 rc = bnxt_qplib_resize_cq(&rdev->qplib_res, &cq->qplib_cq, entries);
3266 if (rc) {
3267 ibdev_err(&rdev->ibdev, "Resize HW CQ %#x failed!",
3268 cq->qplib_cq.id);
3269 goto fail;
3270 }
3271
3272 cq->ib_cq.cqe = cq->resize_cqe;
3273 atomic_inc(&rdev->stats.res.resize_count);
3274
3275 return 0;
3276
3277 fail:
3278 if (cq->resize_umem) {
3279 ib_umem_release(cq->resize_umem);
3280 cq->resize_umem = NULL;
3281 cq->resize_cqe = 0;
3282 memcpy(&cq->qplib_cq.sg_info, &sg_info, sizeof(sg_info));
3283 cq->qplib_cq.dpi = orig_dpi;
3284 }
3285 return rc;
3286 }
3287
__req_to_ib_wc_status(u8 qstatus)3288 static u8 __req_to_ib_wc_status(u8 qstatus)
3289 {
3290 switch (qstatus) {
3291 case CQ_REQ_STATUS_OK:
3292 return IB_WC_SUCCESS;
3293 case CQ_REQ_STATUS_BAD_RESPONSE_ERR:
3294 return IB_WC_BAD_RESP_ERR;
3295 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR:
3296 return IB_WC_LOC_LEN_ERR;
3297 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR:
3298 return IB_WC_LOC_QP_OP_ERR;
3299 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR:
3300 return IB_WC_LOC_PROT_ERR;
3301 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR:
3302 return IB_WC_GENERAL_ERR;
3303 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR:
3304 return IB_WC_REM_INV_REQ_ERR;
3305 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR:
3306 return IB_WC_REM_ACCESS_ERR;
3307 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR:
3308 return IB_WC_REM_OP_ERR;
3309 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR:
3310 return IB_WC_RNR_RETRY_EXC_ERR;
3311 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR:
3312 return IB_WC_RETRY_EXC_ERR;
3313 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR:
3314 return IB_WC_WR_FLUSH_ERR;
3315 default:
3316 return IB_WC_GENERAL_ERR;
3317 }
3318 return 0;
3319 }
3320
__rawqp1_to_ib_wc_status(u8 qstatus)3321 static u8 __rawqp1_to_ib_wc_status(u8 qstatus)
3322 {
3323 switch (qstatus) {
3324 case CQ_RES_RAWETH_QP1_STATUS_OK:
3325 return IB_WC_SUCCESS;
3326 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR:
3327 return IB_WC_LOC_ACCESS_ERR;
3328 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR:
3329 return IB_WC_LOC_LEN_ERR;
3330 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR:
3331 return IB_WC_LOC_PROT_ERR;
3332 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR:
3333 return IB_WC_LOC_QP_OP_ERR;
3334 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR:
3335 return IB_WC_GENERAL_ERR;
3336 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR:
3337 return IB_WC_WR_FLUSH_ERR;
3338 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR:
3339 return IB_WC_WR_FLUSH_ERR;
3340 default:
3341 return IB_WC_GENERAL_ERR;
3342 }
3343 }
3344
__rc_to_ib_wc_status(u8 qstatus)3345 static u8 __rc_to_ib_wc_status(u8 qstatus)
3346 {
3347 switch (qstatus) {
3348 case CQ_RES_RC_STATUS_OK:
3349 return IB_WC_SUCCESS;
3350 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR:
3351 return IB_WC_LOC_ACCESS_ERR;
3352 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR:
3353 return IB_WC_LOC_LEN_ERR;
3354 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR:
3355 return IB_WC_LOC_PROT_ERR;
3356 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR:
3357 return IB_WC_LOC_QP_OP_ERR;
3358 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR:
3359 return IB_WC_GENERAL_ERR;
3360 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR:
3361 return IB_WC_REM_INV_REQ_ERR;
3362 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR:
3363 return IB_WC_WR_FLUSH_ERR;
3364 case CQ_RES_RC_STATUS_HW_FLUSH_ERR:
3365 return IB_WC_WR_FLUSH_ERR;
3366 default:
3367 return IB_WC_GENERAL_ERR;
3368 }
3369 }
3370
bnxt_re_process_req_wc(struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3371 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe)
3372 {
3373 switch (cqe->type) {
3374 case BNXT_QPLIB_SWQE_TYPE_SEND:
3375 wc->opcode = IB_WC_SEND;
3376 break;
3377 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
3378 wc->opcode = IB_WC_SEND;
3379 wc->wc_flags |= IB_WC_WITH_IMM;
3380 break;
3381 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
3382 wc->opcode = IB_WC_SEND;
3383 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3384 break;
3385 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE:
3386 wc->opcode = IB_WC_RDMA_WRITE;
3387 break;
3388 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM:
3389 wc->opcode = IB_WC_RDMA_WRITE;
3390 wc->wc_flags |= IB_WC_WITH_IMM;
3391 break;
3392 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ:
3393 wc->opcode = IB_WC_RDMA_READ;
3394 break;
3395 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP:
3396 wc->opcode = IB_WC_COMP_SWAP;
3397 break;
3398 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD:
3399 wc->opcode = IB_WC_FETCH_ADD;
3400 break;
3401 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV:
3402 wc->opcode = IB_WC_LOCAL_INV;
3403 break;
3404 case BNXT_QPLIB_SWQE_TYPE_REG_MR:
3405 wc->opcode = IB_WC_REG_MR;
3406 break;
3407 default:
3408 wc->opcode = IB_WC_SEND;
3409 break;
3410 }
3411
3412 wc->status = __req_to_ib_wc_status(cqe->status);
3413 }
3414
bnxt_re_check_packet_type(u16 raweth_qp1_flags,u16 raweth_qp1_flags2)3415 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
3416 u16 raweth_qp1_flags2)
3417 {
3418 bool is_ipv6 = false, is_ipv4 = false;
3419
3420 /* raweth_qp1_flags Bit 9-6 indicates itype */
3421 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
3422 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
3423 return -1;
3424
3425 if (raweth_qp1_flags2 &
3426 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC &&
3427 raweth_qp1_flags2 &
3428 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) {
3429 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */
3430 (raweth_qp1_flags2 &
3431 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ?
3432 (is_ipv6 = true) : (is_ipv4 = true);
3433 return ((is_ipv6) ?
3434 BNXT_RE_ROCEV2_IPV6_PACKET :
3435 BNXT_RE_ROCEV2_IPV4_PACKET);
3436 } else {
3437 return BNXT_RE_ROCE_V1_PACKET;
3438 }
3439 }
3440
bnxt_re_to_ib_nw_type(int nw_type)3441 static int bnxt_re_to_ib_nw_type(int nw_type)
3442 {
3443 u8 nw_hdr_type = 0xFF;
3444
3445 switch (nw_type) {
3446 case BNXT_RE_ROCE_V1_PACKET:
3447 nw_hdr_type = RDMA_NETWORK_ROCE_V1;
3448 break;
3449 case BNXT_RE_ROCEV2_IPV4_PACKET:
3450 nw_hdr_type = RDMA_NETWORK_IPV4;
3451 break;
3452 case BNXT_RE_ROCEV2_IPV6_PACKET:
3453 nw_hdr_type = RDMA_NETWORK_IPV6;
3454 break;
3455 }
3456 return nw_hdr_type;
3457 }
3458
bnxt_re_is_loopback_packet(struct bnxt_re_dev * rdev,void * rq_hdr_buf)3459 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev,
3460 void *rq_hdr_buf)
3461 {
3462 u8 *tmp_buf = NULL;
3463 struct ethhdr *eth_hdr;
3464 u16 eth_type;
3465 bool rc = false;
3466
3467 tmp_buf = (u8 *)rq_hdr_buf;
3468 /*
3469 * If dest mac is not same as I/F mac, this could be a
3470 * loopback address or multicast address, check whether
3471 * it is a loopback packet
3472 */
3473 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) {
3474 tmp_buf += 4;
3475 /* Check the ether type */
3476 eth_hdr = (struct ethhdr *)tmp_buf;
3477 eth_type = ntohs(eth_hdr->h_proto);
3478 switch (eth_type) {
3479 case ETH_P_IBOE:
3480 rc = true;
3481 break;
3482 case ETH_P_IP:
3483 case ETH_P_IPV6: {
3484 u32 len;
3485 struct udphdr *udp_hdr;
3486
3487 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) :
3488 sizeof(struct ipv6hdr));
3489 tmp_buf += sizeof(struct ethhdr) + len;
3490 udp_hdr = (struct udphdr *)tmp_buf;
3491 if (ntohs(udp_hdr->dest) ==
3492 ROCE_V2_UDP_DPORT)
3493 rc = true;
3494 break;
3495 }
3496 default:
3497 break;
3498 }
3499 }
3500
3501 return rc;
3502 }
3503
bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp * gsi_qp,struct bnxt_qplib_cqe * cqe)3504 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp,
3505 struct bnxt_qplib_cqe *cqe)
3506 {
3507 struct bnxt_re_dev *rdev = gsi_qp->rdev;
3508 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3509 struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp;
3510 dma_addr_t shrq_hdr_buf_map;
3511 struct ib_sge s_sge[2] = {};
3512 struct ib_sge r_sge[2] = {};
3513 struct bnxt_re_ah *gsi_sah;
3514 struct ib_recv_wr rwr = {};
3515 dma_addr_t rq_hdr_buf_map;
3516 struct ib_ud_wr udwr = {};
3517 struct ib_send_wr *swr;
3518 u32 skip_bytes = 0;
3519 int pkt_type = 0;
3520 void *rq_hdr_buf;
3521 u32 offset = 0;
3522 u32 tbl_idx;
3523 int rc;
3524
3525 swr = &udwr.wr;
3526 tbl_idx = cqe->wr_id;
3527
3528 rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf +
3529 (tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size);
3530 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3531 tbl_idx);
3532
3533 /* Shadow QP header buffer */
3534 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3535 tbl_idx);
3536 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3537
3538 /* Store this cqe */
3539 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe));
3540 sqp_entry->qp1_qp = gsi_qp;
3541
3542 /* Find packet type from the cqe */
3543
3544 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags,
3545 cqe->raweth_qp1_flags2);
3546 if (pkt_type < 0) {
3547 ibdev_err(&rdev->ibdev, "Invalid packet\n");
3548 return -EINVAL;
3549 }
3550
3551 /* Adjust the offset for the user buffer and post in the rq */
3552
3553 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET)
3554 offset = 20;
3555
3556 /*
3557 * QP1 loopback packet has 4 bytes of internal header before
3558 * ether header. Skip these four bytes.
3559 */
3560 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf))
3561 skip_bytes = 4;
3562
3563 /* First send SGE . Skip the ether header*/
3564 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE
3565 + skip_bytes;
3566 s_sge[0].lkey = 0xFFFFFFFF;
3567 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 :
3568 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
3569
3570 /* Second Send SGE */
3571 s_sge[1].addr = s_sge[0].addr + s_sge[0].length +
3572 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE;
3573 if (pkt_type != BNXT_RE_ROCE_V1_PACKET)
3574 s_sge[1].addr += 8;
3575 s_sge[1].lkey = 0xFFFFFFFF;
3576 s_sge[1].length = 256;
3577
3578 /* First recv SGE */
3579
3580 r_sge[0].addr = shrq_hdr_buf_map;
3581 r_sge[0].lkey = 0xFFFFFFFF;
3582 r_sge[0].length = 40;
3583
3584 r_sge[1].addr = sqp_entry->sge.addr + offset;
3585 r_sge[1].lkey = sqp_entry->sge.lkey;
3586 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset;
3587
3588 /* Create receive work request */
3589 rwr.num_sge = 2;
3590 rwr.sg_list = r_sge;
3591 rwr.wr_id = tbl_idx;
3592 rwr.next = NULL;
3593
3594 rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr);
3595 if (rc) {
3596 ibdev_err(&rdev->ibdev,
3597 "Failed to post Rx buffers to shadow QP");
3598 return -ENOMEM;
3599 }
3600
3601 swr->num_sge = 2;
3602 swr->sg_list = s_sge;
3603 swr->wr_id = tbl_idx;
3604 swr->opcode = IB_WR_SEND;
3605 swr->next = NULL;
3606 gsi_sah = rdev->gsi_ctx.gsi_sah;
3607 udwr.ah = &gsi_sah->ib_ah;
3608 udwr.remote_qpn = gsi_sqp->qplib_qp.id;
3609 udwr.remote_qkey = gsi_sqp->qplib_qp.qkey;
3610
3611 /* post data received in the send queue */
3612 return bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr);
3613 }
3614
bnxt_re_process_res_rawqp1_wc(struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3615 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc,
3616 struct bnxt_qplib_cqe *cqe)
3617 {
3618 wc->opcode = IB_WC_RECV;
3619 wc->status = __rawqp1_to_ib_wc_status(cqe->status);
3620 wc->wc_flags |= IB_WC_GRH;
3621 }
3622
bnxt_re_check_if_vlan_valid(struct bnxt_re_dev * rdev,u16 vlan_id)3623 static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev,
3624 u16 vlan_id)
3625 {
3626 /*
3627 * Check if the vlan is configured in the host. If not configured, it
3628 * can be a transparent VLAN. So dont report the vlan id.
3629 */
3630 if (!__vlan_find_dev_deep_rcu(rdev->netdev,
3631 htons(ETH_P_8021Q), vlan_id))
3632 return false;
3633 return true;
3634 }
3635
bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe * orig_cqe,u16 * vid,u8 * sl)3636 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe,
3637 u16 *vid, u8 *sl)
3638 {
3639 bool ret = false;
3640 u32 metadata;
3641 u16 tpid;
3642
3643 metadata = orig_cqe->raweth_qp1_metadata;
3644 if (orig_cqe->raweth_qp1_flags2 &
3645 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) {
3646 tpid = ((metadata &
3647 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >>
3648 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT);
3649 if (tpid == ETH_P_8021Q) {
3650 *vid = metadata &
3651 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK;
3652 *sl = (metadata &
3653 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >>
3654 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT;
3655 ret = true;
3656 }
3657 }
3658
3659 return ret;
3660 }
3661
bnxt_re_process_res_rc_wc(struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3662 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc,
3663 struct bnxt_qplib_cqe *cqe)
3664 {
3665 wc->opcode = IB_WC_RECV;
3666 wc->status = __rc_to_ib_wc_status(cqe->status);
3667
3668 if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
3669 wc->wc_flags |= IB_WC_WITH_IMM;
3670 if (cqe->flags & CQ_RES_RC_FLAGS_INV)
3671 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3672 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
3673 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
3674 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
3675 }
3676
bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp * gsi_sqp,struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3677 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp,
3678 struct ib_wc *wc,
3679 struct bnxt_qplib_cqe *cqe)
3680 {
3681 struct bnxt_re_dev *rdev = gsi_sqp->rdev;
3682 struct bnxt_re_qp *gsi_qp = NULL;
3683 struct bnxt_qplib_cqe *orig_cqe = NULL;
3684 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3685 int nw_type;
3686 u32 tbl_idx;
3687 u16 vlan_id;
3688 u8 sl;
3689
3690 tbl_idx = cqe->wr_id;
3691
3692 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3693 gsi_qp = sqp_entry->qp1_qp;
3694 orig_cqe = &sqp_entry->cqe;
3695
3696 wc->wr_id = sqp_entry->wrid;
3697 wc->byte_len = orig_cqe->length;
3698 wc->qp = &gsi_qp->ib_qp;
3699
3700 wc->ex.imm_data = cpu_to_be32(orig_cqe->immdata);
3701 wc->src_qp = orig_cqe->src_qp;
3702 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
3703 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) {
3704 if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) {
3705 wc->vlan_id = vlan_id;
3706 wc->sl = sl;
3707 wc->wc_flags |= IB_WC_WITH_VLAN;
3708 }
3709 }
3710 wc->port_num = 1;
3711 wc->vendor_err = orig_cqe->status;
3712
3713 wc->opcode = IB_WC_RECV;
3714 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status);
3715 wc->wc_flags |= IB_WC_GRH;
3716
3717 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags,
3718 orig_cqe->raweth_qp1_flags2);
3719 if (nw_type >= 0) {
3720 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3721 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3722 }
3723 }
3724
bnxt_re_process_res_ud_wc(struct bnxt_re_qp * qp,struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3725 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp,
3726 struct ib_wc *wc,
3727 struct bnxt_qplib_cqe *cqe)
3728 {
3729 struct bnxt_re_dev *rdev;
3730 u16 vlan_id = 0;
3731 u8 nw_type;
3732
3733 rdev = qp->rdev;
3734 wc->opcode = IB_WC_RECV;
3735 wc->status = __rc_to_ib_wc_status(cqe->status);
3736
3737 if (cqe->flags & CQ_RES_UD_FLAGS_IMM)
3738 wc->wc_flags |= IB_WC_WITH_IMM;
3739 /* report only on GSI QP for Thor */
3740 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) {
3741 wc->wc_flags |= IB_WC_GRH;
3742 memcpy(wc->smac, cqe->smac, ETH_ALEN);
3743 wc->wc_flags |= IB_WC_WITH_SMAC;
3744 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) {
3745 vlan_id = (cqe->cfa_meta & 0xFFF);
3746 }
3747 /* Mark only if vlan_id is non zero */
3748 if (vlan_id && bnxt_re_check_if_vlan_valid(rdev, vlan_id)) {
3749 wc->vlan_id = vlan_id;
3750 wc->wc_flags |= IB_WC_WITH_VLAN;
3751 }
3752 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >>
3753 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT;
3754 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3755 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3756 }
3757
3758 }
3759
send_phantom_wqe(struct bnxt_re_qp * qp)3760 static int send_phantom_wqe(struct bnxt_re_qp *qp)
3761 {
3762 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp;
3763 unsigned long flags;
3764 int rc;
3765
3766 spin_lock_irqsave(&qp->sq_lock, flags);
3767
3768 rc = bnxt_re_bind_fence_mw(lib_qp);
3769 if (!rc) {
3770 lib_qp->sq.phantom_wqe_cnt++;
3771 ibdev_dbg(&qp->rdev->ibdev,
3772 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n",
3773 lib_qp->id, lib_qp->sq.hwq.prod,
3774 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq),
3775 lib_qp->sq.phantom_wqe_cnt);
3776 }
3777
3778 spin_unlock_irqrestore(&qp->sq_lock, flags);
3779 return rc;
3780 }
3781
bnxt_re_poll_cq(struct ib_cq * ib_cq,int num_entries,struct ib_wc * wc)3782 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc)
3783 {
3784 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3785 struct bnxt_re_qp *qp, *sh_qp;
3786 struct bnxt_qplib_cqe *cqe;
3787 int i, ncqe, budget;
3788 struct bnxt_qplib_q *sq;
3789 struct bnxt_qplib_qp *lib_qp;
3790 u32 tbl_idx;
3791 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3792 unsigned long flags;
3793
3794 /* User CQ; the only processing we do is to
3795 * complete any pending CQ resize operation.
3796 */
3797 if (cq->umem) {
3798 if (cq->resize_umem)
3799 bnxt_re_resize_cq_complete(cq);
3800 return 0;
3801 }
3802
3803 spin_lock_irqsave(&cq->cq_lock, flags);
3804 budget = min_t(u32, num_entries, cq->max_cql);
3805 num_entries = budget;
3806 if (!cq->cql) {
3807 ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use");
3808 goto exit;
3809 }
3810 cqe = &cq->cql[0];
3811 while (budget) {
3812 lib_qp = NULL;
3813 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp);
3814 if (lib_qp) {
3815 sq = &lib_qp->sq;
3816 if (sq->send_phantom) {
3817 qp = container_of(lib_qp,
3818 struct bnxt_re_qp, qplib_qp);
3819 if (send_phantom_wqe(qp) == -ENOMEM)
3820 ibdev_err(&cq->rdev->ibdev,
3821 "Phantom failed! Scheduled to send again\n");
3822 else
3823 sq->send_phantom = false;
3824 }
3825 }
3826 if (ncqe < budget)
3827 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq,
3828 cqe + ncqe,
3829 budget - ncqe);
3830
3831 if (!ncqe)
3832 break;
3833
3834 for (i = 0; i < ncqe; i++, cqe++) {
3835 /* Transcribe each qplib_wqe back to ib_wc */
3836 memset(wc, 0, sizeof(*wc));
3837
3838 wc->wr_id = cqe->wr_id;
3839 wc->byte_len = cqe->length;
3840 qp = container_of
3841 ((struct bnxt_qplib_qp *)
3842 (unsigned long)(cqe->qp_handle),
3843 struct bnxt_re_qp, qplib_qp);
3844 wc->qp = &qp->ib_qp;
3845 if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
3846 wc->ex.imm_data = cpu_to_be32(cqe->immdata);
3847 else
3848 wc->ex.invalidate_rkey = cqe->invrkey;
3849 wc->src_qp = cqe->src_qp;
3850 memcpy(wc->smac, cqe->smac, ETH_ALEN);
3851 wc->port_num = 1;
3852 wc->vendor_err = cqe->status;
3853
3854 switch (cqe->opcode) {
3855 case CQ_BASE_CQE_TYPE_REQ:
3856 sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3857 if (sh_qp &&
3858 qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3859 /* Handle this completion with
3860 * the stored completion
3861 */
3862 memset(wc, 0, sizeof(*wc));
3863 continue;
3864 }
3865 bnxt_re_process_req_wc(wc, cqe);
3866 break;
3867 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
3868 if (!cqe->status) {
3869 int rc = 0;
3870
3871 rc = bnxt_re_process_raw_qp_pkt_rx
3872 (qp, cqe);
3873 if (!rc) {
3874 memset(wc, 0, sizeof(*wc));
3875 continue;
3876 }
3877 cqe->status = -1;
3878 }
3879 /* Errors need not be looped back.
3880 * But change the wr_id to the one
3881 * stored in the table
3882 */
3883 tbl_idx = cqe->wr_id;
3884 sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx];
3885 wc->wr_id = sqp_entry->wrid;
3886 bnxt_re_process_res_rawqp1_wc(wc, cqe);
3887 break;
3888 case CQ_BASE_CQE_TYPE_RES_RC:
3889 bnxt_re_process_res_rc_wc(wc, cqe);
3890 break;
3891 case CQ_BASE_CQE_TYPE_RES_UD:
3892 sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3893 if (sh_qp &&
3894 qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3895 /* Handle this completion with
3896 * the stored completion
3897 */
3898 if (cqe->status) {
3899 continue;
3900 } else {
3901 bnxt_re_process_res_shadow_qp_wc
3902 (qp, wc, cqe);
3903 break;
3904 }
3905 }
3906 bnxt_re_process_res_ud_wc(qp, wc, cqe);
3907 break;
3908 default:
3909 ibdev_err(&cq->rdev->ibdev,
3910 "POLL CQ : type 0x%x not handled",
3911 cqe->opcode);
3912 continue;
3913 }
3914 wc++;
3915 budget--;
3916 }
3917 }
3918 exit:
3919 spin_unlock_irqrestore(&cq->cq_lock, flags);
3920 return num_entries - budget;
3921 }
3922
bnxt_re_req_notify_cq(struct ib_cq * ib_cq,enum ib_cq_notify_flags ib_cqn_flags)3923 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
3924 enum ib_cq_notify_flags ib_cqn_flags)
3925 {
3926 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3927 int type = 0, rc = 0;
3928 unsigned long flags;
3929
3930 spin_lock_irqsave(&cq->cq_lock, flags);
3931 /* Trigger on the very next completion */
3932 if (ib_cqn_flags & IB_CQ_NEXT_COMP)
3933 type = DBC_DBC_TYPE_CQ_ARMALL;
3934 /* Trigger on the next solicited completion */
3935 else if (ib_cqn_flags & IB_CQ_SOLICITED)
3936 type = DBC_DBC_TYPE_CQ_ARMSE;
3937
3938 /* Poll to see if there are missed events */
3939 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
3940 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) {
3941 rc = 1;
3942 goto exit;
3943 }
3944 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type);
3945
3946 exit:
3947 spin_unlock_irqrestore(&cq->cq_lock, flags);
3948 return rc;
3949 }
3950
3951 /* Memory Regions */
bnxt_re_get_dma_mr(struct ib_pd * ib_pd,int mr_access_flags)3952 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags)
3953 {
3954 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3955 struct bnxt_re_dev *rdev = pd->rdev;
3956 struct bnxt_re_mr *mr;
3957 u32 active_mrs;
3958 int rc;
3959
3960 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3961 if (!mr)
3962 return ERR_PTR(-ENOMEM);
3963
3964 mr->rdev = rdev;
3965 mr->qplib_mr.pd = &pd->qplib_pd;
3966 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags);
3967 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3968
3969 if (mr_access_flags & IB_ACCESS_RELAXED_ORDERING)
3970 bnxt_re_check_and_set_relaxed_ordering(rdev, &mr->qplib_mr);
3971
3972 /* Allocate and register 0 as the address */
3973 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3974 if (rc)
3975 goto fail;
3976
3977 mr->qplib_mr.hwq.level = PBL_LVL_MAX;
3978 mr->qplib_mr.total_size = -1; /* Infinte length */
3979 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 0,
3980 PAGE_SIZE);
3981 if (rc)
3982 goto fail_mr;
3983
3984 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3985 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ |
3986 IB_ACCESS_REMOTE_ATOMIC))
3987 mr->ib_mr.rkey = mr->ib_mr.lkey;
3988 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count);
3989 if (active_mrs > rdev->stats.res.mr_watermark)
3990 rdev->stats.res.mr_watermark = active_mrs;
3991
3992 return &mr->ib_mr;
3993
3994 fail_mr:
3995 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3996 fail:
3997 kfree(mr);
3998 return ERR_PTR(rc);
3999 }
4000
bnxt_re_dereg_mr(struct ib_mr * ib_mr,struct ib_udata * udata)4001 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
4002 {
4003 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
4004 struct bnxt_re_dev *rdev = mr->rdev;
4005 int rc;
4006
4007 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
4008 if (rc) {
4009 ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc);
4010 return rc;
4011 }
4012
4013 if (mr->pages) {
4014 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
4015 &mr->qplib_frpl);
4016 kfree(mr->pages);
4017 mr->npages = 0;
4018 mr->pages = NULL;
4019 }
4020 ib_umem_release(mr->ib_umem);
4021
4022 kfree(mr);
4023 atomic_dec(&rdev->stats.res.mr_count);
4024 return rc;
4025 }
4026
bnxt_re_set_page(struct ib_mr * ib_mr,u64 addr)4027 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr)
4028 {
4029 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
4030
4031 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs))
4032 return -ENOMEM;
4033
4034 mr->pages[mr->npages++] = addr;
4035 return 0;
4036 }
4037
bnxt_re_map_mr_sg(struct ib_mr * ib_mr,struct scatterlist * sg,int sg_nents,unsigned int * sg_offset)4038 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents,
4039 unsigned int *sg_offset)
4040 {
4041 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
4042
4043 mr->npages = 0;
4044 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page);
4045 }
4046
bnxt_re_alloc_mr(struct ib_pd * ib_pd,enum ib_mr_type type,u32 max_num_sg)4047 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type,
4048 u32 max_num_sg)
4049 {
4050 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4051 struct bnxt_re_dev *rdev = pd->rdev;
4052 struct bnxt_re_mr *mr = NULL;
4053 u32 active_mrs;
4054 int rc;
4055
4056 if (type != IB_MR_TYPE_MEM_REG) {
4057 ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type);
4058 return ERR_PTR(-EINVAL);
4059 }
4060 if (max_num_sg > MAX_PBL_LVL_1_PGS)
4061 return ERR_PTR(-EINVAL);
4062
4063 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
4064 if (!mr)
4065 return ERR_PTR(-ENOMEM);
4066
4067 mr->rdev = rdev;
4068 mr->qplib_mr.pd = &pd->qplib_pd;
4069 mr->qplib_mr.access_flags = BNXT_QPLIB_FR_PMR;
4070 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
4071
4072 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
4073 if (rc)
4074 goto bail;
4075
4076 mr->ib_mr.lkey = mr->qplib_mr.lkey;
4077 mr->ib_mr.rkey = mr->ib_mr.lkey;
4078
4079 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
4080 if (!mr->pages) {
4081 rc = -ENOMEM;
4082 goto fail;
4083 }
4084 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res,
4085 &mr->qplib_frpl, max_num_sg);
4086 if (rc) {
4087 ibdev_err(&rdev->ibdev,
4088 "Failed to allocate HW FR page list");
4089 goto fail_mr;
4090 }
4091
4092 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count);
4093 if (active_mrs > rdev->stats.res.mr_watermark)
4094 rdev->stats.res.mr_watermark = active_mrs;
4095 return &mr->ib_mr;
4096
4097 fail_mr:
4098 kfree(mr->pages);
4099 fail:
4100 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
4101 bail:
4102 kfree(mr);
4103 return ERR_PTR(rc);
4104 }
4105
bnxt_re_alloc_mw(struct ib_pd * ib_pd,enum ib_mw_type type,struct ib_udata * udata)4106 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type,
4107 struct ib_udata *udata)
4108 {
4109 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4110 struct bnxt_re_dev *rdev = pd->rdev;
4111 struct bnxt_re_mw *mw;
4112 u32 active_mws;
4113 int rc;
4114
4115 mw = kzalloc(sizeof(*mw), GFP_KERNEL);
4116 if (!mw)
4117 return ERR_PTR(-ENOMEM);
4118 mw->rdev = rdev;
4119 mw->qplib_mw.pd = &pd->qplib_pd;
4120
4121 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ?
4122 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 :
4123 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B);
4124 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw);
4125 if (rc) {
4126 ibdev_err(&rdev->ibdev, "Allocate MW failed!");
4127 goto fail;
4128 }
4129 mw->ib_mw.rkey = mw->qplib_mw.rkey;
4130
4131 active_mws = atomic_inc_return(&rdev->stats.res.mw_count);
4132 if (active_mws > rdev->stats.res.mw_watermark)
4133 rdev->stats.res.mw_watermark = active_mws;
4134 return &mw->ib_mw;
4135
4136 fail:
4137 kfree(mw);
4138 return ERR_PTR(rc);
4139 }
4140
bnxt_re_dealloc_mw(struct ib_mw * ib_mw)4141 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw)
4142 {
4143 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw);
4144 struct bnxt_re_dev *rdev = mw->rdev;
4145 int rc;
4146
4147 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw);
4148 if (rc) {
4149 ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc);
4150 return rc;
4151 }
4152
4153 kfree(mw);
4154 atomic_dec(&rdev->stats.res.mw_count);
4155 return rc;
4156 }
4157
__bnxt_re_user_reg_mr(struct ib_pd * ib_pd,u64 length,u64 virt_addr,int mr_access_flags,struct ib_umem * umem)4158 static struct ib_mr *__bnxt_re_user_reg_mr(struct ib_pd *ib_pd, u64 length, u64 virt_addr,
4159 int mr_access_flags, struct ib_umem *umem)
4160 {
4161 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4162 struct bnxt_re_dev *rdev = pd->rdev;
4163 unsigned long page_size;
4164 struct bnxt_re_mr *mr;
4165 int umem_pgs, rc;
4166 u32 active_mrs;
4167
4168 if (length > BNXT_RE_MAX_MR_SIZE) {
4169 ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n",
4170 length, BNXT_RE_MAX_MR_SIZE);
4171 return ERR_PTR(-ENOMEM);
4172 }
4173
4174 page_size = ib_umem_find_best_pgsz(umem, BNXT_RE_PAGE_SIZE_SUPPORTED, virt_addr);
4175 if (!page_size) {
4176 ibdev_err(&rdev->ibdev, "umem page size unsupported!");
4177 return ERR_PTR(-EINVAL);
4178 }
4179
4180 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
4181 if (!mr)
4182 return ERR_PTR(-ENOMEM);
4183
4184 mr->rdev = rdev;
4185 mr->qplib_mr.pd = &pd->qplib_pd;
4186 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags);
4187 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR;
4188
4189 if (!_is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags)) {
4190 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
4191 if (rc) {
4192 ibdev_err(&rdev->ibdev, "Failed to allocate MR rc = %d", rc);
4193 rc = -EIO;
4194 goto free_mr;
4195 }
4196 /* The fixed portion of the rkey is the same as the lkey */
4197 mr->ib_mr.rkey = mr->qplib_mr.rkey;
4198 } else {
4199 mr->qplib_mr.flags = CMDQ_REGISTER_MR_FLAGS_ALLOC_MR;
4200 }
4201 mr->ib_umem = umem;
4202 mr->qplib_mr.va = virt_addr;
4203 mr->qplib_mr.total_size = length;
4204
4205 if (mr_access_flags & IB_ACCESS_RELAXED_ORDERING)
4206 bnxt_re_check_and_set_relaxed_ordering(rdev, &mr->qplib_mr);
4207
4208 umem_pgs = ib_umem_num_dma_blocks(umem, page_size);
4209 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, umem,
4210 umem_pgs, page_size);
4211 if (rc) {
4212 ibdev_err(&rdev->ibdev, "Failed to register user MR - rc = %d\n", rc);
4213 rc = -EIO;
4214 goto free_mrw;
4215 }
4216
4217 mr->ib_mr.lkey = mr->qplib_mr.lkey;
4218 mr->ib_mr.rkey = mr->qplib_mr.lkey;
4219 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count);
4220 if (active_mrs > rdev->stats.res.mr_watermark)
4221 rdev->stats.res.mr_watermark = active_mrs;
4222
4223 return &mr->ib_mr;
4224
4225 free_mrw:
4226 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
4227 free_mr:
4228 kfree(mr);
4229 return ERR_PTR(rc);
4230 }
4231
bnxt_re_reg_user_mr(struct ib_pd * ib_pd,u64 start,u64 length,u64 virt_addr,int mr_access_flags,struct ib_dmah * dmah,struct ib_udata * udata)4232 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length,
4233 u64 virt_addr, int mr_access_flags,
4234 struct ib_dmah *dmah,
4235 struct ib_udata *udata)
4236 {
4237 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4238 struct bnxt_re_dev *rdev = pd->rdev;
4239 struct ib_umem *umem;
4240 struct ib_mr *ib_mr;
4241
4242 if (dmah)
4243 return ERR_PTR(-EOPNOTSUPP);
4244
4245 umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags);
4246 if (IS_ERR(umem))
4247 return ERR_CAST(umem);
4248
4249 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem);
4250 if (IS_ERR(ib_mr))
4251 ib_umem_release(umem);
4252 return ib_mr;
4253 }
4254
bnxt_re_reg_user_mr_dmabuf(struct ib_pd * ib_pd,u64 start,u64 length,u64 virt_addr,int fd,int mr_access_flags,struct ib_dmah * dmah,struct uverbs_attr_bundle * attrs)4255 struct ib_mr *bnxt_re_reg_user_mr_dmabuf(struct ib_pd *ib_pd, u64 start,
4256 u64 length, u64 virt_addr, int fd,
4257 int mr_access_flags,
4258 struct ib_dmah *dmah,
4259 struct uverbs_attr_bundle *attrs)
4260 {
4261 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4262 struct bnxt_re_dev *rdev = pd->rdev;
4263 struct ib_umem_dmabuf *umem_dmabuf;
4264 struct ib_umem *umem;
4265 struct ib_mr *ib_mr;
4266
4267 if (dmah)
4268 return ERR_PTR(-EOPNOTSUPP);
4269
4270 umem_dmabuf = ib_umem_dmabuf_get_pinned(&rdev->ibdev, start, length,
4271 fd, mr_access_flags);
4272 if (IS_ERR(umem_dmabuf))
4273 return ERR_CAST(umem_dmabuf);
4274
4275 umem = &umem_dmabuf->umem;
4276
4277 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem);
4278 if (IS_ERR(ib_mr))
4279 ib_umem_release(umem);
4280 return ib_mr;
4281 }
4282
bnxt_re_alloc_ucontext(struct ib_ucontext * ctx,struct ib_udata * udata)4283 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata)
4284 {
4285 struct ib_device *ibdev = ctx->device;
4286 struct bnxt_re_ucontext *uctx =
4287 container_of(ctx, struct bnxt_re_ucontext, ib_uctx);
4288 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
4289 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr;
4290 struct bnxt_re_user_mmap_entry *entry;
4291 struct bnxt_re_uctx_resp resp = {};
4292 struct bnxt_re_uctx_req ureq = {};
4293 u32 chip_met_rev_num = 0;
4294 int rc;
4295
4296 ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver);
4297
4298 if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) {
4299 ibdev_dbg(ibdev, " is different from the device %d ",
4300 BNXT_RE_ABI_VERSION);
4301 return -EPERM;
4302 }
4303
4304 uctx->rdev = rdev;
4305
4306 uctx->shpg = (void *)__get_free_page(GFP_KERNEL);
4307 if (!uctx->shpg) {
4308 rc = -ENOMEM;
4309 goto fail;
4310 }
4311 spin_lock_init(&uctx->sh_lock);
4312
4313 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX;
4314 chip_met_rev_num = rdev->chip_ctx->chip_num;
4315 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) <<
4316 BNXT_RE_CHIP_ID0_CHIP_REV_SFT;
4317 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) <<
4318 BNXT_RE_CHIP_ID0_CHIP_MET_SFT;
4319 resp.chip_id0 = chip_met_rev_num;
4320 /*Temp, Use xa_alloc instead */
4321 resp.dev_id = rdev->en_dev->pdev->devfn;
4322 resp.max_qp = rdev->qplib_ctx.qpc_count;
4323 resp.pg_size = PAGE_SIZE;
4324 resp.cqe_sz = sizeof(struct cq_base);
4325 resp.max_cqd = dev_attr->max_cq_wqes;
4326
4327 if (rdev->chip_ctx->modes.db_push)
4328 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_WC_DPI_ENABLED;
4329
4330 entry = bnxt_re_mmap_entry_insert(uctx, 0, BNXT_RE_MMAP_SH_PAGE, NULL);
4331 if (!entry) {
4332 rc = -ENOMEM;
4333 goto cfail;
4334 }
4335 uctx->shpage_mmap = &entry->rdma_entry;
4336 if (rdev->pacing.dbr_pacing)
4337 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED;
4338
4339 if (_is_host_msn_table(rdev->qplib_res.dattr->dev_cap_flags2))
4340 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_MSN_TABLE_ENABLED;
4341
4342 if (udata->inlen >= sizeof(ureq)) {
4343 rc = ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq)));
4344 if (rc)
4345 goto cfail;
4346 if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT) {
4347 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED;
4348 uctx->cmask |= BNXT_RE_UCNTX_CAP_POW2_DISABLED;
4349 }
4350 if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_VAR_WQE_SUPPORT) {
4351 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_HAVE_MODE;
4352 resp.mode = rdev->chip_ctx->modes.wqe_mode;
4353 if (resp.mode == BNXT_QPLIB_WQE_MODE_VARIABLE)
4354 uctx->cmask |= BNXT_RE_UCNTX_CAP_VAR_WQE_ENABLED;
4355 }
4356 }
4357
4358 rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
4359 if (rc) {
4360 ibdev_err(ibdev, "Failed to copy user context");
4361 rc = -EFAULT;
4362 goto cfail;
4363 }
4364
4365 return 0;
4366 cfail:
4367 free_page((unsigned long)uctx->shpg);
4368 uctx->shpg = NULL;
4369 fail:
4370 return rc;
4371 }
4372
bnxt_re_dealloc_ucontext(struct ib_ucontext * ib_uctx)4373 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx)
4374 {
4375 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
4376 struct bnxt_re_ucontext,
4377 ib_uctx);
4378
4379 struct bnxt_re_dev *rdev = uctx->rdev;
4380
4381 rdma_user_mmap_entry_remove(uctx->shpage_mmap);
4382 uctx->shpage_mmap = NULL;
4383 if (uctx->shpg)
4384 free_page((unsigned long)uctx->shpg);
4385
4386 if (uctx->dpi.dbr) {
4387 /* Free DPI only if this is the first PD allocated by the
4388 * application and mark the context dpi as NULL
4389 */
4390 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->dpi);
4391 uctx->dpi.dbr = NULL;
4392 }
4393 }
4394
bnxt_re_search_for_cq(struct bnxt_re_dev * rdev,u32 cq_id)4395 static struct bnxt_re_cq *bnxt_re_search_for_cq(struct bnxt_re_dev *rdev, u32 cq_id)
4396 {
4397 struct bnxt_re_cq *cq = NULL, *tmp_cq;
4398
4399 hash_for_each_possible(rdev->cq_hash, tmp_cq, hash_entry, cq_id) {
4400 if (tmp_cq->qplib_cq.id == cq_id) {
4401 cq = tmp_cq;
4402 break;
4403 }
4404 }
4405 return cq;
4406 }
4407
bnxt_re_search_for_srq(struct bnxt_re_dev * rdev,u32 srq_id)4408 static struct bnxt_re_srq *bnxt_re_search_for_srq(struct bnxt_re_dev *rdev, u32 srq_id)
4409 {
4410 struct bnxt_re_srq *srq = NULL, *tmp_srq;
4411
4412 hash_for_each_possible(rdev->srq_hash, tmp_srq, hash_entry, srq_id) {
4413 if (tmp_srq->qplib_srq.id == srq_id) {
4414 srq = tmp_srq;
4415 break;
4416 }
4417 }
4418 return srq;
4419 }
4420
4421 /* Helper function to mmap the virtual memory from user app */
bnxt_re_mmap(struct ib_ucontext * ib_uctx,struct vm_area_struct * vma)4422 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)
4423 {
4424 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
4425 struct bnxt_re_ucontext,
4426 ib_uctx);
4427 struct bnxt_re_user_mmap_entry *bnxt_entry;
4428 struct rdma_user_mmap_entry *rdma_entry;
4429 int ret = 0;
4430 u64 pfn;
4431
4432 rdma_entry = rdma_user_mmap_entry_get(&uctx->ib_uctx, vma);
4433 if (!rdma_entry)
4434 return -EINVAL;
4435
4436 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry,
4437 rdma_entry);
4438
4439 switch (bnxt_entry->mmap_flag) {
4440 case BNXT_RE_MMAP_WC_DB:
4441 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT;
4442 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE,
4443 pgprot_writecombine(vma->vm_page_prot),
4444 rdma_entry);
4445 break;
4446 case BNXT_RE_MMAP_UC_DB:
4447 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT;
4448 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE,
4449 pgprot_noncached(vma->vm_page_prot),
4450 rdma_entry);
4451 break;
4452 case BNXT_RE_MMAP_SH_PAGE:
4453 ret = vm_insert_page(vma, vma->vm_start, virt_to_page(uctx->shpg));
4454 break;
4455 case BNXT_RE_MMAP_DBR_BAR:
4456 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT;
4457 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE,
4458 pgprot_noncached(vma->vm_page_prot),
4459 rdma_entry);
4460 break;
4461 case BNXT_RE_MMAP_DBR_PAGE:
4462 case BNXT_RE_MMAP_TOGGLE_PAGE:
4463 /* Driver doesn't expect write access for user space */
4464 if (vma->vm_flags & VM_WRITE)
4465 ret = -EFAULT;
4466 else
4467 ret = vm_insert_page(vma, vma->vm_start,
4468 virt_to_page((void *)bnxt_entry->mem_offset));
4469 break;
4470 default:
4471 ret = -EINVAL;
4472 break;
4473 }
4474
4475 rdma_user_mmap_entry_put(rdma_entry);
4476 return ret;
4477 }
4478
bnxt_re_mmap_free(struct rdma_user_mmap_entry * rdma_entry)4479 void bnxt_re_mmap_free(struct rdma_user_mmap_entry *rdma_entry)
4480 {
4481 struct bnxt_re_user_mmap_entry *bnxt_entry;
4482
4483 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry,
4484 rdma_entry);
4485
4486 kfree(bnxt_entry);
4487 }
4488
bnxt_re_process_mad(struct ib_device * ibdev,int mad_flags,u32 port_num,const struct ib_wc * in_wc,const struct ib_grh * in_grh,const struct ib_mad * in_mad,struct ib_mad * out_mad,size_t * out_mad_size,u16 * out_mad_pkey_index)4489 int bnxt_re_process_mad(struct ib_device *ibdev, int mad_flags,
4490 u32 port_num, const struct ib_wc *in_wc,
4491 const struct ib_grh *in_grh,
4492 const struct ib_mad *in_mad, struct ib_mad *out_mad,
4493 size_t *out_mad_size, u16 *out_mad_pkey_index)
4494 {
4495 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
4496 struct ib_class_port_info cpi = {};
4497 int ret = IB_MAD_RESULT_SUCCESS;
4498 int rc = 0;
4499
4500 if (in_mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_PERF_MGMT)
4501 return ret;
4502
4503 switch (in_mad->mad_hdr.attr_id) {
4504 case IB_PMA_CLASS_PORT_INFO:
4505 cpi.capability_mask = IB_PMA_CLASS_CAP_EXT_WIDTH;
4506 memcpy((out_mad->data + 40), &cpi, sizeof(cpi));
4507 break;
4508 case IB_PMA_PORT_COUNTERS_EXT:
4509 rc = bnxt_re_assign_pma_port_ext_counters(rdev, out_mad);
4510 break;
4511 case IB_PMA_PORT_COUNTERS:
4512 rc = bnxt_re_assign_pma_port_counters(rdev, out_mad);
4513 break;
4514 default:
4515 rc = -EINVAL;
4516 break;
4517 }
4518 if (rc)
4519 return IB_MAD_RESULT_FAILURE;
4520 ret |= IB_MAD_RESULT_REPLY;
4521 return ret;
4522 }
4523
UVERBS_HANDLER(BNXT_RE_METHOD_NOTIFY_DRV)4524 static int UVERBS_HANDLER(BNXT_RE_METHOD_NOTIFY_DRV)(struct uverbs_attr_bundle *attrs)
4525 {
4526 struct bnxt_re_ucontext *uctx;
4527
4528 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx);
4529 bnxt_re_pacing_alert(uctx->rdev);
4530 return 0;
4531 }
4532
UVERBS_HANDLER(BNXT_RE_METHOD_ALLOC_PAGE)4533 static int UVERBS_HANDLER(BNXT_RE_METHOD_ALLOC_PAGE)(struct uverbs_attr_bundle *attrs)
4534 {
4535 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_ALLOC_PAGE_HANDLE);
4536 enum bnxt_re_alloc_page_type alloc_type;
4537 struct bnxt_re_user_mmap_entry *entry;
4538 enum bnxt_re_mmap_flag mmap_flag;
4539 struct bnxt_qplib_chip_ctx *cctx;
4540 struct bnxt_re_ucontext *uctx;
4541 struct bnxt_re_dev *rdev;
4542 u64 mmap_offset;
4543 u32 length;
4544 u32 dpi;
4545 u64 addr;
4546 int err;
4547
4548 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx);
4549 if (IS_ERR(uctx))
4550 return PTR_ERR(uctx);
4551
4552 err = uverbs_get_const(&alloc_type, attrs, BNXT_RE_ALLOC_PAGE_TYPE);
4553 if (err)
4554 return err;
4555
4556 rdev = uctx->rdev;
4557 cctx = rdev->chip_ctx;
4558
4559 switch (alloc_type) {
4560 case BNXT_RE_ALLOC_WC_PAGE:
4561 if (cctx->modes.db_push) {
4562 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, &uctx->wcdpi,
4563 uctx, BNXT_QPLIB_DPI_TYPE_WC))
4564 return -ENOMEM;
4565 length = PAGE_SIZE;
4566 dpi = uctx->wcdpi.dpi;
4567 addr = (u64)uctx->wcdpi.umdbr;
4568 mmap_flag = BNXT_RE_MMAP_WC_DB;
4569 } else {
4570 return -EINVAL;
4571 }
4572
4573 break;
4574 case BNXT_RE_ALLOC_DBR_BAR_PAGE:
4575 length = PAGE_SIZE;
4576 addr = (u64)rdev->pacing.dbr_bar_addr;
4577 mmap_flag = BNXT_RE_MMAP_DBR_BAR;
4578 break;
4579
4580 case BNXT_RE_ALLOC_DBR_PAGE:
4581 length = PAGE_SIZE;
4582 addr = (u64)rdev->pacing.dbr_page;
4583 mmap_flag = BNXT_RE_MMAP_DBR_PAGE;
4584 break;
4585
4586 default:
4587 return -EOPNOTSUPP;
4588 }
4589
4590 entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mmap_offset);
4591 if (!entry)
4592 return -ENOMEM;
4593
4594 uobj->object = entry;
4595 uverbs_finalize_uobj_create(attrs, BNXT_RE_ALLOC_PAGE_HANDLE);
4596 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_OFFSET,
4597 &mmap_offset, sizeof(mmap_offset));
4598 if (err)
4599 return err;
4600
4601 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_LENGTH,
4602 &length, sizeof(length));
4603 if (err)
4604 return err;
4605
4606 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_DPI,
4607 &dpi, sizeof(length));
4608 if (err)
4609 return err;
4610
4611 return 0;
4612 }
4613
alloc_page_obj_cleanup(struct ib_uobject * uobject,enum rdma_remove_reason why,struct uverbs_attr_bundle * attrs)4614 static int alloc_page_obj_cleanup(struct ib_uobject *uobject,
4615 enum rdma_remove_reason why,
4616 struct uverbs_attr_bundle *attrs)
4617 {
4618 struct bnxt_re_user_mmap_entry *entry = uobject->object;
4619 struct bnxt_re_ucontext *uctx = entry->uctx;
4620
4621 switch (entry->mmap_flag) {
4622 case BNXT_RE_MMAP_WC_DB:
4623 if (uctx && uctx->wcdpi.dbr) {
4624 struct bnxt_re_dev *rdev = uctx->rdev;
4625
4626 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->wcdpi);
4627 uctx->wcdpi.dbr = NULL;
4628 }
4629 break;
4630 case BNXT_RE_MMAP_DBR_BAR:
4631 case BNXT_RE_MMAP_DBR_PAGE:
4632 break;
4633 default:
4634 goto exit;
4635 }
4636 rdma_user_mmap_entry_remove(&entry->rdma_entry);
4637 exit:
4638 return 0;
4639 }
4640
4641 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_ALLOC_PAGE,
4642 UVERBS_ATTR_IDR(BNXT_RE_ALLOC_PAGE_HANDLE,
4643 BNXT_RE_OBJECT_ALLOC_PAGE,
4644 UVERBS_ACCESS_NEW,
4645 UA_MANDATORY),
4646 UVERBS_ATTR_CONST_IN(BNXT_RE_ALLOC_PAGE_TYPE,
4647 enum bnxt_re_alloc_page_type,
4648 UA_MANDATORY),
4649 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_OFFSET,
4650 UVERBS_ATTR_TYPE(u64),
4651 UA_MANDATORY),
4652 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_LENGTH,
4653 UVERBS_ATTR_TYPE(u32),
4654 UA_MANDATORY),
4655 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_DPI,
4656 UVERBS_ATTR_TYPE(u32),
4657 UA_MANDATORY));
4658
4659 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_DESTROY_PAGE,
4660 UVERBS_ATTR_IDR(BNXT_RE_DESTROY_PAGE_HANDLE,
4661 BNXT_RE_OBJECT_ALLOC_PAGE,
4662 UVERBS_ACCESS_DESTROY,
4663 UA_MANDATORY));
4664
4665 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_ALLOC_PAGE,
4666 UVERBS_TYPE_ALLOC_IDR(alloc_page_obj_cleanup),
4667 &UVERBS_METHOD(BNXT_RE_METHOD_ALLOC_PAGE),
4668 &UVERBS_METHOD(BNXT_RE_METHOD_DESTROY_PAGE));
4669
4670 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_NOTIFY_DRV);
4671
4672 DECLARE_UVERBS_GLOBAL_METHODS(BNXT_RE_OBJECT_NOTIFY_DRV,
4673 &UVERBS_METHOD(BNXT_RE_METHOD_NOTIFY_DRV));
4674
4675 /* Toggle MEM */
UVERBS_HANDLER(BNXT_RE_METHOD_GET_TOGGLE_MEM)4676 static int UVERBS_HANDLER(BNXT_RE_METHOD_GET_TOGGLE_MEM)(struct uverbs_attr_bundle *attrs)
4677 {
4678 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_TOGGLE_MEM_HANDLE);
4679 enum bnxt_re_mmap_flag mmap_flag = BNXT_RE_MMAP_TOGGLE_PAGE;
4680 enum bnxt_re_get_toggle_mem_type res_type;
4681 struct bnxt_re_user_mmap_entry *entry;
4682 struct bnxt_re_ucontext *uctx;
4683 struct ib_ucontext *ib_uctx;
4684 struct bnxt_re_dev *rdev;
4685 struct bnxt_re_srq *srq;
4686 u32 length = PAGE_SIZE;
4687 struct bnxt_re_cq *cq;
4688 u64 mem_offset;
4689 u32 offset = 0;
4690 u64 addr = 0;
4691 u32 res_id;
4692 int err;
4693
4694 ib_uctx = ib_uverbs_get_ucontext(attrs);
4695 if (IS_ERR(ib_uctx))
4696 return PTR_ERR(ib_uctx);
4697
4698 err = uverbs_get_const(&res_type, attrs, BNXT_RE_TOGGLE_MEM_TYPE);
4699 if (err)
4700 return err;
4701
4702 uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx);
4703 rdev = uctx->rdev;
4704 err = uverbs_copy_from(&res_id, attrs, BNXT_RE_TOGGLE_MEM_RES_ID);
4705 if (err)
4706 return err;
4707
4708 switch (res_type) {
4709 case BNXT_RE_CQ_TOGGLE_MEM:
4710 cq = bnxt_re_search_for_cq(rdev, res_id);
4711 if (!cq)
4712 return -EINVAL;
4713
4714 addr = (u64)cq->uctx_cq_page;
4715 break;
4716 case BNXT_RE_SRQ_TOGGLE_MEM:
4717 srq = bnxt_re_search_for_srq(rdev, res_id);
4718 if (!srq)
4719 return -EINVAL;
4720
4721 addr = (u64)srq->uctx_srq_page;
4722 break;
4723
4724 default:
4725 return -EOPNOTSUPP;
4726 }
4727
4728 entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mem_offset);
4729 if (!entry)
4730 return -ENOMEM;
4731
4732 uobj->object = entry;
4733 uverbs_finalize_uobj_create(attrs, BNXT_RE_TOGGLE_MEM_HANDLE);
4734 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_PAGE,
4735 &mem_offset, sizeof(mem_offset));
4736 if (err)
4737 return err;
4738
4739 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_LENGTH,
4740 &length, sizeof(length));
4741 if (err)
4742 return err;
4743
4744 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_OFFSET,
4745 &offset, sizeof(offset));
4746 if (err)
4747 return err;
4748
4749 return 0;
4750 }
4751
get_toggle_mem_obj_cleanup(struct ib_uobject * uobject,enum rdma_remove_reason why,struct uverbs_attr_bundle * attrs)4752 static int get_toggle_mem_obj_cleanup(struct ib_uobject *uobject,
4753 enum rdma_remove_reason why,
4754 struct uverbs_attr_bundle *attrs)
4755 {
4756 struct bnxt_re_user_mmap_entry *entry = uobject->object;
4757
4758 rdma_user_mmap_entry_remove(&entry->rdma_entry);
4759 return 0;
4760 }
4761
4762 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM,
4763 UVERBS_ATTR_IDR(BNXT_RE_TOGGLE_MEM_HANDLE,
4764 BNXT_RE_OBJECT_GET_TOGGLE_MEM,
4765 UVERBS_ACCESS_NEW,
4766 UA_MANDATORY),
4767 UVERBS_ATTR_CONST_IN(BNXT_RE_TOGGLE_MEM_TYPE,
4768 enum bnxt_re_get_toggle_mem_type,
4769 UA_MANDATORY),
4770 UVERBS_ATTR_PTR_IN(BNXT_RE_TOGGLE_MEM_RES_ID,
4771 UVERBS_ATTR_TYPE(u32),
4772 UA_MANDATORY),
4773 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_PAGE,
4774 UVERBS_ATTR_TYPE(u64),
4775 UA_MANDATORY),
4776 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_OFFSET,
4777 UVERBS_ATTR_TYPE(u32),
4778 UA_MANDATORY),
4779 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_LENGTH,
4780 UVERBS_ATTR_TYPE(u32),
4781 UA_MANDATORY));
4782
4783 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM,
4784 UVERBS_ATTR_IDR(BNXT_RE_RELEASE_TOGGLE_MEM_HANDLE,
4785 BNXT_RE_OBJECT_GET_TOGGLE_MEM,
4786 UVERBS_ACCESS_DESTROY,
4787 UA_MANDATORY));
4788
4789 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_GET_TOGGLE_MEM,
4790 UVERBS_TYPE_ALLOC_IDR(get_toggle_mem_obj_cleanup),
4791 &UVERBS_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM),
4792 &UVERBS_METHOD(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM));
4793
4794 const struct uapi_definition bnxt_re_uapi_defs[] = {
4795 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_ALLOC_PAGE),
4796 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_NOTIFY_DRV),
4797 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_GET_TOGGLE_MEM),
4798 {}
4799 };
4800