1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: Slow Path Operators 37 */ 38 39 #define dev_fmt(fmt) "QPLIB: " fmt 40 41 #include <linux/interrupt.h> 42 #include <linux/spinlock.h> 43 #include <linux/sched.h> 44 #include <linux/pci.h> 45 46 #include "roce_hsi.h" 47 48 #include "qplib_res.h" 49 #include "qplib_rcfw.h" 50 #include "qplib_sp.h" 51 #include "qplib_tlv.h" 52 53 const struct bnxt_qplib_gid bnxt_qplib_gid_zero = {{ 0, 0, 0, 0, 0, 0, 0, 0, 54 0, 0, 0, 0, 0, 0, 0, 0 } }; 55 56 /* Device */ 57 58 static bool bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw *rcfw) 59 { 60 u16 pcie_ctl2 = 0; 61 62 if (!bnxt_qplib_is_chip_gen_p5_p7(rcfw->res->cctx)) 63 return false; 64 65 pcie_capability_read_word(rcfw->pdev, PCI_EXP_DEVCTL2, &pcie_ctl2); 66 return (pcie_ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ); 67 } 68 69 void bnxt_qplib_query_version(struct bnxt_qplib_rcfw *rcfw) 70 { 71 struct creq_query_version_resp resp = {}; 72 struct bnxt_qplib_cmdqmsg msg = {}; 73 struct cmdq_query_version req = {}; 74 struct bnxt_qplib_dev_attr *attr; 75 int rc; 76 77 attr = rcfw->res->dattr; 78 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 79 CMDQ_BASE_OPCODE_QUERY_VERSION, 80 sizeof(req)); 81 82 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0); 83 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 84 if (rc) 85 return; 86 attr->fw_ver[0] = resp.fw_maj; 87 attr->fw_ver[1] = resp.fw_minor; 88 attr->fw_ver[2] = resp.fw_bld; 89 attr->fw_ver[3] = resp.fw_rsvd; 90 } 91 92 int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw) 93 { 94 struct bnxt_qplib_dev_attr *attr = rcfw->res->dattr; 95 struct creq_query_func_resp resp = {}; 96 struct bnxt_qplib_cmdqmsg msg = {}; 97 struct creq_query_func_resp_sb *sb; 98 struct bnxt_qplib_rcfw_sbuf sbuf; 99 struct bnxt_qplib_chip_ctx *cctx; 100 struct cmdq_query_func req = {}; 101 u8 *tqm_alloc; 102 int i, rc; 103 u32 temp; 104 105 cctx = rcfw->res->cctx; 106 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 107 CMDQ_BASE_OPCODE_QUERY_FUNC, 108 sizeof(req)); 109 110 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 111 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 112 &sbuf.dma_addr, GFP_KERNEL); 113 if (!sbuf.sb) 114 return -ENOMEM; 115 sb = sbuf.sb; 116 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 117 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 118 sizeof(resp), 0); 119 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 120 if (rc) 121 goto bail; 122 123 /* Extract the context from the side buffer */ 124 attr->max_qp = le32_to_cpu(sb->max_qp); 125 /* max_qp value reported by FW doesn't include the QP1 */ 126 attr->max_qp += 1; 127 attr->max_qp_rd_atom = 128 sb->max_qp_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 129 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_rd_atom; 130 attr->max_qp_init_rd_atom = 131 sb->max_qp_init_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 132 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_init_rd_atom; 133 attr->max_qp_wqes = le16_to_cpu(sb->max_qp_wr) - 1; 134 if (!bnxt_qplib_is_chip_gen_p5_p7(rcfw->res->cctx)) { 135 /* 136 * 128 WQEs needs to be reserved for the HW (8916). Prevent 137 * reporting the max number on legacy devices 138 */ 139 attr->max_qp_wqes -= BNXT_QPLIB_RESERVED_QP_WRS + 1; 140 } 141 142 /* Adjust for max_qp_wqes for variable wqe */ 143 if (cctx->modes.wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) 144 attr->max_qp_wqes = BNXT_VAR_MAX_WQE - 1; 145 146 attr->max_qp_sges = cctx->modes.wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE ? 147 min_t(u32, sb->max_sge_var_wqe, BNXT_VAR_MAX_SGE) : 6; 148 attr->max_cq = le32_to_cpu(sb->max_cq); 149 attr->max_cq_wqes = le32_to_cpu(sb->max_cqe); 150 if (!bnxt_qplib_is_chip_gen_p7(rcfw->res->cctx)) 151 attr->max_cq_wqes = min_t(u32, BNXT_QPLIB_MAX_CQ_WQES, attr->max_cq_wqes); 152 attr->max_cq_sges = attr->max_qp_sges; 153 attr->max_mr = le32_to_cpu(sb->max_mr); 154 attr->max_mw = le32_to_cpu(sb->max_mw); 155 156 attr->max_mr_size = le64_to_cpu(sb->max_mr_size); 157 attr->max_pd = 64 * 1024; 158 attr->max_raw_ethy_qp = le32_to_cpu(sb->max_raw_eth_qp); 159 attr->max_ah = le32_to_cpu(sb->max_ah); 160 161 attr->max_srq = le16_to_cpu(sb->max_srq); 162 attr->max_srq_wqes = le32_to_cpu(sb->max_srq_wr) - 1; 163 attr->max_srq_sges = sb->max_srq_sge; 164 attr->max_pkey = 1; 165 attr->max_inline_data = attr->max_qp_sges * sizeof(struct sq_sge); 166 if (!bnxt_qplib_is_chip_gen_p7(rcfw->res->cctx)) 167 attr->l2_db_size = (sb->l2_db_space_size + 1) * 168 (0x01 << RCFW_DBR_BASE_PAGE_SHIFT); 169 /* 170 * Read the max gid supported by HW. 171 * For each entry in HW GID in HW table, we consume 2 172 * GID entries in the kernel GID table. So max_gid reported 173 * to stack can be up to twice the value reported by the HW, up to 256 gids. 174 */ 175 attr->max_sgid = le32_to_cpu(sb->max_gid); 176 attr->max_sgid = min_t(u32, BNXT_QPLIB_NUM_GIDS_SUPPORTED, 2 * attr->max_sgid); 177 attr->dev_cap_flags = le16_to_cpu(sb->dev_cap_flags); 178 attr->dev_cap_flags2 = le16_to_cpu(sb->dev_cap_ext_flags_2); 179 180 if (_is_max_srq_ext_supported(attr->dev_cap_flags2)) 181 attr->max_srq += le16_to_cpu(sb->max_srq_ext); 182 183 for (i = 0; i < MAX_TQM_ALLOC_REQ / 4; i++) { 184 temp = le32_to_cpu(sb->tqm_alloc_reqs[i]); 185 tqm_alloc = (u8 *)&temp; 186 attr->tqm_alloc_reqs[i * 4] = *tqm_alloc; 187 attr->tqm_alloc_reqs[i * 4 + 1] = *(++tqm_alloc); 188 attr->tqm_alloc_reqs[i * 4 + 2] = *(++tqm_alloc); 189 attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc); 190 } 191 192 if (rcfw->res->cctx->hwrm_intf_ver >= HWRM_VERSION_DEV_ATTR_MAX_DPI) 193 attr->max_dpi = le32_to_cpu(sb->max_dpi); 194 195 attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw); 196 197 if (_is_modify_qp_rate_limit_supported(attr->dev_cap_flags2)) { 198 attr->rate_limit_min = le16_to_cpu(sb->rate_limit_min); 199 attr->rate_limit_max = le32_to_cpu(sb->rate_limit_max); 200 } 201 bail: 202 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 203 sbuf.sb, sbuf.dma_addr); 204 return rc; 205 } 206 207 int bnxt_qplib_set_func_resources(struct bnxt_qplib_res *res, 208 struct bnxt_qplib_rcfw *rcfw, 209 struct bnxt_qplib_ctx *ctx) 210 { 211 struct creq_set_func_resources_resp resp = {}; 212 struct cmdq_set_func_resources req = {}; 213 struct bnxt_qplib_cmdqmsg msg = {}; 214 int rc; 215 216 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 217 CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES, 218 sizeof(req)); 219 220 req.number_of_qp = cpu_to_le32(ctx->qpc_count); 221 req.number_of_mrw = cpu_to_le32(ctx->mrw_count); 222 req.number_of_srq = cpu_to_le32(ctx->srqc_count); 223 req.number_of_cq = cpu_to_le32(ctx->cq_count); 224 225 req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf); 226 req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf); 227 req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf); 228 req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf); 229 req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf); 230 231 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 232 sizeof(resp), 0); 233 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 234 if (rc) { 235 dev_err(&res->pdev->dev, "Failed to set function resources\n"); 236 } 237 return rc; 238 } 239 240 /* SGID */ 241 int bnxt_qplib_get_sgid(struct bnxt_qplib_res *res, 242 struct bnxt_qplib_sgid_tbl *sgid_tbl, int index, 243 struct bnxt_qplib_gid *gid) 244 { 245 if (index >= sgid_tbl->max) { 246 dev_err(&res->pdev->dev, 247 "Index %d exceeded SGID table max (%d)\n", 248 index, sgid_tbl->max); 249 return -EINVAL; 250 } 251 memcpy(gid, &sgid_tbl->tbl[index].gid, sizeof(*gid)); 252 return 0; 253 } 254 255 int bnxt_qplib_del_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 256 struct bnxt_qplib_gid *gid, u16 vlan_id, bool update) 257 { 258 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 259 struct bnxt_qplib_res, 260 sgid_tbl); 261 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 262 int index; 263 264 /* Do we need a sgid_lock here? */ 265 if (!sgid_tbl->active) { 266 dev_err(&res->pdev->dev, "SGID table has no active entries\n"); 267 return -ENOMEM; 268 } 269 for (index = 0; index < sgid_tbl->max; index++) { 270 if (!memcmp(&sgid_tbl->tbl[index].gid, gid, sizeof(*gid)) && 271 vlan_id == sgid_tbl->tbl[index].vlan_id) 272 break; 273 } 274 if (index == sgid_tbl->max) { 275 dev_warn(&res->pdev->dev, "GID not found in the SGID table\n"); 276 return 0; 277 } 278 /* Remove GID from the SGID table */ 279 if (update) { 280 struct creq_delete_gid_resp resp = {}; 281 struct bnxt_qplib_cmdqmsg msg = {}; 282 struct cmdq_delete_gid req = {}; 283 int rc; 284 285 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 286 CMDQ_BASE_OPCODE_DELETE_GID, 287 sizeof(req)); 288 if (sgid_tbl->hw_id[index] == 0xFFFF) { 289 dev_err(&res->pdev->dev, 290 "GID entry contains an invalid HW id\n"); 291 return -EINVAL; 292 } 293 req.gid_index = cpu_to_le16(sgid_tbl->hw_id[index]); 294 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 295 sizeof(resp), 0); 296 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 297 if (rc) 298 return rc; 299 } 300 memcpy(&sgid_tbl->tbl[index].gid, &bnxt_qplib_gid_zero, 301 sizeof(bnxt_qplib_gid_zero)); 302 sgid_tbl->tbl[index].vlan_id = 0xFFFF; 303 sgid_tbl->vlan[index] = 0; 304 sgid_tbl->active--; 305 dev_dbg(&res->pdev->dev, 306 "SGID deleted hw_id[0x%x] = 0x%x active = 0x%x\n", 307 index, sgid_tbl->hw_id[index], sgid_tbl->active); 308 sgid_tbl->hw_id[index] = (u16)-1; 309 310 /* unlock */ 311 return 0; 312 } 313 314 int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 315 struct bnxt_qplib_gid *gid, const u8 *smac, 316 u16 vlan_id, bool update, u32 *index, 317 bool is_ugid, u32 stats_ctx_id) 318 { 319 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 320 struct bnxt_qplib_res, 321 sgid_tbl); 322 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 323 int i, free_idx; 324 325 /* Do we need a sgid_lock here? */ 326 if (sgid_tbl->active == sgid_tbl->max) { 327 dev_err(&res->pdev->dev, "SGID table is full\n"); 328 return -ENOMEM; 329 } 330 free_idx = sgid_tbl->max; 331 for (i = 0; i < sgid_tbl->max; i++) { 332 if (!memcmp(&sgid_tbl->tbl[i], gid, sizeof(*gid)) && 333 sgid_tbl->tbl[i].vlan_id == vlan_id) { 334 dev_dbg(&res->pdev->dev, 335 "SGID entry already exist in entry %d!\n", i); 336 *index = i; 337 return -EALREADY; 338 } else if (!memcmp(&sgid_tbl->tbl[i], &bnxt_qplib_gid_zero, 339 sizeof(bnxt_qplib_gid_zero)) && 340 free_idx == sgid_tbl->max) { 341 free_idx = i; 342 } 343 } 344 if (free_idx == sgid_tbl->max) { 345 dev_err(&res->pdev->dev, 346 "SGID table is FULL but count is not MAX??\n"); 347 return -ENOMEM; 348 } 349 if (update) { 350 struct creq_add_gid_resp resp = {}; 351 struct bnxt_qplib_cmdqmsg msg = {}; 352 struct cmdq_add_gid req = {}; 353 int rc; 354 355 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 356 CMDQ_BASE_OPCODE_ADD_GID, 357 sizeof(req)); 358 359 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]); 360 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]); 361 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]); 362 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]); 363 /* 364 * driver should ensure that all RoCE traffic is always VLAN 365 * tagged if RoCE traffic is running on non-zero VLAN ID or 366 * RoCE traffic is running on non-zero Priority. 367 */ 368 if ((vlan_id != 0xFFFF) || res->prio) { 369 if (vlan_id != 0xFFFF) 370 req.vlan = cpu_to_le16 371 (vlan_id & CMDQ_ADD_GID_VLAN_VLAN_ID_MASK); 372 req.vlan |= cpu_to_le16 373 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 | 374 CMDQ_ADD_GID_VLAN_VLAN_EN); 375 } 376 377 /* MAC in network format */ 378 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]); 379 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]); 380 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]); 381 382 req.stats_ctx = cpu_to_le16(CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID | 383 (u16)stats_ctx_id); 384 385 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 386 sizeof(resp), 0); 387 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 388 if (rc) 389 return rc; 390 sgid_tbl->hw_id[free_idx] = le32_to_cpu(resp.xid); 391 } 392 /* Add GID to the sgid_tbl */ 393 memcpy(&sgid_tbl->tbl[free_idx], gid, sizeof(*gid)); 394 sgid_tbl->tbl[free_idx].vlan_id = vlan_id; 395 sgid_tbl->active++; 396 if (vlan_id != 0xFFFF) 397 sgid_tbl->vlan[free_idx] = 1; 398 399 dev_dbg(&res->pdev->dev, 400 "SGID added hw_id[0x%x] = 0x%x active = 0x%x\n", 401 free_idx, sgid_tbl->hw_id[free_idx], sgid_tbl->active); 402 403 *index = free_idx; 404 /* unlock */ 405 return 0; 406 } 407 408 /* AH */ 409 int bnxt_qplib_create_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 410 bool block) 411 { 412 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 413 struct creq_create_ah_resp resp = {}; 414 struct bnxt_qplib_cmdqmsg msg = {}; 415 struct cmdq_create_ah req = {}; 416 u32 temp32[4]; 417 u16 temp16[3]; 418 int rc; 419 420 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 421 CMDQ_BASE_OPCODE_CREATE_AH, 422 sizeof(req)); 423 424 memcpy(temp32, ah->dgid.data, sizeof(struct bnxt_qplib_gid)); 425 req.dgid[0] = cpu_to_le32(temp32[0]); 426 req.dgid[1] = cpu_to_le32(temp32[1]); 427 req.dgid[2] = cpu_to_le32(temp32[2]); 428 req.dgid[3] = cpu_to_le32(temp32[3]); 429 430 req.type = ah->nw_type; 431 req.hop_limit = ah->hop_limit; 432 req.sgid_index = cpu_to_le16(res->sgid_tbl.hw_id[ah->sgid_index]); 433 req.dest_vlan_id_flow_label = cpu_to_le32((ah->flow_label & 434 CMDQ_CREATE_AH_FLOW_LABEL_MASK) | 435 CMDQ_CREATE_AH_DEST_VLAN_ID_MASK); 436 req.pd_id = cpu_to_le32(ah->pd->id); 437 req.traffic_class = ah->traffic_class; 438 439 /* MAC in network format */ 440 memcpy(temp16, ah->dmac, 6); 441 req.dest_mac[0] = cpu_to_le16(temp16[0]); 442 req.dest_mac[1] = cpu_to_le16(temp16[1]); 443 req.dest_mac[2] = cpu_to_le16(temp16[2]); 444 445 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 446 sizeof(resp), block); 447 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 448 if (rc) 449 return rc; 450 451 ah->id = le32_to_cpu(resp.xid); 452 return 0; 453 } 454 455 int bnxt_qplib_destroy_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 456 bool block) 457 { 458 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 459 struct creq_destroy_ah_resp resp = {}; 460 struct bnxt_qplib_cmdqmsg msg = {}; 461 struct cmdq_destroy_ah req = {}; 462 int rc; 463 464 /* Clean up the AH table in the device */ 465 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 466 CMDQ_BASE_OPCODE_DESTROY_AH, 467 sizeof(req)); 468 469 req.ah_cid = cpu_to_le32(ah->id); 470 471 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 472 sizeof(resp), block); 473 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 474 return rc; 475 } 476 477 /* MRW */ 478 int bnxt_qplib_free_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 479 { 480 struct creq_deallocate_key_resp resp = {}; 481 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 482 struct cmdq_deallocate_key req = {}; 483 struct bnxt_qplib_cmdqmsg msg = {}; 484 int rc; 485 486 if (mrw->lkey == 0xFFFFFFFF) { 487 dev_info(&res->pdev->dev, "SP: Free a reserved lkey MRW\n"); 488 return 0; 489 } 490 491 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 492 CMDQ_BASE_OPCODE_DEALLOCATE_KEY, 493 sizeof(req)); 494 495 req.mrw_flags = mrw->type; 496 497 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 498 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 499 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 500 req.key = cpu_to_le32(mrw->rkey); 501 else 502 req.key = cpu_to_le32(mrw->lkey); 503 504 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 505 sizeof(resp), 0); 506 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 507 if (rc) 508 return rc; 509 510 /* Free the qplib's MRW memory */ 511 if (mrw->hwq.max_elements) 512 bnxt_qplib_free_hwq(res, &mrw->hwq); 513 514 return 0; 515 } 516 517 int bnxt_qplib_alloc_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 518 { 519 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 520 struct creq_allocate_mrw_resp resp = {}; 521 struct bnxt_qplib_cmdqmsg msg = {}; 522 struct cmdq_allocate_mrw req = {}; 523 unsigned long tmp; 524 int rc; 525 526 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 527 CMDQ_BASE_OPCODE_ALLOCATE_MRW, 528 sizeof(req)); 529 530 req.pd_id = cpu_to_le32(mrw->pd->id); 531 req.mrw_flags = mrw->type; 532 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR && 533 mrw->access_flags & BNXT_QPLIB_FR_PMR) || 534 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A || 535 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B) 536 req.access = CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY; 537 tmp = (unsigned long)mrw; 538 req.mrw_handle = cpu_to_le64(tmp); 539 540 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 541 sizeof(resp), 0); 542 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 543 if (rc) 544 return rc; 545 546 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 547 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 548 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 549 mrw->rkey = le32_to_cpu(resp.xid); 550 else 551 mrw->lkey = le32_to_cpu(resp.xid); 552 return 0; 553 } 554 555 int bnxt_qplib_dereg_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw, 556 bool block) 557 { 558 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 559 struct creq_deregister_mr_resp resp = {}; 560 struct bnxt_qplib_cmdqmsg msg = {}; 561 struct cmdq_deregister_mr req = {}; 562 int rc; 563 564 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 565 CMDQ_BASE_OPCODE_DEREGISTER_MR, 566 sizeof(req)); 567 568 req.lkey = cpu_to_le32(mrw->lkey); 569 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 570 sizeof(resp), block); 571 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 572 if (rc) 573 return rc; 574 575 /* Free the qplib's MR memory */ 576 if (mrw->hwq.max_elements) { 577 mrw->va = 0; 578 mrw->total_size = 0; 579 bnxt_qplib_free_hwq(res, &mrw->hwq); 580 } 581 582 return 0; 583 } 584 585 int bnxt_qplib_reg_mr(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mr, 586 struct ib_umem *umem, int num_pbls, u32 buf_pg_size, bool unified_mr) 587 { 588 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 589 struct bnxt_qplib_hwq_attr hwq_attr = {}; 590 struct bnxt_qplib_sg_info sginfo = {}; 591 struct creq_register_mr_resp resp = {}; 592 struct bnxt_qplib_cmdqmsg msg = {}; 593 struct cmdq_register_mr req = {}; 594 int pages, rc; 595 u32 pg_size; 596 u16 level; 597 598 if (num_pbls) { 599 pages = roundup_pow_of_two(num_pbls); 600 /* Allocate memory for the non-leaf pages to store buf ptrs. 601 * Non-leaf pages always uses system PAGE_SIZE 602 */ 603 /* Free the hwq if it already exist, must be a rereg */ 604 if (mr->hwq.max_elements) 605 bnxt_qplib_free_hwq(res, &mr->hwq); 606 hwq_attr.res = res; 607 hwq_attr.depth = pages; 608 hwq_attr.stride = sizeof(dma_addr_t); 609 hwq_attr.type = HWQ_TYPE_MR; 610 hwq_attr.sginfo = &sginfo; 611 hwq_attr.sginfo->umem = umem; 612 hwq_attr.sginfo->npages = pages; 613 hwq_attr.sginfo->pgsize = buf_pg_size; 614 hwq_attr.sginfo->pgshft = ilog2(buf_pg_size); 615 rc = bnxt_qplib_alloc_init_hwq(&mr->hwq, &hwq_attr); 616 if (rc) { 617 dev_err(&res->pdev->dev, 618 "SP: Reg MR memory allocation failed\n"); 619 return -ENOMEM; 620 } 621 } 622 623 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 624 CMDQ_BASE_OPCODE_REGISTER_MR, 625 sizeof(req)); 626 627 /* Configure the request */ 628 if (mr->hwq.level == PBL_LVL_MAX) { 629 /* No PBL provided, just use system PAGE_SIZE */ 630 level = 0; 631 req.pbl = 0; 632 pg_size = PAGE_SIZE; 633 } else { 634 level = mr->hwq.level; 635 req.pbl = cpu_to_le64(mr->hwq.pbl[PBL_LVL_0].pg_map_arr[0]); 636 } 637 pg_size = buf_pg_size ? buf_pg_size : PAGE_SIZE; 638 req.log2_pg_size_lvl = (level << CMDQ_REGISTER_MR_LVL_SFT) | 639 ((ilog2(pg_size) << 640 CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT) & 641 CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK); 642 req.log2_pbl_pg_size = cpu_to_le16(((ilog2(PAGE_SIZE) << 643 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT) & 644 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK)); 645 req.access = (mr->access_flags & BNXT_QPLIB_MR_ACCESS_MASK); 646 req.va = cpu_to_le64(mr->va); 647 req.key = cpu_to_le32(mr->lkey); 648 if (unified_mr) 649 req.key = cpu_to_le32(mr->pd->id); 650 req.flags = cpu_to_le16(mr->flags); 651 req.mr_size = cpu_to_le64(mr->total_size); 652 653 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 654 sizeof(resp), 0); 655 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 656 if (rc) 657 goto fail; 658 659 if (unified_mr) { 660 mr->lkey = le32_to_cpu(resp.xid); 661 mr->rkey = mr->lkey; 662 } 663 664 return 0; 665 666 fail: 667 if (mr->hwq.max_elements) 668 bnxt_qplib_free_hwq(res, &mr->hwq); 669 return rc; 670 } 671 672 int bnxt_qplib_alloc_fast_reg_page_list(struct bnxt_qplib_res *res, 673 struct bnxt_qplib_frpl *frpl, 674 int max_pg_ptrs) 675 { 676 struct bnxt_qplib_hwq_attr hwq_attr = {}; 677 struct bnxt_qplib_sg_info sginfo = {}; 678 int pg_ptrs, pages, rc; 679 680 /* Re-calculate the max to fit the HWQ allocation model */ 681 pg_ptrs = roundup_pow_of_two(max_pg_ptrs); 682 pages = pg_ptrs >> MAX_PBL_LVL_1_PGS_SHIFT; 683 if (!pages) 684 pages++; 685 686 if (pages > MAX_PBL_LVL_1_PGS) 687 return -ENOMEM; 688 689 sginfo.pgsize = PAGE_SIZE; 690 sginfo.nopte = true; 691 692 hwq_attr.res = res; 693 hwq_attr.depth = pg_ptrs; 694 hwq_attr.stride = PAGE_SIZE; 695 hwq_attr.sginfo = &sginfo; 696 hwq_attr.type = HWQ_TYPE_CTX; 697 rc = bnxt_qplib_alloc_init_hwq(&frpl->hwq, &hwq_attr); 698 if (!rc) 699 frpl->max_pg_ptrs = pg_ptrs; 700 701 return rc; 702 } 703 704 int bnxt_qplib_free_fast_reg_page_list(struct bnxt_qplib_res *res, 705 struct bnxt_qplib_frpl *frpl) 706 { 707 bnxt_qplib_free_hwq(res, &frpl->hwq); 708 return 0; 709 } 710 711 int bnxt_qplib_get_roce_stats(struct bnxt_qplib_rcfw *rcfw, 712 struct bnxt_qplib_roce_stats *stats) 713 { 714 struct creq_query_roce_stats_resp resp = {}; 715 struct creq_query_roce_stats_resp_sb *sb; 716 struct cmdq_query_roce_stats req = {}; 717 struct bnxt_qplib_cmdqmsg msg = {}; 718 struct bnxt_qplib_rcfw_sbuf sbuf; 719 int rc; 720 721 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 722 CMDQ_BASE_OPCODE_QUERY_ROCE_STATS, 723 sizeof(req)); 724 725 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 726 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 727 &sbuf.dma_addr, GFP_KERNEL); 728 if (!sbuf.sb) 729 return -ENOMEM; 730 sb = sbuf.sb; 731 732 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 733 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 734 sizeof(resp), 0); 735 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 736 if (rc) 737 goto bail; 738 /* Extract the context from the side buffer */ 739 stats->to_retransmits = le64_to_cpu(sb->to_retransmits); 740 stats->seq_err_naks_rcvd = le64_to_cpu(sb->seq_err_naks_rcvd); 741 stats->max_retry_exceeded = le64_to_cpu(sb->max_retry_exceeded); 742 stats->rnr_naks_rcvd = le64_to_cpu(sb->rnr_naks_rcvd); 743 stats->missing_resp = le64_to_cpu(sb->missing_resp); 744 stats->unrecoverable_err = le64_to_cpu(sb->unrecoverable_err); 745 stats->bad_resp_err = le64_to_cpu(sb->bad_resp_err); 746 stats->local_qp_op_err = le64_to_cpu(sb->local_qp_op_err); 747 stats->local_protection_err = le64_to_cpu(sb->local_protection_err); 748 stats->mem_mgmt_op_err = le64_to_cpu(sb->mem_mgmt_op_err); 749 stats->remote_invalid_req_err = le64_to_cpu(sb->remote_invalid_req_err); 750 stats->remote_access_err = le64_to_cpu(sb->remote_access_err); 751 stats->remote_op_err = le64_to_cpu(sb->remote_op_err); 752 stats->dup_req = le64_to_cpu(sb->dup_req); 753 stats->res_exceed_max = le64_to_cpu(sb->res_exceed_max); 754 stats->res_length_mismatch = le64_to_cpu(sb->res_length_mismatch); 755 stats->res_exceeds_wqe = le64_to_cpu(sb->res_exceeds_wqe); 756 stats->res_opcode_err = le64_to_cpu(sb->res_opcode_err); 757 stats->res_rx_invalid_rkey = le64_to_cpu(sb->res_rx_invalid_rkey); 758 stats->res_rx_domain_err = le64_to_cpu(sb->res_rx_domain_err); 759 stats->res_rx_no_perm = le64_to_cpu(sb->res_rx_no_perm); 760 stats->res_rx_range_err = le64_to_cpu(sb->res_rx_range_err); 761 stats->res_tx_invalid_rkey = le64_to_cpu(sb->res_tx_invalid_rkey); 762 stats->res_tx_domain_err = le64_to_cpu(sb->res_tx_domain_err); 763 stats->res_tx_no_perm = le64_to_cpu(sb->res_tx_no_perm); 764 stats->res_tx_range_err = le64_to_cpu(sb->res_tx_range_err); 765 stats->res_irrq_oflow = le64_to_cpu(sb->res_irrq_oflow); 766 stats->res_unsup_opcode = le64_to_cpu(sb->res_unsup_opcode); 767 stats->res_unaligned_atomic = le64_to_cpu(sb->res_unaligned_atomic); 768 stats->res_rem_inv_err = le64_to_cpu(sb->res_rem_inv_err); 769 stats->res_mem_error = le64_to_cpu(sb->res_mem_error); 770 stats->res_srq_err = le64_to_cpu(sb->res_srq_err); 771 stats->res_cmp_err = le64_to_cpu(sb->res_cmp_err); 772 stats->res_invalid_dup_rkey = le64_to_cpu(sb->res_invalid_dup_rkey); 773 stats->res_wqe_format_err = le64_to_cpu(sb->res_wqe_format_err); 774 stats->res_cq_load_err = le64_to_cpu(sb->res_cq_load_err); 775 stats->res_srq_load_err = le64_to_cpu(sb->res_srq_load_err); 776 stats->res_tx_pci_err = le64_to_cpu(sb->res_tx_pci_err); 777 stats->res_rx_pci_err = le64_to_cpu(sb->res_rx_pci_err); 778 if (!rcfw->init_oos_stats) { 779 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 780 rcfw->init_oos_stats = 1; 781 } else { 782 stats->res_oos_drop_count += 783 (le64_to_cpu(sb->res_oos_drop_count) - 784 rcfw->oos_prev) & BNXT_QPLIB_OOS_COUNT_MASK; 785 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 786 } 787 788 bail: 789 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 790 sbuf.sb, sbuf.dma_addr); 791 return rc; 792 } 793 794 int bnxt_qplib_qext_stat(struct bnxt_qplib_rcfw *rcfw, u32 fid, 795 struct bnxt_qplib_ext_stat *estat) 796 { 797 struct creq_query_roce_stats_ext_resp resp = {}; 798 struct creq_query_roce_stats_ext_resp_sb *sb; 799 struct cmdq_query_roce_stats_ext req = {}; 800 struct bnxt_qplib_cmdqmsg msg = {}; 801 struct bnxt_qplib_rcfw_sbuf sbuf; 802 int rc; 803 804 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 805 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 806 &sbuf.dma_addr, GFP_KERNEL); 807 if (!sbuf.sb) 808 return -ENOMEM; 809 810 sb = sbuf.sb; 811 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 812 CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS, 813 sizeof(req)); 814 815 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 816 req.resp_addr = cpu_to_le64(sbuf.dma_addr); 817 if (bnxt_qplib_is_chip_gen_p7(rcfw->res->cctx) && rcfw->res->is_vf) 818 req.function_id = 819 cpu_to_le32(CMDQ_QUERY_ROCE_STATS_EXT_VF_VALID | 820 (fid << CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_SFT)); 821 else 822 req.function_id = cpu_to_le32(fid); 823 req.flags = cpu_to_le16(CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID); 824 825 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 826 sizeof(resp), 0); 827 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 828 if (rc) 829 goto bail; 830 831 estat->tx_atomic_req = le64_to_cpu(sb->tx_atomic_req_pkts); 832 estat->tx_read_req = le64_to_cpu(sb->tx_read_req_pkts); 833 estat->tx_read_res = le64_to_cpu(sb->tx_read_res_pkts); 834 estat->tx_write_req = le64_to_cpu(sb->tx_write_req_pkts); 835 estat->tx_send_req = le64_to_cpu(sb->tx_send_req_pkts); 836 estat->tx_roce_pkts = le64_to_cpu(sb->tx_roce_pkts); 837 estat->tx_roce_bytes = le64_to_cpu(sb->tx_roce_bytes); 838 estat->rx_atomic_req = le64_to_cpu(sb->rx_atomic_req_pkts); 839 estat->rx_read_req = le64_to_cpu(sb->rx_read_req_pkts); 840 estat->rx_read_res = le64_to_cpu(sb->rx_read_res_pkts); 841 estat->rx_write_req = le64_to_cpu(sb->rx_write_req_pkts); 842 estat->rx_send_req = le64_to_cpu(sb->rx_send_req_pkts); 843 estat->rx_roce_pkts = le64_to_cpu(sb->rx_roce_pkts); 844 estat->rx_roce_bytes = le64_to_cpu(sb->rx_roce_bytes); 845 estat->rx_roce_good_pkts = le64_to_cpu(sb->rx_roce_good_pkts); 846 estat->rx_roce_good_bytes = le64_to_cpu(sb->rx_roce_good_bytes); 847 estat->rx_out_of_buffer = le64_to_cpu(sb->rx_out_of_buffer_pkts); 848 estat->rx_out_of_sequence = le64_to_cpu(sb->rx_out_of_sequence_pkts); 849 estat->tx_cnp = le64_to_cpu(sb->tx_cnp_pkts); 850 estat->rx_cnp = le64_to_cpu(sb->rx_cnp_pkts); 851 estat->rx_ecn_marked = le64_to_cpu(sb->rx_ecn_marked_pkts); 852 853 bail: 854 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 855 sbuf.sb, sbuf.dma_addr); 856 return rc; 857 } 858 859 static void bnxt_qplib_fill_cc_gen1(struct cmdq_modify_roce_cc_gen1_tlv *ext_req, 860 struct bnxt_qplib_cc_param_ext *cc_ext) 861 { 862 ext_req->modify_mask = cpu_to_le64(cc_ext->ext_mask); 863 cc_ext->ext_mask = 0; 864 ext_req->inactivity_th_hi = cpu_to_le16(cc_ext->inact_th_hi); 865 ext_req->min_time_between_cnps = cpu_to_le16(cc_ext->min_delta_cnp); 866 ext_req->init_cp = cpu_to_le16(cc_ext->init_cp); 867 ext_req->tr_update_mode = cc_ext->tr_update_mode; 868 ext_req->tr_update_cycles = cc_ext->tr_update_cyls; 869 ext_req->fr_num_rtts = cc_ext->fr_rtt; 870 ext_req->ai_rate_increase = cc_ext->ai_rate_incr; 871 ext_req->reduction_relax_rtts_th = cpu_to_le16(cc_ext->rr_rtt_th); 872 ext_req->additional_relax_cr_th = cpu_to_le16(cc_ext->ar_cr_th); 873 ext_req->cr_min_th = cpu_to_le16(cc_ext->cr_min_th); 874 ext_req->bw_avg_weight = cc_ext->bw_avg_weight; 875 ext_req->actual_cr_factor = cc_ext->cr_factor; 876 ext_req->max_cp_cr_th = cpu_to_le16(cc_ext->cr_th_max_cp); 877 ext_req->cp_bias_en = cc_ext->cp_bias_en; 878 ext_req->cp_bias = cc_ext->cp_bias; 879 ext_req->cnp_ecn = cc_ext->cnp_ecn; 880 ext_req->rtt_jitter_en = cc_ext->rtt_jitter_en; 881 ext_req->link_bytes_per_usec = cpu_to_le16(cc_ext->bytes_per_usec); 882 ext_req->reset_cc_cr_th = cpu_to_le16(cc_ext->cc_cr_reset_th); 883 ext_req->cr_width = cc_ext->cr_width; 884 ext_req->quota_period_min = cc_ext->min_quota; 885 ext_req->quota_period_max = cc_ext->max_quota; 886 ext_req->quota_period_abs_max = cc_ext->abs_max_quota; 887 ext_req->tr_lower_bound = cpu_to_le16(cc_ext->tr_lb); 888 ext_req->cr_prob_factor = cc_ext->cr_prob_fac; 889 ext_req->tr_prob_factor = cc_ext->tr_prob_fac; 890 ext_req->fairness_cr_th = cpu_to_le16(cc_ext->fair_cr_th); 891 ext_req->red_div = cc_ext->red_div; 892 ext_req->cnp_ratio_th = cc_ext->cnp_ratio_th; 893 ext_req->exp_ai_rtts = cpu_to_le16(cc_ext->ai_ext_rtt); 894 ext_req->exp_ai_cr_cp_ratio = cc_ext->exp_crcp_ratio; 895 ext_req->use_rate_table = cc_ext->low_rate_en; 896 ext_req->cp_exp_update_th = cpu_to_le16(cc_ext->cpcr_update_th); 897 ext_req->high_exp_ai_rtts_th1 = cpu_to_le16(cc_ext->ai_rtt_th1); 898 ext_req->high_exp_ai_rtts_th2 = cpu_to_le16(cc_ext->ai_rtt_th2); 899 ext_req->actual_cr_cong_free_rtts_th = cpu_to_le16(cc_ext->cf_rtt_th); 900 ext_req->severe_cong_cr_th1 = cpu_to_le16(cc_ext->sc_cr_th1); 901 ext_req->severe_cong_cr_th2 = cpu_to_le16(cc_ext->sc_cr_th2); 902 ext_req->link64B_per_rtt = cpu_to_le32(cc_ext->l64B_per_rtt); 903 ext_req->cc_ack_bytes = cc_ext->cc_ack_bytes; 904 } 905 906 int bnxt_qplib_modify_cc(struct bnxt_qplib_res *res, 907 struct bnxt_qplib_cc_param *cc_param) 908 { 909 struct bnxt_qplib_tlv_modify_cc_req tlv_req = {}; 910 struct creq_modify_roce_cc_resp resp = {}; 911 struct bnxt_qplib_cmdqmsg msg = {}; 912 struct cmdq_modify_roce_cc *req; 913 int req_size; 914 void *cmd; 915 int rc; 916 917 /* Prepare the older base command */ 918 req = &tlv_req.base_req; 919 cmd = req; 920 req_size = sizeof(*req); 921 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)req, CMDQ_BASE_OPCODE_MODIFY_ROCE_CC, 922 sizeof(*req)); 923 req->modify_mask = cpu_to_le32(cc_param->mask); 924 req->enable_cc = cc_param->enable; 925 req->g = cc_param->g; 926 req->num_phases_per_state = cc_param->nph_per_state; 927 req->time_per_phase = cc_param->time_pph; 928 req->pkts_per_phase = cc_param->pkts_pph; 929 req->init_cr = cpu_to_le16(cc_param->init_cr); 930 req->init_tr = cpu_to_le16(cc_param->init_tr); 931 req->tos_dscp_tos_ecn = (cc_param->tos_dscp << CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT) | 932 (cc_param->tos_ecn & CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK); 933 req->alt_vlan_pcp = cc_param->alt_vlan_pcp; 934 req->alt_tos_dscp = cpu_to_le16(cc_param->alt_tos_dscp); 935 req->rtt = cpu_to_le16(cc_param->rtt); 936 req->tcp_cp = cpu_to_le16(cc_param->tcp_cp); 937 req->cc_mode = cc_param->cc_mode; 938 req->inactivity_th = cpu_to_le16(cc_param->inact_th); 939 940 /* For chip gen P5 onwards fill extended cmd and header */ 941 if (bnxt_qplib_is_chip_gen_p5_p7(res->cctx)) { 942 struct roce_tlv *hdr; 943 u32 payload; 944 u32 chunks; 945 946 cmd = &tlv_req; 947 req_size = sizeof(tlv_req); 948 /* Prepare primary tlv header */ 949 hdr = &tlv_req.tlv_hdr; 950 chunks = CHUNKS(sizeof(struct bnxt_qplib_tlv_modify_cc_req)); 951 payload = sizeof(struct cmdq_modify_roce_cc); 952 __roce_1st_tlv_prep(hdr, chunks, payload, true); 953 /* Prepare secondary tlv header */ 954 hdr = (struct roce_tlv *)&tlv_req.ext_req; 955 payload = sizeof(struct cmdq_modify_roce_cc_gen1_tlv) - 956 sizeof(struct roce_tlv); 957 __roce_ext_tlv_prep(hdr, TLV_TYPE_MODIFY_ROCE_CC_GEN1, payload, false, true); 958 bnxt_qplib_fill_cc_gen1(&tlv_req.ext_req, &cc_param->cc_ext); 959 } 960 961 bnxt_qplib_fill_cmdqmsg(&msg, cmd, &resp, NULL, req_size, 962 sizeof(resp), 0); 963 rc = bnxt_qplib_rcfw_send_message(res->rcfw, &msg); 964 return rc; 965 } 966 967 int bnxt_qplib_read_context(struct bnxt_qplib_rcfw *rcfw, u8 res_type, 968 u32 xid, u32 resp_size, void *resp_va) 969 { 970 struct creq_read_context resp = {}; 971 struct bnxt_qplib_cmdqmsg msg = {}; 972 struct cmdq_read_context req = {}; 973 struct bnxt_qplib_rcfw_sbuf sbuf; 974 int rc; 975 976 sbuf.size = resp_size; 977 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 978 &sbuf.dma_addr, GFP_KERNEL); 979 if (!sbuf.sb) 980 return -ENOMEM; 981 982 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 983 CMDQ_BASE_OPCODE_READ_CONTEXT, sizeof(req)); 984 req.resp_addr = cpu_to_le64(sbuf.dma_addr); 985 req.resp_size = resp_size / BNXT_QPLIB_CMDQE_UNITS; 986 987 req.xid = cpu_to_le32(xid); 988 req.type = res_type; 989 990 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 991 sizeof(resp), 0); 992 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 993 if (rc) 994 goto free_mem; 995 996 memcpy(resp_va, sbuf.sb, resp_size); 997 free_mem: 998 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, sbuf.sb, sbuf.dma_addr); 999 return rc; 1000 } 1001 1002 static void bnxt_qplib_read_cc_gen1(struct bnxt_qplib_cc_param_ext *cc_ext, 1003 struct creq_query_roce_cc_gen1_resp_sb_tlv *sb) 1004 { 1005 cc_ext->inact_th_hi = le16_to_cpu(sb->inactivity_th_hi); 1006 cc_ext->min_delta_cnp = le16_to_cpu(sb->min_time_between_cnps); 1007 cc_ext->init_cp = le16_to_cpu(sb->init_cp); 1008 cc_ext->tr_update_mode = sb->tr_update_mode; 1009 cc_ext->tr_update_cyls = sb->tr_update_cycles; 1010 cc_ext->fr_rtt = sb->fr_num_rtts; 1011 cc_ext->ai_rate_incr = sb->ai_rate_increase; 1012 cc_ext->rr_rtt_th = le16_to_cpu(sb->reduction_relax_rtts_th); 1013 cc_ext->ar_cr_th = le16_to_cpu(sb->additional_relax_cr_th); 1014 cc_ext->cr_min_th = le16_to_cpu(sb->cr_min_th); 1015 cc_ext->bw_avg_weight = sb->bw_avg_weight; 1016 cc_ext->cr_factor = sb->actual_cr_factor; 1017 cc_ext->cr_th_max_cp = le16_to_cpu(sb->max_cp_cr_th); 1018 cc_ext->cp_bias_en = sb->cp_bias_en; 1019 cc_ext->cp_bias = sb->cp_bias; 1020 cc_ext->cnp_ecn = sb->cnp_ecn; 1021 cc_ext->rtt_jitter_en = sb->rtt_jitter_en; 1022 cc_ext->bytes_per_usec = le16_to_cpu(sb->link_bytes_per_usec); 1023 cc_ext->cc_cr_reset_th = le16_to_cpu(sb->reset_cc_cr_th); 1024 cc_ext->cr_width = sb->cr_width; 1025 cc_ext->min_quota = sb->quota_period_min; 1026 cc_ext->max_quota = sb->quota_period_max; 1027 cc_ext->abs_max_quota = sb->quota_period_abs_max; 1028 cc_ext->tr_lb = le16_to_cpu(sb->tr_lower_bound); 1029 cc_ext->cr_prob_fac = sb->cr_prob_factor; 1030 cc_ext->tr_prob_fac = sb->tr_prob_factor; 1031 cc_ext->fair_cr_th = le16_to_cpu(sb->fairness_cr_th); 1032 cc_ext->red_div = sb->red_div; 1033 cc_ext->cnp_ratio_th = sb->cnp_ratio_th; 1034 cc_ext->ai_ext_rtt = le16_to_cpu(sb->exp_ai_rtts); 1035 cc_ext->exp_crcp_ratio = sb->exp_ai_cr_cp_ratio; 1036 cc_ext->low_rate_en = sb->use_rate_table; 1037 cc_ext->cpcr_update_th = le16_to_cpu(sb->cp_exp_update_th); 1038 cc_ext->ai_rtt_th1 = le16_to_cpu(sb->high_exp_ai_rtts_th1); 1039 cc_ext->ai_rtt_th2 = le16_to_cpu(sb->high_exp_ai_rtts_th2); 1040 cc_ext->cf_rtt_th = le16_to_cpu(sb->actual_cr_cong_free_rtts_th); 1041 cc_ext->sc_cr_th1 = le16_to_cpu(sb->severe_cong_cr_th1); 1042 cc_ext->sc_cr_th2 = le16_to_cpu(sb->severe_cong_cr_th2); 1043 cc_ext->l64B_per_rtt = le32_to_cpu(sb->link64B_per_rtt); 1044 cc_ext->cc_ack_bytes = sb->cc_ack_bytes; 1045 cc_ext->reduce_cf_rtt_th = le16_to_cpu(sb->reduce_init_cong_free_rtts_th); 1046 } 1047 1048 int bnxt_qplib_query_cc_param(struct bnxt_qplib_res *res, 1049 struct bnxt_qplib_cc_param *cc_param) 1050 { 1051 struct bnxt_qplib_tlv_query_rcc_sb *ext_sb; 1052 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 1053 struct creq_query_roce_cc_resp resp = {}; 1054 struct creq_query_roce_cc_resp_sb *sb; 1055 struct bnxt_qplib_cmdqmsg msg = {}; 1056 struct cmdq_query_roce_cc req = {}; 1057 struct bnxt_qplib_rcfw_sbuf sbuf; 1058 size_t resp_size; 1059 int rc; 1060 1061 /* Query the parameters from chip */ 1062 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, CMDQ_BASE_OPCODE_QUERY_ROCE_CC, 1063 sizeof(req)); 1064 if (bnxt_qplib_is_chip_gen_p5_p7(res->cctx)) 1065 resp_size = sizeof(*ext_sb); 1066 else 1067 resp_size = sizeof(*sb); 1068 1069 sbuf.size = ALIGN(resp_size, BNXT_QPLIB_CMDQE_UNITS); 1070 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 1071 &sbuf.dma_addr, GFP_KERNEL); 1072 if (!sbuf.sb) 1073 return -ENOMEM; 1074 1075 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 1076 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 1077 sizeof(resp), 0); 1078 rc = bnxt_qplib_rcfw_send_message(res->rcfw, &msg); 1079 if (rc) 1080 goto out; 1081 1082 ext_sb = sbuf.sb; 1083 sb = bnxt_qplib_is_chip_gen_p5_p7(res->cctx) ? &ext_sb->base_sb : 1084 (struct creq_query_roce_cc_resp_sb *)ext_sb; 1085 1086 cc_param->enable = sb->enable_cc & CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC; 1087 cc_param->tos_ecn = (sb->tos_dscp_tos_ecn & 1088 CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK) >> 1089 CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT; 1090 cc_param->tos_dscp = (sb->tos_dscp_tos_ecn & 1091 CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK) >> 1092 CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_SFT; 1093 cc_param->alt_tos_dscp = sb->alt_tos_dscp; 1094 cc_param->alt_vlan_pcp = sb->alt_vlan_pcp; 1095 1096 cc_param->g = sb->g; 1097 cc_param->nph_per_state = sb->num_phases_per_state; 1098 cc_param->init_cr = le16_to_cpu(sb->init_cr); 1099 cc_param->init_tr = le16_to_cpu(sb->init_tr); 1100 cc_param->cc_mode = sb->cc_mode; 1101 cc_param->inact_th = le16_to_cpu(sb->inactivity_th); 1102 cc_param->rtt = le16_to_cpu(sb->rtt); 1103 cc_param->tcp_cp = le16_to_cpu(sb->tcp_cp); 1104 cc_param->time_pph = sb->time_per_phase; 1105 cc_param->pkts_pph = sb->pkts_per_phase; 1106 if (bnxt_qplib_is_chip_gen_p5_p7(res->cctx)) { 1107 bnxt_qplib_read_cc_gen1(&cc_param->cc_ext, &ext_sb->gen1_sb); 1108 cc_param->inact_th |= (cc_param->cc_ext.inact_th_hi & 0x3F) << 16; 1109 } 1110 out: 1111 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, sbuf.sb, sbuf.dma_addr); 1112 return rc; 1113 } 1114 1115 int bnxt_qplib_create_flow(struct bnxt_qplib_res *res) 1116 { 1117 struct creq_roce_mirror_cfg_resp resp = {}; 1118 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 1119 struct cmdq_roce_mirror_cfg req = {}; 1120 struct bnxt_qplib_cmdqmsg msg = {}; 1121 1122 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 1123 CMDQ_BASE_OPCODE_ROCE_MIRROR_CFG, 1124 sizeof(req)); 1125 1126 req.mirror_flags = (u8)CMDQ_ROCE_MIRROR_CFG_MIRROR_ENABLE; 1127 1128 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 1129 sizeof(resp), 0); 1130 return bnxt_qplib_rcfw_send_message(rcfw, &msg); 1131 } 1132 1133 int bnxt_qplib_destroy_flow(struct bnxt_qplib_res *res) 1134 { 1135 struct creq_roce_mirror_cfg_resp resp = {}; 1136 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 1137 struct cmdq_roce_mirror_cfg req = {}; 1138 struct bnxt_qplib_cmdqmsg msg = {}; 1139 1140 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 1141 CMDQ_BASE_OPCODE_ROCE_MIRROR_CFG, 1142 sizeof(req)); 1143 1144 req.mirror_flags &= ~((u8)CMDQ_ROCE_MIRROR_CFG_MIRROR_ENABLE); 1145 1146 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 1147 sizeof(resp), 0); 1148 1149 return bnxt_qplib_rcfw_send_message(rcfw, &msg); 1150 } 1151