1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Network device driver for the BMAC ethernet controller on
4 * Apple Powermacs. Assumes it's under a DBDMA controller.
5 *
6 * Copyright (C) 1998 Randy Gobbel.
7 *
8 * May 1999, Al Viro: proper release of /proc/net/bmac entry, switched to
9 * dynamic procfs inode.
10 */
11 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/string.h>
18 #include <linux/timer.h>
19 #include <linux/proc_fs.h>
20 #include <linux/init.h>
21 #include <linux/spinlock.h>
22 #include <linux/crc32.h>
23 #include <linux/bitrev.h>
24 #include <linux/ethtool.h>
25 #include <linux/slab.h>
26 #include <linux/pgtable.h>
27 #include <asm/dbdma.h>
28 #include <asm/io.h>
29 #include <asm/page.h>
30 #include <asm/machdep.h>
31 #include <asm/pmac_feature.h>
32 #include <asm/macio.h>
33 #include <asm/irq.h>
34
35 #include "bmac.h"
36
37 #define trunc_page(x) ((void *)(((unsigned long)(x)) & ~((unsigned long)(PAGE_SIZE - 1))))
38 #define round_page(x) trunc_page(((unsigned long)(x)) + ((unsigned long)(PAGE_SIZE - 1)))
39
40 /* switch to use multicast code lifted from sunhme driver */
41 #define SUNHME_MULTICAST
42
43 #define N_RX_RING 64
44 #define N_TX_RING 32
45 #define MAX_TX_ACTIVE 1
46 #define ETHERCRC 4
47 #define ETHERMINPACKET 64
48 #define ETHERMTU 1500
49 #define RX_BUFLEN (ETHERMTU + 14 + ETHERCRC + 2)
50 #define TX_TIMEOUT HZ /* 1 second */
51
52 /* Bits in transmit DMA status */
53 #define TX_DMA_ERR 0x80
54
55 #define XXDEBUG(args)
56
57 struct bmac_data {
58 /* volatile struct bmac *bmac; */
59 struct sk_buff_head *queue;
60 volatile struct dbdma_regs __iomem *tx_dma;
61 int tx_dma_intr;
62 volatile struct dbdma_regs __iomem *rx_dma;
63 int rx_dma_intr;
64 volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
65 volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
66 struct macio_dev *mdev;
67 int is_bmac_plus;
68 struct sk_buff *rx_bufs[N_RX_RING];
69 int rx_fill;
70 int rx_empty;
71 struct sk_buff *tx_bufs[N_TX_RING];
72 int tx_fill;
73 int tx_empty;
74 unsigned char tx_fullup;
75 struct timer_list tx_timeout;
76 int timeout_active;
77 int sleeping;
78 int opened;
79 unsigned short hash_use_count[64];
80 unsigned short hash_table_mask[4];
81 spinlock_t lock;
82 };
83
84 #if 0 /* Move that to ethtool */
85
86 typedef struct bmac_reg_entry {
87 char *name;
88 unsigned short reg_offset;
89 } bmac_reg_entry_t;
90
91 #define N_REG_ENTRIES 31
92
93 static bmac_reg_entry_t reg_entries[N_REG_ENTRIES] = {
94 {"MEMADD", MEMADD},
95 {"MEMDATAHI", MEMDATAHI},
96 {"MEMDATALO", MEMDATALO},
97 {"TXPNTR", TXPNTR},
98 {"RXPNTR", RXPNTR},
99 {"IPG1", IPG1},
100 {"IPG2", IPG2},
101 {"ALIMIT", ALIMIT},
102 {"SLOT", SLOT},
103 {"PALEN", PALEN},
104 {"PAPAT", PAPAT},
105 {"TXSFD", TXSFD},
106 {"JAM", JAM},
107 {"TXCFG", TXCFG},
108 {"TXMAX", TXMAX},
109 {"TXMIN", TXMIN},
110 {"PAREG", PAREG},
111 {"DCNT", DCNT},
112 {"NCCNT", NCCNT},
113 {"NTCNT", NTCNT},
114 {"EXCNT", EXCNT},
115 {"LTCNT", LTCNT},
116 {"TXSM", TXSM},
117 {"RXCFG", RXCFG},
118 {"RXMAX", RXMAX},
119 {"RXMIN", RXMIN},
120 {"FRCNT", FRCNT},
121 {"AECNT", AECNT},
122 {"FECNT", FECNT},
123 {"RXSM", RXSM},
124 {"RXCV", RXCV}
125 };
126
127 #endif
128
129 static unsigned char *bmac_emergency_rxbuf;
130
131 /*
132 * Number of bytes of private data per BMAC: allow enough for
133 * the rx and tx dma commands plus a branch dma command each,
134 * and another 16 bytes to allow us to align the dma command
135 * buffers on a 16 byte boundary.
136 */
137 #define PRIV_BYTES (sizeof(struct bmac_data) \
138 + (N_RX_RING + N_TX_RING + 4) * sizeof(struct dbdma_cmd) \
139 + sizeof(struct sk_buff_head))
140
141 static int bmac_open(struct net_device *dev);
142 static int bmac_close(struct net_device *dev);
143 static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev);
144 static void bmac_set_multicast(struct net_device *dev);
145 static void bmac_reset_and_enable(struct net_device *dev);
146 static void bmac_start_chip(struct net_device *dev);
147 static void bmac_init_chip(struct net_device *dev);
148 static void bmac_init_registers(struct net_device *dev);
149 static void bmac_enable_and_reset_chip(struct net_device *dev);
150 static int bmac_set_address(struct net_device *dev, void *addr);
151 static irqreturn_t bmac_misc_intr(int irq, void *dev_id);
152 static irqreturn_t bmac_txdma_intr(int irq, void *dev_id);
153 static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id);
154 static void bmac_set_timeout(struct net_device *dev);
155 static void bmac_tx_timeout(struct timer_list *t);
156 static netdev_tx_t bmac_output(struct sk_buff *skb, struct net_device *dev);
157 static void bmac_start(struct net_device *dev);
158
159 #define DBDMA_SET(x) ( ((x) | (x) << 16) )
160 #define DBDMA_CLEAR(x) ( (x) << 16)
161
162 static inline void
dbdma_st32(volatile __u32 __iomem * a,unsigned long x)163 dbdma_st32(volatile __u32 __iomem *a, unsigned long x)
164 {
165 __asm__ volatile( "stwbrx %0,0,%1" : : "r" (x), "r" (a) : "memory");
166 }
167
168 static inline unsigned long
dbdma_ld32(volatile __u32 __iomem * a)169 dbdma_ld32(volatile __u32 __iomem *a)
170 {
171 __u32 swap;
172 __asm__ volatile ("lwbrx %0,0,%1" : "=r" (swap) : "r" (a));
173 return swap;
174 }
175
176 static void
dbdma_continue(volatile struct dbdma_regs __iomem * dmap)177 dbdma_continue(volatile struct dbdma_regs __iomem *dmap)
178 {
179 dbdma_st32(&dmap->control,
180 DBDMA_SET(RUN|WAKE) | DBDMA_CLEAR(PAUSE|DEAD));
181 eieio();
182 }
183
184 static void
dbdma_reset(volatile struct dbdma_regs __iomem * dmap)185 dbdma_reset(volatile struct dbdma_regs __iomem *dmap)
186 {
187 dbdma_st32(&dmap->control,
188 DBDMA_CLEAR(ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN));
189 eieio();
190 while (dbdma_ld32(&dmap->status) & RUN)
191 eieio();
192 }
193
194 static void
dbdma_setcmd(volatile struct dbdma_cmd * cp,unsigned short cmd,unsigned count,unsigned long addr,unsigned long cmd_dep)195 dbdma_setcmd(volatile struct dbdma_cmd *cp,
196 unsigned short cmd, unsigned count, unsigned long addr,
197 unsigned long cmd_dep)
198 {
199 out_le16(&cp->command, cmd);
200 out_le16(&cp->req_count, count);
201 out_le32(&cp->phy_addr, addr);
202 out_le32(&cp->cmd_dep, cmd_dep);
203 out_le16(&cp->xfer_status, 0);
204 out_le16(&cp->res_count, 0);
205 }
206
207 static inline
bmwrite(struct net_device * dev,unsigned long reg_offset,unsigned data)208 void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data )
209 {
210 out_le16((void __iomem *)dev->base_addr + reg_offset, data);
211 }
212
213
214 static inline
bmread(struct net_device * dev,unsigned long reg_offset)215 unsigned short bmread(struct net_device *dev, unsigned long reg_offset )
216 {
217 return in_le16((void __iomem *)dev->base_addr + reg_offset);
218 }
219
220 static void
bmac_enable_and_reset_chip(struct net_device * dev)221 bmac_enable_and_reset_chip(struct net_device *dev)
222 {
223 struct bmac_data *bp = netdev_priv(dev);
224 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
225 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
226
227 if (rd)
228 dbdma_reset(rd);
229 if (td)
230 dbdma_reset(td);
231
232 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 1);
233 }
234
235 #define MIFDELAY udelay(10)
236
237 static unsigned int
bmac_mif_readbits(struct net_device * dev,int nb)238 bmac_mif_readbits(struct net_device *dev, int nb)
239 {
240 unsigned int val = 0;
241
242 while (--nb >= 0) {
243 bmwrite(dev, MIFCSR, 0);
244 MIFDELAY;
245 if (bmread(dev, MIFCSR) & 8)
246 val |= 1 << nb;
247 bmwrite(dev, MIFCSR, 1);
248 MIFDELAY;
249 }
250 bmwrite(dev, MIFCSR, 0);
251 MIFDELAY;
252 bmwrite(dev, MIFCSR, 1);
253 MIFDELAY;
254 return val;
255 }
256
257 static void
bmac_mif_writebits(struct net_device * dev,unsigned int val,int nb)258 bmac_mif_writebits(struct net_device *dev, unsigned int val, int nb)
259 {
260 int b;
261
262 while (--nb >= 0) {
263 b = (val & (1 << nb))? 6: 4;
264 bmwrite(dev, MIFCSR, b);
265 MIFDELAY;
266 bmwrite(dev, MIFCSR, b|1);
267 MIFDELAY;
268 }
269 }
270
271 static unsigned int
bmac_mif_read(struct net_device * dev,unsigned int addr)272 bmac_mif_read(struct net_device *dev, unsigned int addr)
273 {
274 unsigned int val;
275
276 bmwrite(dev, MIFCSR, 4);
277 MIFDELAY;
278 bmac_mif_writebits(dev, ~0U, 32);
279 bmac_mif_writebits(dev, 6, 4);
280 bmac_mif_writebits(dev, addr, 10);
281 bmwrite(dev, MIFCSR, 2);
282 MIFDELAY;
283 bmwrite(dev, MIFCSR, 1);
284 MIFDELAY;
285 val = bmac_mif_readbits(dev, 17);
286 bmwrite(dev, MIFCSR, 4);
287 MIFDELAY;
288 return val;
289 }
290
291 static void
bmac_mif_write(struct net_device * dev,unsigned int addr,unsigned int val)292 bmac_mif_write(struct net_device *dev, unsigned int addr, unsigned int val)
293 {
294 bmwrite(dev, MIFCSR, 4);
295 MIFDELAY;
296 bmac_mif_writebits(dev, ~0U, 32);
297 bmac_mif_writebits(dev, 5, 4);
298 bmac_mif_writebits(dev, addr, 10);
299 bmac_mif_writebits(dev, 2, 2);
300 bmac_mif_writebits(dev, val, 16);
301 bmac_mif_writebits(dev, 3, 2);
302 }
303
304 static void
bmac_init_registers(struct net_device * dev)305 bmac_init_registers(struct net_device *dev)
306 {
307 struct bmac_data *bp = netdev_priv(dev);
308 volatile unsigned short regValue;
309 const unsigned short *pWord16;
310 int i;
311
312 /* XXDEBUG(("bmac: enter init_registers\n")); */
313
314 bmwrite(dev, RXRST, RxResetValue);
315 bmwrite(dev, TXRST, TxResetBit);
316
317 i = 100;
318 do {
319 --i;
320 udelay(10000);
321 regValue = bmread(dev, TXRST); /* wait for reset to clear..acknowledge */
322 } while ((regValue & TxResetBit) && i > 0);
323
324 if (!bp->is_bmac_plus) {
325 regValue = bmread(dev, XCVRIF);
326 regValue |= ClkBit | SerialMode | COLActiveLow;
327 bmwrite(dev, XCVRIF, regValue);
328 udelay(10000);
329 }
330
331 bmwrite(dev, RSEED, (unsigned short)0x1968);
332
333 regValue = bmread(dev, XIFC);
334 regValue |= TxOutputEnable;
335 bmwrite(dev, XIFC, regValue);
336
337 bmread(dev, PAREG);
338
339 /* set collision counters to 0 */
340 bmwrite(dev, NCCNT, 0);
341 bmwrite(dev, NTCNT, 0);
342 bmwrite(dev, EXCNT, 0);
343 bmwrite(dev, LTCNT, 0);
344
345 /* set rx counters to 0 */
346 bmwrite(dev, FRCNT, 0);
347 bmwrite(dev, LECNT, 0);
348 bmwrite(dev, AECNT, 0);
349 bmwrite(dev, FECNT, 0);
350 bmwrite(dev, RXCV, 0);
351
352 /* set tx fifo information */
353 bmwrite(dev, TXTH, 4); /* 4 octets before tx starts */
354
355 bmwrite(dev, TXFIFOCSR, 0); /* first disable txFIFO */
356 bmwrite(dev, TXFIFOCSR, TxFIFOEnable );
357
358 /* set rx fifo information */
359 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
360 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
361
362 //bmwrite(dev, TXCFG, TxMACEnable); /* TxNeverGiveUp maybe later */
363 bmread(dev, STATUS); /* read it just to clear it */
364
365 /* zero out the chip Hash Filter registers */
366 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0;
367 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
368 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
369 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
370 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
371
372 pWord16 = (const unsigned short *)dev->dev_addr;
373 bmwrite(dev, MADD0, *pWord16++);
374 bmwrite(dev, MADD1, *pWord16++);
375 bmwrite(dev, MADD2, *pWord16);
376
377 bmwrite(dev, RXCFG, RxCRCNoStrip | RxHashFilterEnable | RxRejectOwnPackets);
378
379 bmwrite(dev, INTDISABLE, EnableNormal);
380 }
381
382 #if 0
383 static void
384 bmac_disable_interrupts(struct net_device *dev)
385 {
386 bmwrite(dev, INTDISABLE, DisableAll);
387 }
388
389 static void
390 bmac_enable_interrupts(struct net_device *dev)
391 {
392 bmwrite(dev, INTDISABLE, EnableNormal);
393 }
394 #endif
395
396
397 static void
bmac_start_chip(struct net_device * dev)398 bmac_start_chip(struct net_device *dev)
399 {
400 struct bmac_data *bp = netdev_priv(dev);
401 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
402 unsigned short oldConfig;
403
404 /* enable rx dma channel */
405 dbdma_continue(rd);
406
407 oldConfig = bmread(dev, TXCFG);
408 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
409
410 /* turn on rx plus any other bits already on (promiscuous possibly) */
411 oldConfig = bmread(dev, RXCFG);
412 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
413 udelay(20000);
414 }
415
416 static void
bmac_init_phy(struct net_device * dev)417 bmac_init_phy(struct net_device *dev)
418 {
419 unsigned int addr;
420 struct bmac_data *bp = netdev_priv(dev);
421
422 printk(KERN_DEBUG "phy registers:");
423 for (addr = 0; addr < 32; ++addr) {
424 if ((addr & 7) == 0)
425 printk(KERN_DEBUG);
426 printk(KERN_CONT " %.4x", bmac_mif_read(dev, addr));
427 }
428 printk(KERN_CONT "\n");
429
430 if (bp->is_bmac_plus) {
431 unsigned int capable, ctrl;
432
433 ctrl = bmac_mif_read(dev, 0);
434 capable = ((bmac_mif_read(dev, 1) & 0xf800) >> 6) | 1;
435 if (bmac_mif_read(dev, 4) != capable ||
436 (ctrl & 0x1000) == 0) {
437 bmac_mif_write(dev, 4, capable);
438 bmac_mif_write(dev, 0, 0x1200);
439 } else
440 bmac_mif_write(dev, 0, 0x1000);
441 }
442 }
443
bmac_init_chip(struct net_device * dev)444 static void bmac_init_chip(struct net_device *dev)
445 {
446 bmac_init_phy(dev);
447 bmac_init_registers(dev);
448 }
449
450 #ifdef CONFIG_PM
bmac_suspend(struct macio_dev * mdev,pm_message_t state)451 static int bmac_suspend(struct macio_dev *mdev, pm_message_t state)
452 {
453 struct net_device* dev = macio_get_drvdata(mdev);
454 struct bmac_data *bp = netdev_priv(dev);
455 unsigned long flags;
456 unsigned short config;
457 int i;
458
459 netif_device_detach(dev);
460 /* prolly should wait for dma to finish & turn off the chip */
461 spin_lock_irqsave(&bp->lock, flags);
462 if (bp->timeout_active) {
463 timer_delete(&bp->tx_timeout);
464 bp->timeout_active = 0;
465 }
466 disable_irq(dev->irq);
467 disable_irq(bp->tx_dma_intr);
468 disable_irq(bp->rx_dma_intr);
469 bp->sleeping = 1;
470 spin_unlock_irqrestore(&bp->lock, flags);
471 if (bp->opened) {
472 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
473 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
474
475 config = bmread(dev, RXCFG);
476 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
477 config = bmread(dev, TXCFG);
478 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
479 bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
480 /* disable rx and tx dma */
481 rd->control = cpu_to_le32(DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
482 td->control = cpu_to_le32(DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
483 /* free some skb's */
484 for (i=0; i<N_RX_RING; i++) {
485 if (bp->rx_bufs[i] != NULL) {
486 dev_kfree_skb(bp->rx_bufs[i]);
487 bp->rx_bufs[i] = NULL;
488 }
489 }
490 for (i = 0; i<N_TX_RING; i++) {
491 if (bp->tx_bufs[i] != NULL) {
492 dev_kfree_skb(bp->tx_bufs[i]);
493 bp->tx_bufs[i] = NULL;
494 }
495 }
496 }
497 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
498 return 0;
499 }
500
bmac_resume(struct macio_dev * mdev)501 static int bmac_resume(struct macio_dev *mdev)
502 {
503 struct net_device* dev = macio_get_drvdata(mdev);
504 struct bmac_data *bp = netdev_priv(dev);
505
506 /* see if this is enough */
507 if (bp->opened)
508 bmac_reset_and_enable(dev);
509
510 enable_irq(dev->irq);
511 enable_irq(bp->tx_dma_intr);
512 enable_irq(bp->rx_dma_intr);
513 netif_device_attach(dev);
514
515 return 0;
516 }
517 #endif /* CONFIG_PM */
518
bmac_set_address(struct net_device * dev,void * addr)519 static int bmac_set_address(struct net_device *dev, void *addr)
520 {
521 struct bmac_data *bp = netdev_priv(dev);
522 const unsigned short *pWord16;
523 unsigned long flags;
524
525 XXDEBUG(("bmac: enter set_address\n"));
526 spin_lock_irqsave(&bp->lock, flags);
527
528 eth_hw_addr_set(dev, addr);
529
530 /* load up the hardware address */
531 pWord16 = (const unsigned short *)dev->dev_addr;
532 bmwrite(dev, MADD0, *pWord16++);
533 bmwrite(dev, MADD1, *pWord16++);
534 bmwrite(dev, MADD2, *pWord16);
535
536 spin_unlock_irqrestore(&bp->lock, flags);
537 XXDEBUG(("bmac: exit set_address\n"));
538 return 0;
539 }
540
bmac_set_timeout(struct net_device * dev)541 static inline void bmac_set_timeout(struct net_device *dev)
542 {
543 struct bmac_data *bp = netdev_priv(dev);
544 unsigned long flags;
545
546 spin_lock_irqsave(&bp->lock, flags);
547 if (bp->timeout_active)
548 timer_delete(&bp->tx_timeout);
549 bp->tx_timeout.expires = jiffies + TX_TIMEOUT;
550 add_timer(&bp->tx_timeout);
551 bp->timeout_active = 1;
552 spin_unlock_irqrestore(&bp->lock, flags);
553 }
554
555 static void
bmac_construct_xmt(struct sk_buff * skb,volatile struct dbdma_cmd * cp)556 bmac_construct_xmt(struct sk_buff *skb, volatile struct dbdma_cmd *cp)
557 {
558 void *vaddr;
559 unsigned long baddr;
560 unsigned long len;
561
562 len = skb->len;
563 vaddr = skb->data;
564 baddr = virt_to_bus(vaddr);
565
566 dbdma_setcmd(cp, (OUTPUT_LAST | INTR_ALWAYS | WAIT_IFCLR), len, baddr, 0);
567 }
568
569 static void
bmac_construct_rxbuff(struct sk_buff * skb,volatile struct dbdma_cmd * cp)570 bmac_construct_rxbuff(struct sk_buff *skb, volatile struct dbdma_cmd *cp)
571 {
572 unsigned char *addr = skb? skb->data: bmac_emergency_rxbuf;
573
574 dbdma_setcmd(cp, (INPUT_LAST | INTR_ALWAYS), RX_BUFLEN,
575 virt_to_bus(addr), 0);
576 }
577
578 static void
bmac_init_tx_ring(struct bmac_data * bp)579 bmac_init_tx_ring(struct bmac_data *bp)
580 {
581 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
582
583 memset((char *)bp->tx_cmds, 0, (N_TX_RING+1) * sizeof(struct dbdma_cmd));
584
585 bp->tx_empty = 0;
586 bp->tx_fill = 0;
587 bp->tx_fullup = 0;
588
589 /* put a branch at the end of the tx command list */
590 dbdma_setcmd(&bp->tx_cmds[N_TX_RING],
591 (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->tx_cmds));
592
593 /* reset tx dma */
594 dbdma_reset(td);
595 out_le32(&td->wait_sel, 0x00200020);
596 out_le32(&td->cmdptr, virt_to_bus(bp->tx_cmds));
597 }
598
599 static int
bmac_init_rx_ring(struct net_device * dev)600 bmac_init_rx_ring(struct net_device *dev)
601 {
602 struct bmac_data *bp = netdev_priv(dev);
603 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
604 int i;
605 struct sk_buff *skb;
606
607 /* initialize list of sk_buffs for receiving and set up recv dma */
608 memset((char *)bp->rx_cmds, 0,
609 (N_RX_RING + 1) * sizeof(struct dbdma_cmd));
610 for (i = 0; i < N_RX_RING; i++) {
611 if ((skb = bp->rx_bufs[i]) == NULL) {
612 bp->rx_bufs[i] = skb = netdev_alloc_skb(dev, RX_BUFLEN + 2);
613 if (skb != NULL)
614 skb_reserve(skb, 2);
615 }
616 bmac_construct_rxbuff(skb, &bp->rx_cmds[i]);
617 }
618
619 bp->rx_empty = 0;
620 bp->rx_fill = i;
621
622 /* Put a branch back to the beginning of the receive command list */
623 dbdma_setcmd(&bp->rx_cmds[N_RX_RING],
624 (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->rx_cmds));
625
626 /* start rx dma */
627 dbdma_reset(rd);
628 out_le32(&rd->cmdptr, virt_to_bus(bp->rx_cmds));
629
630 return 1;
631 }
632
633
bmac_transmit_packet(struct sk_buff * skb,struct net_device * dev)634 static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev)
635 {
636 struct bmac_data *bp = netdev_priv(dev);
637 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
638 int i;
639
640 /* see if there's a free slot in the tx ring */
641 /* XXDEBUG(("bmac_xmit_start: empty=%d fill=%d\n", */
642 /* bp->tx_empty, bp->tx_fill)); */
643 i = bp->tx_fill + 1;
644 if (i >= N_TX_RING)
645 i = 0;
646 if (i == bp->tx_empty) {
647 netif_stop_queue(dev);
648 bp->tx_fullup = 1;
649 XXDEBUG(("bmac_transmit_packet: tx ring full\n"));
650 return -1; /* can't take it at the moment */
651 }
652
653 dbdma_setcmd(&bp->tx_cmds[i], DBDMA_STOP, 0, 0, 0);
654
655 bmac_construct_xmt(skb, &bp->tx_cmds[bp->tx_fill]);
656
657 bp->tx_bufs[bp->tx_fill] = skb;
658 bp->tx_fill = i;
659
660 dev->stats.tx_bytes += skb->len;
661
662 dbdma_continue(td);
663
664 return 0;
665 }
666
667 static int rxintcount;
668
bmac_rxdma_intr(int irq,void * dev_id)669 static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id)
670 {
671 struct net_device *dev = (struct net_device *) dev_id;
672 struct bmac_data *bp = netdev_priv(dev);
673 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
674 volatile struct dbdma_cmd *cp;
675 int i, nb, stat;
676 struct sk_buff *skb;
677 unsigned int residual;
678 int last;
679 unsigned long flags;
680
681 spin_lock_irqsave(&bp->lock, flags);
682
683 if (++rxintcount < 10) {
684 XXDEBUG(("bmac_rxdma_intr\n"));
685 }
686
687 last = -1;
688 i = bp->rx_empty;
689
690 while (1) {
691 cp = &bp->rx_cmds[i];
692 stat = le16_to_cpu(cp->xfer_status);
693 residual = le16_to_cpu(cp->res_count);
694 if ((stat & ACTIVE) == 0)
695 break;
696 nb = RX_BUFLEN - residual - 2;
697 if (nb < (ETHERMINPACKET - ETHERCRC)) {
698 skb = NULL;
699 dev->stats.rx_length_errors++;
700 dev->stats.rx_errors++;
701 } else {
702 skb = bp->rx_bufs[i];
703 bp->rx_bufs[i] = NULL;
704 }
705 if (skb != NULL) {
706 nb -= ETHERCRC;
707 skb_put(skb, nb);
708 skb->protocol = eth_type_trans(skb, dev);
709 netif_rx(skb);
710 ++dev->stats.rx_packets;
711 dev->stats.rx_bytes += nb;
712 } else {
713 ++dev->stats.rx_dropped;
714 }
715 if ((skb = bp->rx_bufs[i]) == NULL) {
716 bp->rx_bufs[i] = skb = netdev_alloc_skb(dev, RX_BUFLEN + 2);
717 if (skb != NULL)
718 skb_reserve(bp->rx_bufs[i], 2);
719 }
720 bmac_construct_rxbuff(skb, &bp->rx_cmds[i]);
721 cp->res_count = cpu_to_le16(0);
722 cp->xfer_status = cpu_to_le16(0);
723 last = i;
724 if (++i >= N_RX_RING) i = 0;
725 }
726
727 if (last != -1) {
728 bp->rx_fill = last;
729 bp->rx_empty = i;
730 }
731
732 dbdma_continue(rd);
733 spin_unlock_irqrestore(&bp->lock, flags);
734
735 if (rxintcount < 10) {
736 XXDEBUG(("bmac_rxdma_intr done\n"));
737 }
738 return IRQ_HANDLED;
739 }
740
741 static int txintcount;
742
bmac_txdma_intr(int irq,void * dev_id)743 static irqreturn_t bmac_txdma_intr(int irq, void *dev_id)
744 {
745 struct net_device *dev = (struct net_device *) dev_id;
746 struct bmac_data *bp = netdev_priv(dev);
747 volatile struct dbdma_cmd *cp;
748 int stat;
749 unsigned long flags;
750
751 spin_lock_irqsave(&bp->lock, flags);
752
753 if (txintcount++ < 10) {
754 XXDEBUG(("bmac_txdma_intr\n"));
755 }
756
757 /* timer_delete(&bp->tx_timeout); */
758 /* bp->timeout_active = 0; */
759
760 while (1) {
761 cp = &bp->tx_cmds[bp->tx_empty];
762 stat = le16_to_cpu(cp->xfer_status);
763 if (txintcount < 10) {
764 XXDEBUG(("bmac_txdma_xfer_stat=%#0x\n", stat));
765 }
766 if (!(stat & ACTIVE)) {
767 /*
768 * status field might not have been filled by DBDMA
769 */
770 if (cp == bus_to_virt(in_le32(&bp->tx_dma->cmdptr)))
771 break;
772 }
773
774 if (bp->tx_bufs[bp->tx_empty]) {
775 ++dev->stats.tx_packets;
776 dev_consume_skb_irq(bp->tx_bufs[bp->tx_empty]);
777 }
778 bp->tx_bufs[bp->tx_empty] = NULL;
779 bp->tx_fullup = 0;
780 netif_wake_queue(dev);
781 if (++bp->tx_empty >= N_TX_RING)
782 bp->tx_empty = 0;
783 if (bp->tx_empty == bp->tx_fill)
784 break;
785 }
786
787 spin_unlock_irqrestore(&bp->lock, flags);
788
789 if (txintcount < 10) {
790 XXDEBUG(("bmac_txdma_intr done->bmac_start\n"));
791 }
792
793 bmac_start(dev);
794 return IRQ_HANDLED;
795 }
796
797 #ifndef SUNHME_MULTICAST
798 /*
799 * Add requested mcast addr to BMac's hash table filter.
800 *
801 */
802
803 static void
bmac_addhash(struct bmac_data * bp,unsigned char * addr)804 bmac_addhash(struct bmac_data *bp, unsigned char *addr)
805 {
806 unsigned int crc;
807 unsigned short mask;
808
809 if (!(*addr)) return;
810 crc = crc32(~0, addr, ETH_ALEN) >> 26;
811 if (bp->hash_use_count[crc]++) return; /* This bit is already set */
812 mask = crc % 16;
813 mask = (unsigned char)1 << mask;
814 bp->hash_use_count[crc/16] |= mask;
815 }
816
817 static void
bmac_removehash(struct bmac_data * bp,unsigned char * addr)818 bmac_removehash(struct bmac_data *bp, unsigned char *addr)
819 {
820 unsigned int crc;
821 unsigned char mask;
822
823 /* Now, delete the address from the filter copy, as indicated */
824 crc = crc32(~0, addr, ETH_ALEN) >> 26;
825 if (bp->hash_use_count[crc] == 0) return; /* That bit wasn't in use! */
826 if (--bp->hash_use_count[crc]) return; /* That bit is still in use */
827 mask = crc % 16;
828 mask = ((unsigned char)1 << mask) ^ 0xffff; /* To turn off bit */
829 bp->hash_table_mask[crc/16] &= mask;
830 }
831
832 /*
833 * Sync the adapter with the software copy of the multicast mask
834 * (logical address filter).
835 */
836
837 static void
bmac_rx_off(struct net_device * dev)838 bmac_rx_off(struct net_device *dev)
839 {
840 unsigned short rx_cfg;
841
842 rx_cfg = bmread(dev, RXCFG);
843 rx_cfg &= ~RxMACEnable;
844 bmwrite(dev, RXCFG, rx_cfg);
845 do {
846 rx_cfg = bmread(dev, RXCFG);
847 } while (rx_cfg & RxMACEnable);
848 }
849
850 unsigned short
bmac_rx_on(struct net_device * dev,int hash_enable,int promisc_enable)851 bmac_rx_on(struct net_device *dev, int hash_enable, int promisc_enable)
852 {
853 unsigned short rx_cfg;
854
855 rx_cfg = bmread(dev, RXCFG);
856 rx_cfg |= RxMACEnable;
857 if (hash_enable) rx_cfg |= RxHashFilterEnable;
858 else rx_cfg &= ~RxHashFilterEnable;
859 if (promisc_enable) rx_cfg |= RxPromiscEnable;
860 else rx_cfg &= ~RxPromiscEnable;
861 bmwrite(dev, RXRST, RxResetValue);
862 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
863 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
864 bmwrite(dev, RXCFG, rx_cfg );
865 return rx_cfg;
866 }
867
868 static void
bmac_update_hash_table_mask(struct net_device * dev,struct bmac_data * bp)869 bmac_update_hash_table_mask(struct net_device *dev, struct bmac_data *bp)
870 {
871 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
872 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
873 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
874 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
875 }
876
877 #if 0
878 static void
879 bmac_add_multi(struct net_device *dev,
880 struct bmac_data *bp, unsigned char *addr)
881 {
882 /* XXDEBUG(("bmac: enter bmac_add_multi\n")); */
883 bmac_addhash(bp, addr);
884 bmac_rx_off(dev);
885 bmac_update_hash_table_mask(dev, bp);
886 bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0);
887 /* XXDEBUG(("bmac: exit bmac_add_multi\n")); */
888 }
889
890 static void
891 bmac_remove_multi(struct net_device *dev,
892 struct bmac_data *bp, unsigned char *addr)
893 {
894 bmac_removehash(bp, addr);
895 bmac_rx_off(dev);
896 bmac_update_hash_table_mask(dev, bp);
897 bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0);
898 }
899 #endif
900
901 /* Set or clear the multicast filter for this adaptor.
902 num_addrs == -1 Promiscuous mode, receive all packets
903 num_addrs == 0 Normal mode, clear multicast list
904 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
905 best-effort filtering.
906 */
bmac_set_multicast(struct net_device * dev)907 static void bmac_set_multicast(struct net_device *dev)
908 {
909 struct netdev_hw_addr *ha;
910 struct bmac_data *bp = netdev_priv(dev);
911 int num_addrs = netdev_mc_count(dev);
912 unsigned short rx_cfg;
913 int i;
914
915 if (bp->sleeping)
916 return;
917
918 XXDEBUG(("bmac: enter bmac_set_multicast, n_addrs=%d\n", num_addrs));
919
920 if((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 64)) {
921 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0xffff;
922 bmac_update_hash_table_mask(dev, bp);
923 rx_cfg = bmac_rx_on(dev, 1, 0);
924 XXDEBUG(("bmac: all multi, rx_cfg=%#08x\n"));
925 } else if ((dev->flags & IFF_PROMISC) || (num_addrs < 0)) {
926 rx_cfg = bmread(dev, RXCFG);
927 rx_cfg |= RxPromiscEnable;
928 bmwrite(dev, RXCFG, rx_cfg);
929 rx_cfg = bmac_rx_on(dev, 0, 1);
930 XXDEBUG(("bmac: promisc mode enabled, rx_cfg=%#08x\n", rx_cfg));
931 } else {
932 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0;
933 for (i=0; i<64; i++) bp->hash_use_count[i] = 0;
934 if (num_addrs == 0) {
935 rx_cfg = bmac_rx_on(dev, 0, 0);
936 XXDEBUG(("bmac: multi disabled, rx_cfg=%#08x\n", rx_cfg));
937 } else {
938 netdev_for_each_mc_addr(ha, dev)
939 bmac_addhash(bp, ha->addr);
940 bmac_update_hash_table_mask(dev, bp);
941 rx_cfg = bmac_rx_on(dev, 1, 0);
942 XXDEBUG(("bmac: multi enabled, rx_cfg=%#08x\n", rx_cfg));
943 }
944 }
945 /* XXDEBUG(("bmac: exit bmac_set_multicast\n")); */
946 }
947 #else /* ifdef SUNHME_MULTICAST */
948
949 /* The version of set_multicast below was lifted from sunhme.c */
950
bmac_set_multicast(struct net_device * dev)951 static void bmac_set_multicast(struct net_device *dev)
952 {
953 struct netdev_hw_addr *ha;
954 unsigned short rx_cfg;
955 u32 crc;
956
957 if((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 64)) {
958 bmwrite(dev, BHASH0, 0xffff);
959 bmwrite(dev, BHASH1, 0xffff);
960 bmwrite(dev, BHASH2, 0xffff);
961 bmwrite(dev, BHASH3, 0xffff);
962 } else if(dev->flags & IFF_PROMISC) {
963 rx_cfg = bmread(dev, RXCFG);
964 rx_cfg |= RxPromiscEnable;
965 bmwrite(dev, RXCFG, rx_cfg);
966 } else {
967 u16 hash_table[4] = { 0 };
968
969 rx_cfg = bmread(dev, RXCFG);
970 rx_cfg &= ~RxPromiscEnable;
971 bmwrite(dev, RXCFG, rx_cfg);
972
973 netdev_for_each_mc_addr(ha, dev) {
974 crc = ether_crc_le(6, ha->addr);
975 crc >>= 26;
976 hash_table[crc >> 4] |= 1 << (crc & 0xf);
977 }
978 bmwrite(dev, BHASH0, hash_table[0]);
979 bmwrite(dev, BHASH1, hash_table[1]);
980 bmwrite(dev, BHASH2, hash_table[2]);
981 bmwrite(dev, BHASH3, hash_table[3]);
982 }
983 }
984 #endif /* SUNHME_MULTICAST */
985
986 static int miscintcount;
987
bmac_misc_intr(int irq,void * dev_id)988 static irqreturn_t bmac_misc_intr(int irq, void *dev_id)
989 {
990 struct net_device *dev = (struct net_device *) dev_id;
991 unsigned int status = bmread(dev, STATUS);
992 if (miscintcount++ < 10) {
993 XXDEBUG(("bmac_misc_intr\n"));
994 }
995 /* XXDEBUG(("bmac_misc_intr, status=%#08x\n", status)); */
996 /* bmac_txdma_intr_inner(irq, dev_id); */
997 /* if (status & FrameReceived) dev->stats.rx_dropped++; */
998 if (status & RxErrorMask) dev->stats.rx_errors++;
999 if (status & RxCRCCntExp) dev->stats.rx_crc_errors++;
1000 if (status & RxLenCntExp) dev->stats.rx_length_errors++;
1001 if (status & RxOverFlow) dev->stats.rx_over_errors++;
1002 if (status & RxAlignCntExp) dev->stats.rx_frame_errors++;
1003
1004 /* if (status & FrameSent) dev->stats.tx_dropped++; */
1005 if (status & TxErrorMask) dev->stats.tx_errors++;
1006 if (status & TxUnderrun) dev->stats.tx_fifo_errors++;
1007 if (status & TxNormalCollExp) dev->stats.collisions++;
1008 return IRQ_HANDLED;
1009 }
1010
1011 /*
1012 * Procedure for reading EEPROM
1013 */
1014 #define SROMAddressLength 5
1015 #define DataInOn 0x0008
1016 #define DataInOff 0x0000
1017 #define Clk 0x0002
1018 #define ChipSelect 0x0001
1019 #define SDIShiftCount 3
1020 #define SD0ShiftCount 2
1021 #define DelayValue 1000 /* number of microseconds */
1022 #define SROMStartOffset 10 /* this is in words */
1023 #define SROMReadCount 3 /* number of words to read from SROM */
1024 #define SROMAddressBits 6
1025 #define EnetAddressOffset 20
1026
1027 static unsigned char
bmac_clock_out_bit(struct net_device * dev)1028 bmac_clock_out_bit(struct net_device *dev)
1029 {
1030 unsigned short data;
1031 unsigned short val;
1032
1033 bmwrite(dev, SROMCSR, ChipSelect | Clk);
1034 udelay(DelayValue);
1035
1036 data = bmread(dev, SROMCSR);
1037 udelay(DelayValue);
1038 val = (data >> SD0ShiftCount) & 1;
1039
1040 bmwrite(dev, SROMCSR, ChipSelect);
1041 udelay(DelayValue);
1042
1043 return val;
1044 }
1045
1046 static void
bmac_clock_in_bit(struct net_device * dev,unsigned int val)1047 bmac_clock_in_bit(struct net_device *dev, unsigned int val)
1048 {
1049 unsigned short data;
1050
1051 if (val != 0 && val != 1) return;
1052
1053 data = (val << SDIShiftCount);
1054 bmwrite(dev, SROMCSR, data | ChipSelect );
1055 udelay(DelayValue);
1056
1057 bmwrite(dev, SROMCSR, data | ChipSelect | Clk );
1058 udelay(DelayValue);
1059
1060 bmwrite(dev, SROMCSR, data | ChipSelect);
1061 udelay(DelayValue);
1062 }
1063
1064 static void
reset_and_select_srom(struct net_device * dev)1065 reset_and_select_srom(struct net_device *dev)
1066 {
1067 /* first reset */
1068 bmwrite(dev, SROMCSR, 0);
1069 udelay(DelayValue);
1070
1071 /* send it the read command (110) */
1072 bmac_clock_in_bit(dev, 1);
1073 bmac_clock_in_bit(dev, 1);
1074 bmac_clock_in_bit(dev, 0);
1075 }
1076
1077 static unsigned short
read_srom(struct net_device * dev,unsigned int addr,unsigned int addr_len)1078 read_srom(struct net_device *dev, unsigned int addr, unsigned int addr_len)
1079 {
1080 unsigned short data, val;
1081 int i;
1082
1083 /* send out the address we want to read from */
1084 for (i = 0; i < addr_len; i++) {
1085 val = addr >> (addr_len-i-1);
1086 bmac_clock_in_bit(dev, val & 1);
1087 }
1088
1089 /* Now read in the 16-bit data */
1090 data = 0;
1091 for (i = 0; i < 16; i++) {
1092 val = bmac_clock_out_bit(dev);
1093 data <<= 1;
1094 data |= val;
1095 }
1096 bmwrite(dev, SROMCSR, 0);
1097
1098 return data;
1099 }
1100
1101 /*
1102 * It looks like Cogent and SMC use different methods for calculating
1103 * checksums. What a pain..
1104 */
1105
1106 static int
bmac_verify_checksum(struct net_device * dev)1107 bmac_verify_checksum(struct net_device *dev)
1108 {
1109 unsigned short data, storedCS;
1110
1111 reset_and_select_srom(dev);
1112 data = read_srom(dev, 3, SROMAddressBits);
1113 storedCS = ((data >> 8) & 0x0ff) | ((data << 8) & 0xff00);
1114
1115 return 0;
1116 }
1117
1118
1119 static void
bmac_get_station_address(struct net_device * dev,unsigned char * ea)1120 bmac_get_station_address(struct net_device *dev, unsigned char *ea)
1121 {
1122 int i;
1123 unsigned short data;
1124
1125 for (i = 0; i < 3; i++)
1126 {
1127 reset_and_select_srom(dev);
1128 data = read_srom(dev, i + EnetAddressOffset/2, SROMAddressBits);
1129 ea[2*i] = bitrev8(data & 0x0ff);
1130 ea[2*i+1] = bitrev8((data >> 8) & 0x0ff);
1131 }
1132 }
1133
bmac_reset_and_enable(struct net_device * dev)1134 static void bmac_reset_and_enable(struct net_device *dev)
1135 {
1136 struct bmac_data *bp = netdev_priv(dev);
1137 unsigned long flags;
1138 struct sk_buff *skb;
1139 unsigned char *data;
1140
1141 spin_lock_irqsave(&bp->lock, flags);
1142 bmac_enable_and_reset_chip(dev);
1143 bmac_init_tx_ring(bp);
1144 bmac_init_rx_ring(dev);
1145 bmac_init_chip(dev);
1146 bmac_start_chip(dev);
1147 bmwrite(dev, INTDISABLE, EnableNormal);
1148 bp->sleeping = 0;
1149
1150 /*
1151 * It seems that the bmac can't receive until it's transmitted
1152 * a packet. So we give it a dummy packet to transmit.
1153 */
1154 skb = netdev_alloc_skb(dev, ETHERMINPACKET);
1155 if (skb != NULL) {
1156 data = skb_put_zero(skb, ETHERMINPACKET);
1157 memcpy(data, dev->dev_addr, ETH_ALEN);
1158 memcpy(data + ETH_ALEN, dev->dev_addr, ETH_ALEN);
1159 bmac_transmit_packet(skb, dev);
1160 }
1161 spin_unlock_irqrestore(&bp->lock, flags);
1162 }
1163
1164 static const struct ethtool_ops bmac_ethtool_ops = {
1165 .get_link = ethtool_op_get_link,
1166 };
1167
1168 static const struct net_device_ops bmac_netdev_ops = {
1169 .ndo_open = bmac_open,
1170 .ndo_stop = bmac_close,
1171 .ndo_start_xmit = bmac_output,
1172 .ndo_set_rx_mode = bmac_set_multicast,
1173 .ndo_set_mac_address = bmac_set_address,
1174 .ndo_validate_addr = eth_validate_addr,
1175 };
1176
bmac_probe(struct macio_dev * mdev,const struct of_device_id * match)1177 static int bmac_probe(struct macio_dev *mdev, const struct of_device_id *match)
1178 {
1179 int j, rev, ret;
1180 struct bmac_data *bp;
1181 const unsigned char *prop_addr;
1182 unsigned char addr[6];
1183 u8 macaddr[6];
1184 struct net_device *dev;
1185 int is_bmac_plus = ((int)match->data) != 0;
1186
1187 if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) {
1188 printk(KERN_ERR "BMAC: can't use, need 3 addrs and 3 intrs\n");
1189 return -ENODEV;
1190 }
1191 prop_addr = of_get_property(macio_get_of_node(mdev),
1192 "mac-address", NULL);
1193 if (prop_addr == NULL) {
1194 prop_addr = of_get_property(macio_get_of_node(mdev),
1195 "local-mac-address", NULL);
1196 if (prop_addr == NULL) {
1197 printk(KERN_ERR "BMAC: Can't get mac-address\n");
1198 return -ENODEV;
1199 }
1200 }
1201 memcpy(addr, prop_addr, sizeof(addr));
1202
1203 dev = alloc_etherdev(PRIV_BYTES);
1204 if (!dev)
1205 return -ENOMEM;
1206
1207 bp = netdev_priv(dev);
1208 SET_NETDEV_DEV(dev, &mdev->ofdev.dev);
1209 macio_set_drvdata(mdev, dev);
1210
1211 bp->mdev = mdev;
1212 spin_lock_init(&bp->lock);
1213
1214 if (macio_request_resources(mdev, "bmac")) {
1215 printk(KERN_ERR "BMAC: can't request IO resource !\n");
1216 goto out_free;
1217 }
1218
1219 dev->base_addr = (unsigned long)
1220 ioremap(macio_resource_start(mdev, 0), macio_resource_len(mdev, 0));
1221 if (dev->base_addr == 0)
1222 goto out_release;
1223
1224 dev->irq = macio_irq(mdev, 0);
1225
1226 bmac_enable_and_reset_chip(dev);
1227 bmwrite(dev, INTDISABLE, DisableAll);
1228
1229 rev = addr[0] == 0 && addr[1] == 0xA0;
1230 for (j = 0; j < 6; ++j)
1231 macaddr[j] = rev ? bitrev8(addr[j]): addr[j];
1232
1233 eth_hw_addr_set(dev, macaddr);
1234
1235 /* Enable chip without interrupts for now */
1236 bmac_enable_and_reset_chip(dev);
1237 bmwrite(dev, INTDISABLE, DisableAll);
1238
1239 dev->netdev_ops = &bmac_netdev_ops;
1240 dev->ethtool_ops = &bmac_ethtool_ops;
1241
1242 bmac_get_station_address(dev, addr);
1243 if (bmac_verify_checksum(dev) != 0)
1244 goto err_out_iounmap;
1245
1246 bp->is_bmac_plus = is_bmac_plus;
1247 bp->tx_dma = ioremap(macio_resource_start(mdev, 1), macio_resource_len(mdev, 1));
1248 if (!bp->tx_dma)
1249 goto err_out_iounmap;
1250 bp->tx_dma_intr = macio_irq(mdev, 1);
1251 bp->rx_dma = ioremap(macio_resource_start(mdev, 2), macio_resource_len(mdev, 2));
1252 if (!bp->rx_dma)
1253 goto err_out_iounmap_tx;
1254 bp->rx_dma_intr = macio_irq(mdev, 2);
1255
1256 bp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(bp + 1);
1257 bp->rx_cmds = bp->tx_cmds + N_TX_RING + 1;
1258
1259 bp->queue = (struct sk_buff_head *)(bp->rx_cmds + N_RX_RING + 1);
1260 skb_queue_head_init(bp->queue);
1261
1262 timer_setup(&bp->tx_timeout, bmac_tx_timeout, 0);
1263
1264 ret = request_irq(dev->irq, bmac_misc_intr, IRQF_NO_AUTOEN, "BMAC-misc", dev);
1265 if (ret) {
1266 printk(KERN_ERR "BMAC: can't get irq %d\n", dev->irq);
1267 goto err_out_iounmap_rx;
1268 }
1269 ret = request_irq(bp->tx_dma_intr, bmac_txdma_intr, 0, "BMAC-txdma", dev);
1270 if (ret) {
1271 printk(KERN_ERR "BMAC: can't get irq %d\n", bp->tx_dma_intr);
1272 goto err_out_irq0;
1273 }
1274 ret = request_irq(bp->rx_dma_intr, bmac_rxdma_intr, 0, "BMAC-rxdma", dev);
1275 if (ret) {
1276 printk(KERN_ERR "BMAC: can't get irq %d\n", bp->rx_dma_intr);
1277 goto err_out_irq1;
1278 }
1279
1280 /* Mask chip interrupts and disable chip, will be
1281 * re-enabled on open()
1282 */
1283 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
1284
1285 if (register_netdev(dev) != 0) {
1286 printk(KERN_ERR "BMAC: Ethernet registration failed\n");
1287 goto err_out_irq2;
1288 }
1289
1290 printk(KERN_INFO "%s: BMAC%s at %pM",
1291 dev->name, (is_bmac_plus ? "+" : ""), dev->dev_addr);
1292 XXDEBUG((", base_addr=%#0lx", dev->base_addr));
1293 printk("\n");
1294
1295 return 0;
1296
1297 err_out_irq2:
1298 free_irq(bp->rx_dma_intr, dev);
1299 err_out_irq1:
1300 free_irq(bp->tx_dma_intr, dev);
1301 err_out_irq0:
1302 free_irq(dev->irq, dev);
1303 err_out_iounmap_rx:
1304 iounmap(bp->rx_dma);
1305 err_out_iounmap_tx:
1306 iounmap(bp->tx_dma);
1307 err_out_iounmap:
1308 iounmap((void __iomem *)dev->base_addr);
1309 out_release:
1310 macio_release_resources(mdev);
1311 out_free:
1312 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
1313 free_netdev(dev);
1314
1315 return -ENODEV;
1316 }
1317
bmac_open(struct net_device * dev)1318 static int bmac_open(struct net_device *dev)
1319 {
1320 struct bmac_data *bp = netdev_priv(dev);
1321 /* XXDEBUG(("bmac: enter open\n")); */
1322 /* reset the chip */
1323 bp->opened = 1;
1324 bmac_reset_and_enable(dev);
1325 enable_irq(dev->irq);
1326 return 0;
1327 }
1328
bmac_close(struct net_device * dev)1329 static int bmac_close(struct net_device *dev)
1330 {
1331 struct bmac_data *bp = netdev_priv(dev);
1332 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
1333 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
1334 unsigned short config;
1335 int i;
1336
1337 bp->sleeping = 1;
1338
1339 /* disable rx and tx */
1340 config = bmread(dev, RXCFG);
1341 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1342
1343 config = bmread(dev, TXCFG);
1344 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1345
1346 bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
1347
1348 /* disable rx and tx dma */
1349 rd->control = cpu_to_le32(DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
1350 td->control = cpu_to_le32(DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
1351
1352 /* free some skb's */
1353 XXDEBUG(("bmac: free rx bufs\n"));
1354 for (i=0; i<N_RX_RING; i++) {
1355 if (bp->rx_bufs[i] != NULL) {
1356 dev_kfree_skb(bp->rx_bufs[i]);
1357 bp->rx_bufs[i] = NULL;
1358 }
1359 }
1360 XXDEBUG(("bmac: free tx bufs\n"));
1361 for (i = 0; i<N_TX_RING; i++) {
1362 if (bp->tx_bufs[i] != NULL) {
1363 dev_kfree_skb(bp->tx_bufs[i]);
1364 bp->tx_bufs[i] = NULL;
1365 }
1366 }
1367 XXDEBUG(("bmac: all bufs freed\n"));
1368
1369 bp->opened = 0;
1370 disable_irq(dev->irq);
1371 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
1372
1373 return 0;
1374 }
1375
1376 static void
bmac_start(struct net_device * dev)1377 bmac_start(struct net_device *dev)
1378 {
1379 struct bmac_data *bp = netdev_priv(dev);
1380 int i;
1381 struct sk_buff *skb;
1382 unsigned long flags;
1383
1384 if (bp->sleeping)
1385 return;
1386
1387 spin_lock_irqsave(&bp->lock, flags);
1388 while (1) {
1389 i = bp->tx_fill + 1;
1390 if (i >= N_TX_RING)
1391 i = 0;
1392 if (i == bp->tx_empty)
1393 break;
1394 skb = skb_dequeue(bp->queue);
1395 if (skb == NULL)
1396 break;
1397 bmac_transmit_packet(skb, dev);
1398 }
1399 spin_unlock_irqrestore(&bp->lock, flags);
1400 }
1401
1402 static netdev_tx_t
bmac_output(struct sk_buff * skb,struct net_device * dev)1403 bmac_output(struct sk_buff *skb, struct net_device *dev)
1404 {
1405 struct bmac_data *bp = netdev_priv(dev);
1406 skb_queue_tail(bp->queue, skb);
1407 bmac_start(dev);
1408 return NETDEV_TX_OK;
1409 }
1410
bmac_tx_timeout(struct timer_list * t)1411 static void bmac_tx_timeout(struct timer_list *t)
1412 {
1413 struct bmac_data *bp = timer_container_of(bp, t, tx_timeout);
1414 struct net_device *dev = macio_get_drvdata(bp->mdev);
1415 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
1416 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
1417 volatile struct dbdma_cmd *cp;
1418 unsigned long flags;
1419 unsigned short config, oldConfig;
1420 int i;
1421
1422 XXDEBUG(("bmac: tx_timeout called\n"));
1423 spin_lock_irqsave(&bp->lock, flags);
1424 bp->timeout_active = 0;
1425
1426 /* update various counters */
1427 /* bmac_handle_misc_intrs(bp, 0); */
1428
1429 cp = &bp->tx_cmds[bp->tx_empty];
1430 /* XXDEBUG((KERN_DEBUG "bmac: tx dmastat=%x %x runt=%d pr=%x fs=%x fc=%x\n", */
1431 /* le32_to_cpu(td->status), le16_to_cpu(cp->xfer_status), bp->tx_bad_runt, */
1432 /* mb->pr, mb->xmtfs, mb->fifofc)); */
1433
1434 /* turn off both tx and rx and reset the chip */
1435 config = bmread(dev, RXCFG);
1436 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1437 config = bmread(dev, TXCFG);
1438 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1439 out_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD));
1440 printk(KERN_ERR "bmac: transmit timeout - resetting\n");
1441 bmac_enable_and_reset_chip(dev);
1442
1443 /* restart rx dma */
1444 cp = bus_to_virt(le32_to_cpu(rd->cmdptr));
1445 out_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD));
1446 out_le16(&cp->xfer_status, 0);
1447 out_le32(&rd->cmdptr, virt_to_bus(cp));
1448 out_le32(&rd->control, DBDMA_SET(RUN|WAKE));
1449
1450 /* fix up the transmit side */
1451 XXDEBUG((KERN_DEBUG "bmac: tx empty=%d fill=%d fullup=%d\n",
1452 bp->tx_empty, bp->tx_fill, bp->tx_fullup));
1453 i = bp->tx_empty;
1454 ++dev->stats.tx_errors;
1455 if (i != bp->tx_fill) {
1456 dev_kfree_skb_irq(bp->tx_bufs[i]);
1457 bp->tx_bufs[i] = NULL;
1458 if (++i >= N_TX_RING) i = 0;
1459 bp->tx_empty = i;
1460 }
1461 bp->tx_fullup = 0;
1462 netif_wake_queue(dev);
1463 if (i != bp->tx_fill) {
1464 cp = &bp->tx_cmds[i];
1465 out_le16(&cp->xfer_status, 0);
1466 out_le16(&cp->command, OUTPUT_LAST);
1467 out_le32(&td->cmdptr, virt_to_bus(cp));
1468 out_le32(&td->control, DBDMA_SET(RUN));
1469 /* bmac_set_timeout(dev); */
1470 XXDEBUG((KERN_DEBUG "bmac: starting %d\n", i));
1471 }
1472
1473 /* turn it back on */
1474 oldConfig = bmread(dev, RXCFG);
1475 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
1476 oldConfig = bmread(dev, TXCFG);
1477 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
1478
1479 spin_unlock_irqrestore(&bp->lock, flags);
1480 }
1481
1482 #if 0
1483 static void dump_dbdma(volatile struct dbdma_cmd *cp,int count)
1484 {
1485 int i,*ip;
1486
1487 for (i=0;i< count;i++) {
1488 ip = (int*)(cp+i);
1489
1490 printk("dbdma req 0x%x addr 0x%x baddr 0x%x xfer/res 0x%x\n",
1491 le32_to_cpup(ip+0),
1492 le32_to_cpup(ip+1),
1493 le32_to_cpup(ip+2),
1494 le32_to_cpup(ip+3));
1495 }
1496
1497 }
1498 #endif
1499
1500 #if 0
1501 static int
1502 bmac_proc_info(char *buffer, char **start, off_t offset, int length)
1503 {
1504 int len = 0;
1505 off_t pos = 0;
1506 off_t begin = 0;
1507 int i;
1508
1509 if (bmac_devs == NULL)
1510 return -ENOSYS;
1511
1512 len += sprintf(buffer, "BMAC counters & registers\n");
1513
1514 for (i = 0; i<N_REG_ENTRIES; i++) {
1515 len += sprintf(buffer + len, "%s: %#08x\n",
1516 reg_entries[i].name,
1517 bmread(bmac_devs, reg_entries[i].reg_offset));
1518 pos = begin + len;
1519
1520 if (pos < offset) {
1521 len = 0;
1522 begin = pos;
1523 }
1524
1525 if (pos > offset+length) break;
1526 }
1527
1528 *start = buffer + (offset - begin);
1529 len -= (offset - begin);
1530
1531 if (len > length) len = length;
1532
1533 return len;
1534 }
1535 #endif
1536
bmac_remove(struct macio_dev * mdev)1537 static void bmac_remove(struct macio_dev *mdev)
1538 {
1539 struct net_device *dev = macio_get_drvdata(mdev);
1540 struct bmac_data *bp = netdev_priv(dev);
1541
1542 unregister_netdev(dev);
1543
1544 free_irq(dev->irq, dev);
1545 free_irq(bp->tx_dma_intr, dev);
1546 free_irq(bp->rx_dma_intr, dev);
1547
1548 iounmap((void __iomem *)dev->base_addr);
1549 iounmap(bp->tx_dma);
1550 iounmap(bp->rx_dma);
1551
1552 macio_release_resources(mdev);
1553
1554 free_netdev(dev);
1555 }
1556
1557 static const struct of_device_id bmac_match[] =
1558 {
1559 {
1560 .name = "bmac",
1561 .data = (void *)0,
1562 },
1563 {
1564 .type = "network",
1565 .compatible = "bmac+",
1566 .data = (void *)1,
1567 },
1568 {},
1569 };
1570 MODULE_DEVICE_TABLE (of, bmac_match);
1571
1572 static struct macio_driver bmac_driver =
1573 {
1574 .driver = {
1575 .name = "bmac",
1576 .owner = THIS_MODULE,
1577 .of_match_table = bmac_match,
1578 },
1579 .probe = bmac_probe,
1580 .remove = bmac_remove,
1581 #ifdef CONFIG_PM
1582 .suspend = bmac_suspend,
1583 .resume = bmac_resume,
1584 #endif
1585 };
1586
1587
bmac_init(void)1588 static int __init bmac_init(void)
1589 {
1590 if (bmac_emergency_rxbuf == NULL) {
1591 bmac_emergency_rxbuf = kmalloc(RX_BUFLEN, GFP_KERNEL);
1592 if (bmac_emergency_rxbuf == NULL)
1593 return -ENOMEM;
1594 }
1595
1596 return macio_register_driver(&bmac_driver);
1597 }
1598
bmac_exit(void)1599 static void __exit bmac_exit(void)
1600 {
1601 macio_unregister_driver(&bmac_driver);
1602
1603 kfree(bmac_emergency_rxbuf);
1604 bmac_emergency_rxbuf = NULL;
1605 }
1606
1607 MODULE_AUTHOR("Randy Gobbel/Paul Mackerras");
1608 MODULE_DESCRIPTION("PowerMac BMAC ethernet driver.");
1609 MODULE_LICENSE("GPL");
1610
1611 module_init(bmac_init);
1612 module_exit(bmac_exit);
1613