1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com> 4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sdm660.h> 8#include <dt-bindings/clock/qcom,gpucc-sdm660.h> 9#include <dt-bindings/clock/qcom,mmcc-sdm660.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/firmware/qcom,scm.h> 12#include <dt-bindings/interconnect/qcom,sdm660.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/thermal/thermal.h> 17#include <dt-bindings/soc/qcom,apr.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 aliases { 26 mmc1 = &sdhc_1; 27 mmc2 = &sdhc_2; 28 }; 29 30 chosen { }; 31 32 clocks { 33 xo_board: xo-board { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <19200000>; 37 clock-output-names = "xo_board"; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32764>; 44 clock-output-names = "sleep_clk"; 45 }; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@100 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a53"; 55 reg = <0x0 0x100>; 56 enable-method = "psci"; 57 cpu-idle-states = <&perf_cpu_sleep_0 58 &perf_cpu_sleep_1 59 &perf_cluster_sleep_0 60 &perf_cluster_sleep_1 61 &perf_cluster_sleep_2>; 62 capacity-dmips-mhz = <1126>; 63 #cooling-cells = <2>; 64 next-level-cache = <&l2_1>; 65 l2_1: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 }; 70 }; 71 72 cpu1: cpu@101 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 reg = <0x0 0x101>; 76 enable-method = "psci"; 77 cpu-idle-states = <&perf_cpu_sleep_0 78 &perf_cpu_sleep_1 79 &perf_cluster_sleep_0 80 &perf_cluster_sleep_1 81 &perf_cluster_sleep_2>; 82 capacity-dmips-mhz = <1126>; 83 #cooling-cells = <2>; 84 next-level-cache = <&l2_1>; 85 }; 86 87 cpu2: cpu@102 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x0 0x102>; 91 enable-method = "psci"; 92 cpu-idle-states = <&perf_cpu_sleep_0 93 &perf_cpu_sleep_1 94 &perf_cluster_sleep_0 95 &perf_cluster_sleep_1 96 &perf_cluster_sleep_2>; 97 capacity-dmips-mhz = <1126>; 98 #cooling-cells = <2>; 99 next-level-cache = <&l2_1>; 100 }; 101 102 cpu3: cpu@103 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a53"; 105 reg = <0x0 0x103>; 106 enable-method = "psci"; 107 cpu-idle-states = <&perf_cpu_sleep_0 108 &perf_cpu_sleep_1 109 &perf_cluster_sleep_0 110 &perf_cluster_sleep_1 111 &perf_cluster_sleep_2>; 112 capacity-dmips-mhz = <1126>; 113 #cooling-cells = <2>; 114 next-level-cache = <&l2_1>; 115 }; 116 117 cpu4: cpu@0 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a53"; 120 reg = <0x0 0x0>; 121 enable-method = "psci"; 122 cpu-idle-states = <&pwr_cpu_sleep_0 123 &pwr_cpu_sleep_1 124 &pwr_cluster_sleep_0 125 &pwr_cluster_sleep_1 126 &pwr_cluster_sleep_2>; 127 capacity-dmips-mhz = <1024>; 128 #cooling-cells = <2>; 129 next-level-cache = <&l2_0>; 130 l2_0: l2-cache { 131 compatible = "cache"; 132 cache-level = <2>; 133 cache-unified; 134 }; 135 }; 136 137 cpu5: cpu@1 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a53"; 140 reg = <0x0 0x1>; 141 enable-method = "psci"; 142 cpu-idle-states = <&pwr_cpu_sleep_0 143 &pwr_cpu_sleep_1 144 &pwr_cluster_sleep_0 145 &pwr_cluster_sleep_1 146 &pwr_cluster_sleep_2>; 147 capacity-dmips-mhz = <1024>; 148 #cooling-cells = <2>; 149 next-level-cache = <&l2_0>; 150 }; 151 152 cpu6: cpu@2 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a53"; 155 reg = <0x0 0x2>; 156 enable-method = "psci"; 157 cpu-idle-states = <&pwr_cpu_sleep_0 158 &pwr_cpu_sleep_1 159 &pwr_cluster_sleep_0 160 &pwr_cluster_sleep_1 161 &pwr_cluster_sleep_2>; 162 capacity-dmips-mhz = <1024>; 163 #cooling-cells = <2>; 164 next-level-cache = <&l2_0>; 165 }; 166 167 cpu7: cpu@3 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a53"; 170 reg = <0x0 0x3>; 171 enable-method = "psci"; 172 cpu-idle-states = <&pwr_cpu_sleep_0 173 &pwr_cpu_sleep_1 174 &pwr_cluster_sleep_0 175 &pwr_cluster_sleep_1 176 &pwr_cluster_sleep_2>; 177 capacity-dmips-mhz = <1024>; 178 #cooling-cells = <2>; 179 next-level-cache = <&l2_0>; 180 }; 181 182 cpu-map { 183 cluster0 { 184 core0 { 185 cpu = <&cpu4>; 186 }; 187 188 core1 { 189 cpu = <&cpu5>; 190 }; 191 192 core2 { 193 cpu = <&cpu6>; 194 }; 195 196 core3 { 197 cpu = <&cpu7>; 198 }; 199 }; 200 201 cluster1 { 202 core0 { 203 cpu = <&cpu0>; 204 }; 205 206 core1 { 207 cpu = <&cpu1>; 208 }; 209 210 core2 { 211 cpu = <&cpu2>; 212 }; 213 214 core3 { 215 cpu = <&cpu3>; 216 }; 217 }; 218 }; 219 220 idle-states { 221 entry-method = "psci"; 222 223 pwr_cpu_sleep_0: cpu-sleep-0-0 { 224 compatible = "arm,idle-state"; 225 idle-state-name = "pwr-retention"; 226 arm,psci-suspend-param = <0x40000002>; 227 entry-latency-us = <338>; 228 exit-latency-us = <423>; 229 min-residency-us = <200>; 230 }; 231 232 pwr_cpu_sleep_1: cpu-sleep-0-1 { 233 compatible = "arm,idle-state"; 234 idle-state-name = "pwr-power-collapse"; 235 arm,psci-suspend-param = <0x40000003>; 236 entry-latency-us = <515>; 237 exit-latency-us = <1821>; 238 min-residency-us = <1000>; 239 local-timer-stop; 240 }; 241 242 perf_cpu_sleep_0: cpu-sleep-1-0 { 243 compatible = "arm,idle-state"; 244 idle-state-name = "perf-retention"; 245 arm,psci-suspend-param = <0x40000002>; 246 entry-latency-us = <154>; 247 exit-latency-us = <87>; 248 min-residency-us = <200>; 249 }; 250 251 perf_cpu_sleep_1: cpu-sleep-1-1 { 252 compatible = "arm,idle-state"; 253 idle-state-name = "perf-power-collapse"; 254 arm,psci-suspend-param = <0x40000003>; 255 entry-latency-us = <262>; 256 exit-latency-us = <301>; 257 min-residency-us = <1000>; 258 local-timer-stop; 259 }; 260 261 pwr_cluster_sleep_0: cluster-sleep-0-0 { 262 compatible = "arm,idle-state"; 263 idle-state-name = "pwr-cluster-dynamic-retention"; 264 arm,psci-suspend-param = <0x400000F2>; 265 entry-latency-us = <284>; 266 exit-latency-us = <384>; 267 min-residency-us = <9987>; 268 local-timer-stop; 269 }; 270 271 pwr_cluster_sleep_1: cluster-sleep-0-1 { 272 compatible = "arm,idle-state"; 273 idle-state-name = "pwr-cluster-retention"; 274 arm,psci-suspend-param = <0x400000F3>; 275 entry-latency-us = <338>; 276 exit-latency-us = <423>; 277 min-residency-us = <9987>; 278 local-timer-stop; 279 }; 280 281 pwr_cluster_sleep_2: cluster-sleep-0-2 { 282 compatible = "arm,idle-state"; 283 idle-state-name = "pwr-cluster-retention"; 284 arm,psci-suspend-param = <0x400000F4>; 285 entry-latency-us = <515>; 286 exit-latency-us = <1821>; 287 min-residency-us = <9987>; 288 local-timer-stop; 289 }; 290 291 perf_cluster_sleep_0: cluster-sleep-1-0 { 292 compatible = "arm,idle-state"; 293 idle-state-name = "perf-cluster-dynamic-retention"; 294 arm,psci-suspend-param = <0x400000F2>; 295 entry-latency-us = <272>; 296 exit-latency-us = <329>; 297 min-residency-us = <9987>; 298 local-timer-stop; 299 }; 300 301 perf_cluster_sleep_1: cluster-sleep-1-1 { 302 compatible = "arm,idle-state"; 303 idle-state-name = "perf-cluster-retention"; 304 arm,psci-suspend-param = <0x400000F3>; 305 entry-latency-us = <332>; 306 exit-latency-us = <368>; 307 min-residency-us = <9987>; 308 local-timer-stop; 309 }; 310 311 perf_cluster_sleep_2: cluster-sleep-1-2 { 312 compatible = "arm,idle-state"; 313 idle-state-name = "perf-cluster-retention"; 314 arm,psci-suspend-param = <0x400000F4>; 315 entry-latency-us = <545>; 316 exit-latency-us = <1609>; 317 min-residency-us = <9987>; 318 local-timer-stop; 319 }; 320 }; 321 }; 322 323 firmware { 324 scm { 325 compatible = "qcom,scm-msm8998", "qcom,scm"; 326 }; 327 }; 328 329 memory@80000000 { 330 device_type = "memory"; 331 /* We expect the bootloader to fill in the reg */ 332 reg = <0x0 0x80000000 0x0 0x0>; 333 }; 334 335 dsi_opp_table: opp-table-dsi { 336 compatible = "operating-points-v2"; 337 338 opp-131250000 { 339 opp-hz = /bits/ 64 <131250000>; 340 required-opps = <&rpmpd_opp_svs>; 341 }; 342 343 opp-210000000 { 344 opp-hz = /bits/ 64 <210000000>; 345 required-opps = <&rpmpd_opp_svs_plus>; 346 }; 347 348 opp-262500000 { 349 opp-hz = /bits/ 64 <262500000>; 350 required-opps = <&rpmpd_opp_nom>; 351 }; 352 }; 353 354 pmu { 355 compatible = "arm,armv8-pmuv3"; 356 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 357 }; 358 359 psci { 360 compatible = "arm,psci-1.0"; 361 method = "smc"; 362 }; 363 364 rpm: remoteproc { 365 compatible = "qcom,sdm660-rpm-proc", "qcom,rpm-proc"; 366 367 glink-edge { 368 compatible = "qcom,glink-rpm"; 369 370 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 371 qcom,rpm-msg-ram = <&rpm_msg_ram>; 372 mboxes = <&apcs_glb 0>; 373 374 rpm_requests: rpm-requests { 375 compatible = "qcom,rpm-sdm660", "qcom,glink-smd-rpm"; 376 qcom,glink-channels = "rpm_requests"; 377 378 rpmcc: clock-controller { 379 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; 380 #clock-cells = <1>; 381 }; 382 383 rpmpd: power-controller { 384 compatible = "qcom,sdm660-rpmpd"; 385 #power-domain-cells = <1>; 386 operating-points-v2 = <&rpmpd_opp_table>; 387 388 rpmpd_opp_table: opp-table { 389 compatible = "operating-points-v2"; 390 391 rpmpd_opp_ret: opp1 { 392 opp-level = <RPM_SMD_LEVEL_RETENTION>; 393 }; 394 395 rpmpd_opp_ret_plus: opp2 { 396 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 397 }; 398 399 rpmpd_opp_min_svs: opp3 { 400 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 401 }; 402 403 rpmpd_opp_low_svs: opp4 { 404 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 405 }; 406 407 rpmpd_opp_svs: opp5 { 408 opp-level = <RPM_SMD_LEVEL_SVS>; 409 }; 410 411 rpmpd_opp_svs_plus: opp6 { 412 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 413 }; 414 415 rpmpd_opp_nom: opp7 { 416 opp-level = <RPM_SMD_LEVEL_NOM>; 417 }; 418 419 rpmpd_opp_nom_plus: opp8 { 420 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 421 }; 422 423 rpmpd_opp_turbo: opp9 { 424 opp-level = <RPM_SMD_LEVEL_TURBO>; 425 }; 426 }; 427 }; 428 }; 429 }; 430 }; 431 432 reserved-memory { 433 #address-cells = <2>; 434 #size-cells = <2>; 435 ranges; 436 437 wlan_msa_guard: wlan-msa-guard@85600000 { 438 reg = <0x0 0x85600000 0x0 0x100000>; 439 no-map; 440 }; 441 442 wlan_msa_mem: wlan-msa-mem@85700000 { 443 reg = <0x0 0x85700000 0x0 0x100000>; 444 no-map; 445 }; 446 447 qhee_code: qhee-code@85800000 { 448 reg = <0x0 0x85800000 0x0 0x600000>; 449 no-map; 450 }; 451 452 rmtfs_mem: memory@85e00000 { 453 compatible = "qcom,rmtfs-mem"; 454 reg = <0x0 0x85e00000 0x0 0x200000>; 455 no-map; 456 457 qcom,client-id = <1>; 458 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 459 }; 460 461 smem_region: smem-mem@86000000 { 462 reg = <0 0x86000000 0 0x200000>; 463 no-map; 464 }; 465 466 tz_mem: memory@86200000 { 467 reg = <0x0 0x86200000 0x0 0x3300000>; 468 no-map; 469 }; 470 471 mpss_region: mpss@8ac00000 { 472 reg = <0x0 0x8ac00000 0x0 0x7e00000>; 473 no-map; 474 }; 475 476 adsp_region: adsp@92a00000 { 477 reg = <0x0 0x92a00000 0x0 0x1e00000>; 478 no-map; 479 }; 480 481 mba_region: mba@94800000 { 482 reg = <0x0 0x94800000 0x0 0x200000>; 483 no-map; 484 }; 485 486 buffer_mem: tzbuffer@94a00000 { 487 reg = <0x0 0x94a00000 0x0 0x100000>; 488 no-map; 489 }; 490 491 venus_region: venus@9f800000 { 492 reg = <0x0 0x9f800000 0x0 0x800000>; 493 no-map; 494 }; 495 496 adsp_mem: adsp-region@f6000000 { 497 reg = <0x0 0xf6000000 0x0 0x800000>; 498 no-map; 499 }; 500 501 qseecom_mem: qseecom-region@f6800000 { 502 reg = <0x0 0xf6800000 0x0 0x1400000>; 503 no-map; 504 }; 505 506 zap_shader_region: gpu@fed00000 { 507 compatible = "shared-dma-pool"; 508 reg = <0x0 0xfed00000 0x0 0xa00000>; 509 no-map; 510 }; 511 }; 512 513 smem: smem { 514 compatible = "qcom,smem"; 515 memory-region = <&smem_region>; 516 hwlocks = <&tcsr_mutex 3>; 517 }; 518 519 smp2p-adsp { 520 compatible = "qcom,smp2p"; 521 qcom,smem = <443>, <429>; 522 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 523 mboxes = <&apcs_glb 10>; 524 qcom,local-pid = <0>; 525 qcom,remote-pid = <2>; 526 527 adsp_smp2p_out: master-kernel { 528 qcom,entry-name = "master-kernel"; 529 #qcom,smem-state-cells = <1>; 530 }; 531 532 adsp_smp2p_in: slave-kernel { 533 qcom,entry-name = "slave-kernel"; 534 interrupt-controller; 535 #interrupt-cells = <2>; 536 }; 537 }; 538 539 smp2p-mpss { 540 compatible = "qcom,smp2p"; 541 qcom,smem = <435>, <428>; 542 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 543 mboxes = <&apcs_glb 14>; 544 qcom,local-pid = <0>; 545 qcom,remote-pid = <1>; 546 547 modem_smp2p_out: master-kernel { 548 qcom,entry-name = "master-kernel"; 549 #qcom,smem-state-cells = <1>; 550 }; 551 552 modem_smp2p_in: slave-kernel { 553 qcom,entry-name = "slave-kernel"; 554 interrupt-controller; 555 #interrupt-cells = <2>; 556 }; 557 }; 558 559 soc@0 { 560 #address-cells = <1>; 561 #size-cells = <1>; 562 ranges = <0 0 0 0xffffffff>; 563 compatible = "simple-bus"; 564 565 gcc: clock-controller@100000 { 566 compatible = "qcom,gcc-sdm630"; 567 #clock-cells = <1>; 568 #reset-cells = <1>; 569 #power-domain-cells = <1>; 570 reg = <0x00100000 0x94000>; 571 572 clock-names = "xo", "sleep_clk"; 573 clocks = <&xo_board>, 574 <&sleep_clk>; 575 }; 576 577 rpm_msg_ram: sram@778000 { 578 compatible = "qcom,rpm-msg-ram"; 579 reg = <0x00778000 0x7000>; 580 }; 581 582 qfprom: qfprom@780000 { 583 compatible = "qcom,sdm630-qfprom", "qcom,qfprom"; 584 reg = <0x00780000 0x621c>; 585 #address-cells = <1>; 586 #size-cells = <1>; 587 588 qusb2_hstx_trim: hstx-trim@240 { 589 reg = <0x243 0x1>; 590 bits = <1 3>; 591 }; 592 593 gpu_speed_bin: gpu-speed-bin@41a0 { 594 reg = <0x41a2 0x1>; 595 bits = <5 7>; 596 }; 597 }; 598 599 rng: rng@793000 { 600 compatible = "qcom,prng-ee"; 601 reg = <0x00793000 0x1000>; 602 clocks = <&gcc GCC_PRNG_AHB_CLK>; 603 clock-names = "core"; 604 }; 605 606 bimc: interconnect@1008000 { 607 compatible = "qcom,sdm660-bimc"; 608 reg = <0x01008000 0x78000>; 609 #interconnect-cells = <1>; 610 }; 611 612 restart@10ac000 { 613 compatible = "qcom,pshold"; 614 reg = <0x010ac000 0x4>; 615 }; 616 617 cnoc: interconnect@1500000 { 618 compatible = "qcom,sdm660-cnoc"; 619 reg = <0x01500000 0x10000>; 620 #interconnect-cells = <1>; 621 }; 622 623 snoc: interconnect@1626000 { 624 compatible = "qcom,sdm660-snoc"; 625 reg = <0x01626000 0x7090>; 626 #interconnect-cells = <1>; 627 }; 628 629 anoc2_smmu: iommu@16c0000 { 630 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 631 reg = <0x016c0000 0x40000>; 632 #global-interrupts = <2>; 633 #iommu-cells = <1>; 634 635 interrupts = 636 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 638 639 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>, 641 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>, 642 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>, 643 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>, 644 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>, 645 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 668 }; 669 670 a2noc: interconnect@1704000 { 671 compatible = "qcom,sdm660-a2noc"; 672 reg = <0x01704000 0xc100>; 673 #interconnect-cells = <1>; 674 clock-names = "ipa", 675 "ufs_axi", 676 "aggre2_ufs_axi", 677 "aggre2_usb3_axi", 678 "cfg_noc_usb2_axi"; 679 clocks = <&rpmcc RPM_SMD_IPA_CLK>, 680 <&gcc GCC_UFS_AXI_CLK>, 681 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 682 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 683 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>; 684 }; 685 686 mnoc: interconnect@1745000 { 687 compatible = "qcom,sdm660-mnoc"; 688 reg = <0x01745000 0xa010>; 689 #interconnect-cells = <1>; 690 clock-names = "iface"; 691 clocks = <&mmcc AHB_CLK_SRC>; 692 }; 693 694 tsens: thermal-sensor@10ae000 { 695 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2"; 696 reg = <0x010ae000 0x1000>, /* TM */ 697 <0x010ad000 0x1000>; /* SROT */ 698 #qcom,sensors = <12>; 699 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 701 interrupt-names = "uplow", "critical"; 702 #thermal-sensor-cells = <1>; 703 }; 704 705 tcsr_mutex: hwlock@1f40000 { 706 compatible = "qcom,tcsr-mutex"; 707 reg = <0x01f40000 0x20000>; 708 #hwlock-cells = <1>; 709 }; 710 711 tcsr_regs_1: syscon@1f60000 { 712 compatible = "qcom,sdm630-tcsr", "syscon"; 713 reg = <0x01f60000 0x20000>; 714 }; 715 716 tlmm: pinctrl@3100000 { 717 compatible = "qcom,sdm630-pinctrl"; 718 reg = <0x03100000 0x400000>, 719 <0x03500000 0x400000>, 720 <0x03900000 0x400000>; 721 reg-names = "south", "center", "north"; 722 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 723 gpio-controller; 724 gpio-ranges = <&tlmm 0 0 114>; 725 #gpio-cells = <2>; 726 interrupt-controller; 727 #interrupt-cells = <2>; 728 729 blsp1_uart1_default: blsp1-uart1-default-state { 730 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 731 function = "blsp_uart1"; 732 drive-strength = <2>; 733 bias-disable; 734 }; 735 736 blsp1_uart1_sleep: blsp1-uart1-sleep-state { 737 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 738 function = "gpio"; 739 drive-strength = <2>; 740 bias-disable; 741 }; 742 743 blsp1_uart2_default: blsp1-uart2-default-state { 744 pins = "gpio4", "gpio5"; 745 function = "blsp_uart2"; 746 drive-strength = <2>; 747 bias-disable; 748 }; 749 750 blsp2_uart1_default: blsp2-uart1-active-state { 751 tx-rts-pins { 752 pins = "gpio16", "gpio19"; 753 function = "blsp_uart5"; 754 drive-strength = <2>; 755 bias-disable; 756 }; 757 758 rx-pins { 759 /* 760 * Avoid garbage data while BT module 761 * is powered off or not driving signal 762 */ 763 pins = "gpio17"; 764 function = "blsp_uart5"; 765 drive-strength = <2>; 766 bias-pull-up; 767 }; 768 769 cts-pins { 770 /* Match the pull of the BT module */ 771 pins = "gpio18"; 772 function = "blsp_uart5"; 773 drive-strength = <2>; 774 bias-pull-down; 775 }; 776 }; 777 778 blsp2_uart1_sleep: blsp2-uart1-sleep-state { 779 tx-pins { 780 pins = "gpio16"; 781 function = "gpio"; 782 drive-strength = <2>; 783 bias-pull-up; 784 }; 785 786 rx-cts-rts-pins { 787 pins = "gpio17", "gpio18", "gpio19"; 788 function = "gpio"; 789 drive-strength = <2>; 790 bias-disable; 791 }; 792 }; 793 794 i2c1_default: i2c1-default-state { 795 pins = "gpio2", "gpio3"; 796 function = "blsp_i2c1"; 797 drive-strength = <2>; 798 bias-disable; 799 }; 800 801 i2c1_sleep: i2c1-sleep-state { 802 pins = "gpio2", "gpio3"; 803 function = "blsp_i2c1"; 804 drive-strength = <2>; 805 bias-pull-up; 806 }; 807 808 i2c2_default: i2c2-default-state { 809 pins = "gpio6", "gpio7"; 810 function = "blsp_i2c2"; 811 drive-strength = <2>; 812 bias-disable; 813 }; 814 815 i2c2_sleep: i2c2-sleep-state { 816 pins = "gpio6", "gpio7"; 817 function = "blsp_i2c2"; 818 drive-strength = <2>; 819 bias-pull-up; 820 }; 821 822 i2c3_default: i2c3-default-state { 823 pins = "gpio10", "gpio11"; 824 function = "blsp_i2c3"; 825 drive-strength = <2>; 826 bias-disable; 827 }; 828 829 i2c3_sleep: i2c3-sleep-state { 830 pins = "gpio10", "gpio11"; 831 function = "blsp_i2c3"; 832 drive-strength = <2>; 833 bias-pull-up; 834 }; 835 836 i2c4_default: i2c4-default-state { 837 pins = "gpio14", "gpio15"; 838 function = "blsp_i2c4"; 839 drive-strength = <2>; 840 bias-disable; 841 }; 842 843 i2c4_sleep: i2c4-sleep-state { 844 pins = "gpio14", "gpio15"; 845 function = "blsp_i2c4"; 846 drive-strength = <2>; 847 bias-pull-up; 848 }; 849 850 i2c5_default: i2c5-default-state { 851 pins = "gpio18", "gpio19"; 852 function = "blsp_i2c5"; 853 drive-strength = <2>; 854 bias-disable; 855 }; 856 857 i2c5_sleep: i2c5-sleep-state { 858 pins = "gpio18", "gpio19"; 859 function = "blsp_i2c5"; 860 drive-strength = <2>; 861 bias-pull-up; 862 }; 863 864 i2c6_default: i2c6-default-state { 865 pins = "gpio22", "gpio23"; 866 function = "blsp_i2c6"; 867 drive-strength = <2>; 868 bias-disable; 869 }; 870 871 i2c6_sleep: i2c6-sleep-state { 872 pins = "gpio22", "gpio23"; 873 function = "blsp_i2c6"; 874 drive-strength = <2>; 875 bias-pull-up; 876 }; 877 878 i2c7_default: i2c7-default-state { 879 pins = "gpio26", "gpio27"; 880 function = "blsp_i2c7"; 881 drive-strength = <2>; 882 bias-disable; 883 }; 884 885 i2c7_sleep: i2c7-sleep-state { 886 pins = "gpio26", "gpio27"; 887 function = "blsp_i2c7"; 888 drive-strength = <2>; 889 bias-pull-up; 890 }; 891 892 i2c8_default: i2c8-default-state { 893 pins = "gpio30", "gpio31"; 894 function = "blsp_i2c8_a"; 895 drive-strength = <2>; 896 bias-disable; 897 }; 898 899 i2c8_sleep: i2c8-sleep-state { 900 pins = "gpio30", "gpio31"; 901 function = "blsp_i2c8_a"; 902 drive-strength = <2>; 903 bias-pull-up; 904 }; 905 906 cci0_default: cci0-default-state { 907 pins = "gpio36","gpio37"; 908 function = "cci_i2c"; 909 bias-pull-up; 910 drive-strength = <2>; 911 }; 912 913 cci1_default: cci1-default-state { 914 pins = "gpio38","gpio39"; 915 function = "cci_i2c"; 916 bias-pull-up; 917 drive-strength = <2>; 918 }; 919 920 sdc1_state_on: sdc1-on-state { 921 clk-pins { 922 pins = "sdc1_clk"; 923 bias-disable; 924 drive-strength = <16>; 925 }; 926 927 cmd-pins { 928 pins = "sdc1_cmd"; 929 bias-pull-up; 930 drive-strength = <10>; 931 }; 932 933 data-pins { 934 pins = "sdc1_data"; 935 bias-pull-up; 936 drive-strength = <10>; 937 }; 938 939 rclk-pins { 940 pins = "sdc1_rclk"; 941 bias-pull-down; 942 }; 943 }; 944 945 sdc1_state_off: sdc1-off-state { 946 clk-pins { 947 pins = "sdc1_clk"; 948 bias-disable; 949 drive-strength = <2>; 950 }; 951 952 cmd-pins { 953 pins = "sdc1_cmd"; 954 bias-pull-up; 955 drive-strength = <2>; 956 }; 957 958 data-pins { 959 pins = "sdc1_data"; 960 bias-pull-up; 961 drive-strength = <2>; 962 }; 963 964 rclk-pins { 965 pins = "sdc1_rclk"; 966 bias-pull-down; 967 }; 968 }; 969 970 sdc2_state_on: sdc2-on-state { 971 clk-pins { 972 pins = "sdc2_clk"; 973 bias-disable; 974 drive-strength = <16>; 975 }; 976 977 cmd-pins { 978 pins = "sdc2_cmd"; 979 bias-pull-up; 980 drive-strength = <10>; 981 }; 982 983 data-pins { 984 pins = "sdc2_data"; 985 bias-pull-up; 986 drive-strength = <10>; 987 }; 988 }; 989 990 sdc2_state_off: sdc2-off-state { 991 clk-pins { 992 pins = "sdc2_clk"; 993 bias-disable; 994 drive-strength = <2>; 995 }; 996 997 cmd-pins { 998 pins = "sdc2_cmd"; 999 bias-pull-up; 1000 drive-strength = <2>; 1001 }; 1002 1003 data-pins { 1004 pins = "sdc2_data"; 1005 bias-pull-up; 1006 drive-strength = <2>; 1007 }; 1008 }; 1009 }; 1010 1011 remoteproc_mss: remoteproc@4080000 { 1012 compatible = "qcom,sdm660-mss-pil"; 1013 reg = <0x04080000 0x100>, <0x04180000 0x40>; 1014 reg-names = "qdsp6", "rmb"; 1015 1016 interrupts-extended = <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 1017 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1018 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1019 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1020 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1021 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1022 interrupt-names = "wdog", 1023 "fatal", 1024 "ready", 1025 "handover", 1026 "stop-ack", 1027 "shutdown-ack"; 1028 1029 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1030 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, 1031 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1032 <&gcc GPLL0_OUT_MSSCC>, 1033 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1034 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 1035 <&rpmcc RPM_SMD_QDSS_CLK>, 1036 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1037 clock-names = "iface", 1038 "bus", 1039 "mem", 1040 "gpll0_mss", 1041 "snoc_axi", 1042 "mnoc_axi", 1043 "qdss", 1044 "xo"; 1045 1046 qcom,smem-states = <&modem_smp2p_out 0>; 1047 qcom,smem-state-names = "stop"; 1048 1049 resets = <&gcc GCC_MSS_RESTART>; 1050 reset-names = "mss_restart"; 1051 1052 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 1053 1054 power-domains = <&rpmpd SDM660_VDDCX>, 1055 <&rpmpd SDM660_VDDMX>; 1056 power-domain-names = "cx", "mx"; 1057 1058 memory-region = <&mba_region>, <&mpss_region>; 1059 1060 status = "disabled"; 1061 1062 glink-edge { 1063 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; 1064 label = "modem"; 1065 qcom,remote-pid = <1>; 1066 mboxes = <&apcs_glb 15>; 1067 }; 1068 }; 1069 1070 adreno_gpu: gpu@5000000 { 1071 compatible = "qcom,adreno-508.0", "qcom,adreno"; 1072 1073 reg = <0x05000000 0x40000>; 1074 reg-names = "kgsl_3d0_reg_memory"; 1075 1076 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1077 1078 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1079 <&gpucc GPUCC_RBBMTIMER_CLK>, 1080 <&gcc GCC_BIMC_GFX_CLK>, 1081 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1082 <&gpucc GPUCC_RBCPR_CLK>, 1083 <&gpucc GPUCC_GFX3D_CLK>; 1084 1085 clock-names = "iface", 1086 "rbbmtimer", 1087 "mem", 1088 "mem_iface", 1089 "rbcpr", 1090 "core"; 1091 1092 power-domains = <&rpmpd SDM660_VDDMX>; 1093 iommus = <&kgsl_smmu 0>; 1094 1095 nvmem-cells = <&gpu_speed_bin>; 1096 nvmem-cell-names = "speed_bin"; 1097 1098 interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>; 1099 interconnect-names = "gfx-mem"; 1100 1101 operating-points-v2 = <&gpu_sdm630_opp_table>; 1102 #cooling-cells = <2>; 1103 1104 status = "disabled"; 1105 1106 gpu_sdm630_opp_table: opp-table { 1107 compatible = "operating-points-v2"; 1108 opp-775000000 { 1109 opp-hz = /bits/ 64 <775000000>; 1110 opp-level = <RPM_SMD_LEVEL_TURBO>; 1111 opp-peak-kBps = <5412000>; 1112 opp-supported-hw = <0xa2>; 1113 }; 1114 opp-647000000 { 1115 opp-hz = /bits/ 64 <647000000>; 1116 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1117 opp-peak-kBps = <4068000>; 1118 opp-supported-hw = <0xff>; 1119 }; 1120 opp-588000000 { 1121 opp-hz = /bits/ 64 <588000000>; 1122 opp-level = <RPM_SMD_LEVEL_NOM>; 1123 opp-peak-kBps = <3072000>; 1124 opp-supported-hw = <0xff>; 1125 }; 1126 opp-465000000 { 1127 opp-hz = /bits/ 64 <465000000>; 1128 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1129 opp-peak-kBps = <2724000>; 1130 opp-supported-hw = <0xff>; 1131 }; 1132 opp-370000000 { 1133 opp-hz = /bits/ 64 <370000000>; 1134 opp-level = <RPM_SMD_LEVEL_SVS>; 1135 opp-peak-kBps = <2188000>; 1136 opp-supported-hw = <0xff>; 1137 }; 1138 opp-240000000 { 1139 opp-hz = /bits/ 64 <240000000>; 1140 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1141 opp-peak-kBps = <1648000>; 1142 opp-supported-hw = <0xff>; 1143 }; 1144 opp-160000000 { 1145 opp-hz = /bits/ 64 <160000000>; 1146 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1147 opp-peak-kBps = <1200000>; 1148 opp-supported-hw = <0xff>; 1149 }; 1150 }; 1151 1152 adreno_gpu_zap: zap-shader { 1153 memory-region = <&zap_shader_region>; 1154 }; 1155 }; 1156 1157 kgsl_smmu: iommu@5040000 { 1158 compatible = "qcom,sdm630-smmu-v2", 1159 "qcom,adreno-smmu", "qcom,smmu-v2"; 1160 reg = <0x05040000 0x10000>; 1161 1162 /* 1163 * GX GDSC parent is CX. We need to bring up CX for SMMU 1164 * but we need both up for Adreno. On the other hand, we 1165 * need to manage the GX rpmpd domain in the adreno driver. 1166 * Enable CX/GX GDSCs here so that we can manage just the GX 1167 * RPM Power Domain in the Adreno driver. 1168 */ 1169 power-domains = <&gpucc GPU_GX_GDSC>; 1170 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1171 <&gcc GCC_BIMC_GFX_CLK>, 1172 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1173 clock-names = "iface", 1174 "mem", 1175 "mem_iface"; 1176 #global-interrupts = <2>; 1177 #iommu-cells = <1>; 1178 1179 interrupts = 1180 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1182 1183 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 1191 }; 1192 1193 gpucc: clock-controller@5065000 { 1194 compatible = "qcom,gpucc-sdm630"; 1195 #clock-cells = <1>; 1196 #reset-cells = <1>; 1197 #power-domain-cells = <1>; 1198 reg = <0x05065000 0x9038>; 1199 1200 clocks = <&xo_board>, 1201 <&gcc GCC_GPU_GPLL0_CLK>, 1202 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1203 clock-names = "xo", 1204 "gcc_gpu_gpll0_clk", 1205 "gcc_gpu_gpll0_div_clk"; 1206 }; 1207 1208 lpass_smmu: iommu@5100000 { 1209 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 1210 reg = <0x05100000 0x40000>; 1211 #iommu-cells = <1>; 1212 1213 #global-interrupts = <2>; 1214 interrupts = 1215 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1217 1218 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 1235 }; 1236 1237 sram@290000 { 1238 compatible = "qcom,rpm-stats"; 1239 reg = <0x00290000 0x10000>; 1240 }; 1241 1242 spmi_bus: spmi@800f000 { 1243 compatible = "qcom,spmi-pmic-arb"; 1244 reg = <0x0800f000 0x1000>, 1245 <0x08400000 0x1000000>, 1246 <0x09400000 0x1000000>, 1247 <0x0a400000 0x220000>, 1248 <0x0800a000 0x3000>; 1249 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1250 interrupt-names = "periph_irq"; 1251 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1252 qcom,ee = <0>; 1253 qcom,channel = <0>; 1254 #address-cells = <2>; 1255 #size-cells = <0>; 1256 interrupt-controller; 1257 #interrupt-cells = <4>; 1258 }; 1259 1260 usb3: usb@a8f8800 { 1261 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1262 reg = <0x0a8f8800 0x400>; 1263 status = "disabled"; 1264 #address-cells = <1>; 1265 #size-cells = <1>; 1266 ranges; 1267 1268 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1269 <&gcc GCC_USB30_MASTER_CLK>, 1270 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1271 <&gcc GCC_USB30_SLEEP_CLK>, 1272 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 1273 clock-names = "cfg_noc", 1274 "core", 1275 "iface", 1276 "sleep", 1277 "mock_utmi"; 1278 1279 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1280 <&gcc GCC_USB30_MASTER_CLK>; 1281 assigned-clock-rates = <19200000>, <120000000>; 1282 1283 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1284 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1285 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1286 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1287 interrupt-names = "pwr_event", 1288 "qusb2_phy", 1289 "hs_phy_irq", 1290 "ss_phy_irq"; 1291 1292 power-domains = <&gcc USB_30_GDSC>; 1293 1294 resets = <&gcc GCC_USB_30_BCR>; 1295 1296 usb3_dwc3: usb@a800000 { 1297 compatible = "snps,dwc3"; 1298 reg = <0x0a800000 0xc8d0>; 1299 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1300 snps,dis_u2_susphy_quirk; 1301 snps,dis_enblslpm_quirk; 1302 snps,parkmode-disable-ss-quirk; 1303 1304 phys = <&qusb2phy0>, <&usb3_qmpphy>; 1305 phy-names = "usb2-phy", "usb3-phy"; 1306 snps,hird-threshold = /bits/ 8 <0>; 1307 }; 1308 }; 1309 1310 usb3_qmpphy: phy@c010000 { 1311 compatible = "qcom,sdm660-qmp-usb3-phy"; 1312 reg = <0x0c010000 0x1000>; 1313 1314 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 1315 <&gcc GCC_USB3_CLKREF_CLK>, 1316 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1317 <&gcc GCC_USB3_PHY_PIPE_CLK>; 1318 clock-names = "aux", 1319 "ref", 1320 "cfg_ahb", 1321 "pipe"; 1322 clock-output-names = "usb3_phy_pipe_clk_src"; 1323 #clock-cells = <0>; 1324 #phy-cells = <0>; 1325 1326 resets = <&gcc GCC_USB3_PHY_BCR>, 1327 <&gcc GCC_USB3PHY_PHY_BCR>; 1328 reset-names = "phy", 1329 "phy_phy"; 1330 1331 qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>; 1332 1333 status = "disabled"; 1334 }; 1335 1336 qusb2phy0: phy@c012000 { 1337 compatible = "qcom,sdm660-qusb2-phy"; 1338 reg = <0x0c012000 0x180>; 1339 #phy-cells = <0>; 1340 1341 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1342 <&gcc GCC_RX0_USB2_CLKREF_CLK>; 1343 clock-names = "cfg_ahb", "ref"; 1344 1345 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1346 nvmem-cells = <&qusb2_hstx_trim>; 1347 status = "disabled"; 1348 }; 1349 1350 qusb2phy1: phy@c014000 { 1351 compatible = "qcom,sdm660-qusb2-phy"; 1352 reg = <0x0c014000 0x180>; 1353 #phy-cells = <0>; 1354 1355 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1356 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1357 clock-names = "cfg_ahb", "ref"; 1358 1359 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1360 nvmem-cells = <&qusb2_hstx_trim>; 1361 status = "disabled"; 1362 }; 1363 1364 sdhc_2: mmc@c084000 { 1365 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1366 reg = <0x0c084000 0x1000>; 1367 reg-names = "hc"; 1368 1369 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1371 interrupt-names = "hc_irq", "pwr_irq"; 1372 1373 bus-width = <4>; 1374 1375 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1376 <&gcc GCC_SDCC2_APPS_CLK>, 1377 <&xo_board>; 1378 clock-names = "iface", "core", "xo"; 1379 1380 1381 interconnects = <&a2noc 3 &a2noc 10>, 1382 <&gnoc 0 &cnoc 28>; 1383 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1384 operating-points-v2 = <&sdhc2_opp_table>; 1385 1386 pinctrl-names = "default", "sleep"; 1387 pinctrl-0 = <&sdc2_state_on>; 1388 pinctrl-1 = <&sdc2_state_off>; 1389 power-domains = <&rpmpd SDM660_VDDCX>; 1390 1391 status = "disabled"; 1392 1393 sdhc2_opp_table: opp-table { 1394 compatible = "operating-points-v2"; 1395 1396 opp-50000000 { 1397 opp-hz = /bits/ 64 <50000000>; 1398 required-opps = <&rpmpd_opp_low_svs>; 1399 opp-peak-kBps = <200000 140000>; 1400 opp-avg-kBps = <130718 133320>; 1401 }; 1402 opp-100000000 { 1403 opp-hz = /bits/ 64 <100000000>; 1404 required-opps = <&rpmpd_opp_svs>; 1405 opp-peak-kBps = <250000 160000>; 1406 opp-avg-kBps = <196078 150000>; 1407 }; 1408 opp-200000000 { 1409 opp-hz = /bits/ 64 <200000000>; 1410 required-opps = <&rpmpd_opp_nom>; 1411 opp-peak-kBps = <4096000 4096000>; 1412 opp-avg-kBps = <1338562 1338562>; 1413 }; 1414 }; 1415 }; 1416 1417 sdhc_1: mmc@c0c4000 { 1418 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1419 reg = <0x0c0c4000 0x1000>, 1420 <0x0c0c5000 0x1000>, 1421 <0x0c0c8000 0x8000>; 1422 reg-names = "hc", "cqhci", "ice"; 1423 1424 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1426 interrupt-names = "hc_irq", "pwr_irq"; 1427 1428 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1429 <&gcc GCC_SDCC1_APPS_CLK>, 1430 <&xo_board>, 1431 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1432 clock-names = "iface", "core", "xo", "ice"; 1433 1434 interconnects = <&a2noc 2 &a2noc 10>, 1435 <&gnoc 0 &cnoc 27>; 1436 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1437 operating-points-v2 = <&sdhc1_opp_table>; 1438 pinctrl-names = "default", "sleep"; 1439 pinctrl-0 = <&sdc1_state_on>; 1440 pinctrl-1 = <&sdc1_state_off>; 1441 power-domains = <&rpmpd SDM660_VDDCX>; 1442 1443 bus-width = <8>; 1444 non-removable; 1445 1446 status = "disabled"; 1447 1448 sdhc1_opp_table: opp-table { 1449 compatible = "operating-points-v2"; 1450 1451 opp-50000000 { 1452 opp-hz = /bits/ 64 <50000000>; 1453 required-opps = <&rpmpd_opp_low_svs>; 1454 opp-peak-kBps = <200000 140000>; 1455 opp-avg-kBps = <130718 133320>; 1456 }; 1457 opp-100000000 { 1458 opp-hz = /bits/ 64 <100000000>; 1459 required-opps = <&rpmpd_opp_svs>; 1460 opp-peak-kBps = <250000 160000>; 1461 opp-avg-kBps = <196078 150000>; 1462 }; 1463 opp-384000000 { 1464 opp-hz = /bits/ 64 <384000000>; 1465 required-opps = <&rpmpd_opp_nom>; 1466 opp-peak-kBps = <4096000 4096000>; 1467 opp-avg-kBps = <1338562 1338562>; 1468 }; 1469 }; 1470 }; 1471 1472 usb2: usb@c2f8800 { 1473 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1474 reg = <0x0c2f8800 0x400>; 1475 status = "disabled"; 1476 #address-cells = <1>; 1477 #size-cells = <1>; 1478 ranges; 1479 1480 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>, 1481 <&gcc GCC_USB20_MASTER_CLK>, 1482 <&gcc GCC_USB20_SLEEP_CLK>, 1483 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 1484 clock-names = "cfg_noc", "core", 1485 "sleep", "mock_utmi"; 1486 1487 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1488 <&gcc GCC_USB20_MASTER_CLK>; 1489 assigned-clock-rates = <19200000>, <60000000>; 1490 1491 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1494 interrupt-names = "pwr_event", 1495 "qusb2_phy", 1496 "hs_phy_irq"; 1497 1498 qcom,select-utmi-as-pipe-clk; 1499 1500 resets = <&gcc GCC_USB_20_BCR>; 1501 1502 usb2_dwc3: usb@c200000 { 1503 compatible = "snps,dwc3"; 1504 reg = <0x0c200000 0xc8d0>; 1505 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1506 snps,dis_u2_susphy_quirk; 1507 snps,dis_enblslpm_quirk; 1508 1509 /* This is the HS-only host */ 1510 maximum-speed = "high-speed"; 1511 phys = <&qusb2phy1>; 1512 phy-names = "usb2-phy"; 1513 snps,hird-threshold = /bits/ 8 <0>; 1514 }; 1515 }; 1516 1517 mmcc: clock-controller@c8c0000 { 1518 compatible = "qcom,mmcc-sdm630"; 1519 reg = <0x0c8c0000 0x40000>; 1520 #clock-cells = <1>; 1521 #reset-cells = <1>; 1522 #power-domain-cells = <1>; 1523 clock-names = "xo", 1524 "sleep_clk", 1525 "gpll0", 1526 "gpll0_div", 1527 "dsi0pll", 1528 "dsi0pllbyte", 1529 "dsi1pll", 1530 "dsi1pllbyte", 1531 "dp_link_2x_clk_divsel_five", 1532 "dp_vco_divided_clk_src_mux"; 1533 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1534 <&sleep_clk>, 1535 <&gcc GCC_MMSS_GPLL0_CLK>, 1536 <&gcc GCC_MMSS_GPLL0_DIV_CLK>, 1537 <&mdss_dsi0_phy 1>, 1538 <&mdss_dsi0_phy 0>, 1539 <0>, 1540 <0>, 1541 <0>, 1542 <0>; 1543 }; 1544 1545 mdss: display-subsystem@c900000 { 1546 compatible = "qcom,mdss"; 1547 reg = <0x0c900000 0x1000>, 1548 <0x0c9b0000 0x1040>; 1549 reg-names = "mdss_phys", "vbif_phys"; 1550 1551 power-domains = <&mmcc MDSS_GDSC>; 1552 1553 clocks = <&mmcc MDSS_AHB_CLK>, 1554 <&mmcc MDSS_AXI_CLK>, 1555 <&mmcc MDSS_VSYNC_CLK>, 1556 <&mmcc MDSS_MDP_CLK>; 1557 clock-names = "iface", 1558 "bus", 1559 "vsync", 1560 "core"; 1561 1562 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1563 1564 interrupt-controller; 1565 #interrupt-cells = <1>; 1566 1567 #address-cells = <1>; 1568 #size-cells = <1>; 1569 ranges; 1570 status = "disabled"; 1571 1572 mdp: display-controller@c901000 { 1573 compatible = "qcom,sdm630-mdp5", "qcom,mdp5"; 1574 reg = <0x0c901000 0x89000>; 1575 reg-names = "mdp_phys"; 1576 1577 interrupt-parent = <&mdss>; 1578 interrupts = <0>; 1579 1580 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1581 <&mmcc MDSS_VSYNC_CLK>; 1582 assigned-clock-rates = <300000000>, 1583 <19200000>; 1584 clocks = <&mmcc MDSS_AHB_CLK>, 1585 <&mmcc MDSS_AXI_CLK>, 1586 <&mmcc MDSS_MDP_CLK>, 1587 <&mmcc MDSS_VSYNC_CLK>; 1588 clock-names = "iface", 1589 "bus", 1590 "core", 1591 "vsync"; 1592 1593 interconnects = <&mnoc 2 &bimc 5>, 1594 <&mnoc 3 &bimc 5>, 1595 <&gnoc 0 &mnoc 17>; 1596 interconnect-names = "mdp0-mem", 1597 "mdp1-mem", 1598 "rotator-mem"; 1599 iommus = <&mmss_smmu 0>; 1600 operating-points-v2 = <&mdp_opp_table>; 1601 power-domains = <&rpmpd SDM660_VDDCX>; 1602 1603 ports { 1604 #address-cells = <1>; 1605 #size-cells = <0>; 1606 1607 port@0 { 1608 reg = <0>; 1609 mdp5_intf1_out: endpoint { 1610 remote-endpoint = <&mdss_dsi0_in>; 1611 }; 1612 }; 1613 }; 1614 1615 mdp_opp_table: opp-table { 1616 compatible = "operating-points-v2"; 1617 1618 opp-150000000 { 1619 opp-hz = /bits/ 64 <150000000>; 1620 opp-peak-kBps = <320000 320000 76800>; 1621 required-opps = <&rpmpd_opp_low_svs>; 1622 }; 1623 opp-275000000 { 1624 opp-hz = /bits/ 64 <275000000>; 1625 opp-peak-kBps = <6400000 6400000 160000>; 1626 required-opps = <&rpmpd_opp_svs>; 1627 }; 1628 opp-300000000 { 1629 opp-hz = /bits/ 64 <300000000>; 1630 opp-peak-kBps = <6400000 6400000 190000>; 1631 required-opps = <&rpmpd_opp_svs_plus>; 1632 }; 1633 opp-330000000 { 1634 opp-hz = /bits/ 64 <330000000>; 1635 opp-peak-kBps = <6400000 6400000 240000>; 1636 required-opps = <&rpmpd_opp_nom>; 1637 }; 1638 opp-412500000 { 1639 opp-hz = /bits/ 64 <412500000>; 1640 opp-peak-kBps = <6400000 6400000 320000>; 1641 required-opps = <&rpmpd_opp_turbo>; 1642 }; 1643 }; 1644 }; 1645 1646 mdss_dsi0: dsi@c994000 { 1647 compatible = "qcom,sdm660-dsi-ctrl", 1648 "qcom,mdss-dsi-ctrl"; 1649 reg = <0x0c994000 0x400>; 1650 reg-names = "dsi_ctrl"; 1651 1652 operating-points-v2 = <&dsi_opp_table>; 1653 power-domains = <&rpmpd SDM660_VDDCX>; 1654 1655 interrupt-parent = <&mdss>; 1656 interrupts = <4>; 1657 1658 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1659 <&mmcc PCLK0_CLK_SRC>; 1660 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1661 <&mdss_dsi0_phy 1>; 1662 1663 clocks = <&mmcc MDSS_MDP_CLK>, 1664 <&mmcc MDSS_BYTE0_CLK>, 1665 <&mmcc MDSS_BYTE0_INTF_CLK>, 1666 <&mmcc MNOC_AHB_CLK>, 1667 <&mmcc MDSS_AHB_CLK>, 1668 <&mmcc MDSS_AXI_CLK>, 1669 <&mmcc MISC_AHB_CLK>, 1670 <&mmcc MDSS_PCLK0_CLK>, 1671 <&mmcc MDSS_ESC0_CLK>; 1672 clock-names = "mdp_core", 1673 "byte", 1674 "byte_intf", 1675 "mnoc", 1676 "iface", 1677 "bus", 1678 "core_mmss", 1679 "pixel", 1680 "core"; 1681 1682 phys = <&mdss_dsi0_phy>; 1683 1684 status = "disabled"; 1685 1686 ports { 1687 #address-cells = <1>; 1688 #size-cells = <0>; 1689 1690 port@0 { 1691 reg = <0>; 1692 mdss_dsi0_in: endpoint { 1693 remote-endpoint = <&mdp5_intf1_out>; 1694 }; 1695 }; 1696 1697 port@1 { 1698 reg = <1>; 1699 mdss_dsi0_out: endpoint { 1700 }; 1701 }; 1702 }; 1703 }; 1704 1705 mdss_dsi0_phy: phy@c994400 { 1706 compatible = "qcom,dsi-phy-14nm-660"; 1707 reg = <0x0c994400 0x100>, 1708 <0x0c994500 0x300>, 1709 <0x0c994800 0x188>; 1710 reg-names = "dsi_phy", 1711 "dsi_phy_lane", 1712 "dsi_pll"; 1713 1714 #clock-cells = <1>; 1715 #phy-cells = <0>; 1716 1717 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1718 clock-names = "iface", "ref"; 1719 status = "disabled"; 1720 }; 1721 }; 1722 1723 blsp1_dma: dma-controller@c144000 { 1724 compatible = "qcom,bam-v1.7.0"; 1725 reg = <0x0c144000 0x1f000>; 1726 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1727 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1728 clock-names = "bam_clk"; 1729 #dma-cells = <1>; 1730 qcom,ee = <0>; 1731 qcom,controlled-remotely; 1732 num-channels = <18>; 1733 qcom,num-ees = <4>; 1734 }; 1735 1736 blsp1_uart1: serial@c16f000 { 1737 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1738 reg = <0x0c16f000 0x200>; 1739 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1740 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1741 <&gcc GCC_BLSP1_AHB_CLK>; 1742 clock-names = "core", "iface"; 1743 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1744 dma-names = "tx", "rx"; 1745 pinctrl-names = "default", "sleep"; 1746 pinctrl-0 = <&blsp1_uart1_default>; 1747 pinctrl-1 = <&blsp1_uart1_sleep>; 1748 status = "disabled"; 1749 }; 1750 1751 blsp1_uart2: serial@c170000 { 1752 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1753 reg = <0x0c170000 0x1000>; 1754 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1755 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1756 <&gcc GCC_BLSP1_AHB_CLK>; 1757 clock-names = "core", "iface"; 1758 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1759 dma-names = "tx", "rx"; 1760 pinctrl-names = "default"; 1761 pinctrl-0 = <&blsp1_uart2_default>; 1762 status = "disabled"; 1763 }; 1764 1765 blsp_i2c1: i2c@c175000 { 1766 compatible = "qcom,i2c-qup-v2.2.1"; 1767 reg = <0x0c175000 0x600>; 1768 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1769 1770 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1771 <&gcc GCC_BLSP1_AHB_CLK>; 1772 clock-names = "core", "iface"; 1773 clock-frequency = <400000>; 1774 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1775 dma-names = "tx", "rx"; 1776 1777 pinctrl-names = "default", "sleep"; 1778 pinctrl-0 = <&i2c1_default>; 1779 pinctrl-1 = <&i2c1_sleep>; 1780 #address-cells = <1>; 1781 #size-cells = <0>; 1782 status = "disabled"; 1783 }; 1784 1785 blsp_i2c2: i2c@c176000 { 1786 compatible = "qcom,i2c-qup-v2.2.1"; 1787 reg = <0x0c176000 0x600>; 1788 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1789 1790 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1791 <&gcc GCC_BLSP1_AHB_CLK>; 1792 clock-names = "core", "iface"; 1793 clock-frequency = <400000>; 1794 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1795 dma-names = "tx", "rx"; 1796 1797 pinctrl-names = "default", "sleep"; 1798 pinctrl-0 = <&i2c2_default>; 1799 pinctrl-1 = <&i2c2_sleep>; 1800 #address-cells = <1>; 1801 #size-cells = <0>; 1802 status = "disabled"; 1803 }; 1804 1805 blsp_i2c3: i2c@c177000 { 1806 compatible = "qcom,i2c-qup-v2.2.1"; 1807 reg = <0x0c177000 0x600>; 1808 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1809 1810 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1811 <&gcc GCC_BLSP1_AHB_CLK>; 1812 clock-names = "core", "iface"; 1813 clock-frequency = <400000>; 1814 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1815 dma-names = "tx", "rx"; 1816 1817 pinctrl-names = "default", "sleep"; 1818 pinctrl-0 = <&i2c3_default>; 1819 pinctrl-1 = <&i2c3_sleep>; 1820 #address-cells = <1>; 1821 #size-cells = <0>; 1822 status = "disabled"; 1823 }; 1824 1825 blsp_i2c4: i2c@c178000 { 1826 compatible = "qcom,i2c-qup-v2.2.1"; 1827 reg = <0x0c178000 0x600>; 1828 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1829 1830 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1831 <&gcc GCC_BLSP1_AHB_CLK>; 1832 clock-names = "core", "iface"; 1833 clock-frequency = <400000>; 1834 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1835 dma-names = "tx", "rx"; 1836 1837 pinctrl-names = "default", "sleep"; 1838 pinctrl-0 = <&i2c4_default>; 1839 pinctrl-1 = <&i2c4_sleep>; 1840 #address-cells = <1>; 1841 #size-cells = <0>; 1842 status = "disabled"; 1843 }; 1844 1845 blsp2_dma: dma-controller@c184000 { 1846 compatible = "qcom,bam-v1.7.0"; 1847 reg = <0x0c184000 0x1f000>; 1848 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1849 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1850 clock-names = "bam_clk"; 1851 #dma-cells = <1>; 1852 qcom,ee = <0>; 1853 qcom,controlled-remotely; 1854 num-channels = <18>; 1855 qcom,num-ees = <4>; 1856 }; 1857 1858 blsp2_uart1: serial@c1af000 { 1859 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1860 reg = <0x0c1af000 0x200>; 1861 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1862 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1863 <&gcc GCC_BLSP2_AHB_CLK>; 1864 clock-names = "core", "iface"; 1865 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1866 dma-names = "tx", "rx"; 1867 pinctrl-names = "default", "sleep"; 1868 pinctrl-0 = <&blsp2_uart1_default>; 1869 pinctrl-1 = <&blsp2_uart1_sleep>; 1870 status = "disabled"; 1871 }; 1872 1873 blsp_i2c5: i2c@c1b5000 { 1874 compatible = "qcom,i2c-qup-v2.2.1"; 1875 reg = <0x0c1b5000 0x600>; 1876 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1877 1878 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1879 <&gcc GCC_BLSP2_AHB_CLK>; 1880 clock-names = "core", "iface"; 1881 clock-frequency = <400000>; 1882 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1883 dma-names = "tx", "rx"; 1884 1885 pinctrl-names = "default", "sleep"; 1886 pinctrl-0 = <&i2c5_default>; 1887 pinctrl-1 = <&i2c5_sleep>; 1888 #address-cells = <1>; 1889 #size-cells = <0>; 1890 status = "disabled"; 1891 }; 1892 1893 blsp_i2c6: i2c@c1b6000 { 1894 compatible = "qcom,i2c-qup-v2.2.1"; 1895 reg = <0x0c1b6000 0x600>; 1896 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1897 1898 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1899 <&gcc GCC_BLSP2_AHB_CLK>; 1900 clock-names = "core", "iface"; 1901 clock-frequency = <400000>; 1902 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1903 dma-names = "tx", "rx"; 1904 1905 pinctrl-names = "default", "sleep"; 1906 pinctrl-0 = <&i2c6_default>; 1907 pinctrl-1 = <&i2c6_sleep>; 1908 #address-cells = <1>; 1909 #size-cells = <0>; 1910 status = "disabled"; 1911 }; 1912 1913 blsp_i2c7: i2c@c1b7000 { 1914 compatible = "qcom,i2c-qup-v2.2.1"; 1915 reg = <0x0c1b7000 0x600>; 1916 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1917 1918 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1919 <&gcc GCC_BLSP2_AHB_CLK>; 1920 clock-names = "core", "iface"; 1921 clock-frequency = <400000>; 1922 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1923 dma-names = "tx", "rx"; 1924 1925 pinctrl-names = "default", "sleep"; 1926 pinctrl-0 = <&i2c7_default>; 1927 pinctrl-1 = <&i2c7_sleep>; 1928 #address-cells = <1>; 1929 #size-cells = <0>; 1930 status = "disabled"; 1931 }; 1932 1933 blsp_i2c8: i2c@c1b8000 { 1934 compatible = "qcom,i2c-qup-v2.2.1"; 1935 reg = <0x0c1b8000 0x600>; 1936 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1937 1938 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1939 <&gcc GCC_BLSP2_AHB_CLK>; 1940 clock-names = "core", "iface"; 1941 clock-frequency = <400000>; 1942 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1943 dma-names = "tx", "rx"; 1944 1945 pinctrl-names = "default", "sleep"; 1946 pinctrl-0 = <&i2c8_default>; 1947 pinctrl-1 = <&i2c8_sleep>; 1948 #address-cells = <1>; 1949 #size-cells = <0>; 1950 status = "disabled"; 1951 }; 1952 1953 sram@146bf000 { 1954 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd"; 1955 reg = <0x146bf000 0x1000>; 1956 1957 #address-cells = <1>; 1958 #size-cells = <1>; 1959 1960 ranges = <0 0x146bf000 0x1000>; 1961 1962 pil-reloc@94c { 1963 compatible = "qcom,pil-reloc-info"; 1964 reg = <0x94c 0xc8>; 1965 }; 1966 }; 1967 1968 camss: camss@ca00020 { 1969 compatible = "qcom,sdm660-camss"; 1970 reg = <0x0ca00020 0x10>, 1971 <0x0ca30000 0x100>, 1972 <0x0ca30400 0x100>, 1973 <0x0ca30800 0x100>, 1974 <0x0ca30c00 0x100>, 1975 <0x0c824000 0x1000>, 1976 <0x0ca00120 0x4>, 1977 <0x0c825000 0x1000>, 1978 <0x0ca00124 0x4>, 1979 <0x0c826000 0x1000>, 1980 <0x0ca00128 0x4>, 1981 <0x0ca31000 0x500>, 1982 <0x0ca10000 0x1000>, 1983 <0x0ca14000 0x1000>; 1984 reg-names = "csi_clk_mux", 1985 "csid0", 1986 "csid1", 1987 "csid2", 1988 "csid3", 1989 "csiphy0", 1990 "csiphy0_clk_mux", 1991 "csiphy1", 1992 "csiphy1_clk_mux", 1993 "csiphy2", 1994 "csiphy2_clk_mux", 1995 "ispif", 1996 "vfe0", 1997 "vfe1"; 1998 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1999 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 2000 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 2001 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 2002 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 2003 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 2004 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 2005 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 2006 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 2007 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 2008 interrupt-names = "csid0", 2009 "csid1", 2010 "csid2", 2011 "csid3", 2012 "csiphy0", 2013 "csiphy1", 2014 "csiphy2", 2015 "ispif", 2016 "vfe0", 2017 "vfe1"; 2018 clocks = <&mmcc CAMSS_AHB_CLK>, 2019 <&mmcc CAMSS_CPHY_CSID0_CLK>, 2020 <&mmcc CAMSS_CPHY_CSID1_CLK>, 2021 <&mmcc CAMSS_CPHY_CSID2_CLK>, 2022 <&mmcc CAMSS_CPHY_CSID3_CLK>, 2023 <&mmcc CAMSS_CSI0_AHB_CLK>, 2024 <&mmcc CAMSS_CSI0_CLK>, 2025 <&mmcc CAMSS_CPHY_CSID0_CLK>, 2026 <&mmcc CAMSS_CSI0PIX_CLK>, 2027 <&mmcc CAMSS_CSI0RDI_CLK>, 2028 <&mmcc CAMSS_CSI1_AHB_CLK>, 2029 <&mmcc CAMSS_CSI1_CLK>, 2030 <&mmcc CAMSS_CPHY_CSID1_CLK>, 2031 <&mmcc CAMSS_CSI1PIX_CLK>, 2032 <&mmcc CAMSS_CSI1RDI_CLK>, 2033 <&mmcc CAMSS_CSI2_AHB_CLK>, 2034 <&mmcc CAMSS_CSI2_CLK>, 2035 <&mmcc CAMSS_CPHY_CSID2_CLK>, 2036 <&mmcc CAMSS_CSI2PIX_CLK>, 2037 <&mmcc CAMSS_CSI2RDI_CLK>, 2038 <&mmcc CAMSS_CSI3_AHB_CLK>, 2039 <&mmcc CAMSS_CSI3_CLK>, 2040 <&mmcc CAMSS_CPHY_CSID3_CLK>, 2041 <&mmcc CAMSS_CSI3PIX_CLK>, 2042 <&mmcc CAMSS_CSI3RDI_CLK>, 2043 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 2044 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 2045 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 2046 <&mmcc CSIPHY_AHB2CRIF_CLK>, 2047 <&mmcc CAMSS_CSI_VFE0_CLK>, 2048 <&mmcc CAMSS_CSI_VFE1_CLK>, 2049 <&mmcc CAMSS_ISPIF_AHB_CLK>, 2050 <&mmcc THROTTLE_CAMSS_AXI_CLK>, 2051 <&mmcc CAMSS_TOP_AHB_CLK>, 2052 <&mmcc CAMSS_VFE0_AHB_CLK>, 2053 <&mmcc CAMSS_VFE0_CLK>, 2054 <&mmcc CAMSS_VFE0_STREAM_CLK>, 2055 <&mmcc CAMSS_VFE1_AHB_CLK>, 2056 <&mmcc CAMSS_VFE1_CLK>, 2057 <&mmcc CAMSS_VFE1_STREAM_CLK>, 2058 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 2059 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>; 2060 clock-names = "ahb", 2061 "cphy_csid0", 2062 "cphy_csid1", 2063 "cphy_csid2", 2064 "cphy_csid3", 2065 "csi0_ahb", 2066 "csi0", 2067 "csi0_phy", 2068 "csi0_pix", 2069 "csi0_rdi", 2070 "csi1_ahb", 2071 "csi1", 2072 "csi1_phy", 2073 "csi1_pix", 2074 "csi1_rdi", 2075 "csi2_ahb", 2076 "csi2", 2077 "csi2_phy", 2078 "csi2_pix", 2079 "csi2_rdi", 2080 "csi3_ahb", 2081 "csi3", 2082 "csi3_phy", 2083 "csi3_pix", 2084 "csi3_rdi", 2085 "csiphy0_timer", 2086 "csiphy1_timer", 2087 "csiphy2_timer", 2088 "csiphy_ahb2crif", 2089 "csi_vfe0", 2090 "csi_vfe1", 2091 "ispif_ahb", 2092 "throttle_axi", 2093 "top_ahb", 2094 "vfe0_ahb", 2095 "vfe0", 2096 "vfe0_stream", 2097 "vfe1_ahb", 2098 "vfe1", 2099 "vfe1_stream", 2100 "vfe_ahb", 2101 "vfe_axi"; 2102 interconnects = <&mnoc 5 &bimc 5>; 2103 interconnect-names = "vfe-mem"; 2104 iommus = <&mmss_smmu 0xc00>, 2105 <&mmss_smmu 0xc01>, 2106 <&mmss_smmu 0xc02>, 2107 <&mmss_smmu 0xc03>; 2108 power-domains = <&mmcc CAMSS_VFE0_GDSC>, 2109 <&mmcc CAMSS_VFE1_GDSC>; 2110 status = "disabled"; 2111 2112 ports { 2113 #address-cells = <1>; 2114 #size-cells = <0>; 2115 }; 2116 }; 2117 2118 cci: cci@ca0c000 { 2119 compatible = "qcom,msm8996-cci"; 2120 #address-cells = <1>; 2121 #size-cells = <0>; 2122 reg = <0x0ca0c000 0x1000>; 2123 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2124 2125 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2126 <&mmcc CAMSS_CCI_CLK>; 2127 assigned-clock-rates = <80800000>, <37500000>; 2128 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2129 <&mmcc CAMSS_CCI_AHB_CLK>, 2130 <&mmcc CAMSS_CCI_CLK>, 2131 <&mmcc CAMSS_AHB_CLK>; 2132 clock-names = "camss_top_ahb", 2133 "cci_ahb", 2134 "cci", 2135 "camss_ahb"; 2136 2137 pinctrl-names = "default"; 2138 pinctrl-0 = <&cci0_default &cci1_default>; 2139 power-domains = <&mmcc CAMSS_TOP_GDSC>; 2140 status = "disabled"; 2141 2142 cci_i2c0: i2c-bus@0 { 2143 reg = <0>; 2144 clock-frequency = <400000>; 2145 #address-cells = <1>; 2146 #size-cells = <0>; 2147 }; 2148 2149 cci_i2c1: i2c-bus@1 { 2150 reg = <1>; 2151 clock-frequency = <400000>; 2152 #address-cells = <1>; 2153 #size-cells = <0>; 2154 }; 2155 }; 2156 2157 venus: video-codec@cc00000 { 2158 compatible = "qcom,sdm660-venus"; 2159 reg = <0x0cc00000 0xff000>; 2160 clocks = <&mmcc VIDEO_CORE_CLK>, 2161 <&mmcc VIDEO_AHB_CLK>, 2162 <&mmcc VIDEO_AXI_CLK>, 2163 <&mmcc THROTTLE_VIDEO_AXI_CLK>; 2164 clock-names = "core", "iface", "bus", "bus_throttle"; 2165 interconnects = <&gnoc 0 &mnoc 13>, 2166 <&mnoc 4 &bimc 5>; 2167 interconnect-names = "cpu-cfg", "video-mem"; 2168 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2169 iommus = <&mmss_smmu 0x400>, 2170 <&mmss_smmu 0x401>, 2171 <&mmss_smmu 0x40a>, 2172 <&mmss_smmu 0x407>, 2173 <&mmss_smmu 0x40e>, 2174 <&mmss_smmu 0x40f>, 2175 <&mmss_smmu 0x408>, 2176 <&mmss_smmu 0x409>, 2177 <&mmss_smmu 0x40b>, 2178 <&mmss_smmu 0x40c>, 2179 <&mmss_smmu 0x40d>, 2180 <&mmss_smmu 0x410>, 2181 <&mmss_smmu 0x421>, 2182 <&mmss_smmu 0x428>, 2183 <&mmss_smmu 0x429>, 2184 <&mmss_smmu 0x42b>, 2185 <&mmss_smmu 0x42c>, 2186 <&mmss_smmu 0x42d>, 2187 <&mmss_smmu 0x411>, 2188 <&mmss_smmu 0x431>; 2189 memory-region = <&venus_region>; 2190 power-domains = <&mmcc VENUS_GDSC>; 2191 status = "disabled"; 2192 2193 video-decoder { 2194 compatible = "venus-decoder"; 2195 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2196 clock-names = "vcodec0_core"; 2197 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2198 }; 2199 2200 video-encoder { 2201 compatible = "venus-encoder"; 2202 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2203 clock-names = "vcodec0_core"; 2204 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2205 }; 2206 }; 2207 2208 mmss_smmu: iommu@cd00000 { 2209 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 2210 reg = <0x0cd00000 0x40000>; 2211 2212 clocks = <&mmcc MNOC_AHB_CLK>, 2213 <&mmcc BIMC_SMMU_AHB_CLK>, 2214 <&mmcc BIMC_SMMU_AXI_CLK>; 2215 clock-names = "iface-mm", "iface-smmu", 2216 "bus-smmu"; 2217 #global-interrupts = <2>; 2218 #iommu-cells = <1>; 2219 2220 interrupts = 2221 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2222 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2223 2224 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2226 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2227 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2228 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2229 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2230 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2231 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2232 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2233 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2234 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2235 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2236 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2237 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2238 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2239 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2240 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2241 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2242 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2243 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 2244 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 2245 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 2246 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 2247 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 2248 2249 status = "disabled"; 2250 }; 2251 2252 adsp_pil: remoteproc@15700000 { 2253 compatible = "qcom,sdm660-adsp-pas"; 2254 reg = <0x15700000 0x4040>; 2255 2256 interrupts-extended = 2257 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2258 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2259 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2260 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2261 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2262 interrupt-names = "wdog", "fatal", "ready", 2263 "handover", "stop-ack"; 2264 2265 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2266 clock-names = "xo"; 2267 2268 memory-region = <&adsp_region>; 2269 power-domains = <&rpmpd SDM660_VDDCX>; 2270 power-domain-names = "cx"; 2271 2272 qcom,smem-states = <&adsp_smp2p_out 0>; 2273 qcom,smem-state-names = "stop"; 2274 2275 glink-edge { 2276 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2277 2278 label = "lpass"; 2279 mboxes = <&apcs_glb 9>; 2280 qcom,remote-pid = <2>; 2281 2282 apr { 2283 compatible = "qcom,apr-v2"; 2284 qcom,glink-channels = "apr_audio_svc"; 2285 qcom,domain = <APR_DOMAIN_ADSP>; 2286 #address-cells = <1>; 2287 #size-cells = <0>; 2288 2289 service@3 { 2290 reg = <APR_SVC_ADSP_CORE>; 2291 compatible = "qcom,q6core"; 2292 }; 2293 2294 q6afe: service@4 { 2295 compatible = "qcom,q6afe"; 2296 reg = <APR_SVC_AFE>; 2297 q6afedai: dais { 2298 compatible = "qcom,q6afe-dais"; 2299 #address-cells = <1>; 2300 #size-cells = <0>; 2301 #sound-dai-cells = <1>; 2302 }; 2303 }; 2304 2305 q6asm: service@7 { 2306 compatible = "qcom,q6asm"; 2307 reg = <APR_SVC_ASM>; 2308 q6asmdai: dais { 2309 compatible = "qcom,q6asm-dais"; 2310 #address-cells = <1>; 2311 #size-cells = <0>; 2312 #sound-dai-cells = <1>; 2313 iommus = <&lpass_smmu 1>; 2314 }; 2315 }; 2316 2317 q6adm: service@8 { 2318 compatible = "qcom,q6adm"; 2319 reg = <APR_SVC_ADM>; 2320 q6routing: routing { 2321 compatible = "qcom,q6adm-routing"; 2322 #sound-dai-cells = <0>; 2323 }; 2324 }; 2325 }; 2326 }; 2327 }; 2328 2329 gnoc: interconnect@17900000 { 2330 compatible = "qcom,sdm660-gnoc"; 2331 reg = <0x17900000 0xe000>; 2332 #interconnect-cells = <1>; 2333 }; 2334 2335 apcs_glb: mailbox@17911000 { 2336 compatible = "qcom,sdm660-apcs-hmss-global", 2337 "qcom,msm8994-apcs-kpss-global"; 2338 reg = <0x17911000 0x1000>; 2339 2340 #mbox-cells = <1>; 2341 }; 2342 2343 timer@17920000 { 2344 #address-cells = <1>; 2345 #size-cells = <1>; 2346 ranges; 2347 compatible = "arm,armv7-timer-mem"; 2348 reg = <0x17920000 0x1000>; 2349 clock-frequency = <19200000>; 2350 2351 frame@17921000 { 2352 frame-number = <0>; 2353 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2354 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2355 reg = <0x17921000 0x1000>, 2356 <0x17922000 0x1000>; 2357 }; 2358 2359 frame@17923000 { 2360 frame-number = <1>; 2361 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2362 reg = <0x17923000 0x1000>; 2363 status = "disabled"; 2364 }; 2365 2366 frame@17924000 { 2367 frame-number = <2>; 2368 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2369 reg = <0x17924000 0x1000>; 2370 status = "disabled"; 2371 }; 2372 2373 frame@17925000 { 2374 frame-number = <3>; 2375 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2376 reg = <0x17925000 0x1000>; 2377 status = "disabled"; 2378 }; 2379 2380 frame@17926000 { 2381 frame-number = <4>; 2382 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2383 reg = <0x17926000 0x1000>; 2384 status = "disabled"; 2385 }; 2386 2387 frame@17927000 { 2388 frame-number = <5>; 2389 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2390 reg = <0x17927000 0x1000>; 2391 status = "disabled"; 2392 }; 2393 2394 frame@17928000 { 2395 frame-number = <6>; 2396 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2397 reg = <0x17928000 0x1000>; 2398 status = "disabled"; 2399 }; 2400 }; 2401 2402 intc: interrupt-controller@17a00000 { 2403 compatible = "arm,gic-v3"; 2404 reg = <0x17a00000 0x10000>, /* GICD */ 2405 <0x17b00000 0x100000>; /* GICR * 8 */ 2406 #interrupt-cells = <3>; 2407 #address-cells = <1>; 2408 #size-cells = <1>; 2409 ranges; 2410 interrupt-controller; 2411 #redistributor-regions = <1>; 2412 redistributor-stride = <0x0 0x20000>; 2413 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2414 }; 2415 2416 wifi: wifi@18800000 { 2417 compatible = "qcom,wcn3990-wifi"; 2418 reg = <0x18800000 0x800000>; 2419 reg-names = "membase"; 2420 memory-region = <&wlan_msa_mem>; 2421 clocks = <&rpmcc RPM_SMD_RF_CLK1_PIN>; 2422 clock-names = "cxo_ref_clk_pin"; 2423 interrupts = 2424 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 2425 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2426 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2427 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2428 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2429 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2430 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2431 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2432 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2433 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2434 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2435 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2436 iommus = <&anoc2_smmu 0x1a00>, 2437 <&anoc2_smmu 0x1a01>; 2438 qcom,snoc-host-cap-8bit-quirk; 2439 qcom,no-msa-ready-indicator; 2440 status = "disabled"; 2441 }; 2442 }; 2443 2444 sound: sound { 2445 }; 2446 2447 thermal-zones { 2448 aoss-thermal { 2449 polling-delay-passive = <250>; 2450 2451 thermal-sensors = <&tsens 0>; 2452 2453 trips { 2454 aoss_alert0: trip-point0 { 2455 temperature = <105000>; 2456 hysteresis = <1000>; 2457 type = "hot"; 2458 }; 2459 }; 2460 }; 2461 2462 cpuss0-thermal { 2463 polling-delay-passive = <250>; 2464 2465 thermal-sensors = <&tsens 1>; 2466 2467 trips { 2468 cpuss0_alert0: trip-point0 { 2469 temperature = <125000>; 2470 hysteresis = <1000>; 2471 type = "hot"; 2472 }; 2473 }; 2474 }; 2475 2476 cpuss1-thermal { 2477 polling-delay-passive = <250>; 2478 2479 thermal-sensors = <&tsens 2>; 2480 2481 trips { 2482 cpuss1_alert0: trip-point0 { 2483 temperature = <125000>; 2484 hysteresis = <1000>; 2485 type = "hot"; 2486 }; 2487 }; 2488 }; 2489 2490 cpu0-thermal { 2491 polling-delay-passive = <250>; 2492 2493 thermal-sensors = <&tsens 3>; 2494 2495 trips { 2496 cpu0_alert0: trip-point0 { 2497 temperature = <70000>; 2498 hysteresis = <1000>; 2499 type = "passive"; 2500 }; 2501 2502 cpu0_crit: cpu-crit { 2503 temperature = <110000>; 2504 hysteresis = <1000>; 2505 type = "critical"; 2506 }; 2507 }; 2508 }; 2509 2510 cpu1-thermal { 2511 polling-delay-passive = <250>; 2512 2513 thermal-sensors = <&tsens 4>; 2514 2515 trips { 2516 cpu1_alert0: trip-point0 { 2517 temperature = <70000>; 2518 hysteresis = <1000>; 2519 type = "passive"; 2520 }; 2521 2522 cpu1_crit: cpu-crit { 2523 temperature = <110000>; 2524 hysteresis = <1000>; 2525 type = "critical"; 2526 }; 2527 }; 2528 }; 2529 2530 cpu2-thermal { 2531 polling-delay-passive = <250>; 2532 2533 thermal-sensors = <&tsens 5>; 2534 2535 trips { 2536 cpu2_alert0: trip-point0 { 2537 temperature = <70000>; 2538 hysteresis = <1000>; 2539 type = "passive"; 2540 }; 2541 2542 cpu2_crit: cpu-crit { 2543 temperature = <110000>; 2544 hysteresis = <1000>; 2545 type = "critical"; 2546 }; 2547 }; 2548 }; 2549 2550 cpu3-thermal { 2551 polling-delay-passive = <250>; 2552 2553 thermal-sensors = <&tsens 6>; 2554 2555 trips { 2556 cpu3_alert0: trip-point0 { 2557 temperature = <70000>; 2558 hysteresis = <1000>; 2559 type = "passive"; 2560 }; 2561 2562 cpu3_crit: cpu-crit { 2563 temperature = <110000>; 2564 hysteresis = <1000>; 2565 type = "critical"; 2566 }; 2567 }; 2568 }; 2569 2570 /* 2571 * According to what downstream DTS says, 2572 * the entire power efficient cluster has 2573 * only a single thermal sensor. 2574 */ 2575 2576 pwr-cluster-thermal { 2577 polling-delay-passive = <250>; 2578 2579 thermal-sensors = <&tsens 7>; 2580 2581 trips { 2582 pwr_cluster_alert0: trip-point0 { 2583 temperature = <70000>; 2584 hysteresis = <1000>; 2585 type = "passive"; 2586 }; 2587 2588 pwr_cluster_crit: cpu-crit { 2589 temperature = <110000>; 2590 hysteresis = <1000>; 2591 type = "critical"; 2592 }; 2593 }; 2594 }; 2595 2596 gpu-thermal { 2597 polling-delay-passive = <250>; 2598 2599 thermal-sensors = <&tsens 8>; 2600 2601 cooling-maps { 2602 map0 { 2603 trip = <&gpu_alert0>; 2604 cooling-device = <&adreno_gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2605 }; 2606 }; 2607 2608 trips { 2609 gpu_alert0: trip-point0 { 2610 temperature = <85000>; 2611 hysteresis = <1000>; 2612 type = "passive"; 2613 }; 2614 2615 trip-point1 { 2616 temperature = <90000>; 2617 hysteresis = <1000>; 2618 type = "hot"; 2619 }; 2620 2621 trip-point2 { 2622 temperature = <110000>; 2623 hysteresis = <1000>; 2624 type = "critical"; 2625 }; 2626 }; 2627 }; 2628 }; 2629 2630 timer { 2631 compatible = "arm,armv8-timer"; 2632 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2633 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2634 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2635 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2636 }; 2637}; 2638 2639