1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 6#include <dt-bindings/clock/qcom,gcc-msm8998.h> 7#include <dt-bindings/clock/qcom,gpucc-msm8998.h> 8#include <dt-bindings/clock/qcom,mmcc-msm8998.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/firmware/qcom,scm.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/gpio/gpio.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 17 qcom,msm-id = <292 0x0>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 memory@80000000 { 25 device_type = "memory"; 26 /* We expect the bootloader to fill in the reg */ 27 reg = <0x0 0x80000000 0x0 0x0>; 28 }; 29 30 reserved-memory { 31 #address-cells = <2>; 32 #size-cells = <2>; 33 ranges; 34 35 hyp_mem: memory@85800000 { 36 reg = <0x0 0x85800000 0x0 0x600000>; 37 no-map; 38 }; 39 40 xbl_mem: memory@85e00000 { 41 reg = <0x0 0x85e00000 0x0 0x100000>; 42 no-map; 43 }; 44 45 smem_mem: smem-mem@86000000 { 46 reg = <0x0 0x86000000 0x0 0x200000>; 47 no-map; 48 }; 49 50 tz_mem: memory@86200000 { 51 reg = <0x0 0x86200000 0x0 0x2d00000>; 52 no-map; 53 }; 54 55 rmtfs_mem: memory@88f00000 { 56 compatible = "qcom,rmtfs-mem"; 57 reg = <0x0 0x88f00000 0x0 0x200000>; 58 no-map; 59 60 qcom,client-id = <1>; 61 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 62 }; 63 64 spss_mem: memory@8ab00000 { 65 reg = <0x0 0x8ab00000 0x0 0x700000>; 66 no-map; 67 }; 68 69 adsp_mem: memory@8b200000 { 70 reg = <0x0 0x8b200000 0x0 0x1a00000>; 71 no-map; 72 }; 73 74 mpss_mem: memory@8cc00000 { 75 reg = <0x0 0x8cc00000 0x0 0x7000000>; 76 no-map; 77 }; 78 79 venus_mem: memory@93c00000 { 80 reg = <0x0 0x93c00000 0x0 0x500000>; 81 no-map; 82 }; 83 84 mba_mem: memory@94100000 { 85 reg = <0x0 0x94100000 0x0 0x200000>; 86 no-map; 87 }; 88 89 slpi_mem: memory@94300000 { 90 reg = <0x0 0x94300000 0x0 0xf00000>; 91 no-map; 92 }; 93 94 ipa_fw_mem: memory@95200000 { 95 reg = <0x0 0x95200000 0x0 0x10000>; 96 no-map; 97 }; 98 99 ipa_gsi_mem: memory@95210000 { 100 reg = <0x0 0x95210000 0x0 0x5000>; 101 no-map; 102 }; 103 104 gpu_mem: memory@95600000 { 105 reg = <0x0 0x95600000 0x0 0x100000>; 106 no-map; 107 }; 108 109 wlan_msa_mem: memory@95700000 { 110 reg = <0x0 0x95700000 0x0 0x100000>; 111 no-map; 112 }; 113 114 mdata_mem: mpss-metadata { 115 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 116 size = <0x0 0x4000>; 117 no-map; 118 }; 119 }; 120 121 clocks { 122 xo: xo-board { 123 compatible = "fixed-clock"; 124 #clock-cells = <0>; 125 clock-frequency = <19200000>; 126 clock-output-names = "xo_board"; 127 }; 128 129 sleep_clk: sleep-clk { 130 compatible = "fixed-clock"; 131 #clock-cells = <0>; 132 clock-frequency = <32764>; 133 }; 134 }; 135 136 cpus { 137 #address-cells = <2>; 138 #size-cells = <0>; 139 140 cpu0: cpu@0 { 141 device_type = "cpu"; 142 compatible = "qcom,kryo280"; 143 reg = <0x0 0x0>; 144 enable-method = "psci"; 145 capacity-dmips-mhz = <1024>; 146 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 147 next-level-cache = <&l2_0>; 148 l2_0: l2-cache { 149 compatible = "cache"; 150 cache-level = <2>; 151 cache-unified; 152 }; 153 }; 154 155 cpu1: cpu@1 { 156 device_type = "cpu"; 157 compatible = "qcom,kryo280"; 158 reg = <0x0 0x1>; 159 enable-method = "psci"; 160 capacity-dmips-mhz = <1024>; 161 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 162 next-level-cache = <&l2_0>; 163 }; 164 165 cpu2: cpu@2 { 166 device_type = "cpu"; 167 compatible = "qcom,kryo280"; 168 reg = <0x0 0x2>; 169 enable-method = "psci"; 170 capacity-dmips-mhz = <1024>; 171 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 172 next-level-cache = <&l2_0>; 173 }; 174 175 cpu3: cpu@3 { 176 device_type = "cpu"; 177 compatible = "qcom,kryo280"; 178 reg = <0x0 0x3>; 179 enable-method = "psci"; 180 capacity-dmips-mhz = <1024>; 181 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 182 next-level-cache = <&l2_0>; 183 }; 184 185 cpu4: cpu@100 { 186 device_type = "cpu"; 187 compatible = "qcom,kryo280"; 188 reg = <0x0 0x100>; 189 enable-method = "psci"; 190 capacity-dmips-mhz = <1536>; 191 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 192 next-level-cache = <&l2_1>; 193 l2_1: l2-cache { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-unified; 197 }; 198 }; 199 200 cpu5: cpu@101 { 201 device_type = "cpu"; 202 compatible = "qcom,kryo280"; 203 reg = <0x0 0x101>; 204 enable-method = "psci"; 205 capacity-dmips-mhz = <1536>; 206 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 207 next-level-cache = <&l2_1>; 208 }; 209 210 cpu6: cpu@102 { 211 device_type = "cpu"; 212 compatible = "qcom,kryo280"; 213 reg = <0x0 0x102>; 214 enable-method = "psci"; 215 capacity-dmips-mhz = <1536>; 216 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 217 next-level-cache = <&l2_1>; 218 }; 219 220 cpu7: cpu@103 { 221 device_type = "cpu"; 222 compatible = "qcom,kryo280"; 223 reg = <0x0 0x103>; 224 enable-method = "psci"; 225 capacity-dmips-mhz = <1536>; 226 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 227 next-level-cache = <&l2_1>; 228 }; 229 230 cpu-map { 231 cluster0 { 232 core0 { 233 cpu = <&cpu0>; 234 }; 235 236 core1 { 237 cpu = <&cpu1>; 238 }; 239 240 core2 { 241 cpu = <&cpu2>; 242 }; 243 244 core3 { 245 cpu = <&cpu3>; 246 }; 247 }; 248 249 cluster1 { 250 core0 { 251 cpu = <&cpu4>; 252 }; 253 254 core1 { 255 cpu = <&cpu5>; 256 }; 257 258 core2 { 259 cpu = <&cpu6>; 260 }; 261 262 core3 { 263 cpu = <&cpu7>; 264 }; 265 }; 266 }; 267 268 idle-states { 269 entry-method = "psci"; 270 271 little_cpu_sleep_0: cpu-sleep-0-0 { 272 compatible = "arm,idle-state"; 273 idle-state-name = "little-retention"; 274 /* CPU Retention (C2D), L2 Active */ 275 arm,psci-suspend-param = <0x00000002>; 276 entry-latency-us = <81>; 277 exit-latency-us = <86>; 278 min-residency-us = <504>; 279 }; 280 281 little_cpu_sleep_1: cpu-sleep-0-1 { 282 compatible = "arm,idle-state"; 283 idle-state-name = "little-power-collapse"; 284 /* CPU + L2 Power Collapse (C3, D4) */ 285 arm,psci-suspend-param = <0x40000003>; 286 entry-latency-us = <814>; 287 exit-latency-us = <4562>; 288 min-residency-us = <9183>; 289 local-timer-stop; 290 }; 291 292 big_cpu_sleep_0: cpu-sleep-1-0 { 293 compatible = "arm,idle-state"; 294 idle-state-name = "big-retention"; 295 /* CPU Retention (C2D), L2 Active */ 296 arm,psci-suspend-param = <0x00000002>; 297 entry-latency-us = <79>; 298 exit-latency-us = <82>; 299 min-residency-us = <1302>; 300 }; 301 302 big_cpu_sleep_1: cpu-sleep-1-1 { 303 compatible = "arm,idle-state"; 304 idle-state-name = "big-power-collapse"; 305 /* CPU + L2 Power Collapse (C3, D4) */ 306 arm,psci-suspend-param = <0x40000003>; 307 entry-latency-us = <724>; 308 exit-latency-us = <2027>; 309 min-residency-us = <9419>; 310 local-timer-stop; 311 }; 312 }; 313 }; 314 315 firmware { 316 scm { 317 compatible = "qcom,scm-msm8998", "qcom,scm"; 318 }; 319 }; 320 321 dsi_opp_table: opp-table-dsi { 322 compatible = "operating-points-v2"; 323 324 opp-131250000 { 325 opp-hz = /bits/ 64 <131250000>; 326 required-opps = <&rpmpd_opp_low_svs>; 327 }; 328 329 opp-210000000 { 330 opp-hz = /bits/ 64 <210000000>; 331 required-opps = <&rpmpd_opp_svs>; 332 }; 333 334 opp-312500000 { 335 opp-hz = /bits/ 64 <312500000>; 336 required-opps = <&rpmpd_opp_nom>; 337 }; 338 }; 339 340 psci { 341 compatible = "arm,psci-1.0"; 342 method = "smc"; 343 }; 344 345 rpm: remoteproc { 346 compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc"; 347 348 glink-edge { 349 compatible = "qcom,glink-rpm"; 350 351 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 352 qcom,rpm-msg-ram = <&rpm_msg_ram>; 353 mboxes = <&apcs_glb 0>; 354 355 rpm_requests: rpm-requests { 356 compatible = "qcom,rpm-msm8998", "qcom,glink-smd-rpm"; 357 qcom,glink-channels = "rpm_requests"; 358 359 rpmcc: clock-controller { 360 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; 361 clocks = <&xo>; 362 clock-names = "xo"; 363 #clock-cells = <1>; 364 }; 365 366 rpmpd: power-controller { 367 compatible = "qcom,msm8998-rpmpd"; 368 #power-domain-cells = <1>; 369 operating-points-v2 = <&rpmpd_opp_table>; 370 371 rpmpd_opp_table: opp-table { 372 compatible = "operating-points-v2"; 373 374 rpmpd_opp_ret: opp1 { 375 opp-level = <RPM_SMD_LEVEL_RETENTION>; 376 }; 377 378 rpmpd_opp_ret_plus: opp2 { 379 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 380 }; 381 382 rpmpd_opp_min_svs: opp3 { 383 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 384 }; 385 386 rpmpd_opp_low_svs: opp4 { 387 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 388 }; 389 390 rpmpd_opp_svs: opp5 { 391 opp-level = <RPM_SMD_LEVEL_SVS>; 392 }; 393 394 rpmpd_opp_svs_plus: opp6 { 395 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 396 }; 397 398 rpmpd_opp_nom: opp7 { 399 opp-level = <RPM_SMD_LEVEL_NOM>; 400 }; 401 402 rpmpd_opp_nom_plus: opp8 { 403 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 404 }; 405 406 rpmpd_opp_turbo: opp9 { 407 opp-level = <RPM_SMD_LEVEL_TURBO>; 408 }; 409 410 rpmpd_opp_turbo_plus: opp10 { 411 opp-level = <RPM_SMD_LEVEL_BINNING>; 412 }; 413 }; 414 }; 415 }; 416 }; 417 }; 418 419 smem { 420 compatible = "qcom,smem"; 421 memory-region = <&smem_mem>; 422 hwlocks = <&tcsr_mutex 3>; 423 }; 424 425 smp2p-lpass { 426 compatible = "qcom,smp2p"; 427 qcom,smem = <443>, <429>; 428 429 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 430 431 mboxes = <&apcs_glb 10>; 432 433 qcom,local-pid = <0>; 434 qcom,remote-pid = <2>; 435 436 adsp_smp2p_out: master-kernel { 437 qcom,entry-name = "master-kernel"; 438 #qcom,smem-state-cells = <1>; 439 }; 440 441 adsp_smp2p_in: slave-kernel { 442 qcom,entry-name = "slave-kernel"; 443 444 interrupt-controller; 445 #interrupt-cells = <2>; 446 }; 447 }; 448 449 smp2p-mpss { 450 compatible = "qcom,smp2p"; 451 qcom,smem = <435>, <428>; 452 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 453 mboxes = <&apcs_glb 14>; 454 qcom,local-pid = <0>; 455 qcom,remote-pid = <1>; 456 457 modem_smp2p_out: master-kernel { 458 qcom,entry-name = "master-kernel"; 459 #qcom,smem-state-cells = <1>; 460 }; 461 462 modem_smp2p_in: slave-kernel { 463 qcom,entry-name = "slave-kernel"; 464 interrupt-controller; 465 #interrupt-cells = <2>; 466 }; 467 }; 468 469 smp2p-slpi { 470 compatible = "qcom,smp2p"; 471 qcom,smem = <481>, <430>; 472 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 473 mboxes = <&apcs_glb 26>; 474 qcom,local-pid = <0>; 475 qcom,remote-pid = <3>; 476 477 slpi_smp2p_out: master-kernel { 478 qcom,entry-name = "master-kernel"; 479 #qcom,smem-state-cells = <1>; 480 }; 481 482 slpi_smp2p_in: slave-kernel { 483 qcom,entry-name = "slave-kernel"; 484 interrupt-controller; 485 #interrupt-cells = <2>; 486 }; 487 }; 488 489 thermal-zones { 490 cpu0-thermal { 491 polling-delay-passive = <250>; 492 493 thermal-sensors = <&tsens0 1>; 494 495 trips { 496 cpu0_alert0: trip-point0 { 497 temperature = <75000>; 498 hysteresis = <2000>; 499 type = "passive"; 500 }; 501 502 cpu0_crit: cpu-crit { 503 temperature = <110000>; 504 hysteresis = <2000>; 505 type = "critical"; 506 }; 507 }; 508 }; 509 510 cpu1-thermal { 511 polling-delay-passive = <250>; 512 513 thermal-sensors = <&tsens0 2>; 514 515 trips { 516 cpu1_alert0: trip-point0 { 517 temperature = <75000>; 518 hysteresis = <2000>; 519 type = "passive"; 520 }; 521 522 cpu1_crit: cpu-crit { 523 temperature = <110000>; 524 hysteresis = <2000>; 525 type = "critical"; 526 }; 527 }; 528 }; 529 530 cpu2-thermal { 531 polling-delay-passive = <250>; 532 533 thermal-sensors = <&tsens0 3>; 534 535 trips { 536 cpu2_alert0: trip-point0 { 537 temperature = <75000>; 538 hysteresis = <2000>; 539 type = "passive"; 540 }; 541 542 cpu2_crit: cpu-crit { 543 temperature = <110000>; 544 hysteresis = <2000>; 545 type = "critical"; 546 }; 547 }; 548 }; 549 550 cpu3-thermal { 551 polling-delay-passive = <250>; 552 553 thermal-sensors = <&tsens0 4>; 554 555 trips { 556 cpu3_alert0: trip-point0 { 557 temperature = <75000>; 558 hysteresis = <2000>; 559 type = "passive"; 560 }; 561 562 cpu3_crit: cpu-crit { 563 temperature = <110000>; 564 hysteresis = <2000>; 565 type = "critical"; 566 }; 567 }; 568 }; 569 570 cpu4-thermal { 571 polling-delay-passive = <250>; 572 573 thermal-sensors = <&tsens0 7>; 574 575 trips { 576 cpu4_alert0: trip-point0 { 577 temperature = <75000>; 578 hysteresis = <2000>; 579 type = "passive"; 580 }; 581 582 cpu4_crit: cpu-crit { 583 temperature = <110000>; 584 hysteresis = <2000>; 585 type = "critical"; 586 }; 587 }; 588 }; 589 590 cpu5-thermal { 591 polling-delay-passive = <250>; 592 593 thermal-sensors = <&tsens0 8>; 594 595 trips { 596 cpu5_alert0: trip-point0 { 597 temperature = <75000>; 598 hysteresis = <2000>; 599 type = "passive"; 600 }; 601 602 cpu5_crit: cpu-crit { 603 temperature = <110000>; 604 hysteresis = <2000>; 605 type = "critical"; 606 }; 607 }; 608 }; 609 610 cpu6-thermal { 611 polling-delay-passive = <250>; 612 613 thermal-sensors = <&tsens0 9>; 614 615 trips { 616 cpu6_alert0: trip-point0 { 617 temperature = <75000>; 618 hysteresis = <2000>; 619 type = "passive"; 620 }; 621 622 cpu6_crit: cpu-crit { 623 temperature = <110000>; 624 hysteresis = <2000>; 625 type = "critical"; 626 }; 627 }; 628 }; 629 630 cpu7-thermal { 631 polling-delay-passive = <250>; 632 633 thermal-sensors = <&tsens0 10>; 634 635 trips { 636 cpu7_alert0: trip-point0 { 637 temperature = <75000>; 638 hysteresis = <2000>; 639 type = "passive"; 640 }; 641 642 cpu7_crit: cpu-crit { 643 temperature = <110000>; 644 hysteresis = <2000>; 645 type = "critical"; 646 }; 647 }; 648 }; 649 650 gpu-bottom-thermal { 651 polling-delay-passive = <250>; 652 653 thermal-sensors = <&tsens0 12>; 654 655 trips { 656 gpu1_alert0: trip-point0 { 657 temperature = <90000>; 658 hysteresis = <2000>; 659 type = "hot"; 660 }; 661 }; 662 }; 663 664 gpu-top-thermal { 665 polling-delay-passive = <250>; 666 667 thermal-sensors = <&tsens0 13>; 668 669 trips { 670 gpu2_alert0: trip-point0 { 671 temperature = <90000>; 672 hysteresis = <2000>; 673 type = "hot"; 674 }; 675 }; 676 }; 677 678 clust0-mhm-thermal { 679 polling-delay-passive = <250>; 680 681 thermal-sensors = <&tsens0 5>; 682 683 trips { 684 cluster0_mhm_alert0: trip-point0 { 685 temperature = <90000>; 686 hysteresis = <2000>; 687 type = "hot"; 688 }; 689 }; 690 }; 691 692 clust1-mhm-thermal { 693 polling-delay-passive = <250>; 694 695 thermal-sensors = <&tsens0 6>; 696 697 trips { 698 cluster1_mhm_alert0: trip-point0 { 699 temperature = <90000>; 700 hysteresis = <2000>; 701 type = "hot"; 702 }; 703 }; 704 }; 705 706 cluster1-l2-thermal { 707 polling-delay-passive = <250>; 708 709 thermal-sensors = <&tsens0 11>; 710 711 trips { 712 cluster1_l2_alert0: trip-point0 { 713 temperature = <90000>; 714 hysteresis = <2000>; 715 type = "hot"; 716 }; 717 }; 718 }; 719 720 modem-thermal { 721 polling-delay-passive = <250>; 722 723 thermal-sensors = <&tsens1 1>; 724 725 trips { 726 modem_alert0: trip-point0 { 727 temperature = <90000>; 728 hysteresis = <2000>; 729 type = "hot"; 730 }; 731 }; 732 }; 733 734 mem-thermal { 735 polling-delay-passive = <250>; 736 737 thermal-sensors = <&tsens1 2>; 738 739 trips { 740 mem_alert0: trip-point0 { 741 temperature = <90000>; 742 hysteresis = <2000>; 743 type = "hot"; 744 }; 745 }; 746 }; 747 748 wlan-thermal { 749 polling-delay-passive = <250>; 750 751 thermal-sensors = <&tsens1 3>; 752 753 trips { 754 wlan_alert0: trip-point0 { 755 temperature = <90000>; 756 hysteresis = <2000>; 757 type = "hot"; 758 }; 759 }; 760 }; 761 762 q6-dsp-thermal { 763 polling-delay-passive = <250>; 764 765 thermal-sensors = <&tsens1 4>; 766 767 trips { 768 q6_dsp_alert0: trip-point0 { 769 temperature = <90000>; 770 hysteresis = <2000>; 771 type = "hot"; 772 }; 773 }; 774 }; 775 776 camera-thermal { 777 polling-delay-passive = <250>; 778 779 thermal-sensors = <&tsens1 5>; 780 781 trips { 782 camera_alert0: trip-point0 { 783 temperature = <90000>; 784 hysteresis = <2000>; 785 type = "hot"; 786 }; 787 }; 788 }; 789 790 multimedia-thermal { 791 polling-delay-passive = <250>; 792 793 thermal-sensors = <&tsens1 6>; 794 795 trips { 796 multimedia_alert0: trip-point0 { 797 temperature = <90000>; 798 hysteresis = <2000>; 799 type = "hot"; 800 }; 801 }; 802 }; 803 }; 804 805 timer { 806 compatible = "arm,armv8-timer"; 807 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 808 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 809 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 810 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 811 }; 812 813 soc: soc@0 { 814 #address-cells = <1>; 815 #size-cells = <1>; 816 ranges = <0 0 0 0xffffffff>; 817 compatible = "simple-bus"; 818 819 gcc: clock-controller@100000 { 820 compatible = "qcom,gcc-msm8998"; 821 #clock-cells = <1>; 822 #reset-cells = <1>; 823 #power-domain-cells = <1>; 824 reg = <0x00100000 0xb0000>; 825 826 clock-names = "xo", "sleep_clk"; 827 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 828 829 /* 830 * The hypervisor typically configures the memory region where these clocks 831 * reside as read-only for the HLOS. If the HLOS tried to enable or disable 832 * these clocks on a device with such configuration (e.g. because they are 833 * enabled but unused during boot-up), the device will most likely decide 834 * to reboot. 835 * In light of that, we are conservative here and we list all such clocks 836 * as protected. The board dts (or a user-supplied dts) can override the 837 * list of protected clocks if it differs from the norm, and it is in fact 838 * desired for the HLOS to manage these clocks 839 */ 840 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>, 841 <SSC_XO>, 842 <SSC_CNOC_AHBS_CLK>; 843 }; 844 845 rpm_msg_ram: sram@778000 { 846 compatible = "qcom,rpm-msg-ram"; 847 reg = <0x00778000 0x7000>; 848 }; 849 850 qfprom: qfprom@784000 { 851 compatible = "qcom,msm8998-qfprom", "qcom,qfprom"; 852 reg = <0x00784000 0x621c>; 853 #address-cells = <1>; 854 #size-cells = <1>; 855 856 qusb2_hstx_trim: hstx-trim@23a { 857 reg = <0x23a 0x1>; 858 bits = <0 4>; 859 }; 860 }; 861 862 tsens0: thermal@10ab000 { 863 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 864 reg = <0x010ab000 0x1000>, /* TM */ 865 <0x010aa000 0x1000>; /* SROT */ 866 #qcom,sensors = <14>; 867 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 869 interrupt-names = "uplow", "critical"; 870 #thermal-sensor-cells = <1>; 871 }; 872 873 tsens1: thermal@10ae000 { 874 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 875 reg = <0x010ae000 0x1000>, /* TM */ 876 <0x010ad000 0x1000>; /* SROT */ 877 #qcom,sensors = <8>; 878 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 880 interrupt-names = "uplow", "critical"; 881 #thermal-sensor-cells = <1>; 882 }; 883 884 anoc1_smmu: iommu@1680000 { 885 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 886 reg = <0x01680000 0x10000>; 887 #iommu-cells = <1>; 888 889 #global-interrupts = <0>; 890 interrupts = 891 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 892 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 893 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 894 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 895 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 896 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>; 897 }; 898 899 anoc2_smmu: iommu@16c0000 { 900 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 901 reg = <0x016c0000 0x40000>; 902 #iommu-cells = <1>; 903 904 #global-interrupts = <0>; 905 interrupts = 906 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 907 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, 908 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, 909 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, 910 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, 911 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, 912 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>, 913 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>, 914 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 915 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>; 916 }; 917 918 pcie0: pcie@1c00000 { 919 compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996"; 920 reg = <0x01c00000 0x2000>, 921 <0x1b000000 0xf1d>, 922 <0x1b000f20 0xa8>, 923 <0x1b100000 0x100000>; 924 reg-names = "parf", "dbi", "elbi", "config"; 925 device_type = "pci"; 926 linux,pci-domain = <0>; 927 bus-range = <0x00 0xff>; 928 #address-cells = <3>; 929 #size-cells = <2>; 930 num-lanes = <1>; 931 phys = <&pcie_phy>; 932 phy-names = "pciephy"; 933 status = "disabled"; 934 935 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>, 936 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; 937 938 #interrupt-cells = <1>; 939 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 940 interrupt-names = "msi"; 941 interrupt-map-mask = <0 0 0 0x7>; 942 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, 943 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>, 944 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>, 945 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>; 946 947 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 948 <&gcc GCC_PCIE_0_AUX_CLK>, 949 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 950 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 951 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 952 clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave"; 953 954 power-domains = <&gcc PCIE_0_GDSC>; 955 iommu-map = <0x100 &anoc1_smmu 0x1480 1>; 956 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; 957 958 pcie@0 { 959 device_type = "pci"; 960 reg = <0x0 0x0 0x0 0x0 0x0>; 961 bus-range = <0x01 0xff>; 962 963 #address-cells = <3>; 964 #size-cells = <2>; 965 ranges; 966 }; 967 }; 968 969 pcie_phy: phy@1c06000 { 970 compatible = "qcom,msm8998-qmp-pcie-phy"; 971 reg = <0x01c06000 0x1000>; 972 status = "disabled"; 973 974 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 975 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 976 <&gcc GCC_PCIE_CLKREF_CLK>, 977 <&gcc GCC_PCIE_0_PIPE_CLK>; 978 clock-names = "aux", 979 "cfg_ahb", 980 "ref", 981 "pipe"; 982 983 clock-output-names = "pcie_0_pipe_clk_src"; 984 #clock-cells = <0>; 985 986 #phy-cells = <0>; 987 988 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; 989 reset-names = "phy", "common"; 990 991 vdda-phy-supply = <&vreg_l1a_0p875>; 992 vdda-pll-supply = <&vreg_l2a_1p2>; 993 }; 994 995 ufshc: ufshc@1da4000 { 996 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 997 reg = <0x01da4000 0x2500>; 998 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 999 phys = <&ufsphy>; 1000 phy-names = "ufsphy"; 1001 lanes-per-direction = <2>; 1002 power-domains = <&gcc UFS_GDSC>; 1003 status = "disabled"; 1004 #reset-cells = <1>; 1005 1006 clock-names = 1007 "core_clk", 1008 "bus_aggr_clk", 1009 "iface_clk", 1010 "core_clk_unipro", 1011 "ref_clk", 1012 "tx_lane0_sync_clk", 1013 "rx_lane0_sync_clk", 1014 "rx_lane1_sync_clk"; 1015 clocks = 1016 <&gcc GCC_UFS_AXI_CLK>, 1017 <&gcc GCC_AGGRE1_UFS_AXI_CLK>, 1018 <&gcc GCC_UFS_AHB_CLK>, 1019 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1020 <&rpmcc RPM_SMD_LN_BB_CLK1>, 1021 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1022 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, 1023 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; 1024 freq-table-hz = 1025 <50000000 200000000>, 1026 <0 0>, 1027 <0 0>, 1028 <37500000 150000000>, 1029 <0 0>, 1030 <0 0>, 1031 <0 0>, 1032 <0 0>; 1033 1034 resets = <&gcc GCC_UFS_BCR>; 1035 reset-names = "rst"; 1036 }; 1037 1038 ufsphy: phy@1da7000 { 1039 compatible = "qcom,msm8998-qmp-ufs-phy"; 1040 reg = <0x01da7000 0x1000>; 1041 1042 clocks = <&rpmcc RPM_SMD_LN_BB_CLK1>, 1043 <&gcc GCC_UFS_PHY_AUX_CLK>, 1044 <&gcc GCC_UFS_CLKREF_CLK>; 1045 clock-names = "ref", 1046 "ref_aux", 1047 "qref"; 1048 1049 reset-names = "ufsphy"; 1050 resets = <&ufshc 0>; 1051 1052 #phy-cells = <0>; 1053 status = "disabled"; 1054 }; 1055 1056 tcsr_mutex: hwlock@1f40000 { 1057 compatible = "qcom,tcsr-mutex"; 1058 reg = <0x01f40000 0x20000>; 1059 #hwlock-cells = <1>; 1060 }; 1061 1062 tcsr_regs_1: syscon@1f60000 { 1063 compatible = "qcom,msm8998-tcsr", "syscon"; 1064 reg = <0x01f60000 0x20000>; 1065 }; 1066 1067 tcsr_regs_2: syscon@1fc0000 { 1068 compatible = "qcom,msm8998-tcsr", "syscon"; 1069 reg = <0x01fc0000 0x26000>; 1070 }; 1071 1072 tlmm: pinctrl@3400000 { 1073 compatible = "qcom,msm8998-pinctrl"; 1074 reg = <0x03400000 0xc00000>; 1075 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1076 gpio-ranges = <&tlmm 0 0 150>; 1077 gpio-controller; 1078 #gpio-cells = <2>; 1079 interrupt-controller; 1080 #interrupt-cells = <2>; 1081 1082 sdc2_on: sdc2-on-state { 1083 clk-pins { 1084 pins = "sdc2_clk"; 1085 drive-strength = <16>; 1086 bias-disable; 1087 }; 1088 1089 cmd-pins { 1090 pins = "sdc2_cmd"; 1091 drive-strength = <10>; 1092 bias-pull-up; 1093 }; 1094 1095 data-pins { 1096 pins = "sdc2_data"; 1097 drive-strength = <10>; 1098 bias-pull-up; 1099 }; 1100 }; 1101 1102 sdc2_off: sdc2-off-state { 1103 clk-pins { 1104 pins = "sdc2_clk"; 1105 drive-strength = <2>; 1106 bias-disable; 1107 }; 1108 1109 cmd-pins { 1110 pins = "sdc2_cmd"; 1111 drive-strength = <2>; 1112 bias-pull-up; 1113 }; 1114 1115 data-pins { 1116 pins = "sdc2_data"; 1117 drive-strength = <2>; 1118 bias-pull-up; 1119 }; 1120 }; 1121 1122 sdc2_cd: sdc2-cd-state { 1123 pins = "gpio95"; 1124 function = "gpio"; 1125 bias-pull-up; 1126 drive-strength = <2>; 1127 }; 1128 1129 blsp1_uart3_on: blsp1-uart3-on-state { 1130 tx-pins { 1131 pins = "gpio45"; 1132 function = "blsp_uart3_a"; 1133 drive-strength = <2>; 1134 bias-disable; 1135 }; 1136 1137 rx-pins { 1138 pins = "gpio46"; 1139 function = "blsp_uart3_a"; 1140 drive-strength = <2>; 1141 bias-disable; 1142 }; 1143 1144 cts-pins { 1145 pins = "gpio47"; 1146 function = "blsp_uart3_a"; 1147 drive-strength = <2>; 1148 bias-disable; 1149 }; 1150 1151 rfr-pins { 1152 pins = "gpio48"; 1153 function = "blsp_uart3_a"; 1154 drive-strength = <2>; 1155 bias-disable; 1156 }; 1157 }; 1158 1159 blsp1_i2c1_default: blsp1-i2c1-default-state { 1160 pins = "gpio2", "gpio3"; 1161 function = "blsp_i2c1"; 1162 drive-strength = <2>; 1163 bias-disable; 1164 }; 1165 1166 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state { 1167 pins = "gpio2", "gpio3"; 1168 function = "blsp_i2c1"; 1169 drive-strength = <2>; 1170 bias-pull-up; 1171 }; 1172 1173 blsp1_i2c2_default: blsp1-i2c2-default-state { 1174 pins = "gpio32", "gpio33"; 1175 function = "blsp_i2c2"; 1176 drive-strength = <2>; 1177 bias-disable; 1178 }; 1179 1180 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state { 1181 pins = "gpio32", "gpio33"; 1182 function = "blsp_i2c2"; 1183 drive-strength = <2>; 1184 bias-pull-up; 1185 }; 1186 1187 blsp1_i2c3_default: blsp1-i2c3-default-state { 1188 pins = "gpio47", "gpio48"; 1189 function = "blsp_i2c3"; 1190 drive-strength = <2>; 1191 bias-disable; 1192 }; 1193 1194 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1195 pins = "gpio47", "gpio48"; 1196 function = "blsp_i2c3"; 1197 drive-strength = <2>; 1198 bias-pull-up; 1199 }; 1200 1201 blsp1_i2c4_default: blsp1-i2c4-default-state { 1202 pins = "gpio10", "gpio11"; 1203 function = "blsp_i2c4"; 1204 drive-strength = <2>; 1205 bias-disable; 1206 }; 1207 1208 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { 1209 pins = "gpio10", "gpio11"; 1210 function = "blsp_i2c4"; 1211 drive-strength = <2>; 1212 bias-pull-up; 1213 }; 1214 1215 blsp1_i2c5_default: blsp1-i2c5-default-state { 1216 pins = "gpio87", "gpio88"; 1217 function = "blsp_i2c5"; 1218 drive-strength = <2>; 1219 bias-disable; 1220 }; 1221 1222 blsp1_i2c5_sleep: blsp1-i2c5-sleep-state { 1223 pins = "gpio87", "gpio88"; 1224 function = "blsp_i2c5"; 1225 drive-strength = <2>; 1226 bias-pull-up; 1227 }; 1228 1229 blsp1_i2c6_default: blsp1-i2c6-default-state { 1230 pins = "gpio43", "gpio44"; 1231 function = "blsp_i2c6"; 1232 drive-strength = <2>; 1233 bias-disable; 1234 }; 1235 1236 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1237 pins = "gpio43", "gpio44"; 1238 function = "blsp_i2c6"; 1239 drive-strength = <2>; 1240 bias-pull-up; 1241 }; 1242 1243 blsp1_spi_b_default: blsp1-spi-b-default-state { 1244 pins = "gpio23", "gpio28"; 1245 function = "blsp1_spi_b"; 1246 drive-strength = <6>; 1247 bias-disable; 1248 }; 1249 1250 blsp1_spi1_default: blsp1-spi1-default-state { 1251 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1252 function = "blsp_spi1"; 1253 drive-strength = <6>; 1254 bias-disable; 1255 }; 1256 1257 blsp1_spi2_default: blsp1-spi2-default-state { 1258 pins = "gpio31", "gpio34", "gpio32", "gpio33"; 1259 function = "blsp_spi2"; 1260 drive-strength = <6>; 1261 bias-disable; 1262 }; 1263 1264 blsp1_spi3_default: blsp1-spi3-default-state { 1265 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 1266 function = "blsp_spi2"; 1267 drive-strength = <6>; 1268 bias-disable; 1269 }; 1270 1271 blsp1_spi4_default: blsp1-spi4-default-state { 1272 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 1273 function = "blsp_spi4"; 1274 drive-strength = <6>; 1275 bias-disable; 1276 }; 1277 1278 blsp1_spi5_default: blsp1-spi5-default-state { 1279 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1280 function = "blsp_spi5"; 1281 drive-strength = <6>; 1282 bias-disable; 1283 }; 1284 1285 blsp1_spi6_default: blsp1-spi6-default-state { 1286 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1287 function = "blsp_spi6"; 1288 drive-strength = <6>; 1289 bias-disable; 1290 }; 1291 1292 1293 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1294 blsp2_i2c1_default: blsp2-i2c1-default-state { 1295 pins = "gpio55", "gpio56"; 1296 function = "blsp_i2c7"; 1297 drive-strength = <2>; 1298 bias-disable; 1299 }; 1300 1301 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1302 pins = "gpio55", "gpio56"; 1303 function = "blsp_i2c7"; 1304 drive-strength = <2>; 1305 bias-pull-up; 1306 }; 1307 1308 blsp2_i2c2_default: blsp2-i2c2-default-state { 1309 pins = "gpio6", "gpio7"; 1310 function = "blsp_i2c8"; 1311 drive-strength = <2>; 1312 bias-disable; 1313 }; 1314 1315 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1316 pins = "gpio6", "gpio7"; 1317 function = "blsp_i2c8"; 1318 drive-strength = <2>; 1319 bias-pull-up; 1320 }; 1321 1322 blsp2_i2c3_default: blsp2-i2c3-default-state { 1323 pins = "gpio51", "gpio52"; 1324 function = "blsp_i2c9"; 1325 drive-strength = <2>; 1326 bias-disable; 1327 }; 1328 1329 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1330 pins = "gpio51", "gpio52"; 1331 function = "blsp_i2c9"; 1332 drive-strength = <2>; 1333 bias-pull-up; 1334 }; 1335 1336 blsp2_i2c4_default: blsp2-i2c4-default-state { 1337 pins = "gpio67", "gpio68"; 1338 function = "blsp_i2c10"; 1339 drive-strength = <2>; 1340 bias-disable; 1341 }; 1342 1343 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { 1344 pins = "gpio67", "gpio68"; 1345 function = "blsp_i2c10"; 1346 drive-strength = <2>; 1347 bias-pull-up; 1348 }; 1349 1350 blsp2_i2c5_default: blsp2-i2c5-default-state { 1351 pins = "gpio60", "gpio61"; 1352 function = "blsp_i2c11"; 1353 drive-strength = <2>; 1354 bias-disable; 1355 }; 1356 1357 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { 1358 pins = "gpio60", "gpio61"; 1359 function = "blsp_i2c11"; 1360 drive-strength = <2>; 1361 bias-pull-up; 1362 }; 1363 1364 blsp2_i2c6_default: blsp2-i2c6-default-state { 1365 pins = "gpio83", "gpio84"; 1366 function = "blsp_i2c12"; 1367 drive-strength = <2>; 1368 bias-disable; 1369 }; 1370 1371 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1372 pins = "gpio83", "gpio84"; 1373 function = "blsp_i2c12"; 1374 drive-strength = <2>; 1375 bias-pull-up; 1376 }; 1377 1378 blsp2_spi1_default: blsp2-spi1-default-state { 1379 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1380 function = "blsp_spi7"; 1381 drive-strength = <6>; 1382 bias-disable; 1383 }; 1384 1385 blsp2_spi2_default: blsp2-spi2-default-state { 1386 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 1387 function = "blsp_spi8"; 1388 drive-strength = <6>; 1389 bias-disable; 1390 }; 1391 1392 blsp2_spi3_default: blsp2-spi3-default-state { 1393 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1394 function = "blsp_spi9"; 1395 drive-strength = <6>; 1396 bias-disable; 1397 }; 1398 1399 blsp2_spi4_default: blsp2-spi4-default-state { 1400 pins = "gpio65", "gpio66", "gpio67", "gpio68"; 1401 function = "blsp_spi10"; 1402 drive-strength = <6>; 1403 bias-disable; 1404 }; 1405 1406 blsp2_spi5_default: blsp2-spi5-default-state { 1407 pins = "gpio58", "gpio59", "gpio60", "gpio61"; 1408 function = "blsp_spi11"; 1409 drive-strength = <6>; 1410 bias-disable; 1411 }; 1412 1413 blsp2_spi6_default: blsp2-spi6-default-state { 1414 pins = "gpio81", "gpio82", "gpio83", "gpio84"; 1415 function = "blsp_spi12"; 1416 drive-strength = <6>; 1417 bias-disable; 1418 }; 1419 1420 hdmi_cec_default: hdmi-cec-default-state { 1421 pins = "gpio31"; 1422 function = "hdmi_cec"; 1423 drive-strength = <2>; 1424 bias-pull-up; 1425 }; 1426 1427 hdmi_ddc_default: hdmi-ddc-default-state { 1428 pins = "gpio32", "gpio33"; 1429 function = "hdmi_ddc"; 1430 drive-strength = <2>; 1431 bias-pull-up; 1432 }; 1433 1434 hdmi_hpd_default: hdmi-hpd-default-state { 1435 pins = "gpio34"; 1436 function = "hdmi_hot"; 1437 drive-strength = <16>; 1438 bias-pull-down; 1439 }; 1440 1441 hdmi_hpd_sleep: hdmi-hpd-sleep-state { 1442 pins = "gpio34"; 1443 function = "hdmi_hot"; 1444 drive-strength = <2>; 1445 bias-pull-down; 1446 }; 1447 }; 1448 1449 remoteproc_mss: remoteproc@4080000 { 1450 compatible = "qcom,msm8998-mss-pil"; 1451 reg = <0x04080000 0x100>, <0x04180000 0x20>; 1452 reg-names = "qdsp6", "rmb"; 1453 1454 interrupts-extended = 1455 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 1456 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1457 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1458 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1459 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1460 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1461 interrupt-names = "wdog", "fatal", "ready", 1462 "handover", "stop-ack", 1463 "shutdown-ack"; 1464 1465 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1466 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, 1467 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1468 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 1469 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1470 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 1471 <&rpmcc RPM_SMD_QDSS_CLK>, 1472 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1473 clock-names = "iface", "bus", "mem", "gpll0_mss", 1474 "snoc_axi", "mnoc_axi", "qdss", "xo"; 1475 1476 qcom,smem-states = <&modem_smp2p_out 0>; 1477 qcom,smem-state-names = "stop"; 1478 1479 resets = <&gcc GCC_MSS_RESTART>; 1480 reset-names = "mss_restart"; 1481 1482 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 1483 1484 power-domains = <&rpmpd MSM8998_VDDCX>, 1485 <&rpmpd MSM8998_VDDMX>; 1486 power-domain-names = "cx", "mx"; 1487 1488 status = "disabled"; 1489 1490 mba { 1491 memory-region = <&mba_mem>; 1492 }; 1493 1494 mpss { 1495 memory-region = <&mpss_mem>; 1496 }; 1497 1498 metadata { 1499 memory-region = <&mdata_mem>; 1500 }; 1501 1502 glink-edge { 1503 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; 1504 label = "modem"; 1505 qcom,remote-pid = <1>; 1506 mboxes = <&apcs_glb 15>; 1507 }; 1508 }; 1509 1510 adreno_gpu: gpu@5000000 { 1511 compatible = "qcom,adreno-540.1", "qcom,adreno"; 1512 reg = <0x05000000 0x40000>; 1513 reg-names = "kgsl_3d0_reg_memory"; 1514 1515 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1516 <&gpucc RBBMTIMER_CLK>, 1517 <&gcc GCC_BIMC_GFX_CLK>, 1518 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1519 <&gpucc RBCPR_CLK>, 1520 <&gpucc GFX3D_CLK>; 1521 clock-names = "iface", 1522 "rbbmtimer", 1523 "mem", 1524 "mem_iface", 1525 "rbcpr", 1526 "core"; 1527 1528 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1529 iommus = <&adreno_smmu 0>; 1530 operating-points-v2 = <&gpu_opp_table>; 1531 power-domains = <&rpmpd MSM8998_VDDMX>; 1532 status = "disabled"; 1533 1534 gpu_opp_table: opp-table { 1535 compatible = "operating-points-v2"; 1536 opp-710000097 { 1537 opp-hz = /bits/ 64 <710000097>; 1538 opp-level = <RPM_SMD_LEVEL_TURBO>; 1539 opp-supported-hw = <0xff>; 1540 }; 1541 1542 opp-670000048 { 1543 opp-hz = /bits/ 64 <670000048>; 1544 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1545 opp-supported-hw = <0xff>; 1546 }; 1547 1548 opp-596000097 { 1549 opp-hz = /bits/ 64 <596000097>; 1550 opp-level = <RPM_SMD_LEVEL_NOM>; 1551 opp-supported-hw = <0xff>; 1552 }; 1553 1554 opp-515000097 { 1555 opp-hz = /bits/ 64 <515000097>; 1556 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1557 opp-supported-hw = <0xff>; 1558 }; 1559 1560 opp-414000000 { 1561 opp-hz = /bits/ 64 <414000000>; 1562 opp-level = <RPM_SMD_LEVEL_SVS>; 1563 opp-supported-hw = <0xff>; 1564 }; 1565 1566 opp-342000000 { 1567 opp-hz = /bits/ 64 <342000000>; 1568 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1569 opp-supported-hw = <0xff>; 1570 }; 1571 1572 opp-257000000 { 1573 opp-hz = /bits/ 64 <257000000>; 1574 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1575 opp-supported-hw = <0xff>; 1576 }; 1577 }; 1578 }; 1579 1580 adreno_smmu: iommu@5040000 { 1581 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 1582 reg = <0x05040000 0x10000>; 1583 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1584 <&gcc GCC_BIMC_GFX_CLK>, 1585 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1586 clock-names = "iface", "mem", "mem_iface"; 1587 1588 #global-interrupts = <0>; 1589 #iommu-cells = <1>; 1590 interrupts = 1591 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1594 /* 1595 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the 1596 * GPU-CX for SMMU but we need both of them up for Adreno. 1597 * Contemporarily, we also need to manage the VDDMX rpmpd 1598 * domain in the Adreno driver. 1599 * Enable GPU CX/GX GDSCs here so that we can manage the 1600 * SoC VDDMX RPM Power Domain in the Adreno driver. 1601 */ 1602 power-domains = <&gpucc GPU_GX_GDSC>; 1603 }; 1604 1605 gpucc: clock-controller@5065000 { 1606 compatible = "qcom,msm8998-gpucc"; 1607 #clock-cells = <1>; 1608 #reset-cells = <1>; 1609 #power-domain-cells = <1>; 1610 reg = <0x05065000 0x9000>; 1611 1612 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1613 <&gcc GCC_GPU_GPLL0_CLK>; 1614 clock-names = "xo", 1615 "gpll0"; 1616 }; 1617 1618 lpass_q6_smmu: iommu@5100000 { 1619 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 1620 reg = <0x05100000 0x40000>; 1621 clocks = <&gcc HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; 1622 clock-names = "bus"; 1623 1624 #global-interrupts = <0>; 1625 #iommu-cells = <1>; 1626 interrupts = 1627 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1640 1641 power-domains = <&gcc LPASS_ADSP_GDSC>; 1642 status = "disabled"; 1643 }; 1644 1645 remoteproc_slpi: remoteproc@5800000 { 1646 compatible = "qcom,msm8998-slpi-pas"; 1647 reg = <0x05800000 0x4040>; 1648 1649 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>, 1650 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1651 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1652 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1653 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1654 interrupt-names = "wdog", "fatal", "ready", 1655 "handover", "stop-ack"; 1656 1657 px-supply = <&vreg_lvs2a_1p8>; 1658 1659 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1660 clock-names = "xo"; 1661 1662 memory-region = <&slpi_mem>; 1663 1664 qcom,smem-states = <&slpi_smp2p_out 0>; 1665 qcom,smem-state-names = "stop"; 1666 1667 power-domains = <&rpmpd MSM8998_SSCCX>; 1668 power-domain-names = "ssc_cx"; 1669 1670 status = "disabled"; 1671 1672 glink-edge { 1673 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 1674 label = "dsps"; 1675 qcom,remote-pid = <3>; 1676 mboxes = <&apcs_glb 27>; 1677 }; 1678 }; 1679 1680 stm: stm@6002000 { 1681 compatible = "arm,coresight-stm", "arm,primecell"; 1682 reg = <0x06002000 0x1000>, 1683 <0x16280000 0x180000>; 1684 reg-names = "stm-base", "stm-stimulus-base"; 1685 status = "disabled"; 1686 1687 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1688 clock-names = "apb_pclk", "atclk"; 1689 1690 out-ports { 1691 port { 1692 stm_out: endpoint { 1693 remote-endpoint = <&funnel0_in7>; 1694 }; 1695 }; 1696 }; 1697 }; 1698 1699 funnel1: funnel@6041000 { 1700 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1701 reg = <0x06041000 0x1000>; 1702 status = "disabled"; 1703 1704 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1705 clock-names = "apb_pclk", "atclk"; 1706 1707 out-ports { 1708 port { 1709 funnel0_out: endpoint { 1710 remote-endpoint = 1711 <&merge_funnel_in0>; 1712 }; 1713 }; 1714 }; 1715 1716 in-ports { 1717 #address-cells = <1>; 1718 #size-cells = <0>; 1719 1720 port@7 { 1721 reg = <7>; 1722 funnel0_in7: endpoint { 1723 remote-endpoint = <&stm_out>; 1724 }; 1725 }; 1726 }; 1727 }; 1728 1729 funnel2: funnel@6042000 { 1730 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1731 reg = <0x06042000 0x1000>; 1732 status = "disabled"; 1733 1734 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1735 clock-names = "apb_pclk", "atclk"; 1736 1737 out-ports { 1738 port { 1739 funnel1_out: endpoint { 1740 remote-endpoint = 1741 <&merge_funnel_in1>; 1742 }; 1743 }; 1744 }; 1745 1746 in-ports { 1747 #address-cells = <1>; 1748 #size-cells = <0>; 1749 1750 port@6 { 1751 reg = <6>; 1752 funnel1_in6: endpoint { 1753 remote-endpoint = 1754 <&apss_merge_funnel_out>; 1755 }; 1756 }; 1757 }; 1758 }; 1759 1760 funnel3: funnel@6045000 { 1761 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1762 reg = <0x06045000 0x1000>; 1763 status = "disabled"; 1764 1765 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1766 clock-names = "apb_pclk", "atclk"; 1767 1768 out-ports { 1769 port { 1770 merge_funnel_out: endpoint { 1771 remote-endpoint = 1772 <&etf_in>; 1773 }; 1774 }; 1775 }; 1776 1777 in-ports { 1778 #address-cells = <1>; 1779 #size-cells = <0>; 1780 1781 port@0 { 1782 reg = <0>; 1783 merge_funnel_in0: endpoint { 1784 remote-endpoint = 1785 <&funnel0_out>; 1786 }; 1787 }; 1788 1789 port@1 { 1790 reg = <1>; 1791 merge_funnel_in1: endpoint { 1792 remote-endpoint = 1793 <&funnel1_out>; 1794 }; 1795 }; 1796 }; 1797 }; 1798 1799 replicator1: replicator@6046000 { 1800 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1801 reg = <0x06046000 0x1000>; 1802 status = "disabled"; 1803 1804 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1805 clock-names = "apb_pclk", "atclk"; 1806 1807 out-ports { 1808 port { 1809 replicator_out: endpoint { 1810 remote-endpoint = <&etr_in>; 1811 }; 1812 }; 1813 }; 1814 1815 in-ports { 1816 port { 1817 replicator_in: endpoint { 1818 remote-endpoint = <&etf_out>; 1819 }; 1820 }; 1821 }; 1822 }; 1823 1824 etf: etf@6047000 { 1825 compatible = "arm,coresight-tmc", "arm,primecell"; 1826 reg = <0x06047000 0x1000>; 1827 status = "disabled"; 1828 1829 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1830 clock-names = "apb_pclk", "atclk"; 1831 1832 out-ports { 1833 port { 1834 etf_out: endpoint { 1835 remote-endpoint = 1836 <&replicator_in>; 1837 }; 1838 }; 1839 }; 1840 1841 in-ports { 1842 port { 1843 etf_in: endpoint { 1844 remote-endpoint = 1845 <&merge_funnel_out>; 1846 }; 1847 }; 1848 }; 1849 }; 1850 1851 etr: etr@6048000 { 1852 compatible = "arm,coresight-tmc", "arm,primecell"; 1853 reg = <0x06048000 0x1000>; 1854 status = "disabled"; 1855 1856 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1857 clock-names = "apb_pclk", "atclk"; 1858 arm,scatter-gather; 1859 1860 in-ports { 1861 port { 1862 etr_in: endpoint { 1863 remote-endpoint = 1864 <&replicator_out>; 1865 }; 1866 }; 1867 }; 1868 }; 1869 1870 etm1: etm@7840000 { 1871 compatible = "arm,coresight-etm4x", "arm,primecell"; 1872 reg = <0x07840000 0x1000>; 1873 status = "disabled"; 1874 1875 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1876 clock-names = "apb_pclk", "atclk"; 1877 1878 cpu = <&cpu0>; 1879 1880 out-ports { 1881 port { 1882 etm0_out: endpoint { 1883 remote-endpoint = 1884 <&apss_funnel_in0>; 1885 }; 1886 }; 1887 }; 1888 }; 1889 1890 etm2: etm@7940000 { 1891 compatible = "arm,coresight-etm4x", "arm,primecell"; 1892 reg = <0x07940000 0x1000>; 1893 status = "disabled"; 1894 1895 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1896 clock-names = "apb_pclk", "atclk"; 1897 1898 cpu = <&cpu1>; 1899 1900 out-ports { 1901 port { 1902 etm1_out: endpoint { 1903 remote-endpoint = 1904 <&apss_funnel_in1>; 1905 }; 1906 }; 1907 }; 1908 }; 1909 1910 etm3: etm@7a40000 { 1911 compatible = "arm,coresight-etm4x", "arm,primecell"; 1912 reg = <0x07a40000 0x1000>; 1913 status = "disabled"; 1914 1915 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1916 clock-names = "apb_pclk", "atclk"; 1917 1918 cpu = <&cpu2>; 1919 1920 out-ports { 1921 port { 1922 etm2_out: endpoint { 1923 remote-endpoint = 1924 <&apss_funnel_in2>; 1925 }; 1926 }; 1927 }; 1928 }; 1929 1930 etm4: etm@7b40000 { 1931 compatible = "arm,coresight-etm4x", "arm,primecell"; 1932 reg = <0x07b40000 0x1000>; 1933 status = "disabled"; 1934 1935 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1936 clock-names = "apb_pclk", "atclk"; 1937 1938 cpu = <&cpu3>; 1939 1940 out-ports { 1941 port { 1942 etm3_out: endpoint { 1943 remote-endpoint = 1944 <&apss_funnel_in3>; 1945 }; 1946 }; 1947 }; 1948 }; 1949 1950 funnel4: funnel@7b60000 { /* APSS Funnel */ 1951 compatible = "arm,coresight-etm4x", "arm,primecell"; 1952 reg = <0x07b60000 0x1000>; 1953 status = "disabled"; 1954 1955 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1956 clock-names = "apb_pclk", "atclk"; 1957 1958 out-ports { 1959 port { 1960 apss_funnel_out: endpoint { 1961 remote-endpoint = 1962 <&apss_merge_funnel_in>; 1963 }; 1964 }; 1965 }; 1966 1967 in-ports { 1968 #address-cells = <1>; 1969 #size-cells = <0>; 1970 1971 port@0 { 1972 reg = <0>; 1973 apss_funnel_in0: endpoint { 1974 remote-endpoint = 1975 <&etm0_out>; 1976 }; 1977 }; 1978 1979 port@1 { 1980 reg = <1>; 1981 apss_funnel_in1: endpoint { 1982 remote-endpoint = 1983 <&etm1_out>; 1984 }; 1985 }; 1986 1987 port@2 { 1988 reg = <2>; 1989 apss_funnel_in2: endpoint { 1990 remote-endpoint = 1991 <&etm2_out>; 1992 }; 1993 }; 1994 1995 port@3 { 1996 reg = <3>; 1997 apss_funnel_in3: endpoint { 1998 remote-endpoint = 1999 <&etm3_out>; 2000 }; 2001 }; 2002 2003 port@4 { 2004 reg = <4>; 2005 apss_funnel_in4: endpoint { 2006 remote-endpoint = 2007 <&etm4_out>; 2008 }; 2009 }; 2010 2011 port@5 { 2012 reg = <5>; 2013 apss_funnel_in5: endpoint { 2014 remote-endpoint = 2015 <&etm5_out>; 2016 }; 2017 }; 2018 2019 port@6 { 2020 reg = <6>; 2021 apss_funnel_in6: endpoint { 2022 remote-endpoint = 2023 <&etm6_out>; 2024 }; 2025 }; 2026 2027 port@7 { 2028 reg = <7>; 2029 apss_funnel_in7: endpoint { 2030 remote-endpoint = 2031 <&etm7_out>; 2032 }; 2033 }; 2034 }; 2035 }; 2036 2037 funnel5: funnel@7b70000 { 2038 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2039 reg = <0x07b70000 0x1000>; 2040 status = "disabled"; 2041 2042 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2043 clock-names = "apb_pclk", "atclk"; 2044 2045 out-ports { 2046 port { 2047 apss_merge_funnel_out: endpoint { 2048 remote-endpoint = 2049 <&funnel1_in6>; 2050 }; 2051 }; 2052 }; 2053 2054 in-ports { 2055 port { 2056 apss_merge_funnel_in: endpoint { 2057 remote-endpoint = 2058 <&apss_funnel_out>; 2059 }; 2060 }; 2061 }; 2062 }; 2063 2064 etm5: etm@7c40000 { 2065 compatible = "arm,coresight-etm4x", "arm,primecell"; 2066 reg = <0x07c40000 0x1000>; 2067 status = "disabled"; 2068 2069 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2070 clock-names = "apb_pclk", "atclk"; 2071 2072 cpu = <&cpu4>; 2073 2074 out-ports { 2075 port { 2076 etm4_out: endpoint { 2077 remote-endpoint = <&apss_funnel_in4>; 2078 }; 2079 }; 2080 }; 2081 }; 2082 2083 etm6: etm@7d40000 { 2084 compatible = "arm,coresight-etm4x", "arm,primecell"; 2085 reg = <0x07d40000 0x1000>; 2086 status = "disabled"; 2087 2088 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2089 clock-names = "apb_pclk", "atclk"; 2090 2091 cpu = <&cpu5>; 2092 2093 out-ports { 2094 port { 2095 etm5_out: endpoint { 2096 remote-endpoint = <&apss_funnel_in5>; 2097 }; 2098 }; 2099 }; 2100 }; 2101 2102 etm7: etm@7e40000 { 2103 compatible = "arm,coresight-etm4x", "arm,primecell"; 2104 reg = <0x07e40000 0x1000>; 2105 status = "disabled"; 2106 2107 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2108 clock-names = "apb_pclk", "atclk"; 2109 2110 cpu = <&cpu6>; 2111 2112 out-ports { 2113 port { 2114 etm6_out: endpoint { 2115 remote-endpoint = <&apss_funnel_in6>; 2116 }; 2117 }; 2118 }; 2119 }; 2120 2121 etm8: etm@7f40000 { 2122 compatible = "arm,coresight-etm4x", "arm,primecell"; 2123 reg = <0x07f40000 0x1000>; 2124 status = "disabled"; 2125 2126 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2127 clock-names = "apb_pclk", "atclk"; 2128 2129 cpu = <&cpu7>; 2130 2131 out-ports { 2132 port { 2133 etm7_out: endpoint { 2134 remote-endpoint = <&apss_funnel_in7>; 2135 }; 2136 }; 2137 }; 2138 }; 2139 2140 sram@290000 { 2141 compatible = "qcom,rpm-stats"; 2142 reg = <0x00290000 0x10000>; 2143 }; 2144 2145 spmi_bus: spmi@800f000 { 2146 compatible = "qcom,spmi-pmic-arb"; 2147 reg = <0x0800f000 0x1000>, 2148 <0x08400000 0x1000000>, 2149 <0x09400000 0x1000000>, 2150 <0x0a400000 0x220000>, 2151 <0x0800a000 0x3000>; 2152 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2153 interrupt-names = "periph_irq"; 2154 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 2155 qcom,ee = <0>; 2156 qcom,channel = <0>; 2157 #address-cells = <2>; 2158 #size-cells = <0>; 2159 interrupt-controller; 2160 #interrupt-cells = <4>; 2161 }; 2162 2163 usb3: usb@a8f8800 { 2164 compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; 2165 reg = <0x0a8f8800 0x400>; 2166 status = "disabled"; 2167 #address-cells = <1>; 2168 #size-cells = <1>; 2169 ranges; 2170 2171 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 2172 <&gcc GCC_USB30_MASTER_CLK>, 2173 <&gcc GCC_AGGRE1_USB3_AXI_CLK>, 2174 <&gcc GCC_USB30_SLEEP_CLK>, 2175 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 2176 clock-names = "cfg_noc", 2177 "core", 2178 "iface", 2179 "sleep", 2180 "mock_utmi"; 2181 2182 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2183 <&gcc GCC_USB30_MASTER_CLK>; 2184 assigned-clock-rates = <19200000>, <120000000>; 2185 2186 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2188 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2189 interrupt-names = "pwr_event", 2190 "qusb2_phy", 2191 "ss_phy_irq"; 2192 2193 power-domains = <&gcc USB_30_GDSC>; 2194 2195 resets = <&gcc GCC_USB_30_BCR>; 2196 2197 usb3_dwc3: usb@a800000 { 2198 compatible = "snps,dwc3"; 2199 reg = <0x0a800000 0xcd00>; 2200 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2201 snps,dis_u2_susphy_quirk; 2202 snps,dis_enblslpm_quirk; 2203 snps,parkmode-disable-ss-quirk; 2204 phys = <&qusb2phy>, <&usb3phy>; 2205 phy-names = "usb2-phy", "usb3-phy"; 2206 snps,has-lpm-erratum; 2207 snps,hird-threshold = /bits/ 8 <0x10>; 2208 }; 2209 }; 2210 2211 usb3phy: phy@c010000 { 2212 compatible = "qcom,msm8998-qmp-usb3-phy"; 2213 reg = <0x0c010000 0x1000>; 2214 2215 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 2216 <&gcc GCC_USB3_CLKREF_CLK>, 2217 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2218 <&gcc GCC_USB3_PHY_PIPE_CLK>; 2219 clock-names = "aux", 2220 "ref", 2221 "cfg_ahb", 2222 "pipe"; 2223 clock-output-names = "usb3_phy_pipe_clk_src"; 2224 #clock-cells = <0>; 2225 #phy-cells = <0>; 2226 2227 resets = <&gcc GCC_USB3_PHY_BCR>, 2228 <&gcc GCC_USB3PHY_PHY_BCR>; 2229 reset-names = "phy", 2230 "phy_phy"; 2231 2232 qcom,tcsr-reg = <&tcsr_regs_2 0xb244>; 2233 2234 status = "disabled"; 2235 }; 2236 2237 qusb2phy: phy@c012000 { 2238 compatible = "qcom,msm8998-qusb2-phy"; 2239 reg = <0x0c012000 0x2a8>; 2240 status = "disabled"; 2241 #phy-cells = <0>; 2242 2243 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2244 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 2245 clock-names = "cfg_ahb", "ref"; 2246 2247 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2248 2249 nvmem-cells = <&qusb2_hstx_trim>; 2250 }; 2251 2252 sdhc2: mmc@c0a4900 { 2253 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4"; 2254 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; 2255 reg-names = "hc", "core"; 2256 2257 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2258 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2259 interrupt-names = "hc_irq", "pwr_irq"; 2260 2261 clock-names = "iface", "core", "xo"; 2262 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2263 <&gcc GCC_SDCC2_APPS_CLK>, 2264 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2265 bus-width = <4>; 2266 status = "disabled"; 2267 }; 2268 2269 blsp1_dma: dma-controller@c144000 { 2270 compatible = "qcom,bam-v1.7.0"; 2271 reg = <0x0c144000 0x25000>; 2272 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 2273 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 2274 clock-names = "bam_clk"; 2275 #dma-cells = <1>; 2276 qcom,ee = <0>; 2277 qcom,controlled-remotely; 2278 num-channels = <18>; 2279 qcom,num-ees = <4>; 2280 }; 2281 2282 blsp1_uart3: serial@c171000 { 2283 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2284 reg = <0x0c171000 0x1000>; 2285 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 2286 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 2287 <&gcc GCC_BLSP1_AHB_CLK>; 2288 clock-names = "core", "iface"; 2289 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 2290 dma-names = "tx", "rx"; 2291 pinctrl-names = "default"; 2292 pinctrl-0 = <&blsp1_uart3_on>; 2293 status = "disabled"; 2294 }; 2295 2296 blsp1_i2c1: i2c@c175000 { 2297 compatible = "qcom,i2c-qup-v2.2.1"; 2298 reg = <0x0c175000 0x600>; 2299 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2300 2301 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 2302 <&gcc GCC_BLSP1_AHB_CLK>; 2303 clock-names = "core", "iface"; 2304 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 2305 dma-names = "tx", "rx"; 2306 pinctrl-names = "default", "sleep"; 2307 pinctrl-0 = <&blsp1_i2c1_default>; 2308 pinctrl-1 = <&blsp1_i2c1_sleep>; 2309 clock-frequency = <400000>; 2310 2311 status = "disabled"; 2312 #address-cells = <1>; 2313 #size-cells = <0>; 2314 }; 2315 2316 blsp1_i2c2: i2c@c176000 { 2317 compatible = "qcom,i2c-qup-v2.2.1"; 2318 reg = <0x0c176000 0x600>; 2319 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2320 2321 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 2322 <&gcc GCC_BLSP1_AHB_CLK>; 2323 clock-names = "core", "iface"; 2324 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 2325 dma-names = "tx", "rx"; 2326 pinctrl-names = "default", "sleep"; 2327 pinctrl-0 = <&blsp1_i2c2_default>; 2328 pinctrl-1 = <&blsp1_i2c2_sleep>; 2329 clock-frequency = <400000>; 2330 2331 status = "disabled"; 2332 #address-cells = <1>; 2333 #size-cells = <0>; 2334 }; 2335 2336 blsp1_i2c3: i2c@c177000 { 2337 compatible = "qcom,i2c-qup-v2.2.1"; 2338 reg = <0x0c177000 0x600>; 2339 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2340 2341 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 2342 <&gcc GCC_BLSP1_AHB_CLK>; 2343 clock-names = "core", "iface"; 2344 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 2345 dma-names = "tx", "rx"; 2346 pinctrl-names = "default", "sleep"; 2347 pinctrl-0 = <&blsp1_i2c3_default>; 2348 pinctrl-1 = <&blsp1_i2c3_sleep>; 2349 clock-frequency = <400000>; 2350 2351 status = "disabled"; 2352 #address-cells = <1>; 2353 #size-cells = <0>; 2354 }; 2355 2356 blsp1_i2c4: i2c@c178000 { 2357 compatible = "qcom,i2c-qup-v2.2.1"; 2358 reg = <0x0c178000 0x600>; 2359 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2360 2361 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 2362 <&gcc GCC_BLSP1_AHB_CLK>; 2363 clock-names = "core", "iface"; 2364 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2365 dma-names = "tx", "rx"; 2366 pinctrl-names = "default", "sleep"; 2367 pinctrl-0 = <&blsp1_i2c4_default>; 2368 pinctrl-1 = <&blsp1_i2c4_sleep>; 2369 clock-frequency = <400000>; 2370 2371 status = "disabled"; 2372 #address-cells = <1>; 2373 #size-cells = <0>; 2374 }; 2375 2376 blsp1_i2c5: i2c@c179000 { 2377 compatible = "qcom,i2c-qup-v2.2.1"; 2378 reg = <0x0c179000 0x600>; 2379 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2380 2381 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 2382 <&gcc GCC_BLSP1_AHB_CLK>; 2383 clock-names = "core", "iface"; 2384 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 2385 dma-names = "tx", "rx"; 2386 pinctrl-names = "default", "sleep"; 2387 pinctrl-0 = <&blsp1_i2c5_default>; 2388 pinctrl-1 = <&blsp1_i2c5_sleep>; 2389 clock-frequency = <400000>; 2390 2391 status = "disabled"; 2392 #address-cells = <1>; 2393 #size-cells = <0>; 2394 }; 2395 2396 blsp1_i2c6: i2c@c17a000 { 2397 compatible = "qcom,i2c-qup-v2.2.1"; 2398 reg = <0x0c17a000 0x600>; 2399 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2400 2401 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 2402 <&gcc GCC_BLSP1_AHB_CLK>; 2403 clock-names = "core", "iface"; 2404 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2405 dma-names = "tx", "rx"; 2406 pinctrl-names = "default", "sleep"; 2407 pinctrl-0 = <&blsp1_i2c6_default>; 2408 pinctrl-1 = <&blsp1_i2c6_sleep>; 2409 clock-frequency = <400000>; 2410 2411 status = "disabled"; 2412 #address-cells = <1>; 2413 #size-cells = <0>; 2414 }; 2415 2416 blsp1_spi1: spi@c175000 { 2417 compatible = "qcom,spi-qup-v2.2.1"; 2418 reg = <0x0c175000 0x600>; 2419 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2420 2421 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 2422 <&gcc GCC_BLSP1_AHB_CLK>; 2423 clock-names = "core", "iface"; 2424 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 2425 dma-names = "tx", "rx"; 2426 pinctrl-names = "default"; 2427 pinctrl-0 = <&blsp1_spi1_default>; 2428 2429 status = "disabled"; 2430 #address-cells = <1>; 2431 #size-cells = <0>; 2432 }; 2433 2434 blsp1_spi2: spi@c176000 { 2435 compatible = "qcom,spi-qup-v2.2.1"; 2436 reg = <0x0c176000 0x600>; 2437 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2438 2439 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 2440 <&gcc GCC_BLSP1_AHB_CLK>; 2441 clock-names = "core", "iface"; 2442 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 2443 dma-names = "tx", "rx"; 2444 pinctrl-names = "default"; 2445 pinctrl-0 = <&blsp1_spi2_default>; 2446 2447 status = "disabled"; 2448 #address-cells = <1>; 2449 #size-cells = <0>; 2450 }; 2451 2452 blsp1_spi3: spi@c177000 { 2453 compatible = "qcom,spi-qup-v2.2.1"; 2454 reg = <0x0c177000 0x600>; 2455 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2456 2457 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 2458 <&gcc GCC_BLSP1_AHB_CLK>; 2459 clock-names = "core", "iface"; 2460 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 2461 dma-names = "tx", "rx"; 2462 pinctrl-names = "default"; 2463 pinctrl-0 = <&blsp1_spi3_default>; 2464 2465 status = "disabled"; 2466 #address-cells = <1>; 2467 #size-cells = <0>; 2468 }; 2469 2470 blsp1_spi4: spi@c178000 { 2471 compatible = "qcom,spi-qup-v2.2.1"; 2472 reg = <0x0c178000 0x600>; 2473 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2474 2475 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 2476 <&gcc GCC_BLSP1_AHB_CLK>; 2477 clock-names = "core", "iface"; 2478 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2479 dma-names = "tx", "rx"; 2480 pinctrl-names = "default"; 2481 pinctrl-0 = <&blsp1_spi4_default>; 2482 2483 status = "disabled"; 2484 #address-cells = <1>; 2485 #size-cells = <0>; 2486 }; 2487 2488 blsp1_spi5: spi@c179000 { 2489 compatible = "qcom,spi-qup-v2.2.1"; 2490 reg = <0x0c179000 0x600>; 2491 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2492 2493 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 2494 <&gcc GCC_BLSP1_AHB_CLK>; 2495 clock-names = "core", "iface"; 2496 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 2497 dma-names = "tx", "rx"; 2498 pinctrl-names = "default"; 2499 pinctrl-0 = <&blsp1_spi5_default>; 2500 2501 status = "disabled"; 2502 #address-cells = <1>; 2503 #size-cells = <0>; 2504 }; 2505 2506 blsp1_spi6: spi@c17a000 { 2507 compatible = "qcom,spi-qup-v2.2.1"; 2508 reg = <0x0c17a000 0x600>; 2509 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2510 2511 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 2512 <&gcc GCC_BLSP1_AHB_CLK>; 2513 clock-names = "core", "iface"; 2514 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2515 dma-names = "tx", "rx"; 2516 pinctrl-names = "default"; 2517 pinctrl-0 = <&blsp1_spi6_default>; 2518 2519 status = "disabled"; 2520 #address-cells = <1>; 2521 #size-cells = <0>; 2522 }; 2523 2524 blsp2_dma: dma-controller@c184000 { 2525 compatible = "qcom,bam-v1.7.0"; 2526 reg = <0x0c184000 0x25000>; 2527 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 2528 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 2529 clock-names = "bam_clk"; 2530 #dma-cells = <1>; 2531 qcom,ee = <0>; 2532 qcom,controlled-remotely; 2533 num-channels = <18>; 2534 qcom,num-ees = <4>; 2535 }; 2536 2537 blsp2_uart1: serial@c1b0000 { 2538 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2539 reg = <0x0c1b0000 0x1000>; 2540 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 2541 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 2542 <&gcc GCC_BLSP2_AHB_CLK>; 2543 clock-names = "core", "iface"; 2544 status = "disabled"; 2545 }; 2546 2547 blsp2_i2c1: i2c@c1b5000 { 2548 compatible = "qcom,i2c-qup-v2.2.1"; 2549 reg = <0x0c1b5000 0x600>; 2550 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2551 2552 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 2553 <&gcc GCC_BLSP2_AHB_CLK>; 2554 clock-names = "core", "iface"; 2555 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 2556 dma-names = "tx", "rx"; 2557 pinctrl-names = "default", "sleep"; 2558 pinctrl-0 = <&blsp2_i2c1_default>; 2559 pinctrl-1 = <&blsp2_i2c1_sleep>; 2560 clock-frequency = <400000>; 2561 2562 status = "disabled"; 2563 #address-cells = <1>; 2564 #size-cells = <0>; 2565 }; 2566 2567 blsp2_i2c2: i2c@c1b6000 { 2568 compatible = "qcom,i2c-qup-v2.2.1"; 2569 reg = <0x0c1b6000 0x600>; 2570 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2571 2572 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 2573 <&gcc GCC_BLSP2_AHB_CLK>; 2574 clock-names = "core", "iface"; 2575 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 2576 dma-names = "tx", "rx"; 2577 pinctrl-names = "default", "sleep"; 2578 pinctrl-0 = <&blsp2_i2c2_default>; 2579 pinctrl-1 = <&blsp2_i2c2_sleep>; 2580 clock-frequency = <400000>; 2581 2582 status = "disabled"; 2583 #address-cells = <1>; 2584 #size-cells = <0>; 2585 }; 2586 2587 blsp2_i2c3: i2c@c1b7000 { 2588 compatible = "qcom,i2c-qup-v2.2.1"; 2589 reg = <0x0c1b7000 0x600>; 2590 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2591 2592 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 2593 <&gcc GCC_BLSP2_AHB_CLK>; 2594 clock-names = "core", "iface"; 2595 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 2596 dma-names = "tx", "rx"; 2597 pinctrl-names = "default", "sleep"; 2598 pinctrl-0 = <&blsp2_i2c3_default>; 2599 pinctrl-1 = <&blsp2_i2c3_sleep>; 2600 clock-frequency = <400000>; 2601 2602 status = "disabled"; 2603 #address-cells = <1>; 2604 #size-cells = <0>; 2605 }; 2606 2607 blsp2_i2c4: i2c@c1b8000 { 2608 compatible = "qcom,i2c-qup-v2.2.1"; 2609 reg = <0x0c1b8000 0x600>; 2610 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2611 2612 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 2613 <&gcc GCC_BLSP2_AHB_CLK>; 2614 clock-names = "core", "iface"; 2615 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2616 dma-names = "tx", "rx"; 2617 pinctrl-names = "default", "sleep"; 2618 pinctrl-0 = <&blsp2_i2c4_default>; 2619 pinctrl-1 = <&blsp2_i2c4_sleep>; 2620 clock-frequency = <400000>; 2621 2622 status = "disabled"; 2623 #address-cells = <1>; 2624 #size-cells = <0>; 2625 }; 2626 2627 blsp2_i2c5: i2c@c1b9000 { 2628 compatible = "qcom,i2c-qup-v2.2.1"; 2629 reg = <0x0c1b9000 0x600>; 2630 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2631 2632 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 2633 <&gcc GCC_BLSP2_AHB_CLK>; 2634 clock-names = "core", "iface"; 2635 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2636 dma-names = "tx", "rx"; 2637 pinctrl-names = "default", "sleep"; 2638 pinctrl-0 = <&blsp2_i2c5_default>; 2639 pinctrl-1 = <&blsp2_i2c5_sleep>; 2640 clock-frequency = <400000>; 2641 2642 status = "disabled"; 2643 #address-cells = <1>; 2644 #size-cells = <0>; 2645 }; 2646 2647 blsp2_i2c6: i2c@c1ba000 { 2648 compatible = "qcom,i2c-qup-v2.2.1"; 2649 reg = <0x0c1ba000 0x600>; 2650 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2651 2652 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 2653 <&gcc GCC_BLSP2_AHB_CLK>; 2654 clock-names = "core", "iface"; 2655 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2656 dma-names = "tx", "rx"; 2657 pinctrl-names = "default", "sleep"; 2658 pinctrl-0 = <&blsp2_i2c6_default>; 2659 pinctrl-1 = <&blsp2_i2c6_sleep>; 2660 clock-frequency = <400000>; 2661 2662 status = "disabled"; 2663 #address-cells = <1>; 2664 #size-cells = <0>; 2665 }; 2666 2667 blsp2_spi1: spi@c1b5000 { 2668 compatible = "qcom,spi-qup-v2.2.1"; 2669 reg = <0x0c1b5000 0x600>; 2670 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2671 2672 clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>, 2673 <&gcc GCC_BLSP2_AHB_CLK>; 2674 clock-names = "core", "iface"; 2675 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 2676 dma-names = "tx", "rx"; 2677 pinctrl-names = "default"; 2678 pinctrl-0 = <&blsp2_spi1_default>; 2679 2680 status = "disabled"; 2681 #address-cells = <1>; 2682 #size-cells = <0>; 2683 }; 2684 2685 blsp2_spi2: spi@c1b6000 { 2686 compatible = "qcom,spi-qup-v2.2.1"; 2687 reg = <0x0c1b6000 0x600>; 2688 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2689 2690 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, 2691 <&gcc GCC_BLSP2_AHB_CLK>; 2692 clock-names = "core", "iface"; 2693 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 2694 dma-names = "tx", "rx"; 2695 pinctrl-names = "default"; 2696 pinctrl-0 = <&blsp2_spi2_default>; 2697 2698 status = "disabled"; 2699 #address-cells = <1>; 2700 #size-cells = <0>; 2701 }; 2702 2703 blsp2_spi3: spi@c1b7000 { 2704 compatible = "qcom,spi-qup-v2.2.1"; 2705 reg = <0x0c1b7000 0x600>; 2706 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2707 2708 clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>, 2709 <&gcc GCC_BLSP2_AHB_CLK>; 2710 clock-names = "core", "iface"; 2711 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 2712 dma-names = "tx", "rx"; 2713 pinctrl-names = "default"; 2714 pinctrl-0 = <&blsp2_spi3_default>; 2715 2716 status = "disabled"; 2717 #address-cells = <1>; 2718 #size-cells = <0>; 2719 }; 2720 2721 blsp2_spi4: spi@c1b8000 { 2722 compatible = "qcom,spi-qup-v2.2.1"; 2723 reg = <0x0c1b8000 0x600>; 2724 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2725 2726 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, 2727 <&gcc GCC_BLSP2_AHB_CLK>; 2728 clock-names = "core", "iface"; 2729 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2730 dma-names = "tx", "rx"; 2731 pinctrl-names = "default"; 2732 pinctrl-0 = <&blsp2_spi4_default>; 2733 2734 status = "disabled"; 2735 #address-cells = <1>; 2736 #size-cells = <0>; 2737 }; 2738 2739 blsp2_spi5: spi@c1b9000 { 2740 compatible = "qcom,spi-qup-v2.2.1"; 2741 reg = <0x0c1b9000 0x600>; 2742 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2743 2744 clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, 2745 <&gcc GCC_BLSP2_AHB_CLK>; 2746 clock-names = "core", "iface"; 2747 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2748 dma-names = "tx", "rx"; 2749 pinctrl-names = "default"; 2750 pinctrl-0 = <&blsp2_spi5_default>; 2751 2752 status = "disabled"; 2753 #address-cells = <1>; 2754 #size-cells = <0>; 2755 }; 2756 2757 blsp2_spi6: spi@c1ba000 { 2758 compatible = "qcom,spi-qup-v2.2.1"; 2759 reg = <0x0c1ba000 0x600>; 2760 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2761 2762 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 2763 <&gcc GCC_BLSP2_AHB_CLK>; 2764 clock-names = "core", "iface"; 2765 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2766 dma-names = "tx", "rx"; 2767 pinctrl-names = "default"; 2768 pinctrl-0 = <&blsp2_spi6_default>; 2769 2770 status = "disabled"; 2771 #address-cells = <1>; 2772 #size-cells = <0>; 2773 }; 2774 2775 mmcc: clock-controller@c8c0000 { 2776 compatible = "qcom,mmcc-msm8998"; 2777 #clock-cells = <1>; 2778 #reset-cells = <1>; 2779 #power-domain-cells = <1>; 2780 reg = <0xc8c0000 0x40000>; 2781 2782 clock-names = "xo", 2783 "gpll0", 2784 "dsi0dsi", 2785 "dsi0byte", 2786 "dsi1dsi", 2787 "dsi1byte", 2788 "hdmipll", 2789 "dplink", 2790 "dpvco", 2791 "gpll0_div"; 2792 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2793 <&gcc GCC_MMSS_GPLL0_CLK>, 2794 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 2795 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2796 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 2797 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 2798 <&mdss_hdmi_phy>, 2799 <0>, 2800 <0>, 2801 <&gcc GCC_MMSS_GPLL0_DIV_CLK>; 2802 }; 2803 2804 mdss: display-subsystem@c900000 { 2805 compatible = "qcom,msm8998-mdss"; 2806 reg = <0x0c900000 0x1000>; 2807 reg-names = "mdss"; 2808 2809 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2810 interrupt-controller; 2811 #interrupt-cells = <1>; 2812 2813 clocks = <&mmcc MDSS_AHB_CLK>, 2814 <&mmcc MDSS_AXI_CLK>, 2815 <&mmcc MDSS_MDP_CLK>; 2816 clock-names = "iface", 2817 "bus", 2818 "core"; 2819 2820 power-domains = <&mmcc MDSS_GDSC>; 2821 iommus = <&mmss_smmu 0>; 2822 2823 #address-cells = <1>; 2824 #size-cells = <1>; 2825 ranges; 2826 2827 status = "disabled"; 2828 2829 mdss_mdp: display-controller@c901000 { 2830 compatible = "qcom,msm8998-dpu"; 2831 reg = <0x0c901000 0x8f000>, 2832 <0x0c9a8e00 0xf0>, 2833 <0x0c9b0000 0x3000>, 2834 <0x0c9b8000 0x3000>; 2835 reg-names = "mdp", 2836 "regdma", 2837 "vbif", 2838 "vbif_nrt"; 2839 2840 interrupt-parent = <&mdss>; 2841 interrupts = <0>; 2842 2843 clocks = <&mmcc MDSS_AHB_CLK>, 2844 <&mmcc MDSS_AXI_CLK>, 2845 <&mmcc MNOC_AHB_CLK>, 2846 <&mmcc MDSS_MDP_CLK>, 2847 <&mmcc MDSS_VSYNC_CLK>; 2848 clock-names = "iface", 2849 "bus", 2850 "mnoc", 2851 "core", 2852 "vsync"; 2853 2854 assigned-clocks = <&mmcc MDSS_VSYNC_CLK>; 2855 assigned-clock-rates = <19200000>; 2856 2857 operating-points-v2 = <&mdp_opp_table>; 2858 power-domains = <&rpmpd MSM8998_VDDMX>; 2859 2860 mdp_opp_table: opp-table { 2861 compatible = "operating-points-v2"; 2862 2863 opp-171430000 { 2864 opp-hz = /bits/ 64 <171430000>; 2865 required-opps = <&rpmpd_opp_low_svs>; 2866 }; 2867 2868 opp-275000000 { 2869 opp-hz = /bits/ 64 <275000000>; 2870 required-opps = <&rpmpd_opp_svs>; 2871 }; 2872 2873 opp-330000000 { 2874 opp-hz = /bits/ 64 <330000000>; 2875 required-opps = <&rpmpd_opp_nom>; 2876 }; 2877 2878 opp-412500000 { 2879 opp-hz = /bits/ 64 <412500000>; 2880 required-opps = <&rpmpd_opp_turbo>; 2881 }; 2882 }; 2883 2884 ports { 2885 #address-cells = <1>; 2886 #size-cells = <0>; 2887 2888 port@0 { 2889 reg = <0>; 2890 2891 dpu_intf1_out: endpoint { 2892 remote-endpoint = <&mdss_dsi0_in>; 2893 }; 2894 }; 2895 2896 port@1 { 2897 reg = <1>; 2898 2899 dpu_intf2_out: endpoint { 2900 remote-endpoint = <&mdss_dsi1_in>; 2901 }; 2902 }; 2903 2904 port@2 { 2905 reg = <2>; 2906 2907 dpu_intf3_out: endpoint { 2908 remote-endpoint = <&hdmi_in>; 2909 }; 2910 }; 2911 }; 2912 }; 2913 2914 mdss_dsi0: dsi@c994000 { 2915 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2916 reg = <0x0c994000 0x400>; 2917 reg-names = "dsi_ctrl"; 2918 2919 interrupt-parent = <&mdss>; 2920 interrupts = <4>; 2921 2922 clocks = <&mmcc MDSS_BYTE0_CLK>, 2923 <&mmcc MDSS_BYTE0_INTF_CLK>, 2924 <&mmcc MDSS_PCLK0_CLK>, 2925 <&mmcc MDSS_ESC0_CLK>, 2926 <&mmcc MDSS_AHB_CLK>, 2927 <&mmcc MDSS_AXI_CLK>; 2928 clock-names = "byte", 2929 "byte_intf", 2930 "pixel", 2931 "core", 2932 "iface", 2933 "bus"; 2934 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 2935 <&mmcc PCLK0_CLK_SRC>; 2936 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2937 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 2938 2939 operating-points-v2 = <&dsi_opp_table>; 2940 power-domains = <&rpmpd MSM8998_VDDCX>; 2941 2942 phys = <&mdss_dsi0_phy>; 2943 phy-names = "dsi"; 2944 2945 #address-cells = <1>; 2946 #size-cells = <0>; 2947 2948 status = "disabled"; 2949 2950 ports { 2951 #address-cells = <1>; 2952 #size-cells = <0>; 2953 2954 port@0 { 2955 reg = <0>; 2956 2957 mdss_dsi0_in: endpoint { 2958 remote-endpoint = <&dpu_intf1_out>; 2959 }; 2960 }; 2961 2962 port@1 { 2963 reg = <1>; 2964 2965 mdss_dsi0_out: endpoint { 2966 }; 2967 }; 2968 }; 2969 }; 2970 2971 mdss_dsi0_phy: phy@c994400 { 2972 compatible = "qcom,dsi-phy-10nm-8998"; 2973 reg = <0x0c994400 0x200>, 2974 <0x0c994600 0x280>, 2975 <0x0c994a00 0x1e0>; 2976 reg-names = "dsi_phy", 2977 "dsi_phy_lane", 2978 "dsi_pll"; 2979 2980 clocks = <&mmcc MDSS_AHB_CLK>, 2981 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2982 clock-names = "iface", "ref"; 2983 2984 #clock-cells = <1>; 2985 #phy-cells = <0>; 2986 2987 status = "disabled"; 2988 }; 2989 2990 mdss_dsi1: dsi@c996000 { 2991 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2992 reg = <0x0c996000 0x400>; 2993 reg-names = "dsi_ctrl"; 2994 2995 interrupt-parent = <&mdss>; 2996 interrupts = <5>; 2997 2998 clocks = <&mmcc MDSS_BYTE1_CLK>, 2999 <&mmcc MDSS_BYTE1_INTF_CLK>, 3000 <&mmcc MDSS_PCLK1_CLK>, 3001 <&mmcc MDSS_ESC1_CLK>, 3002 <&mmcc MDSS_AHB_CLK>, 3003 <&mmcc MDSS_AXI_CLK>; 3004 clock-names = "byte", 3005 "byte_intf", 3006 "pixel", 3007 "core", 3008 "iface", 3009 "bus"; 3010 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, 3011 <&mmcc PCLK1_CLK_SRC>; 3012 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3013 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 3014 3015 operating-points-v2 = <&dsi_opp_table>; 3016 power-domains = <&rpmpd MSM8998_VDDCX>; 3017 3018 phys = <&mdss_dsi1_phy>; 3019 phy-names = "dsi"; 3020 3021 #address-cells = <1>; 3022 #size-cells = <0>; 3023 3024 status = "disabled"; 3025 3026 ports { 3027 #address-cells = <1>; 3028 #size-cells = <0>; 3029 3030 port@0 { 3031 reg = <0>; 3032 3033 mdss_dsi1_in: endpoint { 3034 remote-endpoint = <&dpu_intf2_out>; 3035 }; 3036 }; 3037 3038 port@1 { 3039 reg = <1>; 3040 3041 mdss_dsi1_out: endpoint { 3042 }; 3043 }; 3044 }; 3045 }; 3046 3047 mdss_dsi1_phy: phy@c996400 { 3048 compatible = "qcom,dsi-phy-10nm-8998"; 3049 reg = <0x0c996400 0x200>, 3050 <0x0c996600 0x280>, 3051 <0x0c996a00 0x10e>; 3052 reg-names = "dsi_phy", 3053 "dsi_phy_lane", 3054 "dsi_pll"; 3055 3056 clocks = <&mmcc MDSS_AHB_CLK>, 3057 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3058 clock-names = "iface", 3059 "ref"; 3060 3061 #clock-cells = <1>; 3062 #phy-cells = <0>; 3063 3064 status = "disabled"; 3065 }; 3066 3067 mdss_hdmi: hdmi-tx@c9a0000 { 3068 compatible = "qcom,hdmi-tx-8998"; 3069 reg = <0x0c9a0000 0x50c>, 3070 <0x00780000 0x6220>, 3071 <0x0c9e0000 0x2c>; 3072 reg-names = "core_physical", 3073 "qfprom_physical", 3074 "hdcp_physical"; 3075 3076 interrupt-parent = <&mdss>; 3077 interrupts = <8>; 3078 3079 clocks = <&mmcc MDSS_MDP_CLK>, 3080 <&mmcc MDSS_AHB_CLK>, 3081 <&mmcc MDSS_HDMI_CLK>, 3082 <&mmcc MDSS_HDMI_DP_AHB_CLK>, 3083 <&mmcc MDSS_EXTPCLK_CLK>, 3084 <&mmcc MDSS_AXI_CLK>, 3085 <&mmcc MNOC_AHB_CLK>, 3086 <&mmcc MISC_AHB_CLK>; 3087 clock-names = 3088 "mdp_core", 3089 "iface", 3090 "core", 3091 "alt_iface", 3092 "extp", 3093 "bus", 3094 "mnoc", 3095 "iface_mmss"; 3096 3097 phys = <&mdss_hdmi_phy>; 3098 #sound-dai-cells = <1>; 3099 3100 pinctrl-0 = <&hdmi_hpd_default>, 3101 <&hdmi_ddc_default>, 3102 <&hdmi_cec_default>; 3103 pinctrl-1 = <&hdmi_hpd_sleep>, 3104 <&hdmi_ddc_default>, 3105 <&hdmi_cec_default>; 3106 pinctrl-names = "default", "sleep"; 3107 3108 status = "disabled"; 3109 3110 ports { 3111 #address-cells = <1>; 3112 #size-cells = <0>; 3113 3114 port@0 { 3115 reg = <0>; 3116 hdmi_in: endpoint { 3117 remote-endpoint = <&dpu_intf3_out>; 3118 }; 3119 }; 3120 3121 port@1 { 3122 reg = <1>; 3123 hdmi_out: endpoint { 3124 }; 3125 }; 3126 }; 3127 }; 3128 3129 mdss_hdmi_phy: hdmi-phy@c9a0600 { 3130 compatible = "qcom,hdmi-phy-8998"; 3131 reg = <0x0c9a0600 0x18b>, 3132 <0x0c9a0a00 0x38>, 3133 <0x0c9a0c00 0x38>, 3134 <0x0c9a0e00 0x38>, 3135 <0x0c9a1000 0x38>, 3136 <0x0c9a1200 0x0e8>; 3137 reg-names = "hdmi_pll", 3138 "hdmi_tx_l0", 3139 "hdmi_tx_l1", 3140 "hdmi_tx_l2", 3141 "hdmi_tx_l3", 3142 "hdmi_phy"; 3143 3144 #clock-cells = <0>; 3145 #phy-cells = <0>; 3146 3147 clocks = <&mmcc MDSS_AHB_CLK>, 3148 <&gcc GCC_HDMI_CLKREF_CLK>, 3149 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3150 clock-names = "iface", 3151 "ref", 3152 "xo"; 3153 3154 status = "disabled"; 3155 }; 3156 }; 3157 3158 venus: video-codec@cc00000 { 3159 compatible = "qcom,msm8998-venus"; 3160 reg = <0x0cc00000 0xff000>; 3161 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 3162 power-domains = <&mmcc VIDEO_TOP_GDSC>; 3163 clocks = <&mmcc VIDEO_CORE_CLK>, 3164 <&mmcc VIDEO_AHB_CLK>, 3165 <&mmcc VIDEO_AXI_CLK>, 3166 <&mmcc VIDEO_MAXI_CLK>; 3167 clock-names = "core", "iface", "bus", "mbus"; 3168 iommus = <&mmss_smmu 0x400>, 3169 <&mmss_smmu 0x401>, 3170 <&mmss_smmu 0x40a>, 3171 <&mmss_smmu 0x407>, 3172 <&mmss_smmu 0x40e>, 3173 <&mmss_smmu 0x40f>, 3174 <&mmss_smmu 0x408>, 3175 <&mmss_smmu 0x409>, 3176 <&mmss_smmu 0x40b>, 3177 <&mmss_smmu 0x40c>, 3178 <&mmss_smmu 0x40d>, 3179 <&mmss_smmu 0x410>, 3180 <&mmss_smmu 0x421>, 3181 <&mmss_smmu 0x428>, 3182 <&mmss_smmu 0x429>, 3183 <&mmss_smmu 0x42b>, 3184 <&mmss_smmu 0x42c>, 3185 <&mmss_smmu 0x42d>, 3186 <&mmss_smmu 0x411>, 3187 <&mmss_smmu 0x431>; 3188 memory-region = <&venus_mem>; 3189 status = "disabled"; 3190 3191 video-decoder { 3192 compatible = "venus-decoder"; 3193 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 3194 clock-names = "core"; 3195 power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>; 3196 }; 3197 3198 video-encoder { 3199 compatible = "venus-encoder"; 3200 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 3201 clock-names = "core"; 3202 power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>; 3203 }; 3204 }; 3205 3206 mmss_smmu: iommu@cd00000 { 3207 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 3208 reg = <0x0cd00000 0x40000>; 3209 #iommu-cells = <1>; 3210 3211 clocks = <&mmcc MNOC_AHB_CLK>, 3212 <&mmcc BIMC_SMMU_AHB_CLK>, 3213 <&mmcc BIMC_SMMU_AXI_CLK>; 3214 clock-names = "iface-mm", 3215 "iface-smmu", 3216 "bus-smmu"; 3217 3218 #global-interrupts = <0>; 3219 interrupts = 3220 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 3221 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 3222 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 3223 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 3224 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 3225 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 3226 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 3227 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 3228 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 3229 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 3230 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 3231 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 3232 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 3233 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 3234 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 3235 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 3236 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 3237 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 3238 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 3239 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 3240 3241 power-domains = <&mmcc BIMC_SMMU_GDSC>; 3242 }; 3243 3244 remoteproc_adsp: remoteproc@17300000 { 3245 compatible = "qcom,msm8998-adsp-pas"; 3246 reg = <0x17300000 0x4040>; 3247 3248 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3249 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3250 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3251 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3252 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3253 interrupt-names = "wdog", "fatal", "ready", 3254 "handover", "stop-ack"; 3255 3256 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 3257 clock-names = "xo"; 3258 3259 memory-region = <&adsp_mem>; 3260 3261 qcom,smem-states = <&adsp_smp2p_out 0>; 3262 qcom,smem-state-names = "stop"; 3263 3264 power-domains = <&rpmpd MSM8998_VDDCX>; 3265 power-domain-names = "cx"; 3266 3267 status = "disabled"; 3268 3269 glink-edge { 3270 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 3271 label = "lpass"; 3272 qcom,remote-pid = <2>; 3273 mboxes = <&apcs_glb 9>; 3274 }; 3275 }; 3276 3277 apcs_glb: mailbox@17911000 { 3278 compatible = "qcom,msm8998-apcs-hmss-global", 3279 "qcom,msm8994-apcs-kpss-global"; 3280 reg = <0x17911000 0x1000>; 3281 3282 #mbox-cells = <1>; 3283 }; 3284 3285 timer@17920000 { 3286 #address-cells = <1>; 3287 #size-cells = <1>; 3288 ranges; 3289 compatible = "arm,armv7-timer-mem"; 3290 reg = <0x17920000 0x1000>; 3291 3292 frame@17921000 { 3293 frame-number = <0>; 3294 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3295 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 3296 reg = <0x17921000 0x1000>, 3297 <0x17922000 0x1000>; 3298 }; 3299 3300 frame@17923000 { 3301 frame-number = <1>; 3302 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3303 reg = <0x17923000 0x1000>; 3304 status = "disabled"; 3305 }; 3306 3307 frame@17924000 { 3308 frame-number = <2>; 3309 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3310 reg = <0x17924000 0x1000>; 3311 status = "disabled"; 3312 }; 3313 3314 frame@17925000 { 3315 frame-number = <3>; 3316 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3317 reg = <0x17925000 0x1000>; 3318 status = "disabled"; 3319 }; 3320 3321 frame@17926000 { 3322 frame-number = <4>; 3323 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3324 reg = <0x17926000 0x1000>; 3325 status = "disabled"; 3326 }; 3327 3328 frame@17927000 { 3329 frame-number = <5>; 3330 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3331 reg = <0x17927000 0x1000>; 3332 status = "disabled"; 3333 }; 3334 3335 frame@17928000 { 3336 frame-number = <6>; 3337 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3338 reg = <0x17928000 0x1000>; 3339 status = "disabled"; 3340 }; 3341 }; 3342 3343 intc: interrupt-controller@17a00000 { 3344 compatible = "arm,gic-v3"; 3345 reg = <0x17a00000 0x10000>, /* GICD */ 3346 <0x17b00000 0x100000>; /* GICR * 8 */ 3347 #interrupt-cells = <3>; 3348 #address-cells = <1>; 3349 #size-cells = <1>; 3350 ranges; 3351 interrupt-controller; 3352 #redistributor-regions = <1>; 3353 redistributor-stride = <0x0 0x20000>; 3354 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3355 }; 3356 3357 wifi: wifi@18800000 { 3358 compatible = "qcom,wcn3990-wifi"; 3359 status = "disabled"; 3360 reg = <0x18800000 0x800000>; 3361 reg-names = "membase"; 3362 memory-region = <&wlan_msa_mem>; 3363 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>; 3364 clock-names = "cxo_ref_clk_pin"; 3365 interrupts = 3366 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3378 iommus = <&anoc2_smmu 0x1900>, 3379 <&anoc2_smmu 0x1901>; 3380 qcom,snoc-host-cap-8bit-quirk; 3381 qcom,no-msa-ready-indicator; 3382 }; 3383 }; 3384}; 3385