1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip Polarfire FPGA programming over slave SPI interface. 4 */ 5 6 #include <linux/unaligned.h> 7 #include <linux/delay.h> 8 #include <linux/fpga/fpga-mgr.h> 9 #include <linux/iopoll.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/spi/spi.h> 13 14 #define MPF_SPI_ISC_ENABLE 0x0B 15 #define MPF_SPI_ISC_DISABLE 0x0C 16 #define MPF_SPI_READ_STATUS 0x00 17 #define MPF_SPI_READ_DATA 0x01 18 #define MPF_SPI_FRAME_INIT 0xAE 19 #define MPF_SPI_FRAME 0xEE 20 #define MPF_SPI_PRG_MODE 0x01 21 #define MPF_SPI_RELEASE 0x23 22 23 #define MPF_SPI_FRAME_SIZE 16 24 25 #define MPF_HEADER_SIZE_OFFSET 24 26 #define MPF_DATA_SIZE_OFFSET 55 27 28 #define MPF_LOOKUP_TABLE_RECORD_SIZE 9 29 #define MPF_LOOKUP_TABLE_BLOCK_ID_OFFSET 0 30 #define MPF_LOOKUP_TABLE_BLOCK_START_OFFSET 1 31 32 #define MPF_COMPONENTS_SIZE_ID 5 33 #define MPF_BITSTREAM_ID 8 34 35 #define MPF_BITS_PER_COMPONENT_SIZE 22 36 37 #define MPF_STATUS_POLL_TIMEOUT (2 * USEC_PER_SEC) 38 #define MPF_STATUS_BUSY BIT(0) 39 #define MPF_STATUS_READY BIT(1) 40 #define MPF_STATUS_SPI_VIOLATION BIT(2) 41 #define MPF_STATUS_SPI_ERROR BIT(3) 42 43 struct mpf_priv { 44 struct spi_device *spi; 45 bool program_mode; 46 u8 tx __aligned(ARCH_KMALLOC_MINALIGN); 47 u8 rx; 48 }; 49 50 static int mpf_read_status(struct mpf_priv *priv) 51 { 52 /* 53 * HW status is returned on MISO in the first byte after CS went 54 * active. However, first reading can be inadequate, so we submit 55 * two identical SPI transfers and use result of the later one. 56 */ 57 struct spi_transfer xfers[2] = { 58 { 59 .tx_buf = &priv->tx, 60 .rx_buf = &priv->rx, 61 .len = 1, 62 .cs_change = 1, 63 }, { 64 .tx_buf = &priv->tx, 65 .rx_buf = &priv->rx, 66 .len = 1, 67 }, 68 }; 69 u8 status; 70 int ret; 71 72 priv->tx = MPF_SPI_READ_STATUS; 73 74 ret = spi_sync_transfer(priv->spi, xfers, 2); 75 if (ret) 76 return ret; 77 78 status = priv->rx; 79 80 if ((status & MPF_STATUS_SPI_VIOLATION) || 81 (status & MPF_STATUS_SPI_ERROR)) 82 return -EIO; 83 84 return status; 85 } 86 87 static enum fpga_mgr_states mpf_ops_state(struct fpga_manager *mgr) 88 { 89 struct mpf_priv *priv = mgr->priv; 90 bool program_mode; 91 int status; 92 93 program_mode = priv->program_mode; 94 status = mpf_read_status(priv); 95 96 if (!program_mode && !status) 97 return FPGA_MGR_STATE_OPERATING; 98 99 return FPGA_MGR_STATE_UNKNOWN; 100 } 101 102 static int mpf_ops_parse_header(struct fpga_manager *mgr, 103 struct fpga_image_info *info, 104 const char *buf, size_t count) 105 { 106 size_t component_size_byte_num, component_size_byte_off, 107 components_size_start, bitstream_start, 108 block_id_offset, block_start_offset; 109 u8 header_size, blocks_num, block_id; 110 u32 block_start, component_size; 111 u16 components_num, i; 112 113 if (!buf) { 114 dev_err(&mgr->dev, "Image buffer is not provided\n"); 115 return -EINVAL; 116 } 117 118 header_size = *(buf + MPF_HEADER_SIZE_OFFSET); 119 if (!header_size) 120 return -EINVAL; 121 122 if (header_size > count) { 123 info->header_size = header_size; 124 return -EAGAIN; 125 } 126 127 /* 128 * Go through look-up table to find out where actual bitstream starts 129 * and where sizes of components of the bitstream lies. 130 */ 131 blocks_num = *(buf + header_size - 1); 132 block_id_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_ID_OFFSET; 133 block_start_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_START_OFFSET; 134 135 header_size += blocks_num * MPF_LOOKUP_TABLE_RECORD_SIZE; 136 if (header_size > count) { 137 info->header_size = header_size; 138 return -EAGAIN; 139 } 140 141 components_size_start = 0; 142 bitstream_start = 0; 143 144 while (blocks_num--) { 145 block_id = *(buf + block_id_offset); 146 block_start = get_unaligned_le32(buf + block_start_offset); 147 148 switch (block_id) { 149 case MPF_BITSTREAM_ID: 150 bitstream_start = block_start; 151 info->header_size = block_start; 152 if (block_start > count) 153 return -EAGAIN; 154 155 break; 156 case MPF_COMPONENTS_SIZE_ID: 157 components_size_start = block_start; 158 break; 159 default: 160 break; 161 } 162 163 if (bitstream_start && components_size_start) 164 break; 165 166 block_id_offset += MPF_LOOKUP_TABLE_RECORD_SIZE; 167 block_start_offset += MPF_LOOKUP_TABLE_RECORD_SIZE; 168 } 169 170 if (!bitstream_start || !components_size_start) { 171 dev_err(&mgr->dev, "Failed to parse header look-up table\n"); 172 return -EFAULT; 173 } 174 175 /* 176 * Parse bitstream size. 177 * Sizes of components of the bitstream are 22-bits long placed next 178 * to each other. Image header should be extended by now up to where 179 * actual bitstream starts, so no need for overflow check anymore. 180 */ 181 components_num = get_unaligned_le16(buf + MPF_DATA_SIZE_OFFSET); 182 183 for (i = 0; i < components_num; i++) { 184 component_size_byte_num = 185 (i * MPF_BITS_PER_COMPONENT_SIZE) / BITS_PER_BYTE; 186 component_size_byte_off = 187 (i * MPF_BITS_PER_COMPONENT_SIZE) % BITS_PER_BYTE; 188 189 component_size = get_unaligned_le32(buf + 190 components_size_start + 191 component_size_byte_num); 192 component_size >>= component_size_byte_off; 193 component_size &= GENMASK(MPF_BITS_PER_COMPONENT_SIZE - 1, 0); 194 195 info->data_size += component_size * MPF_SPI_FRAME_SIZE; 196 } 197 198 return 0; 199 } 200 201 static int mpf_poll_status(struct mpf_priv *priv, u8 mask) 202 { 203 int ret, status; 204 205 /* 206 * Busy poll HW status. Polling stops if any of the following 207 * conditions are met: 208 * - timeout is reached 209 * - mpf_read_status() returns an error 210 * - busy bit is cleared AND mask bits are set 211 */ 212 ret = read_poll_timeout(mpf_read_status, status, 213 (status < 0) || 214 ((status & (MPF_STATUS_BUSY | mask)) == mask), 215 0, MPF_STATUS_POLL_TIMEOUT, false, priv); 216 if (ret < 0) 217 return ret; 218 219 return status; 220 } 221 222 static int mpf_spi_write(struct mpf_priv *priv, const void *buf, size_t buf_size) 223 { 224 int status = mpf_poll_status(priv, 0); 225 226 if (status < 0) 227 return status; 228 229 return spi_write_then_read(priv->spi, buf, buf_size, NULL, 0); 230 } 231 232 static int mpf_spi_write_then_read(struct mpf_priv *priv, 233 const void *txbuf, size_t txbuf_size, 234 void *rxbuf, size_t rxbuf_size) 235 { 236 const u8 read_command[] = { MPF_SPI_READ_DATA }; 237 int ret; 238 239 ret = mpf_spi_write(priv, txbuf, txbuf_size); 240 if (ret) 241 return ret; 242 243 ret = mpf_poll_status(priv, MPF_STATUS_READY); 244 if (ret < 0) 245 return ret; 246 247 return spi_write_then_read(priv->spi, read_command, sizeof(read_command), 248 rxbuf, rxbuf_size); 249 } 250 251 static int mpf_ops_write_init(struct fpga_manager *mgr, 252 struct fpga_image_info *info, const char *buf, 253 size_t count) 254 { 255 const u8 program_mode[] = { MPF_SPI_FRAME_INIT, MPF_SPI_PRG_MODE }; 256 const u8 isc_en_command[] = { MPF_SPI_ISC_ENABLE }; 257 struct mpf_priv *priv = mgr->priv; 258 struct device *dev = &mgr->dev; 259 u32 isc_ret = 0; 260 int ret; 261 262 if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { 263 dev_err(dev, "Partial reconfiguration is not supported\n"); 264 return -EOPNOTSUPP; 265 } 266 267 ret = mpf_spi_write_then_read(priv, isc_en_command, sizeof(isc_en_command), 268 &isc_ret, sizeof(isc_ret)); 269 if (ret || isc_ret) { 270 dev_err(dev, "Failed to enable ISC: spi_ret %d, isc_ret %u\n", 271 ret, isc_ret); 272 return -EFAULT; 273 } 274 275 ret = mpf_spi_write(priv, program_mode, sizeof(program_mode)); 276 if (ret) { 277 dev_err(dev, "Failed to enter program mode: %d\n", ret); 278 return ret; 279 } 280 281 priv->program_mode = true; 282 283 return 0; 284 } 285 286 static int mpf_spi_frame_write(struct mpf_priv *priv, const char *buf) 287 { 288 struct spi_transfer xfers[2] = { 289 { 290 .tx_buf = &priv->tx, 291 .len = 1, 292 }, { 293 .tx_buf = buf, 294 .len = MPF_SPI_FRAME_SIZE, 295 }, 296 }; 297 int ret; 298 299 ret = mpf_poll_status(priv, 0); 300 if (ret < 0) 301 return ret; 302 303 priv->tx = MPF_SPI_FRAME; 304 305 return spi_sync_transfer(priv->spi, xfers, ARRAY_SIZE(xfers)); 306 } 307 308 static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count) 309 { 310 struct mpf_priv *priv = mgr->priv; 311 struct device *dev = &mgr->dev; 312 int ret, i; 313 314 if (count % MPF_SPI_FRAME_SIZE) { 315 dev_err(dev, "Bitstream size is not a multiple of %d\n", 316 MPF_SPI_FRAME_SIZE); 317 return -EINVAL; 318 } 319 320 for (i = 0; i < count / MPF_SPI_FRAME_SIZE; i++) { 321 ret = mpf_spi_frame_write(priv, buf + i * MPF_SPI_FRAME_SIZE); 322 if (ret) { 323 dev_err(dev, "Failed to write bitstream frame %d/%zu\n", 324 i, count / MPF_SPI_FRAME_SIZE); 325 return ret; 326 } 327 } 328 329 return 0; 330 } 331 332 static int mpf_ops_write_complete(struct fpga_manager *mgr, 333 struct fpga_image_info *info) 334 { 335 const u8 isc_dis_command[] = { MPF_SPI_ISC_DISABLE }; 336 const u8 release_command[] = { MPF_SPI_RELEASE }; 337 struct mpf_priv *priv = mgr->priv; 338 struct device *dev = &mgr->dev; 339 int ret; 340 341 ret = mpf_spi_write(priv, isc_dis_command, sizeof(isc_dis_command)); 342 if (ret) { 343 dev_err(dev, "Failed to disable ISC: %d\n", ret); 344 return ret; 345 } 346 347 usleep_range(1000, 2000); 348 349 ret = mpf_spi_write(priv, release_command, sizeof(release_command)); 350 if (ret) { 351 dev_err(dev, "Failed to exit program mode: %d\n", ret); 352 return ret; 353 } 354 355 priv->program_mode = false; 356 357 return 0; 358 } 359 360 static const struct fpga_manager_ops mpf_ops = { 361 .state = mpf_ops_state, 362 .initial_header_size = 71, 363 .skip_header = true, 364 .parse_header = mpf_ops_parse_header, 365 .write_init = mpf_ops_write_init, 366 .write = mpf_ops_write, 367 .write_complete = mpf_ops_write_complete, 368 }; 369 370 static int mpf_probe(struct spi_device *spi) 371 { 372 struct device *dev = &spi->dev; 373 struct fpga_manager *mgr; 374 struct mpf_priv *priv; 375 376 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 377 if (!priv) 378 return -ENOMEM; 379 380 priv->spi = spi; 381 382 mgr = devm_fpga_mgr_register(dev, "Microchip Polarfire SPI FPGA Manager", 383 &mpf_ops, priv); 384 385 return PTR_ERR_OR_ZERO(mgr); 386 } 387 388 static const struct spi_device_id mpf_spi_ids[] = { 389 { .name = "mpf-spi-fpga-mgr", }, 390 {}, 391 }; 392 MODULE_DEVICE_TABLE(spi, mpf_spi_ids); 393 394 #if IS_ENABLED(CONFIG_OF) 395 static const struct of_device_id mpf_of_ids[] = { 396 { .compatible = "microchip,mpf-spi-fpga-mgr" }, 397 {}, 398 }; 399 MODULE_DEVICE_TABLE(of, mpf_of_ids); 400 #endif /* IS_ENABLED(CONFIG_OF) */ 401 402 static struct spi_driver mpf_driver = { 403 .probe = mpf_probe, 404 .id_table = mpf_spi_ids, 405 .driver = { 406 .name = "microchip_mpf_spi_fpga_mgr", 407 .of_match_table = of_match_ptr(mpf_of_ids), 408 }, 409 }; 410 411 module_spi_driver(mpf_driver); 412 413 MODULE_DESCRIPTION("Microchip Polarfire SPI FPGA Manager"); 414 MODULE_AUTHOR("Ivan Bornyakov <i.bornyakov@metrotek.ru>"); 415 MODULE_LICENSE("GPL"); 416