1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "core_types.h" 28 29 #include "ObjectID.h" 30 #include "atomfirmware.h" 31 32 #include "dc_bios_types.h" 33 #include "include/grph_object_ctrl_defs.h" 34 #include "include/bios_parser_interface.h" 35 #include "include/logger_interface.h" 36 37 #include "command_table2.h" 38 39 #include "bios_parser_helper.h" 40 #include "command_table_helper2.h" 41 #include "bios_parser2.h" 42 #include "bios_parser_types_internal2.h" 43 #include "bios_parser_interface.h" 44 45 #include "bios_parser_common.h" 46 47 #define DC_LOGGER \ 48 bp->base.ctx->logger 49 50 #define LAST_RECORD_TYPE 0xff 51 #define SMU9_SYSPLL0_ID 0 52 53 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, 54 struct atom_i2c_record *record, 55 struct graphics_object_i2c_info *info); 56 57 static enum bp_result bios_parser_get_firmware_info( 58 struct dc_bios *dcb, 59 struct dc_firmware_info *info); 60 61 static enum bp_result bios_parser_get_encoder_cap_info( 62 struct dc_bios *dcb, 63 struct graphics_object_id object_id, 64 struct bp_encoder_cap_info *info); 65 66 static enum bp_result get_firmware_info_v3_1( 67 struct bios_parser *bp, 68 struct dc_firmware_info *info); 69 70 static enum bp_result get_firmware_info_v3_2( 71 struct bios_parser *bp, 72 struct dc_firmware_info *info); 73 74 static enum bp_result get_firmware_info_v3_4( 75 struct bios_parser *bp, 76 struct dc_firmware_info *info); 77 78 static enum bp_result get_firmware_info_v3_5( 79 struct bios_parser *bp, 80 struct dc_firmware_info *info); 81 82 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, 83 struct atom_display_object_path_v2 *object); 84 85 static struct atom_encoder_caps_record *get_encoder_cap_record( 86 struct bios_parser *bp, 87 struct atom_display_object_path_v2 *object); 88 89 #define BIOS_IMAGE_SIZE_OFFSET 2 90 #define BIOS_IMAGE_SIZE_UNIT 512 91 92 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table) 93 94 static void bios_parser2_destruct(struct bios_parser *bp) 95 { 96 kfree(bp->base.bios_local_image); 97 kfree(bp->base.integrated_info); 98 } 99 100 static void firmware_parser_destroy(struct dc_bios **dcb) 101 { 102 struct bios_parser *bp = BP_FROM_DCB(*dcb); 103 104 if (!bp) { 105 BREAK_TO_DEBUGGER(); 106 return; 107 } 108 109 bios_parser2_destruct(bp); 110 111 kfree(bp); 112 *dcb = NULL; 113 } 114 115 static void get_atom_data_table_revision( 116 struct atom_common_table_header *atom_data_tbl, 117 struct atom_data_revision *tbl_revision) 118 { 119 if (!tbl_revision) 120 return; 121 122 /* initialize the revision to 0 which is invalid revision */ 123 tbl_revision->major = 0; 124 tbl_revision->minor = 0; 125 126 if (!atom_data_tbl) 127 return; 128 129 tbl_revision->major = 130 (uint32_t) atom_data_tbl->format_revision & 0x3f; 131 tbl_revision->minor = 132 (uint32_t) atom_data_tbl->content_revision & 0x3f; 133 } 134 135 /* BIOS oject table displaypath is per connector. 136 * There is extra path not for connector. BIOS fill its encoderid as 0 137 */ 138 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) 139 { 140 struct bios_parser *bp = BP_FROM_DCB(dcb); 141 unsigned int count = 0; 142 unsigned int i; 143 144 switch (bp->object_info_tbl.revision.minor) { 145 default: 146 case 4: 147 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) 148 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0) 149 count++; 150 151 break; 152 153 case 5: 154 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) 155 if (bp->object_info_tbl.v1_5->display_path[i].encoderobjid != 0) 156 count++; 157 158 break; 159 } 160 return count; 161 } 162 163 static struct graphics_object_id bios_parser_get_connector_id( 164 struct dc_bios *dcb, 165 uint8_t i) 166 { 167 struct bios_parser *bp = BP_FROM_DCB(dcb); 168 struct graphics_object_id object_id = dal_graphics_object_id_init( 169 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 170 struct object_info_table *tbl = &bp->object_info_tbl; 171 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4; 172 173 struct display_object_info_table_v1_5 *v1_5 = tbl->v1_5; 174 175 switch (bp->object_info_tbl.revision.minor) { 176 default: 177 case 4: 178 if (v1_4->number_of_path > i) { 179 /* If display_objid is generic object id, the encoderObj 180 * /extencoderobjId should be 0 181 */ 182 if (v1_4->display_path[i].encoderobjid != 0 && 183 v1_4->display_path[i].display_objid != 0) 184 object_id = object_id_from_bios_object_id( 185 v1_4->display_path[i].display_objid); 186 } 187 break; 188 189 case 5: 190 if (v1_5->number_of_path > i) { 191 /* If display_objid is generic object id, the encoderObjId 192 * should be 0 193 */ 194 if (v1_5->display_path[i].encoderobjid != 0 && 195 v1_5->display_path[i].display_objid != 0) 196 object_id = object_id_from_bios_object_id( 197 v1_5->display_path[i].display_objid); 198 } 199 break; 200 } 201 return object_id; 202 } 203 204 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, 205 struct graphics_object_id object_id, uint32_t index, 206 struct graphics_object_id *src_object_id) 207 { 208 (void)index; 209 struct bios_parser *bp = BP_FROM_DCB(dcb); 210 unsigned int i; 211 enum bp_result bp_result = BP_RESULT_BADINPUT; 212 struct graphics_object_id obj_id = { 0 }; 213 struct object_info_table *tbl = &bp->object_info_tbl; 214 215 if (!src_object_id) 216 return bp_result; 217 218 switch (object_id.type) { 219 /* Encoder's Source is GPU. BIOS does not provide GPU, since all 220 * displaypaths point to same GPU (0x1100). Hardcode GPU object type 221 */ 222 case OBJECT_TYPE_ENCODER: 223 /* TODO: since num of src must be less than 2. 224 * If found in for loop, should break. 225 * DAL2 implementation may be changed too 226 */ 227 switch (bp->object_info_tbl.revision.minor) { 228 default: 229 case 4: 230 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 231 obj_id = object_id_from_bios_object_id( 232 tbl->v1_4->display_path[i].encoderobjid); 233 if (object_id.type == obj_id.type && 234 object_id.id == obj_id.id && 235 object_id.enum_id == obj_id.enum_id) { 236 *src_object_id = 237 object_id_from_bios_object_id( 238 0x1100); 239 /* break; */ 240 } 241 } 242 bp_result = BP_RESULT_OK; 243 break; 244 245 case 5: 246 for (i = 0; i < tbl->v1_5->number_of_path; i++) { 247 obj_id = object_id_from_bios_object_id( 248 tbl->v1_5->display_path[i].encoderobjid); 249 if (object_id.type == obj_id.type && 250 object_id.id == obj_id.id && 251 object_id.enum_id == obj_id.enum_id) { 252 *src_object_id = 253 object_id_from_bios_object_id( 254 0x1100); 255 /* break; */ 256 } 257 } 258 bp_result = BP_RESULT_OK; 259 break; 260 } 261 break; 262 case OBJECT_TYPE_CONNECTOR: 263 switch (bp->object_info_tbl.revision.minor) { 264 default: 265 case 4: 266 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 267 obj_id = object_id_from_bios_object_id( 268 tbl->v1_4->display_path[i] 269 .display_objid); 270 271 if (object_id.type == obj_id.type && 272 object_id.id == obj_id.id && 273 object_id.enum_id == obj_id.enum_id) { 274 *src_object_id = 275 object_id_from_bios_object_id( 276 tbl->v1_4 277 ->display_path[i] 278 .encoderobjid); 279 /* break; */ 280 } 281 } 282 bp_result = BP_RESULT_OK; 283 break; 284 } 285 bp_result = BP_RESULT_OK; 286 break; 287 case 5: 288 for (i = 0; i < tbl->v1_5->number_of_path; i++) { 289 obj_id = object_id_from_bios_object_id( 290 tbl->v1_5->display_path[i].display_objid); 291 292 if (object_id.type == obj_id.type && 293 object_id.id == obj_id.id && 294 object_id.enum_id == obj_id.enum_id) { 295 *src_object_id = object_id_from_bios_object_id( 296 tbl->v1_5->display_path[i].encoderobjid); 297 /* break; */ 298 } 299 } 300 bp_result = BP_RESULT_OK; 301 break; 302 303 default: 304 bp_result = BP_RESULT_OK; 305 break; 306 } 307 308 return bp_result; 309 } 310 311 /* from graphics_object_id, find display path which includes the object_id */ 312 static struct atom_display_object_path_v2 *get_bios_object( 313 struct bios_parser *bp, 314 struct graphics_object_id id) 315 { 316 unsigned int i; 317 struct graphics_object_id obj_id = {0}; 318 319 switch (id.type) { 320 case OBJECT_TYPE_ENCODER: 321 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 322 obj_id = object_id_from_bios_object_id( 323 bp->object_info_tbl.v1_4->display_path[i].encoderobjid); 324 if (id.type == obj_id.type && id.id == obj_id.id 325 && id.enum_id == obj_id.enum_id) 326 return &bp->object_info_tbl.v1_4->display_path[i]; 327 } 328 fallthrough; 329 case OBJECT_TYPE_CONNECTOR: 330 case OBJECT_TYPE_GENERIC: 331 /* Both Generic and Connector Object ID 332 * will be stored on display_objid 333 */ 334 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 335 obj_id = object_id_from_bios_object_id( 336 bp->object_info_tbl.v1_4->display_path[i].display_objid); 337 if (id.type == obj_id.type && id.id == obj_id.id 338 && id.enum_id == obj_id.enum_id) 339 return &bp->object_info_tbl.v1_4->display_path[i]; 340 } 341 fallthrough; 342 default: 343 return NULL; 344 } 345 } 346 347 /* from graphics_object_id, find display path which includes the object_id */ 348 static struct atom_display_object_path_v3 *get_bios_object_from_path_v3(struct bios_parser *bp, 349 struct graphics_object_id id) 350 { 351 unsigned int i; 352 struct graphics_object_id obj_id = {0}; 353 354 switch (id.type) { 355 case OBJECT_TYPE_ENCODER: 356 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) { 357 obj_id = object_id_from_bios_object_id( 358 bp->object_info_tbl.v1_5->display_path[i].encoderobjid); 359 if (id.type == obj_id.type && id.id == obj_id.id 360 && id.enum_id == obj_id.enum_id) 361 return &bp->object_info_tbl.v1_5->display_path[i]; 362 } 363 break; 364 365 case OBJECT_TYPE_CONNECTOR: 366 case OBJECT_TYPE_GENERIC: 367 /* Both Generic and Connector Object ID 368 * will be stored on display_objid 369 */ 370 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) { 371 obj_id = object_id_from_bios_object_id( 372 bp->object_info_tbl.v1_5->display_path[i].display_objid); 373 if (id.type == obj_id.type && id.id == obj_id.id 374 && id.enum_id == obj_id.enum_id) 375 return &bp->object_info_tbl.v1_5->display_path[i]; 376 } 377 break; 378 379 default: 380 return NULL; 381 } 382 383 return NULL; 384 } 385 386 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, 387 struct graphics_object_id id, 388 struct graphics_object_i2c_info *info) 389 { 390 uint32_t offset; 391 struct atom_display_object_path_v2 *object; 392 393 struct atom_display_object_path_v3 *object_path_v3; 394 395 struct atom_common_record_header *header; 396 struct atom_i2c_record *record; 397 struct atom_i2c_record dummy_record = {0}; 398 struct bios_parser *bp = BP_FROM_DCB(dcb); 399 400 if (!info) 401 return BP_RESULT_BADINPUT; 402 403 if (id.type == OBJECT_TYPE_GENERIC) { 404 dummy_record.i2c_id = id.id; 405 406 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK) 407 return BP_RESULT_OK; 408 else 409 return BP_RESULT_NORECORD; 410 } 411 412 switch (bp->object_info_tbl.revision.minor) { 413 case 4: 414 default: 415 object = get_bios_object(bp, id); 416 417 if (!object) 418 return BP_RESULT_BADINPUT; 419 420 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 421 break; 422 case 5: 423 object_path_v3 = get_bios_object_from_path_v3(bp, id); 424 425 if (!object_path_v3) 426 return BP_RESULT_BADINPUT; 427 428 offset = object_path_v3->disp_recordoffset + bp->object_info_tbl_offset; 429 break; 430 } 431 432 for (;;) { 433 header = GET_IMAGE(struct atom_common_record_header, offset); 434 435 if (!header) 436 return BP_RESULT_BADBIOSTABLE; 437 438 if (header->record_type == LAST_RECORD_TYPE || 439 !header->record_size) 440 break; 441 442 if (header->record_type == ATOM_I2C_RECORD_TYPE 443 && sizeof(struct atom_i2c_record) <= 444 header->record_size) { 445 /* get the I2C info */ 446 record = (struct atom_i2c_record *) header; 447 448 if (get_gpio_i2c_info(bp, record, info) == 449 BP_RESULT_OK) 450 return BP_RESULT_OK; 451 } 452 453 offset += header->record_size; 454 } 455 456 return BP_RESULT_NORECORD; 457 } 458 459 static enum bp_result get_gpio_i2c_info( 460 struct bios_parser *bp, 461 struct atom_i2c_record *record, 462 struct graphics_object_i2c_info *info) 463 { 464 struct atom_gpio_pin_lut_v2_1 *header; 465 uint32_t count = 0; 466 unsigned int table_index = 0; 467 bool find_valid = false; 468 struct atom_gpio_pin_assignment *pin; 469 470 if (!info) 471 return BP_RESULT_BADINPUT; 472 473 /* get the GPIO_I2C info */ 474 if (!DATA_TABLES(gpio_pin_lut)) 475 return BP_RESULT_BADBIOSTABLE; 476 477 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 478 DATA_TABLES(gpio_pin_lut)); 479 if (!header) 480 return BP_RESULT_BADBIOSTABLE; 481 482 if (sizeof(struct atom_common_table_header) + 483 sizeof(struct atom_gpio_pin_assignment) > 484 le16_to_cpu(header->table_header.structuresize)) 485 return BP_RESULT_BADBIOSTABLE; 486 487 /* TODO: is version change? */ 488 if (header->table_header.content_revision != 1) 489 return BP_RESULT_UNSUPPORTED; 490 491 /* get data count */ 492 count = (le16_to_cpu(header->table_header.structuresize) 493 - sizeof(struct atom_common_table_header)) 494 / sizeof(struct atom_gpio_pin_assignment); 495 496 pin = (struct atom_gpio_pin_assignment *) header->gpio_pin; 497 498 for (table_index = 0; table_index < count; table_index++) { 499 if (((record->i2c_id & I2C_HW_CAP) == (pin->gpio_id & I2C_HW_CAP)) && 500 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == (pin->gpio_id & I2C_HW_ENGINE_ID_MASK)) && 501 ((record->i2c_id & I2C_HW_LANE_MUX) == (pin->gpio_id & I2C_HW_LANE_MUX))) { 502 /* still valid */ 503 find_valid = true; 504 break; 505 } 506 pin = (struct atom_gpio_pin_assignment *)((uint8_t *)pin + sizeof(struct atom_gpio_pin_assignment)); 507 } 508 509 /* If we don't find the entry that we are looking for then 510 * we will return BP_Result_BadBiosTable. 511 */ 512 if (find_valid == false) 513 return BP_RESULT_BADBIOSTABLE; 514 515 /* get the GPIO_I2C_INFO */ 516 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false; 517 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX; 518 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4; 519 info->i2c_slave_address = record->i2c_slave_addr; 520 521 /* TODO: check how to get register offset for en, Y, etc. */ 522 info->gpio_info.clk_a_register_index = le16_to_cpu(pin->data_a_reg_index); 523 info->gpio_info.clk_a_shift = pin->gpio_bitshift; 524 525 return BP_RESULT_OK; 526 } 527 528 static struct atom_hpd_int_record *get_hpd_record_for_path_v3(struct bios_parser *bp, 529 struct atom_display_object_path_v3 *object) 530 { 531 struct atom_common_record_header *header; 532 uint32_t offset; 533 534 if (!object) { 535 BREAK_TO_DEBUGGER(); /* Invalid object */ 536 return NULL; 537 } 538 539 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 540 541 for (;;) { 542 header = GET_IMAGE(struct atom_common_record_header, offset); 543 544 if (!header) 545 return NULL; 546 547 if (header->record_type == ATOM_RECORD_END_TYPE || 548 !header->record_size) 549 break; 550 551 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 552 && sizeof(struct atom_hpd_int_record) <= 553 header->record_size) 554 return (struct atom_hpd_int_record *) header; 555 556 offset += header->record_size; 557 } 558 559 return NULL; 560 } 561 562 static enum bp_result bios_parser_get_hpd_info( 563 struct dc_bios *dcb, 564 struct graphics_object_id id, 565 struct graphics_object_hpd_info *info) 566 { 567 struct bios_parser *bp = BP_FROM_DCB(dcb); 568 struct atom_display_object_path_v2 *object; 569 struct atom_display_object_path_v3 *object_path_v3; 570 struct atom_hpd_int_record *record = NULL; 571 572 if (!info) 573 return BP_RESULT_BADINPUT; 574 575 switch (bp->object_info_tbl.revision.minor) { 576 case 4: 577 default: 578 object = get_bios_object(bp, id); 579 580 if (!object) 581 return BP_RESULT_BADINPUT; 582 583 record = get_hpd_record(bp, object); 584 break; 585 case 5: 586 object_path_v3 = get_bios_object_from_path_v3(bp, id); 587 588 if (!object_path_v3) 589 return BP_RESULT_BADINPUT; 590 591 record = get_hpd_record_for_path_v3(bp, object_path_v3); 592 break; 593 } 594 595 if (record != NULL) { 596 info->hpd_int_gpio_uid = record->pin_id; 597 info->hpd_active = record->plugin_pin_state; 598 return BP_RESULT_OK; 599 } 600 601 return BP_RESULT_NORECORD; 602 } 603 604 static struct atom_hpd_int_record *get_hpd_record( 605 struct bios_parser *bp, 606 struct atom_display_object_path_v2 *object) 607 { 608 struct atom_common_record_header *header; 609 uint32_t offset; 610 611 if (!object) { 612 BREAK_TO_DEBUGGER(); /* Invalid object */ 613 return NULL; 614 } 615 616 offset = le16_to_cpu(object->disp_recordoffset) 617 + bp->object_info_tbl_offset; 618 619 for (;;) { 620 header = GET_IMAGE(struct atom_common_record_header, offset); 621 622 if (!header) 623 return NULL; 624 625 if (header->record_type == LAST_RECORD_TYPE || 626 !header->record_size) 627 break; 628 629 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 630 && sizeof(struct atom_hpd_int_record) <= 631 header->record_size) 632 return (struct atom_hpd_int_record *) header; 633 634 offset += header->record_size; 635 } 636 637 return NULL; 638 } 639 640 /** 641 * bios_parser_get_gpio_pin_info 642 * Get GpioPin information of input gpio id 643 * 644 * @dcb: pointer to the DC BIOS 645 * @gpio_id: GPIO ID 646 * @info: GpioPin information structure 647 * return: Bios parser result code 648 * note: 649 * to get the GPIO PIN INFO, we need: 650 * 1. get the GPIO_ID from other object table, see GetHPDInfo() 651 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, 652 * to get the registerA offset/mask 653 */ 654 static enum bp_result bios_parser_get_gpio_pin_info( 655 struct dc_bios *dcb, 656 uint32_t gpio_id, 657 struct gpio_pin_info *info) 658 { 659 struct bios_parser *bp = BP_FROM_DCB(dcb); 660 struct atom_gpio_pin_lut_v2_1 *header; 661 uint32_t count = 0; 662 uint32_t i = 0; 663 664 if (!DATA_TABLES(gpio_pin_lut)) 665 return BP_RESULT_BADBIOSTABLE; 666 667 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 668 DATA_TABLES(gpio_pin_lut)); 669 if (!header) 670 return BP_RESULT_BADBIOSTABLE; 671 672 if (sizeof(struct atom_common_table_header) + 673 sizeof(struct atom_gpio_pin_assignment) 674 > le16_to_cpu(header->table_header.structuresize)) 675 return BP_RESULT_BADBIOSTABLE; 676 677 if (header->table_header.content_revision != 1) 678 return BP_RESULT_UNSUPPORTED; 679 680 /* Temporary hard code gpio pin info */ 681 count = (le16_to_cpu(header->table_header.structuresize) 682 - sizeof(struct atom_common_table_header)) 683 / sizeof(struct atom_gpio_pin_assignment); 684 for (i = 0; i < count; ++i) { 685 if (header->gpio_pin[i].gpio_id != gpio_id) 686 continue; 687 688 info->offset = 689 (uint32_t) le16_to_cpu( 690 header->gpio_pin[i].data_a_reg_index); 691 info->offset_y = info->offset + 2; 692 info->offset_en = info->offset + 1; 693 info->offset_mask = info->offset - 1; 694 695 info->mask = (uint32_t) (1 << 696 header->gpio_pin[i].gpio_bitshift); 697 info->mask_y = info->mask + 2; 698 info->mask_en = info->mask + 1; 699 info->mask_mask = info->mask - 1; 700 701 return BP_RESULT_OK; 702 } 703 704 return BP_RESULT_NORECORD; 705 } 706 707 static struct device_id device_type_from_device_id(uint16_t device_id) 708 { 709 710 struct device_id result_device_id; 711 712 result_device_id.raw_device_tag = device_id; 713 714 switch (device_id) { 715 case ATOM_DISPLAY_LCD1_SUPPORT: 716 result_device_id.device_type = DEVICE_TYPE_LCD; 717 result_device_id.enum_id = 1; 718 break; 719 720 case ATOM_DISPLAY_LCD2_SUPPORT: 721 result_device_id.device_type = DEVICE_TYPE_LCD; 722 result_device_id.enum_id = 2; 723 break; 724 725 case ATOM_DISPLAY_DFP1_SUPPORT: 726 result_device_id.device_type = DEVICE_TYPE_DFP; 727 result_device_id.enum_id = 1; 728 break; 729 730 case ATOM_DISPLAY_DFP2_SUPPORT: 731 result_device_id.device_type = DEVICE_TYPE_DFP; 732 result_device_id.enum_id = 2; 733 break; 734 735 case ATOM_DISPLAY_DFP3_SUPPORT: 736 result_device_id.device_type = DEVICE_TYPE_DFP; 737 result_device_id.enum_id = 3; 738 break; 739 740 case ATOM_DISPLAY_DFP4_SUPPORT: 741 result_device_id.device_type = DEVICE_TYPE_DFP; 742 result_device_id.enum_id = 4; 743 break; 744 745 case ATOM_DISPLAY_DFP5_SUPPORT: 746 result_device_id.device_type = DEVICE_TYPE_DFP; 747 result_device_id.enum_id = 5; 748 break; 749 750 case ATOM_DISPLAY_DFP6_SUPPORT: 751 result_device_id.device_type = DEVICE_TYPE_DFP; 752 result_device_id.enum_id = 6; 753 break; 754 755 default: 756 BREAK_TO_DEBUGGER(); /* Invalid device Id */ 757 result_device_id.device_type = DEVICE_TYPE_UNKNOWN; 758 result_device_id.enum_id = 0; 759 } 760 return result_device_id; 761 } 762 763 static enum bp_result bios_parser_get_device_tag( 764 struct dc_bios *dcb, 765 struct graphics_object_id connector_object_id, 766 uint32_t device_tag_index, 767 struct connector_device_tag_info *info) 768 { 769 (void)device_tag_index; 770 struct bios_parser *bp = BP_FROM_DCB(dcb); 771 struct atom_display_object_path_v2 *object; 772 773 struct atom_display_object_path_v3 *object_path_v3; 774 775 776 if (!info) 777 return BP_RESULT_BADINPUT; 778 779 switch (bp->object_info_tbl.revision.minor) { 780 case 4: 781 default: 782 /* getBiosObject will return MXM object */ 783 object = get_bios_object(bp, connector_object_id); 784 785 if (!object) { 786 BREAK_TO_DEBUGGER(); /* Invalid object id */ 787 return BP_RESULT_BADINPUT; 788 } 789 790 info->acpi_device = 0; /* BIOS no longer provides this */ 791 info->dev_id = device_type_from_device_id(object->device_tag); 792 break; 793 case 5: 794 object_path_v3 = get_bios_object_from_path_v3(bp, connector_object_id); 795 796 if (!object_path_v3) { 797 BREAK_TO_DEBUGGER(); /* Invalid object id */ 798 return BP_RESULT_BADINPUT; 799 } 800 info->acpi_device = 0; /* BIOS no longer provides this */ 801 info->dev_id = device_type_from_device_id(object_path_v3->device_tag); 802 break; 803 } 804 805 return BP_RESULT_OK; 806 } 807 808 static enum bp_result get_ss_info_v4_1( 809 struct bios_parser *bp, 810 uint32_t id, 811 uint32_t index, 812 struct spread_spectrum_info *ss_info) 813 { 814 (void)index; 815 enum bp_result result = BP_RESULT_OK; 816 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 817 struct atom_smu_info_v3_3 *smu_info = NULL; 818 819 if (!ss_info) 820 return BP_RESULT_BADINPUT; 821 822 if (!DATA_TABLES(dce_info)) 823 return BP_RESULT_BADBIOSTABLE; 824 825 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 826 DATA_TABLES(dce_info)); 827 if (!disp_cntl_tbl) 828 return BP_RESULT_BADBIOSTABLE; 829 830 831 ss_info->type.STEP_AND_DELAY_INFO = false; 832 ss_info->spread_percentage_divider = 1000; 833 /* BIOS no longer uses target clock. Always enable for now */ 834 ss_info->target_clock_range = 0xffffffff; 835 836 switch (id) { 837 case AS_SIGNAL_TYPE_DVI: 838 ss_info->spread_spectrum_percentage = 839 disp_cntl_tbl->dvi_ss_percentage; 840 ss_info->spread_spectrum_range = 841 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 842 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 843 ss_info->type.CENTER_MODE = true; 844 845 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 846 break; 847 case AS_SIGNAL_TYPE_HDMI: 848 ss_info->spread_spectrum_percentage = 849 disp_cntl_tbl->hdmi_ss_percentage; 850 ss_info->spread_spectrum_range = 851 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 852 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 853 ss_info->type.CENTER_MODE = true; 854 855 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 856 break; 857 /* TODO LVDS not support anymore? */ 858 case AS_SIGNAL_TYPE_DISPLAY_PORT: 859 ss_info->spread_spectrum_percentage = 860 disp_cntl_tbl->dp_ss_percentage; 861 ss_info->spread_spectrum_range = 862 disp_cntl_tbl->dp_ss_rate_10hz * 10; 863 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 864 ss_info->type.CENTER_MODE = true; 865 866 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 867 break; 868 case AS_SIGNAL_TYPE_GPU_PLL: 869 /* atom_firmware: DAL only get data from dce_info table. 870 * if data within smu_info is needed for DAL, VBIOS should 871 * copy it into dce_info 872 */ 873 result = BP_RESULT_UNSUPPORTED; 874 break; 875 case AS_SIGNAL_TYPE_XGMI: 876 smu_info = GET_IMAGE(struct atom_smu_info_v3_3, 877 DATA_TABLES(smu_info)); 878 if (!smu_info) 879 return BP_RESULT_BADBIOSTABLE; 880 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage); 881 ss_info->spread_spectrum_percentage = 882 smu_info->waflclk_ss_percentage; 883 ss_info->spread_spectrum_range = 884 smu_info->gpuclk_ss_rate_10hz * 10; 885 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 886 ss_info->type.CENTER_MODE = true; 887 888 DC_LOG_BIOS("AS_SIGNAL_TYPE_XGMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 889 break; 890 default: 891 result = BP_RESULT_UNSUPPORTED; 892 } 893 894 return result; 895 } 896 897 static enum bp_result get_ss_info_v4_2( 898 struct bios_parser *bp, 899 uint32_t id, 900 uint32_t index, 901 struct spread_spectrum_info *ss_info) 902 { 903 (void)index; 904 enum bp_result result = BP_RESULT_OK; 905 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 906 struct atom_smu_info_v3_1 *smu_info = NULL; 907 908 if (!ss_info) 909 return BP_RESULT_BADINPUT; 910 911 if (!DATA_TABLES(dce_info)) 912 return BP_RESULT_BADBIOSTABLE; 913 914 if (!DATA_TABLES(smu_info)) 915 return BP_RESULT_BADBIOSTABLE; 916 917 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 918 DATA_TABLES(dce_info)); 919 if (!disp_cntl_tbl) 920 return BP_RESULT_BADBIOSTABLE; 921 922 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info)); 923 if (!smu_info) 924 return BP_RESULT_BADBIOSTABLE; 925 926 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage); 927 ss_info->type.STEP_AND_DELAY_INFO = false; 928 ss_info->spread_percentage_divider = 1000; 929 /* BIOS no longer uses target clock. Always enable for now */ 930 ss_info->target_clock_range = 0xffffffff; 931 932 switch (id) { 933 case AS_SIGNAL_TYPE_DVI: 934 ss_info->spread_spectrum_percentage = 935 disp_cntl_tbl->dvi_ss_percentage; 936 ss_info->spread_spectrum_range = 937 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 938 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 939 ss_info->type.CENTER_MODE = true; 940 941 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 942 break; 943 case AS_SIGNAL_TYPE_HDMI: 944 ss_info->spread_spectrum_percentage = 945 disp_cntl_tbl->hdmi_ss_percentage; 946 ss_info->spread_spectrum_range = 947 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 948 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 949 ss_info->type.CENTER_MODE = true; 950 951 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 952 break; 953 /* TODO LVDS not support anymore? */ 954 case AS_SIGNAL_TYPE_DISPLAY_PORT: 955 ss_info->spread_spectrum_percentage = 956 smu_info->gpuclk_ss_percentage; 957 ss_info->spread_spectrum_range = 958 smu_info->gpuclk_ss_rate_10hz * 10; 959 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 960 ss_info->type.CENTER_MODE = true; 961 962 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 963 break; 964 case AS_SIGNAL_TYPE_GPU_PLL: 965 /* atom_firmware: DAL only get data from dce_info table. 966 * if data within smu_info is needed for DAL, VBIOS should 967 * copy it into dce_info 968 */ 969 result = BP_RESULT_UNSUPPORTED; 970 break; 971 default: 972 result = BP_RESULT_UNSUPPORTED; 973 } 974 975 return result; 976 } 977 978 static enum bp_result get_ss_info_v4_5( 979 struct bios_parser *bp, 980 uint32_t id, 981 uint32_t index, 982 struct spread_spectrum_info *ss_info) 983 { 984 (void)index; 985 enum bp_result result = BP_RESULT_OK; 986 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 987 988 if (!ss_info) 989 return BP_RESULT_BADINPUT; 990 991 if (!DATA_TABLES(dce_info)) 992 return BP_RESULT_BADBIOSTABLE; 993 994 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 995 DATA_TABLES(dce_info)); 996 if (!disp_cntl_tbl) 997 return BP_RESULT_BADBIOSTABLE; 998 999 ss_info->type.STEP_AND_DELAY_INFO = false; 1000 ss_info->spread_percentage_divider = 1000; 1001 /* BIOS no longer uses target clock. Always enable for now */ 1002 ss_info->target_clock_range = 0xffffffff; 1003 1004 switch (id) { 1005 case AS_SIGNAL_TYPE_DVI: 1006 ss_info->spread_spectrum_percentage = 1007 disp_cntl_tbl->dvi_ss_percentage; 1008 ss_info->spread_spectrum_range = 1009 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 1010 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1011 ss_info->type.CENTER_MODE = true; 1012 1013 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 1014 break; 1015 case AS_SIGNAL_TYPE_HDMI: 1016 ss_info->spread_spectrum_percentage = 1017 disp_cntl_tbl->hdmi_ss_percentage; 1018 ss_info->spread_spectrum_range = 1019 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 1020 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1021 ss_info->type.CENTER_MODE = true; 1022 1023 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 1024 break; 1025 case AS_SIGNAL_TYPE_DISPLAY_PORT: 1026 if (bp->base.integrated_info) { 1027 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", bp->base.integrated_info->gpuclk_ss_percentage); 1028 ss_info->spread_spectrum_percentage = 1029 bp->base.integrated_info->gpuclk_ss_percentage; 1030 ss_info->type.CENTER_MODE = 1031 bp->base.integrated_info->gpuclk_ss_type; 1032 } else { 1033 ss_info->spread_spectrum_percentage = 1034 disp_cntl_tbl->dp_ss_percentage; 1035 ss_info->spread_spectrum_range = 1036 disp_cntl_tbl->dp_ss_rate_10hz * 10; 1037 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1038 ss_info->type.CENTER_MODE = true; 1039 } 1040 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 1041 break; 1042 case AS_SIGNAL_TYPE_GPU_PLL: 1043 /* atom_smu_info_v4_0 does not have fields for SS for SMU Display PLL anymore. 1044 * SMU Display PLL supposed to be without spread. 1045 * Better place for it would be in atom_display_controller_info_v4_5 table. 1046 */ 1047 result = BP_RESULT_UNSUPPORTED; 1048 break; 1049 default: 1050 result = BP_RESULT_UNSUPPORTED; 1051 break; 1052 } 1053 1054 return result; 1055 } 1056 1057 /** 1058 * bios_parser_get_spread_spectrum_info 1059 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or 1060 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info 1061 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info 1062 * ver 3.1, 1063 * there is only one entry for each signal /ss id. However, there is 1064 * no planning of supporting multiple spread Sprectum entry for EverGreen 1065 * @dcb: pointer to the DC BIOS 1066 * @signal: ASSignalType to be converted to info index 1067 * @index: number of entries that match the converted info index 1068 * @ss_info: sprectrum information structure, 1069 * return: Bios parser result code 1070 */ 1071 static enum bp_result bios_parser_get_spread_spectrum_info( 1072 struct dc_bios *dcb, 1073 enum as_signal_type signal, 1074 uint32_t index, 1075 struct spread_spectrum_info *ss_info) 1076 { 1077 struct bios_parser *bp = BP_FROM_DCB(dcb); 1078 enum bp_result result = BP_RESULT_UNSUPPORTED; 1079 struct atom_common_table_header *header; 1080 struct atom_data_revision tbl_revision; 1081 1082 if (!ss_info) /* check for bad input */ 1083 return BP_RESULT_BADINPUT; 1084 1085 if (!DATA_TABLES(dce_info)) 1086 return BP_RESULT_UNSUPPORTED; 1087 1088 header = GET_IMAGE(struct atom_common_table_header, 1089 DATA_TABLES(dce_info)); 1090 get_atom_data_table_revision(header, &tbl_revision); 1091 1092 switch (tbl_revision.major) { 1093 case 4: 1094 switch (tbl_revision.minor) { 1095 case 1: 1096 return get_ss_info_v4_1(bp, signal, index, ss_info); 1097 case 2: 1098 case 3: 1099 case 4: 1100 return get_ss_info_v4_2(bp, signal, index, ss_info); 1101 case 5: 1102 return get_ss_info_v4_5(bp, signal, index, ss_info); 1103 1104 default: 1105 ASSERT(0); 1106 break; 1107 } 1108 break; 1109 default: 1110 break; 1111 } 1112 /* there can not be more then one entry for SS Info table */ 1113 return result; 1114 } 1115 1116 static enum bp_result get_soc_bb_info_v4_4( 1117 struct bios_parser *bp, 1118 struct bp_soc_bb_info *soc_bb_info) 1119 { 1120 enum bp_result result = BP_RESULT_OK; 1121 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 1122 1123 if (!soc_bb_info) 1124 return BP_RESULT_BADINPUT; 1125 1126 if (!DATA_TABLES(dce_info)) 1127 return BP_RESULT_BADBIOSTABLE; 1128 1129 if (!DATA_TABLES(smu_info)) 1130 return BP_RESULT_BADBIOSTABLE; 1131 1132 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 1133 DATA_TABLES(dce_info)); 1134 if (!disp_cntl_tbl) 1135 return BP_RESULT_BADBIOSTABLE; 1136 1137 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 1138 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 1139 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 1140 1141 return result; 1142 } 1143 1144 static enum bp_result get_soc_bb_info_v4_5( 1145 struct bios_parser *bp, 1146 struct bp_soc_bb_info *soc_bb_info) 1147 { 1148 enum bp_result result = BP_RESULT_OK; 1149 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 1150 1151 if (!soc_bb_info) 1152 return BP_RESULT_BADINPUT; 1153 1154 if (!DATA_TABLES(dce_info)) 1155 return BP_RESULT_BADBIOSTABLE; 1156 1157 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 1158 DATA_TABLES(dce_info)); 1159 if (!disp_cntl_tbl) 1160 return BP_RESULT_BADBIOSTABLE; 1161 1162 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 1163 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 1164 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 1165 1166 return result; 1167 } 1168 1169 static enum bp_result bios_parser_get_soc_bb_info( 1170 struct dc_bios *dcb, 1171 struct bp_soc_bb_info *soc_bb_info) 1172 { 1173 struct bios_parser *bp = BP_FROM_DCB(dcb); 1174 enum bp_result result = BP_RESULT_UNSUPPORTED; 1175 struct atom_common_table_header *header; 1176 struct atom_data_revision tbl_revision; 1177 1178 if (!soc_bb_info) /* check for bad input */ 1179 return BP_RESULT_BADINPUT; 1180 1181 if (!DATA_TABLES(dce_info)) 1182 return BP_RESULT_UNSUPPORTED; 1183 1184 header = GET_IMAGE(struct atom_common_table_header, 1185 DATA_TABLES(dce_info)); 1186 get_atom_data_table_revision(header, &tbl_revision); 1187 1188 switch (tbl_revision.major) { 1189 case 4: 1190 switch (tbl_revision.minor) { 1191 case 1: 1192 case 2: 1193 case 3: 1194 break; 1195 case 4: 1196 result = get_soc_bb_info_v4_4(bp, soc_bb_info); 1197 break; 1198 case 5: 1199 result = get_soc_bb_info_v4_5(bp, soc_bb_info); 1200 break; 1201 default: 1202 break; 1203 } 1204 break; 1205 default: 1206 break; 1207 } 1208 1209 return result; 1210 } 1211 1212 static enum bp_result get_disp_caps_v4_1( 1213 struct bios_parser *bp, 1214 uint8_t *dce_caps) 1215 { 1216 enum bp_result result = BP_RESULT_OK; 1217 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 1218 1219 if (!dce_caps) 1220 return BP_RESULT_BADINPUT; 1221 1222 if (!DATA_TABLES(dce_info)) 1223 return BP_RESULT_BADBIOSTABLE; 1224 1225 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 1226 DATA_TABLES(dce_info)); 1227 1228 if (!disp_cntl_tbl) 1229 return BP_RESULT_BADBIOSTABLE; 1230 1231 *dce_caps = disp_cntl_tbl->display_caps; 1232 1233 return result; 1234 } 1235 1236 static enum bp_result get_disp_caps_v4_2( 1237 struct bios_parser *bp, 1238 uint8_t *dce_caps) 1239 { 1240 enum bp_result result = BP_RESULT_OK; 1241 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 1242 1243 if (!dce_caps) 1244 return BP_RESULT_BADINPUT; 1245 1246 if (!DATA_TABLES(dce_info)) 1247 return BP_RESULT_BADBIOSTABLE; 1248 1249 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 1250 DATA_TABLES(dce_info)); 1251 1252 if (!disp_cntl_tbl) 1253 return BP_RESULT_BADBIOSTABLE; 1254 1255 *dce_caps = disp_cntl_tbl->display_caps; 1256 1257 return result; 1258 } 1259 1260 static enum bp_result get_disp_caps_v4_3( 1261 struct bios_parser *bp, 1262 uint8_t *dce_caps) 1263 { 1264 enum bp_result result = BP_RESULT_OK; 1265 struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL; 1266 1267 if (!dce_caps) 1268 return BP_RESULT_BADINPUT; 1269 1270 if (!DATA_TABLES(dce_info)) 1271 return BP_RESULT_BADBIOSTABLE; 1272 1273 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3, 1274 DATA_TABLES(dce_info)); 1275 1276 if (!disp_cntl_tbl) 1277 return BP_RESULT_BADBIOSTABLE; 1278 1279 *dce_caps = disp_cntl_tbl->display_caps; 1280 1281 return result; 1282 } 1283 1284 static enum bp_result get_disp_caps_v4_4( 1285 struct bios_parser *bp, 1286 uint8_t *dce_caps) 1287 { 1288 enum bp_result result = BP_RESULT_OK; 1289 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 1290 1291 if (!dce_caps) 1292 return BP_RESULT_BADINPUT; 1293 1294 if (!DATA_TABLES(dce_info)) 1295 return BP_RESULT_BADBIOSTABLE; 1296 1297 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 1298 DATA_TABLES(dce_info)); 1299 1300 if (!disp_cntl_tbl) 1301 return BP_RESULT_BADBIOSTABLE; 1302 1303 *dce_caps = disp_cntl_tbl->display_caps; 1304 1305 return result; 1306 } 1307 1308 static enum bp_result get_disp_caps_v4_5( 1309 struct bios_parser *bp, 1310 uint8_t *dce_caps) 1311 { 1312 enum bp_result result = BP_RESULT_OK; 1313 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 1314 1315 if (!dce_caps) 1316 return BP_RESULT_BADINPUT; 1317 1318 if (!DATA_TABLES(dce_info)) 1319 return BP_RESULT_BADBIOSTABLE; 1320 1321 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 1322 DATA_TABLES(dce_info)); 1323 1324 if (!disp_cntl_tbl) 1325 return BP_RESULT_BADBIOSTABLE; 1326 1327 *dce_caps = disp_cntl_tbl->display_caps; 1328 1329 return result; 1330 } 1331 1332 static enum bp_result bios_parser_get_lttpr_interop( 1333 struct dc_bios *dcb, 1334 uint8_t *dce_caps) 1335 { 1336 struct bios_parser *bp = BP_FROM_DCB(dcb); 1337 enum bp_result result = BP_RESULT_UNSUPPORTED; 1338 struct atom_common_table_header *header; 1339 struct atom_data_revision tbl_revision; 1340 1341 if (!DATA_TABLES(dce_info)) 1342 return BP_RESULT_UNSUPPORTED; 1343 1344 header = GET_IMAGE(struct atom_common_table_header, 1345 DATA_TABLES(dce_info)); 1346 get_atom_data_table_revision(header, &tbl_revision); 1347 switch (tbl_revision.major) { 1348 case 4: 1349 switch (tbl_revision.minor) { 1350 case 1: 1351 result = get_disp_caps_v4_1(bp, dce_caps); 1352 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1353 break; 1354 case 2: 1355 result = get_disp_caps_v4_2(bp, dce_caps); 1356 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1357 break; 1358 case 3: 1359 result = get_disp_caps_v4_3(bp, dce_caps); 1360 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1361 break; 1362 case 4: 1363 result = get_disp_caps_v4_4(bp, dce_caps); 1364 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1365 break; 1366 case 5: 1367 result = get_disp_caps_v4_5(bp, dce_caps); 1368 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1369 break; 1370 1371 default: 1372 break; 1373 } 1374 break; 1375 default: 1376 break; 1377 } 1378 DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor); 1379 return result; 1380 } 1381 1382 static enum bp_result bios_parser_get_lttpr_caps( 1383 struct dc_bios *dcb, 1384 uint8_t *dce_caps) 1385 { 1386 struct bios_parser *bp = BP_FROM_DCB(dcb); 1387 enum bp_result result = BP_RESULT_UNSUPPORTED; 1388 struct atom_common_table_header *header; 1389 struct atom_data_revision tbl_revision; 1390 1391 if (!DATA_TABLES(dce_info)) 1392 return BP_RESULT_UNSUPPORTED; 1393 1394 *dce_caps = 0; 1395 header = GET_IMAGE(struct atom_common_table_header, 1396 DATA_TABLES(dce_info)); 1397 get_atom_data_table_revision(header, &tbl_revision); 1398 switch (tbl_revision.major) { 1399 case 4: 1400 switch (tbl_revision.minor) { 1401 case 1: 1402 result = get_disp_caps_v4_1(bp, dce_caps); 1403 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1404 break; 1405 case 2: 1406 result = get_disp_caps_v4_2(bp, dce_caps); 1407 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1408 break; 1409 case 3: 1410 result = get_disp_caps_v4_3(bp, dce_caps); 1411 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1412 break; 1413 case 4: 1414 result = get_disp_caps_v4_4(bp, dce_caps); 1415 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1416 break; 1417 case 5: 1418 result = get_disp_caps_v4_5(bp, dce_caps); 1419 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1420 break; 1421 default: 1422 break; 1423 } 1424 break; 1425 default: 1426 break; 1427 } 1428 DC_LOG_BIOS("DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor); 1429 if (dcb->ctx->dc->config.force_bios_enable_lttpr && *dce_caps == 0) { 1430 *dce_caps = 1; 1431 DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: forced enabled"); 1432 } 1433 return result; 1434 } 1435 1436 static enum bp_result get_embedded_panel_info_v2_1( 1437 struct bios_parser *bp, 1438 struct embedded_panel_info *info) 1439 { 1440 struct lcd_info_v2_1 *lvds; 1441 1442 if (!info) 1443 return BP_RESULT_BADINPUT; 1444 1445 if (!DATA_TABLES(lcd_info)) 1446 return BP_RESULT_UNSUPPORTED; 1447 1448 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); 1449 1450 if (!lvds) 1451 return BP_RESULT_BADBIOSTABLE; 1452 1453 /* TODO: previous vv1_3, should v2_1 */ 1454 if (!((lvds->table_header.format_revision == 2) 1455 && (lvds->table_header.content_revision >= 1))) 1456 return BP_RESULT_UNSUPPORTED; 1457 1458 memset(info, 0, sizeof(struct embedded_panel_info)); 1459 1460 /* We need to convert from 10KHz units into KHz units */ 1461 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; 1462 /* usHActive does not include borders, according to VBIOS team */ 1463 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active); 1464 /* usHBlanking_Time includes borders, so we should really be 1465 * subtractingborders duing this translation, but LVDS generally 1466 * doesn't have borders, so we should be okay leaving this as is for 1467 * now. May need to revisit if we ever have LVDS with borders 1468 */ 1469 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time); 1470 /* usVActive does not include borders, according to VBIOS team*/ 1471 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active); 1472 /* usVBlanking_Time includes borders, so we should really be 1473 * subtracting borders duing this translation, but LVDS generally 1474 * doesn't have borders, so we should be okay leaving this as is for 1475 * now. May need to revisit if we ever have LVDS with borders 1476 */ 1477 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time); 1478 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset); 1479 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width); 1480 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset); 1481 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth); 1482 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border; 1483 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border; 1484 1485 /* not provided by VBIOS */ 1486 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0; 1487 1488 info->lcd_timing.misc_info.H_SYNC_POLARITY = !(lvds->lcd_timing.miscinfo & 1489 ATOM_HSYNC_POLARITY); 1490 info->lcd_timing.misc_info.V_SYNC_POLARITY = !(lvds->lcd_timing.miscinfo & 1491 ATOM_VSYNC_POLARITY); 1492 1493 /* not provided by VBIOS */ 1494 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0; 1495 1496 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1497 & ATOM_H_REPLICATIONBY2); 1498 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1499 & ATOM_V_REPLICATIONBY2); 1500 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo 1501 & ATOM_COMPOSITESYNC); 1502 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE); 1503 1504 /* not provided by VBIOS*/ 1505 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0; 1506 /* not provided by VBIOS*/ 1507 info->ss_id = 0; 1508 1509 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID); 1510 1511 return BP_RESULT_OK; 1512 } 1513 1514 static enum bp_result bios_parser_get_embedded_panel_info( 1515 struct dc_bios *dcb, 1516 struct embedded_panel_info *info) 1517 { 1518 struct bios_parser 1519 *bp = BP_FROM_DCB(dcb); 1520 struct atom_common_table_header *header; 1521 struct atom_data_revision tbl_revision; 1522 1523 if (!DATA_TABLES(lcd_info)) 1524 return BP_RESULT_FAILURE; 1525 1526 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info)); 1527 1528 if (!header) 1529 return BP_RESULT_BADBIOSTABLE; 1530 1531 get_atom_data_table_revision(header, &tbl_revision); 1532 1533 switch (tbl_revision.major) { 1534 case 2: 1535 switch (tbl_revision.minor) { 1536 case 1: 1537 return get_embedded_panel_info_v2_1(bp, info); 1538 default: 1539 break; 1540 } 1541 break; 1542 default: 1543 break; 1544 } 1545 1546 return BP_RESULT_FAILURE; 1547 } 1548 1549 static uint32_t get_support_mask_for_device_id(struct device_id device_id) 1550 { 1551 enum dal_device_type device_type = device_id.device_type; 1552 uint32_t enum_id = device_id.enum_id; 1553 1554 switch (device_type) { 1555 case DEVICE_TYPE_LCD: 1556 switch (enum_id) { 1557 case 1: 1558 return ATOM_DISPLAY_LCD1_SUPPORT; 1559 default: 1560 break; 1561 } 1562 break; 1563 case DEVICE_TYPE_DFP: 1564 switch (enum_id) { 1565 case 1: 1566 return ATOM_DISPLAY_DFP1_SUPPORT; 1567 case 2: 1568 return ATOM_DISPLAY_DFP2_SUPPORT; 1569 case 3: 1570 return ATOM_DISPLAY_DFP3_SUPPORT; 1571 case 4: 1572 return ATOM_DISPLAY_DFP4_SUPPORT; 1573 case 5: 1574 return ATOM_DISPLAY_DFP5_SUPPORT; 1575 case 6: 1576 return ATOM_DISPLAY_DFP6_SUPPORT; 1577 default: 1578 break; 1579 } 1580 break; 1581 default: 1582 break; 1583 } 1584 1585 /* Unidentified device ID, return empty support mask. */ 1586 return 0; 1587 } 1588 1589 static bool bios_parser_is_device_id_supported( 1590 struct dc_bios *dcb, 1591 struct device_id id) 1592 { 1593 struct bios_parser *bp = BP_FROM_DCB(dcb); 1594 1595 uint32_t mask = get_support_mask_for_device_id(id); 1596 1597 switch (bp->object_info_tbl.revision.minor) { 1598 case 4: 1599 default: 1600 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & mask) != 0; 1601 break; 1602 case 5: 1603 return (le16_to_cpu(bp->object_info_tbl.v1_5->supporteddevices) & mask) != 0; 1604 break; 1605 } 1606 } 1607 1608 static uint32_t bios_parser_get_ss_entry_number( 1609 struct dc_bios *dcb, 1610 enum as_signal_type signal) 1611 { 1612 (void)dcb; 1613 (void)signal; 1614 /* TODO: DAL2 atomfirmware implementation does not need this. 1615 * why DAL3 need this? 1616 */ 1617 return 1; 1618 } 1619 1620 static enum bp_result bios_parser_transmitter_control( 1621 struct dc_bios *dcb, 1622 struct bp_transmitter_control *cntl) 1623 { 1624 struct bios_parser *bp = BP_FROM_DCB(dcb); 1625 1626 if (!bp->cmd_tbl.transmitter_control) 1627 return BP_RESULT_FAILURE; 1628 1629 return bp->cmd_tbl.transmitter_control(bp, cntl); 1630 } 1631 1632 static enum bp_result bios_parser_encoder_control( 1633 struct dc_bios *dcb, 1634 struct bp_encoder_control *cntl) 1635 { 1636 struct bios_parser *bp = BP_FROM_DCB(dcb); 1637 1638 if (!bp->cmd_tbl.dig_encoder_control) 1639 return BP_RESULT_FAILURE; 1640 1641 return bp->cmd_tbl.dig_encoder_control(bp, cntl); 1642 } 1643 1644 static enum bp_result bios_parser_set_pixel_clock( 1645 struct dc_bios *dcb, 1646 struct bp_pixel_clock_parameters *bp_params) 1647 { 1648 struct bios_parser *bp = BP_FROM_DCB(dcb); 1649 1650 if (!bp->cmd_tbl.set_pixel_clock) 1651 return BP_RESULT_FAILURE; 1652 1653 return bp->cmd_tbl.set_pixel_clock(bp, bp_params); 1654 } 1655 1656 static enum bp_result bios_parser_set_dce_clock( 1657 struct dc_bios *dcb, 1658 struct bp_set_dce_clock_parameters *bp_params) 1659 { 1660 struct bios_parser *bp = BP_FROM_DCB(dcb); 1661 1662 if (!bp->cmd_tbl.set_dce_clock) 1663 return BP_RESULT_FAILURE; 1664 1665 return bp->cmd_tbl.set_dce_clock(bp, bp_params); 1666 } 1667 1668 static enum bp_result bios_parser_program_crtc_timing( 1669 struct dc_bios *dcb, 1670 struct bp_hw_crtc_timing_parameters *bp_params) 1671 { 1672 struct bios_parser *bp = BP_FROM_DCB(dcb); 1673 1674 if (!bp->cmd_tbl.set_crtc_timing) 1675 return BP_RESULT_FAILURE; 1676 1677 return bp->cmd_tbl.set_crtc_timing(bp, bp_params); 1678 } 1679 1680 static enum bp_result bios_parser_enable_crtc( 1681 struct dc_bios *dcb, 1682 enum controller_id id, 1683 bool enable) 1684 { 1685 struct bios_parser *bp = BP_FROM_DCB(dcb); 1686 1687 if (!bp->cmd_tbl.enable_crtc) 1688 return BP_RESULT_FAILURE; 1689 1690 return bp->cmd_tbl.enable_crtc(bp, id, enable); 1691 } 1692 1693 static enum bp_result bios_parser_enable_disp_power_gating( 1694 struct dc_bios *dcb, 1695 enum controller_id controller_id, 1696 enum bp_pipe_control_action action) 1697 { 1698 struct bios_parser *bp = BP_FROM_DCB(dcb); 1699 1700 if (!bp->cmd_tbl.enable_disp_power_gating) 1701 return BP_RESULT_FAILURE; 1702 1703 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id, 1704 action); 1705 } 1706 1707 static enum bp_result bios_parser_enable_lvtma_control( 1708 struct dc_bios *dcb, 1709 uint8_t uc_pwr_on, 1710 uint8_t pwrseq_instance, 1711 uint8_t bypass_panel_control_wait) 1712 { 1713 struct bios_parser *bp = BP_FROM_DCB(dcb); 1714 1715 if (!bp->cmd_tbl.enable_lvtma_control) 1716 return BP_RESULT_FAILURE; 1717 1718 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, pwrseq_instance, bypass_panel_control_wait); 1719 } 1720 1721 static bool bios_parser_is_accelerated_mode( 1722 struct dc_bios *dcb) 1723 { 1724 return bios_is_accelerated_mode(dcb); 1725 } 1726 1727 /** 1728 * bios_parser_set_scratch_critical_state - update critical state bit 1729 * in VBIOS scratch register 1730 * 1731 * @dcb: pointer to the DC BIO 1732 * @state: set or reset state 1733 */ 1734 static void bios_parser_set_scratch_critical_state( 1735 struct dc_bios *dcb, 1736 bool state) 1737 { 1738 bios_set_scratch_critical_state(dcb, state); 1739 } 1740 1741 static enum bp_result bios_parser_get_firmware_info( 1742 struct dc_bios *dcb, 1743 struct dc_firmware_info *info) 1744 { 1745 struct bios_parser *bp = BP_FROM_DCB(dcb); 1746 static enum bp_result result = BP_RESULT_BADBIOSTABLE; 1747 struct atom_common_table_header *header; 1748 1749 struct atom_data_revision revision; 1750 1751 if (info && DATA_TABLES(firmwareinfo)) { 1752 header = GET_IMAGE(struct atom_common_table_header, 1753 DATA_TABLES(firmwareinfo)); 1754 get_atom_data_table_revision(header, &revision); 1755 switch (revision.major) { 1756 case 3: 1757 switch (revision.minor) { 1758 case 1: 1759 result = get_firmware_info_v3_1(bp, info); 1760 break; 1761 case 2: 1762 case 3: 1763 result = get_firmware_info_v3_2(bp, info); 1764 break; 1765 case 4: 1766 result = get_firmware_info_v3_4(bp, info); 1767 break; 1768 case 5: 1769 result = get_firmware_info_v3_5(bp, info); 1770 break; 1771 default: 1772 break; 1773 } 1774 break; 1775 default: 1776 break; 1777 } 1778 } 1779 1780 return result; 1781 } 1782 1783 static enum bp_result get_firmware_info_v3_1( 1784 struct bios_parser *bp, 1785 struct dc_firmware_info *info) 1786 { 1787 struct atom_firmware_info_v3_1 *firmware_info; 1788 struct atom_firmware_info_v3_2 *firmware_info32; 1789 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1790 1791 if (!info) 1792 return BP_RESULT_BADINPUT; 1793 1794 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1, 1795 DATA_TABLES(firmwareinfo)); 1796 firmware_info32 = GET_IMAGE(struct atom_firmware_info_v3_2, 1797 DATA_TABLES(firmwareinfo)); 1798 1799 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1800 DATA_TABLES(dce_info)); 1801 1802 if (!firmware_info || !firmware_info32 || !dce_info) 1803 return BP_RESULT_BADBIOSTABLE; 1804 1805 memset(info, 0, sizeof(*info)); 1806 1807 /* Pixel clock pll information. */ 1808 /* We need to convert from 10KHz units into KHz units */ 1809 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1810 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10; 1811 1812 /* 27MHz for Vega10: */ 1813 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1814 1815 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1816 if (info->pll_info.crystal_frequency == 0) 1817 info->pll_info.crystal_frequency = 27000; 1818 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1819 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1820 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1821 1822 /* Get GPU PLL VCO Clock */ 1823 1824 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1825 /* VBIOS gives in 10KHz */ 1826 info->smu_gpu_pll_output_freq = 1827 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1828 } 1829 1830 /* These fields are marked as reserved in v3_1, but they appear to be populated 1831 * properly. 1832 */ 1833 if (firmware_info32 && firmware_info32->board_i2c_feature_id == 0x2) { 1834 info->oem_i2c_present = true; 1835 info->oem_i2c_obj_id = firmware_info32->board_i2c_feature_gpio_id; 1836 } else { 1837 info->oem_i2c_present = false; 1838 } 1839 1840 return BP_RESULT_OK; 1841 } 1842 1843 static enum bp_result get_firmware_info_v3_2( 1844 struct bios_parser *bp, 1845 struct dc_firmware_info *info) 1846 { 1847 struct atom_firmware_info_v3_2 *firmware_info; 1848 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1849 struct atom_common_table_header *header; 1850 struct atom_data_revision revision; 1851 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL; 1852 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL; 1853 1854 if (!info) 1855 return BP_RESULT_BADINPUT; 1856 1857 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2, 1858 DATA_TABLES(firmwareinfo)); 1859 1860 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1861 DATA_TABLES(dce_info)); 1862 1863 if (!firmware_info || !dce_info) 1864 return BP_RESULT_BADBIOSTABLE; 1865 1866 memset(info, 0, sizeof(*info)); 1867 1868 header = GET_IMAGE(struct atom_common_table_header, 1869 DATA_TABLES(smu_info)); 1870 get_atom_data_table_revision(header, &revision); 1871 1872 if (revision.minor == 2) { 1873 /* Vega12 */ 1874 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2, 1875 DATA_TABLES(smu_info)); 1876 if (!smu_info_v3_2) 1877 return BP_RESULT_BADBIOSTABLE; 1878 1879 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_2->gpuclk_ss_percentage); 1880 1881 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10; 1882 } else if (revision.minor == 3) { 1883 /* Vega20 */ 1884 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3, 1885 DATA_TABLES(smu_info)); 1886 if (!smu_info_v3_3) 1887 return BP_RESULT_BADBIOSTABLE; 1888 1889 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_3->gpuclk_ss_percentage); 1890 1891 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10; 1892 } 1893 1894 // We need to convert from 10KHz units into KHz units. 1895 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1896 1897 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */ 1898 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1899 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1900 if (info->pll_info.crystal_frequency == 0) { 1901 if (revision.minor == 2) 1902 info->pll_info.crystal_frequency = 27000; 1903 else if (revision.minor == 3) 1904 info->pll_info.crystal_frequency = 100000; 1905 } 1906 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1907 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1908 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1909 1910 /* Get GPU PLL VCO Clock */ 1911 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1912 if (revision.minor == 2) 1913 info->smu_gpu_pll_output_freq = 1914 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1915 else if (revision.minor == 3) 1916 info->smu_gpu_pll_output_freq = 1917 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10; 1918 } 1919 1920 if (firmware_info->board_i2c_feature_id == 0x2) { 1921 info->oem_i2c_present = true; 1922 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 1923 } else { 1924 info->oem_i2c_present = false; 1925 } 1926 1927 return BP_RESULT_OK; 1928 } 1929 1930 static enum bp_result get_firmware_info_v3_4( 1931 struct bios_parser *bp, 1932 struct dc_firmware_info *info) 1933 { 1934 struct atom_firmware_info_v3_4 *firmware_info; 1935 struct atom_common_table_header *header; 1936 struct atom_data_revision revision; 1937 struct atom_display_controller_info_v4_1 *dce_info_v4_1 = NULL; 1938 struct atom_display_controller_info_v4_4 *dce_info_v4_4 = NULL; 1939 1940 struct atom_smu_info_v3_5 *smu_info_v3_5 = NULL; 1941 struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL; 1942 struct atom_smu_info_v4_0 *smu_info_v4_0 = NULL; 1943 1944 if (!info) 1945 return BP_RESULT_BADINPUT; 1946 1947 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_4, 1948 DATA_TABLES(firmwareinfo)); 1949 1950 if (!firmware_info) 1951 return BP_RESULT_BADBIOSTABLE; 1952 1953 memset(info, 0, sizeof(*info)); 1954 1955 header = GET_IMAGE(struct atom_common_table_header, 1956 DATA_TABLES(dce_info)); 1957 1958 get_atom_data_table_revision(header, &revision); 1959 1960 switch (revision.major) { 1961 case 4: 1962 switch (revision.minor) { 1963 case 5: 1964 dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5, 1965 DATA_TABLES(dce_info)); 1966 1967 if (!dce_info_v4_5) 1968 return BP_RESULT_BADBIOSTABLE; 1969 1970 /* 100MHz expected */ 1971 info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10; 1972 info->dp_phy_ref_clk = dce_info_v4_5->dpphy_refclk_10khz * 10; 1973 /* 50MHz expected */ 1974 info->i2c_engine_ref_clk = dce_info_v4_5->i2c_engine_refclk_10khz * 10; 1975 1976 /* For DCN32/321 Display PLL VCO Frequency from dce_info_v4_5 may not be reliable */ 1977 break; 1978 1979 case 4: 1980 dce_info_v4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 1981 DATA_TABLES(dce_info)); 1982 1983 if (!dce_info_v4_4) 1984 return BP_RESULT_BADBIOSTABLE; 1985 1986 /* 100MHz expected */ 1987 info->pll_info.crystal_frequency = dce_info_v4_4->dce_refclk_10khz * 10; 1988 info->dp_phy_ref_clk = dce_info_v4_4->dpphy_refclk_10khz * 10; 1989 /* 50MHz expected */ 1990 info->i2c_engine_ref_clk = dce_info_v4_4->i2c_engine_refclk_10khz * 10; 1991 1992 /* Get SMU Display PLL VCO Frequency in KHz*/ 1993 info->smu_gpu_pll_output_freq = dce_info_v4_4->dispclk_pll_vco_freq * 10; 1994 break; 1995 1996 default: 1997 /* should not come here, keep as backup, as was before */ 1998 dce_info_v4_1 = GET_IMAGE(struct atom_display_controller_info_v4_1, 1999 DATA_TABLES(dce_info)); 2000 2001 if (!dce_info_v4_1) 2002 return BP_RESULT_BADBIOSTABLE; 2003 2004 info->pll_info.crystal_frequency = dce_info_v4_1->dce_refclk_10khz * 10; 2005 info->dp_phy_ref_clk = dce_info_v4_1->dpphy_refclk_10khz * 10; 2006 info->i2c_engine_ref_clk = dce_info_v4_1->i2c_engine_refclk_10khz * 10; 2007 break; 2008 } 2009 break; 2010 2011 default: 2012 ASSERT(0); 2013 break; 2014 } 2015 2016 header = GET_IMAGE(struct atom_common_table_header, 2017 DATA_TABLES(smu_info)); 2018 get_atom_data_table_revision(header, &revision); 2019 2020 switch (revision.major) { 2021 case 3: 2022 switch (revision.minor) { 2023 case 5: 2024 smu_info_v3_5 = GET_IMAGE(struct atom_smu_info_v3_5, 2025 DATA_TABLES(smu_info)); 2026 2027 if (!smu_info_v3_5) 2028 return BP_RESULT_BADBIOSTABLE; 2029 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_5->gpuclk_ss_percentage); 2030 info->default_engine_clk = smu_info_v3_5->bootup_dcefclk_10khz * 10; 2031 break; 2032 2033 default: 2034 break; 2035 } 2036 break; 2037 2038 case 4: 2039 switch (revision.minor) { 2040 case 0: 2041 smu_info_v4_0 = GET_IMAGE(struct atom_smu_info_v4_0, 2042 DATA_TABLES(smu_info)); 2043 2044 if (!smu_info_v4_0) 2045 return BP_RESULT_BADBIOSTABLE; 2046 2047 /* For DCN32/321 bootup DCFCLK from smu_info_v4_0 may not be reliable */ 2048 break; 2049 2050 default: 2051 break; 2052 } 2053 break; 2054 2055 default: 2056 break; 2057 } 2058 2059 // We need to convert from 10KHz units into KHz units. 2060 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 2061 2062 if (firmware_info->board_i2c_feature_id == 0x2) { 2063 info->oem_i2c_present = true; 2064 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 2065 } else { 2066 info->oem_i2c_present = false; 2067 } 2068 2069 return BP_RESULT_OK; 2070 } 2071 2072 static enum bp_result get_firmware_info_v3_5( 2073 struct bios_parser *bp, 2074 struct dc_firmware_info *info) 2075 { 2076 struct atom_firmware_info_v3_5 *firmware_info; 2077 struct atom_common_table_header *header; 2078 struct atom_data_revision revision; 2079 struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL; 2080 2081 if (!info) 2082 return BP_RESULT_BADINPUT; 2083 2084 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_5, 2085 DATA_TABLES(firmwareinfo)); 2086 2087 if (!firmware_info) 2088 return BP_RESULT_BADBIOSTABLE; 2089 2090 memset(info, 0, sizeof(*info)); 2091 2092 if (firmware_info->board_i2c_feature_id == 0x2) { 2093 info->oem_i2c_present = true; 2094 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 2095 } else { 2096 info->oem_i2c_present = false; 2097 } 2098 2099 header = GET_IMAGE(struct atom_common_table_header, 2100 DATA_TABLES(dce_info)); 2101 2102 get_atom_data_table_revision(header, &revision); 2103 2104 switch (revision.major) { 2105 case 4: 2106 switch (revision.minor) { 2107 case 5: 2108 dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5, 2109 DATA_TABLES(dce_info)); 2110 2111 if (!dce_info_v4_5) 2112 return BP_RESULT_BADBIOSTABLE; 2113 2114 /* 100MHz expected */ 2115 info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10; 2116 break; 2117 default: 2118 break; 2119 } 2120 break; 2121 default: 2122 break; 2123 } 2124 2125 2126 return BP_RESULT_OK; 2127 } 2128 2129 static enum bp_result bios_parser_get_encoder_cap_info( 2130 struct dc_bios *dcb, 2131 struct graphics_object_id object_id, 2132 struct bp_encoder_cap_info *info) 2133 { 2134 struct bios_parser *bp = BP_FROM_DCB(dcb); 2135 struct atom_display_object_path_v2 *object; 2136 struct atom_encoder_caps_record *record = NULL; 2137 2138 if (!info) 2139 return BP_RESULT_BADINPUT; 2140 2141 #if defined(CONFIG_DRM_AMD_DC_FP) 2142 /* encoder cap record not available in v1_5 */ 2143 if (bp->object_info_tbl.revision.minor == 5) 2144 return BP_RESULT_NORECORD; 2145 #endif 2146 2147 object = get_bios_object(bp, object_id); 2148 2149 if (!object) 2150 return BP_RESULT_BADINPUT; 2151 2152 record = get_encoder_cap_record(bp, object); 2153 if (!record) 2154 return BP_RESULT_NORECORD; 2155 DC_LOG_BIOS("record->encodercaps 0x%x for object_id 0x%x", record->encodercaps, object_id.id); 2156 2157 info->DP_HBR2_CAP = (record->encodercaps & 2158 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0; 2159 info->DP_HBR2_EN = (record->encodercaps & 2160 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0; 2161 info->DP_HBR3_EN = (record->encodercaps & 2162 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0; 2163 info->HDMI_6GB_EN = (record->encodercaps & 2164 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0; 2165 info->IS_DP2_CAPABLE = (record->encodercaps & 2166 ATOM_ENCODER_CAP_RECORD_DP2) ? 1 : 0; 2167 info->DP_UHBR10_EN = (record->encodercaps & 2168 ATOM_ENCODER_CAP_RECORD_UHBR10_EN) ? 1 : 0; 2169 info->DP_UHBR13_5_EN = (record->encodercaps & 2170 ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN) ? 1 : 0; 2171 info->DP_UHBR20_EN = (record->encodercaps & 2172 ATOM_ENCODER_CAP_RECORD_UHBR20_EN) ? 1 : 0; 2173 info->DP_IS_USB_C = (record->encodercaps & 2174 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0; 2175 DC_LOG_BIOS("\t info->DP_IS_USB_C %d", info->DP_IS_USB_C); 2176 2177 return BP_RESULT_OK; 2178 } 2179 2180 2181 static struct atom_encoder_caps_record *get_encoder_cap_record( 2182 struct bios_parser *bp, 2183 struct atom_display_object_path_v2 *object) 2184 { 2185 struct atom_common_record_header *header; 2186 uint32_t offset; 2187 2188 if (!object) { 2189 BREAK_TO_DEBUGGER(); /* Invalid object */ 2190 return NULL; 2191 } 2192 2193 offset = object->encoder_recordoffset + bp->object_info_tbl_offset; 2194 2195 for (;;) { 2196 header = GET_IMAGE(struct atom_common_record_header, offset); 2197 2198 if (!header) 2199 return NULL; 2200 2201 offset += header->record_size; 2202 2203 if (header->record_type == LAST_RECORD_TYPE || 2204 !header->record_size) 2205 break; 2206 2207 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE) 2208 continue; 2209 2210 if (sizeof(struct atom_encoder_caps_record) <= 2211 header->record_size) 2212 return (struct atom_encoder_caps_record *)header; 2213 } 2214 2215 return NULL; 2216 } 2217 2218 static struct atom_disp_connector_caps_record *get_disp_connector_caps_record( 2219 struct bios_parser *bp, 2220 struct atom_display_object_path_v2 *object) 2221 { 2222 struct atom_common_record_header *header; 2223 uint32_t offset; 2224 2225 if (!object) { 2226 BREAK_TO_DEBUGGER(); /* Invalid object */ 2227 return NULL; 2228 } 2229 2230 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2231 2232 for (;;) { 2233 header = GET_IMAGE(struct atom_common_record_header, offset); 2234 2235 if (!header) 2236 return NULL; 2237 2238 offset += header->record_size; 2239 2240 if (header->record_type == LAST_RECORD_TYPE || 2241 !header->record_size) 2242 break; 2243 2244 if (header->record_type != ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE) 2245 continue; 2246 2247 if (sizeof(struct atom_disp_connector_caps_record) <= 2248 header->record_size) 2249 return (struct atom_disp_connector_caps_record *)header; 2250 } 2251 2252 return NULL; 2253 } 2254 2255 static struct atom_connector_caps_record *get_connector_caps_record(struct bios_parser *bp, 2256 struct atom_display_object_path_v3 *object) 2257 { 2258 struct atom_common_record_header *header; 2259 uint32_t offset; 2260 2261 if (!object) { 2262 BREAK_TO_DEBUGGER(); /* Invalid object */ 2263 return NULL; 2264 } 2265 2266 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2267 2268 for (;;) { 2269 header = GET_IMAGE(struct atom_common_record_header, offset); 2270 2271 if (!header) 2272 return NULL; 2273 2274 offset += header->record_size; 2275 2276 if (header->record_type == ATOM_RECORD_END_TYPE || 2277 !header->record_size) 2278 break; 2279 2280 if (header->record_type != ATOM_CONNECTOR_CAP_RECORD_TYPE) 2281 continue; 2282 2283 if (sizeof(struct atom_connector_caps_record) <= header->record_size) 2284 return (struct atom_connector_caps_record *)header; 2285 } 2286 2287 return NULL; 2288 } 2289 2290 static enum bp_result bios_parser_get_disp_connector_caps_info( 2291 struct dc_bios *dcb, 2292 struct graphics_object_id object_id, 2293 struct bp_disp_connector_caps_info *info) 2294 { 2295 struct bios_parser *bp = BP_FROM_DCB(dcb); 2296 struct atom_display_object_path_v2 *object; 2297 struct atom_display_object_path_v3 *object_path_v3; 2298 struct atom_connector_caps_record *record_path_v3; 2299 struct atom_disp_connector_caps_record *record = NULL; 2300 2301 if (!info) 2302 return BP_RESULT_BADINPUT; 2303 2304 switch (bp->object_info_tbl.revision.minor) { 2305 case 4: 2306 default: 2307 object = get_bios_object(bp, object_id); 2308 2309 if (!object) 2310 return BP_RESULT_BADINPUT; 2311 2312 record = get_disp_connector_caps_record(bp, object); 2313 if (!record) 2314 return BP_RESULT_NORECORD; 2315 2316 info->INTERNAL_DISPLAY = 2317 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) ? 1 : 0; 2318 info->INTERNAL_DISPLAY_BL = 2319 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) ? 1 : 0; 2320 break; 2321 case 5: 2322 object_path_v3 = get_bios_object_from_path_v3(bp, object_id); 2323 2324 if (!object_path_v3) 2325 return BP_RESULT_BADINPUT; 2326 2327 record_path_v3 = get_connector_caps_record(bp, object_path_v3); 2328 if (!record_path_v3) 2329 return BP_RESULT_NORECORD; 2330 2331 info->INTERNAL_DISPLAY = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) 2332 ? 1 : 0; 2333 info->INTERNAL_DISPLAY_BL = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) 2334 ? 1 : 0; 2335 break; 2336 } 2337 2338 return BP_RESULT_OK; 2339 } 2340 2341 static struct atom_connector_speed_record *get_connector_speed_cap_record(struct bios_parser *bp, 2342 struct atom_display_object_path_v3 *object) 2343 { 2344 struct atom_common_record_header *header; 2345 uint32_t offset; 2346 2347 if (!object) { 2348 BREAK_TO_DEBUGGER(); /* Invalid object */ 2349 return NULL; 2350 } 2351 2352 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2353 2354 for (;;) { 2355 header = GET_IMAGE(struct atom_common_record_header, offset); 2356 2357 if (!header) 2358 return NULL; 2359 2360 offset += header->record_size; 2361 2362 if (header->record_type == ATOM_RECORD_END_TYPE || 2363 !header->record_size) 2364 break; 2365 2366 if (header->record_type != ATOM_CONNECTOR_SPEED_UPTO) 2367 continue; 2368 2369 if (sizeof(struct atom_connector_speed_record) <= header->record_size) 2370 return (struct atom_connector_speed_record *)header; 2371 } 2372 2373 return NULL; 2374 } 2375 2376 static enum bp_result bios_parser_get_connector_speed_cap_info( 2377 struct dc_bios *dcb, 2378 struct graphics_object_id object_id, 2379 struct bp_connector_speed_cap_info *info) 2380 { 2381 struct bios_parser *bp = BP_FROM_DCB(dcb); 2382 struct atom_display_object_path_v3 *object_path_v3; 2383 //struct atom_connector_speed_record *record = NULL; 2384 struct atom_connector_speed_record *record; 2385 2386 if (!info) 2387 return BP_RESULT_BADINPUT; 2388 2389 object_path_v3 = get_bios_object_from_path_v3(bp, object_id); 2390 2391 if (!object_path_v3) 2392 return BP_RESULT_BADINPUT; 2393 2394 record = get_connector_speed_cap_record(bp, object_path_v3); 2395 if (!record) 2396 return BP_RESULT_NORECORD; 2397 2398 info->DP_HBR2_EN = (record->connector_max_speed >= 5400) ? 1 : 0; 2399 info->DP_HBR3_EN = (record->connector_max_speed >= 8100) ? 1 : 0; 2400 info->HDMI_6GB_EN = (record->connector_max_speed >= 5940) ? 1 : 0; 2401 info->DP_UHBR10_EN = (record->connector_max_speed >= 10000) ? 1 : 0; 2402 info->DP_UHBR13_5_EN = (record->connector_max_speed >= 13500) ? 1 : 0; 2403 info->DP_UHBR20_EN = (record->connector_max_speed >= 20000) ? 1 : 0; 2404 return BP_RESULT_OK; 2405 } 2406 2407 static enum bp_result get_vram_info_v23( 2408 struct bios_parser *bp, 2409 struct dc_vram_info *info) 2410 { 2411 struct atom_vram_info_header_v2_3 *info_v23; 2412 static enum bp_result result = BP_RESULT_OK; 2413 2414 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3, 2415 DATA_TABLES(vram_info)); 2416 2417 if (info_v23 == NULL) 2418 return BP_RESULT_BADBIOSTABLE; 2419 2420 info->num_chans = info_v23->vram_module[0].channel_num; 2421 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8; 2422 2423 return result; 2424 } 2425 2426 static enum bp_result get_vram_info_v24( 2427 struct bios_parser *bp, 2428 struct dc_vram_info *info) 2429 { 2430 struct atom_vram_info_header_v2_4 *info_v24; 2431 static enum bp_result result = BP_RESULT_OK; 2432 2433 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4, 2434 DATA_TABLES(vram_info)); 2435 2436 if (info_v24 == NULL) 2437 return BP_RESULT_BADBIOSTABLE; 2438 2439 info->num_chans = info_v24->vram_module[0].channel_num; 2440 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8; 2441 2442 return result; 2443 } 2444 2445 static enum bp_result get_vram_info_v25( 2446 struct bios_parser *bp, 2447 struct dc_vram_info *info) 2448 { 2449 struct atom_vram_info_header_v2_5 *info_v25; 2450 static enum bp_result result = BP_RESULT_OK; 2451 2452 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5, 2453 DATA_TABLES(vram_info)); 2454 2455 if (info_v25 == NULL) 2456 return BP_RESULT_BADBIOSTABLE; 2457 2458 info->num_chans = info_v25->vram_module[0].channel_num; 2459 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8; 2460 2461 return result; 2462 } 2463 2464 static enum bp_result get_vram_info_v30( 2465 struct bios_parser *bp, 2466 struct dc_vram_info *info) 2467 { 2468 struct atom_vram_info_header_v3_0 *info_v30; 2469 enum bp_result result = BP_RESULT_OK; 2470 2471 info_v30 = GET_IMAGE(struct atom_vram_info_header_v3_0, 2472 DATA_TABLES(vram_info)); 2473 2474 if (info_v30 == NULL) 2475 return BP_RESULT_BADBIOSTABLE; 2476 2477 info->num_chans = info_v30->channel_num; 2478 info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8; 2479 2480 return result; 2481 } 2482 2483 static enum bp_result get_vram_info_from_umc_info_v40( 2484 struct bios_parser *bp, 2485 struct dc_vram_info *info) 2486 { 2487 struct atom_umc_info_v4_0 *info_v40; 2488 enum bp_result result = BP_RESULT_OK; 2489 2490 info_v40 = GET_IMAGE(struct atom_umc_info_v4_0, 2491 DATA_TABLES(umc_info)); 2492 2493 if (info_v40 == NULL) 2494 return BP_RESULT_BADBIOSTABLE; 2495 2496 info->num_chans = info_v40->channel_num; 2497 info->dram_channel_width_bytes = (1 << info_v40->channel_width) / 8; 2498 2499 return result; 2500 } 2501 2502 /* 2503 * get_integrated_info_v11 2504 * 2505 * @brief 2506 * Get V8 integrated BIOS information 2507 * 2508 * @param 2509 * bios_parser *bp - [in]BIOS parser handler to get master data table 2510 * integrated_info *info - [out] store and output integrated info 2511 * 2512 * @return 2513 * static enum bp_result - BP_RESULT_OK if information is available, 2514 * BP_RESULT_BADBIOSTABLE otherwise. 2515 */ 2516 static enum bp_result get_integrated_info_v11( 2517 struct bios_parser *bp, 2518 struct integrated_info *info) 2519 { 2520 struct atom_integrated_system_info_v1_11 *info_v11; 2521 uint32_t i; 2522 2523 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11, 2524 DATA_TABLES(integratedsysteminfo)); 2525 2526 if (info_v11 == NULL) 2527 return BP_RESULT_BADBIOSTABLE; 2528 2529 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v11->gpuclk_ss_percentage); 2530 2531 info->gpu_cap_info = 2532 le32_to_cpu(info_v11->gpucapinfo); 2533 /* 2534 * system_config: Bit[0] = 0 : PCIE power gating disabled 2535 * = 1 : PCIE power gating enabled 2536 * Bit[1] = 0 : DDR-PLL shut down disabled 2537 * = 1 : DDR-PLL shut down enabled 2538 * Bit[2] = 0 : DDR-PLL power down disabled 2539 * = 1 : DDR-PLL power down enabled 2540 */ 2541 info->system_config = le32_to_cpu(info_v11->system_config); 2542 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo); 2543 info->memory_type = info_v11->memorytype; 2544 info->ma_channel_number = info_v11->umachannelnumber; 2545 info->lvds_ss_percentage = 2546 le16_to_cpu(info_v11->lvds_ss_percentage); 2547 info->dp_ss_control = 2548 le16_to_cpu(info_v11->reserved1); 2549 info->lvds_sspread_rate_in_10hz = 2550 le16_to_cpu(info_v11->lvds_ss_rate_10hz); 2551 info->hdmi_ss_percentage = 2552 le16_to_cpu(info_v11->hdmi_ss_percentage); 2553 info->hdmi_sspread_rate_in_10hz = 2554 le16_to_cpu(info_v11->hdmi_ss_rate_10hz); 2555 info->dvi_ss_percentage = 2556 le16_to_cpu(info_v11->dvi_ss_percentage); 2557 info->dvi_sspread_rate_in_10_hz = 2558 le16_to_cpu(info_v11->dvi_ss_rate_10hz); 2559 info->lvds_misc = info_v11->lvds_misc; 2560 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2561 info->ext_disp_conn_info.gu_id[i] = 2562 info_v11->extdispconninfo.guid[i]; 2563 } 2564 2565 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2566 info->ext_disp_conn_info.path[i].device_connector_id = 2567 object_id_from_bios_object_id( 2568 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid)); 2569 2570 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2571 object_id_from_bios_object_id( 2572 le16_to_cpu( 2573 info_v11->extdispconninfo.path[i].ext_encoder_objid)); 2574 2575 info->ext_disp_conn_info.path[i].device_tag = 2576 le16_to_cpu( 2577 info_v11->extdispconninfo.path[i].device_tag); 2578 info->ext_disp_conn_info.path[i].device_acpi_enum = 2579 le16_to_cpu( 2580 info_v11->extdispconninfo.path[i].device_acpi_enum); 2581 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2582 info_v11->extdispconninfo.path[i].auxddclut_index; 2583 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2584 info_v11->extdispconninfo.path[i].hpdlut_index; 2585 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2586 info_v11->extdispconninfo.path[i].channelmapping; 2587 info->ext_disp_conn_info.path[i].caps = 2588 le16_to_cpu(info_v11->extdispconninfo.path[i].caps); 2589 } 2590 info->ext_disp_conn_info.checksum = 2591 info_v11->extdispconninfo.checksum; 2592 2593 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr; 2594 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum; 2595 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 2596 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 2597 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2598 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 2599 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2600 } 2601 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum; 2602 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 2603 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2604 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2605 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2606 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2607 } 2608 2609 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr; 2610 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum; 2611 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 2612 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 2613 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2614 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 2615 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2616 } 2617 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum; 2618 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 2619 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2620 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2621 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2622 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2623 } 2624 2625 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr; 2626 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum; 2627 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 2628 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 2629 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2630 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 2631 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2632 } 2633 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum; 2634 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 2635 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2636 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2637 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2638 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2639 } 2640 2641 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr; 2642 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum; 2643 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 2644 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 2645 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2646 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 2647 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2648 } 2649 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum; 2650 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 2651 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2652 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2653 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2654 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2655 } 2656 2657 2658 /** TODO - review **/ 2659 #if 0 2660 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock) 2661 * 10; 2662 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10; 2663 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10; 2664 2665 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 2666 /* Convert [10KHz] into [KHz] */ 2667 info->disp_clk_voltage[i].max_supported_clk = 2668 le32_to_cpu(info_v11->sDISPCLK_Voltage[i]. 2669 ulMaximumSupportedCLK) * 10; 2670 info->disp_clk_voltage[i].voltage_index = 2671 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex); 2672 } 2673 2674 info->boot_up_req_display_vector = 2675 le32_to_cpu(info_v11->ulBootUpReqDisplayVector); 2676 info->boot_up_nb_voltage = 2677 le16_to_cpu(info_v11->usBootUpNBVoltage); 2678 info->ext_disp_conn_info_offset = 2679 le16_to_cpu(info_v11->usExtDispConnInfoOffset); 2680 info->gmc_restore_reset_time = 2681 le32_to_cpu(info_v11->ulGMCRestoreResetTime); 2682 info->minimum_n_clk = 2683 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]); 2684 for (i = 1; i < 4; ++i) 2685 info->minimum_n_clk = 2686 info->minimum_n_clk < 2687 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ? 2688 info->minimum_n_clk : le32_to_cpu( 2689 info_v11->ulNbpStateNClkFreq[i]); 2690 2691 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk); 2692 info->ddr_dll_power_up_time = 2693 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime); 2694 info->ddr_pll_power_up_time = 2695 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime); 2696 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType); 2697 info->max_lvds_pclk_freq_in_single_link = 2698 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 2699 info->max_lvds_pclk_freq_in_single_link = 2700 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 2701 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms = 2702 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 2703 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms = 2704 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 2705 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms = 2706 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 2707 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms = 2708 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 2709 info->lvds_pwr_off_seq_de_to_dig_on_in4ms = 2710 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 2711 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms = 2712 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 2713 info->lvds_off_to_on_delay_in_4ms = 2714 info_v11->ucLVDSOffToOnDelay_in4Ms; 2715 info->lvds_bit_depth_control_val = 2716 le32_to_cpu(info_v11->ulLCDBitDepthControlVal); 2717 2718 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) { 2719 /* Convert [10KHz] into [KHz] */ 2720 info->avail_s_clk[i].supported_s_clk = 2721 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK) 2722 * 10; 2723 info->avail_s_clk[i].voltage_index = 2724 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex); 2725 info->avail_s_clk[i].voltage_id = 2726 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID); 2727 } 2728 #endif /* TODO*/ 2729 2730 return BP_RESULT_OK; 2731 } 2732 2733 static enum bp_result get_integrated_info_v2_1( 2734 struct bios_parser *bp, 2735 struct integrated_info *info) 2736 { 2737 struct atom_integrated_system_info_v2_1 *info_v2_1; 2738 uint32_t i; 2739 2740 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1, 2741 DATA_TABLES(integratedsysteminfo)); 2742 2743 if (info_v2_1 == NULL) 2744 return BP_RESULT_BADBIOSTABLE; 2745 2746 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_1->gpuclk_ss_percentage); 2747 2748 info->gpu_cap_info = 2749 le32_to_cpu(info_v2_1->gpucapinfo); 2750 /* 2751 * system_config: Bit[0] = 0 : PCIE power gating disabled 2752 * = 1 : PCIE power gating enabled 2753 * Bit[1] = 0 : DDR-PLL shut down disabled 2754 * = 1 : DDR-PLL shut down enabled 2755 * Bit[2] = 0 : DDR-PLL power down disabled 2756 * = 1 : DDR-PLL power down enabled 2757 */ 2758 info->system_config = le32_to_cpu(info_v2_1->system_config); 2759 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo); 2760 info->memory_type = info_v2_1->memorytype; 2761 info->ma_channel_number = info_v2_1->umachannelnumber; 2762 info->dp_ss_control = 2763 le16_to_cpu(info_v2_1->reserved1); 2764 2765 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2766 info->ext_disp_conn_info.gu_id[i] = 2767 info_v2_1->extdispconninfo.guid[i]; 2768 } 2769 2770 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2771 info->ext_disp_conn_info.path[i].device_connector_id = 2772 object_id_from_bios_object_id( 2773 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid)); 2774 2775 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2776 object_id_from_bios_object_id( 2777 le16_to_cpu( 2778 info_v2_1->extdispconninfo.path[i].ext_encoder_objid)); 2779 2780 info->ext_disp_conn_info.path[i].device_tag = 2781 le16_to_cpu( 2782 info_v2_1->extdispconninfo.path[i].device_tag); 2783 info->ext_disp_conn_info.path[i].device_acpi_enum = 2784 le16_to_cpu( 2785 info_v2_1->extdispconninfo.path[i].device_acpi_enum); 2786 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2787 info_v2_1->extdispconninfo.path[i].auxddclut_index; 2788 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2789 info_v2_1->extdispconninfo.path[i].hpdlut_index; 2790 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2791 info_v2_1->extdispconninfo.path[i].channelmapping; 2792 info->ext_disp_conn_info.path[i].caps = 2793 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps); 2794 } 2795 2796 info->ext_disp_conn_info.checksum = 2797 info_v2_1->extdispconninfo.checksum; 2798 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr; 2799 info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum; 2800 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 2801 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 2802 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2803 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 2804 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2805 } 2806 info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum; 2807 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 2808 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2809 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2810 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2811 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2812 } 2813 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr; 2814 info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum; 2815 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 2816 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 2817 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2818 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 2819 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2820 } 2821 info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum; 2822 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 2823 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2824 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2825 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2826 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2827 } 2828 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr; 2829 info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum; 2830 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 2831 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 2832 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2833 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 2834 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2835 } 2836 info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum; 2837 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 2838 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2839 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2840 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2841 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2842 } 2843 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr; 2844 info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum; 2845 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 2846 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 2847 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2848 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 2849 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2850 } 2851 info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum; 2852 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 2853 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2854 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2855 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2856 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2857 } 2858 2859 info->edp1_info.edp_backlight_pwm_hz = 2860 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz); 2861 info->edp1_info.edp_ss_percentage = 2862 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage); 2863 info->edp1_info.edp_ss_rate_10hz = 2864 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz); 2865 info->edp1_info.edp_pwr_on_off_delay = 2866 info_v2_1->edp1_info.edp_pwr_on_off_delay; 2867 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2868 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon; 2869 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2870 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2871 info->edp1_info.edp_panel_bpc = 2872 info_v2_1->edp1_info.edp_panel_bpc; 2873 info->edp1_info.edp_bootup_bl_level = info_v2_1->edp1_info.edp_bootup_bl_level; 2874 2875 info->edp2_info.edp_backlight_pwm_hz = 2876 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz); 2877 info->edp2_info.edp_ss_percentage = 2878 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage); 2879 info->edp2_info.edp_ss_rate_10hz = 2880 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz); 2881 info->edp2_info.edp_pwr_on_off_delay = 2882 info_v2_1->edp2_info.edp_pwr_on_off_delay; 2883 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 2884 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon; 2885 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 2886 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 2887 info->edp2_info.edp_panel_bpc = 2888 info_v2_1->edp2_info.edp_panel_bpc; 2889 info->edp2_info.edp_bootup_bl_level = 2890 info_v2_1->edp2_info.edp_bootup_bl_level; 2891 2892 return BP_RESULT_OK; 2893 } 2894 2895 static enum bp_result get_integrated_info_v2_2( 2896 struct bios_parser *bp, 2897 struct integrated_info *info) 2898 { 2899 struct atom_integrated_system_info_v2_2 *info_v2_2; 2900 uint32_t i; 2901 2902 info_v2_2 = GET_IMAGE(struct atom_integrated_system_info_v2_2, 2903 DATA_TABLES(integratedsysteminfo)); 2904 2905 if (info_v2_2 == NULL) 2906 return BP_RESULT_BADBIOSTABLE; 2907 2908 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_2->gpuclk_ss_percentage); 2909 2910 info->gpu_cap_info = 2911 le32_to_cpu(info_v2_2->gpucapinfo); 2912 /* 2913 * system_config: Bit[0] = 0 : PCIE power gating disabled 2914 * = 1 : PCIE power gating enabled 2915 * Bit[1] = 0 : DDR-PLL shut down disabled 2916 * = 1 : DDR-PLL shut down enabled 2917 * Bit[2] = 0 : DDR-PLL power down disabled 2918 * = 1 : DDR-PLL power down enabled 2919 */ 2920 info->system_config = le32_to_cpu(info_v2_2->system_config); 2921 info->cpu_cap_info = le32_to_cpu(info_v2_2->cpucapinfo); 2922 info->memory_type = info_v2_2->memorytype; 2923 info->ma_channel_number = info_v2_2->umachannelnumber; 2924 info->dp_ss_control = 2925 le16_to_cpu(info_v2_2->reserved1); 2926 info->gpuclk_ss_percentage = info_v2_2->gpuclk_ss_percentage; 2927 info->gpuclk_ss_type = info_v2_2->gpuclk_ss_type; 2928 2929 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2930 info->ext_disp_conn_info.gu_id[i] = 2931 info_v2_2->extdispconninfo.guid[i]; 2932 } 2933 2934 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2935 info->ext_disp_conn_info.path[i].device_connector_id = 2936 object_id_from_bios_object_id( 2937 le16_to_cpu(info_v2_2->extdispconninfo.path[i].connectorobjid)); 2938 2939 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2940 object_id_from_bios_object_id( 2941 le16_to_cpu( 2942 info_v2_2->extdispconninfo.path[i].ext_encoder_objid)); 2943 2944 info->ext_disp_conn_info.path[i].device_tag = 2945 le16_to_cpu( 2946 info_v2_2->extdispconninfo.path[i].device_tag); 2947 info->ext_disp_conn_info.path[i].device_acpi_enum = 2948 le16_to_cpu( 2949 info_v2_2->extdispconninfo.path[i].device_acpi_enum); 2950 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2951 info_v2_2->extdispconninfo.path[i].auxddclut_index; 2952 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2953 info_v2_2->extdispconninfo.path[i].hpdlut_index; 2954 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2955 info_v2_2->extdispconninfo.path[i].channelmapping; 2956 info->ext_disp_conn_info.path[i].caps = 2957 le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps); 2958 } 2959 2960 info->ext_disp_conn_info.checksum = 2961 info_v2_2->extdispconninfo.checksum; 2962 info->ext_disp_conn_info.fixdpvoltageswing = 2963 info_v2_2->extdispconninfo.fixdpvoltageswing; 2964 2965 info->edp1_info.edp_backlight_pwm_hz = 2966 le16_to_cpu(info_v2_2->edp1_info.edp_backlight_pwm_hz); 2967 info->edp1_info.edp_ss_percentage = 2968 le16_to_cpu(info_v2_2->edp1_info.edp_ss_percentage); 2969 info->edp1_info.edp_ss_rate_10hz = 2970 le16_to_cpu(info_v2_2->edp1_info.edp_ss_rate_10hz); 2971 info->edp1_info.edp_pwr_on_off_delay = 2972 info_v2_2->edp1_info.edp_pwr_on_off_delay; 2973 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2974 info_v2_2->edp1_info.edp_pwr_on_vary_bl_to_blon; 2975 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2976 info_v2_2->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2977 info->edp1_info.edp_panel_bpc = 2978 info_v2_2->edp1_info.edp_panel_bpc; 2979 info->edp1_info.edp_bootup_bl_level = 2980 2981 info->edp2_info.edp_backlight_pwm_hz = 2982 le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz); 2983 info->edp2_info.edp_ss_percentage = 2984 le16_to_cpu(info_v2_2->edp2_info.edp_ss_percentage); 2985 info->edp2_info.edp_ss_rate_10hz = 2986 le16_to_cpu(info_v2_2->edp2_info.edp_ss_rate_10hz); 2987 info->edp2_info.edp_pwr_on_off_delay = 2988 info_v2_2->edp2_info.edp_pwr_on_off_delay; 2989 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 2990 info_v2_2->edp2_info.edp_pwr_on_vary_bl_to_blon; 2991 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 2992 info_v2_2->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 2993 info->edp2_info.edp_panel_bpc = 2994 info_v2_2->edp2_info.edp_panel_bpc; 2995 info->edp2_info.edp_bootup_bl_level = 2996 info_v2_2->edp2_info.edp_bootup_bl_level; 2997 2998 return BP_RESULT_OK; 2999 } 3000 3001 /* 3002 * construct_integrated_info 3003 * 3004 * @brief 3005 * Get integrated BIOS information based on table revision 3006 * 3007 * @param 3008 * bios_parser *bp - [in]BIOS parser handler to get master data table 3009 * integrated_info *info - [out] store and output integrated info 3010 * 3011 * @return 3012 * static enum bp_result - BP_RESULT_OK if information is available, 3013 * BP_RESULT_BADBIOSTABLE otherwise. 3014 */ 3015 static enum bp_result construct_integrated_info( 3016 struct bios_parser *bp, 3017 struct integrated_info *info) 3018 { 3019 static enum bp_result result = BP_RESULT_BADBIOSTABLE; 3020 3021 struct atom_common_table_header *header; 3022 struct atom_data_revision revision; 3023 3024 int32_t i; 3025 int32_t j; 3026 3027 if (!info) 3028 return result; 3029 3030 if (info && DATA_TABLES(integratedsysteminfo)) { 3031 header = GET_IMAGE(struct atom_common_table_header, 3032 DATA_TABLES(integratedsysteminfo)); 3033 3034 get_atom_data_table_revision(header, &revision); 3035 3036 switch (revision.major) { 3037 case 1: 3038 switch (revision.minor) { 3039 case 11: 3040 case 12: 3041 result = get_integrated_info_v11(bp, info); 3042 break; 3043 default: 3044 return result; 3045 } 3046 break; 3047 case 2: 3048 switch (revision.minor) { 3049 case 1: 3050 result = get_integrated_info_v2_1(bp, info); 3051 break; 3052 case 2: 3053 case 3: 3054 result = get_integrated_info_v2_2(bp, info); 3055 break; 3056 default: 3057 return result; 3058 } 3059 break; 3060 default: 3061 return result; 3062 } 3063 if (result == BP_RESULT_OK) { 3064 3065 DC_LOG_BIOS("edp1:\n" 3066 "\tedp_pwr_on_off_delay = %d\n" 3067 "\tedp_pwr_on_vary_bl_to_blon = %d\n" 3068 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n" 3069 "\tedp_bootup_bl_level = %d\n", 3070 info->edp1_info.edp_pwr_on_off_delay, 3071 info->edp1_info.edp_pwr_on_vary_bl_to_blon, 3072 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff, 3073 info->edp1_info.edp_bootup_bl_level); 3074 DC_LOG_BIOS("edp2:\n" 3075 "\tedp_pwr_on_off_delayv = %d\n" 3076 "\tedp_pwr_on_vary_bl_to_blon = %d\n" 3077 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n" 3078 "\tedp_bootup_bl_level = %d\n", 3079 info->edp2_info.edp_pwr_on_off_delay, 3080 info->edp2_info.edp_pwr_on_vary_bl_to_blon, 3081 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff, 3082 info->edp2_info.edp_bootup_bl_level); 3083 } 3084 } 3085 3086 if (result != BP_RESULT_OK) 3087 return result; 3088 else { 3089 // Log each external path 3090 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) { 3091 if (info->ext_disp_conn_info.path[i].device_tag != 0) 3092 DC_LOG_BIOS("integrated_info:For EXTERNAL DISPLAY PATH %d --------------\n" 3093 "DEVICE_TAG: 0x%x\n" 3094 "DEVICE_ACPI_ENUM: 0x%x\n" 3095 "DEVICE_CONNECTOR_ID: 0x%x\n" 3096 "EXT_AUX_DDC_LUT_INDEX: %d\n" 3097 "EXT_HPD_PIN_LUT_INDEX: %d\n" 3098 "EXT_ENCODER_OBJ_ID: 0x%x\n" 3099 "Encoder CAPS: 0x%x\n", 3100 i, 3101 info->ext_disp_conn_info.path[i].device_tag, 3102 info->ext_disp_conn_info.path[i].device_acpi_enum, 3103 info->ext_disp_conn_info.path[i].device_connector_id.id, 3104 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index, 3105 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index, 3106 info->ext_disp_conn_info.path[i].ext_encoder_obj_id.id, 3107 info->ext_disp_conn_info.path[i].caps 3108 ); 3109 if ((info->ext_disp_conn_info.path[i].caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) 3110 DC_LOG_BIOS("BIOS AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i); 3111 else if (bp->base.ctx->dc->config.force_bios_fixed_vs) { 3112 info->ext_disp_conn_info.path[i].caps &= ~AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 3113 info->ext_disp_conn_info.path[i].caps |= AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN; 3114 DC_LOG_BIOS("driver forced AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i); 3115 } 3116 } 3117 // Log the Checksum and Voltage Swing 3118 DC_LOG_BIOS("Integrated info table CHECKSUM: %d\n" 3119 "Integrated info table FIX_DP_VOLTAGE_SWING: %d\n", 3120 info->ext_disp_conn_info.checksum, 3121 info->ext_disp_conn_info.fixdpvoltageswing); 3122 if (bp->base.ctx->dc->config.force_bios_fixed_vs && info->ext_disp_conn_info.fixdpvoltageswing == 0) { 3123 info->ext_disp_conn_info.fixdpvoltageswing = bp->base.ctx->dc->config.force_bios_fixed_vs & 0xF; 3124 DC_LOG_BIOS("driver forced fixdpvoltageswing = %d\n", info->ext_disp_conn_info.fixdpvoltageswing); 3125 } 3126 } 3127 /* Sort voltage table from low to high*/ 3128 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 3129 for (j = i; j > 0; --j) { 3130 if (info->disp_clk_voltage[j].max_supported_clk < 3131 info->disp_clk_voltage[j-1].max_supported_clk) 3132 swap(info->disp_clk_voltage[j-1], info->disp_clk_voltage[j]); 3133 } 3134 } 3135 3136 return result; 3137 } 3138 3139 static enum bp_result bios_parser_get_vram_info( 3140 struct dc_bios *dcb, 3141 struct dc_vram_info *info) 3142 { 3143 struct bios_parser *bp = BP_FROM_DCB(dcb); 3144 enum bp_result result = BP_RESULT_BADBIOSTABLE; 3145 struct atom_common_table_header *header; 3146 struct atom_data_revision revision; 3147 3148 // vram info moved to umc_info for DCN4x 3149 if (info && DATA_TABLES(umc_info)) { 3150 header = GET_IMAGE(struct atom_common_table_header, 3151 DATA_TABLES(umc_info)); 3152 3153 get_atom_data_table_revision(header, &revision); 3154 3155 switch (revision.major) { 3156 case 4: 3157 switch (revision.minor) { 3158 case 0: 3159 result = get_vram_info_from_umc_info_v40(bp, info); 3160 break; 3161 default: 3162 break; 3163 } 3164 break; 3165 default: 3166 break; 3167 } 3168 } 3169 3170 if (result != BP_RESULT_OK && info && DATA_TABLES(vram_info)) { 3171 header = GET_IMAGE(struct atom_common_table_header, 3172 DATA_TABLES(vram_info)); 3173 3174 get_atom_data_table_revision(header, &revision); 3175 3176 switch (revision.major) { 3177 case 2: 3178 switch (revision.minor) { 3179 case 3: 3180 result = get_vram_info_v23(bp, info); 3181 break; 3182 case 4: 3183 result = get_vram_info_v24(bp, info); 3184 break; 3185 case 5: 3186 result = get_vram_info_v25(bp, info); 3187 break; 3188 default: 3189 break; 3190 } 3191 break; 3192 3193 case 3: 3194 switch (revision.minor) { 3195 case 0: 3196 result = get_vram_info_v30(bp, info); 3197 break; 3198 default: 3199 break; 3200 } 3201 break; 3202 3203 default: 3204 return result; 3205 } 3206 3207 } 3208 return result; 3209 } 3210 3211 static struct integrated_info *bios_parser_create_integrated_info( 3212 struct dc_bios *dcb) 3213 { 3214 struct bios_parser *bp = BP_FROM_DCB(dcb); 3215 struct integrated_info *info; 3216 3217 info = kzalloc_obj(struct integrated_info); 3218 3219 if (info == NULL) { 3220 ASSERT_CRITICAL(0); 3221 return NULL; 3222 } 3223 3224 if (construct_integrated_info(bp, info) == BP_RESULT_OK) 3225 return info; 3226 3227 kfree(info); 3228 3229 return NULL; 3230 } 3231 3232 static enum bp_result update_slot_layout_info( 3233 struct dc_bios *dcb, 3234 unsigned int i, 3235 struct slot_layout_info *slot_layout_info) 3236 { 3237 unsigned int record_offset; 3238 unsigned int j; 3239 struct atom_display_object_path_v2 *object; 3240 struct atom_bracket_layout_record *record; 3241 struct atom_common_record_header *record_header; 3242 static enum bp_result result; 3243 struct bios_parser *bp; 3244 struct object_info_table *tbl; 3245 struct display_object_info_table_v1_4 *v1_4; 3246 3247 record = NULL; 3248 record_header = NULL; 3249 result = BP_RESULT_NORECORD; 3250 3251 bp = BP_FROM_DCB(dcb); 3252 tbl = &bp->object_info_tbl; 3253 v1_4 = tbl->v1_4; 3254 3255 object = &v1_4->display_path[i]; 3256 record_offset = (unsigned int) 3257 (object->disp_recordoffset) + 3258 (unsigned int)(bp->object_info_tbl_offset); 3259 3260 for (;;) { 3261 3262 record_header = (struct atom_common_record_header *) 3263 GET_IMAGE(struct atom_common_record_header, 3264 record_offset); 3265 if (record_header == NULL) { 3266 result = BP_RESULT_BADBIOSTABLE; 3267 break; 3268 } 3269 3270 /* the end of the list */ 3271 if (record_header->record_type == 0xff || 3272 record_header->record_size == 0) { 3273 break; 3274 } 3275 3276 if (record_header->record_type == 3277 ATOM_BRACKET_LAYOUT_RECORD_TYPE && 3278 sizeof(struct atom_bracket_layout_record) 3279 <= record_header->record_size) { 3280 record = (struct atom_bracket_layout_record *) 3281 (record_header); 3282 result = BP_RESULT_OK; 3283 break; 3284 } 3285 3286 record_offset += record_header->record_size; 3287 } 3288 3289 /* return if the record not found */ 3290 if (result != BP_RESULT_OK) 3291 return result; 3292 3293 /* get slot sizes */ 3294 slot_layout_info->length = record->bracketlen; 3295 slot_layout_info->width = record->bracketwidth; 3296 3297 /* get info for each connector in the slot */ 3298 slot_layout_info->num_of_connectors = record->conn_num; 3299 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) { 3300 slot_layout_info->connectors[j].connector_type = 3301 (enum connector_layout_type) 3302 (record->conn_info[j].connector_type); 3303 switch (record->conn_info[j].connector_type) { 3304 case CONNECTOR_TYPE_DVI_D: 3305 slot_layout_info->connectors[j].connector_type = 3306 CONNECTOR_LAYOUT_TYPE_DVI_D; 3307 slot_layout_info->connectors[j].length = 3308 CONNECTOR_SIZE_DVI; 3309 break; 3310 3311 case CONNECTOR_TYPE_HDMI: 3312 slot_layout_info->connectors[j].connector_type = 3313 CONNECTOR_LAYOUT_TYPE_HDMI; 3314 slot_layout_info->connectors[j].length = 3315 CONNECTOR_SIZE_HDMI; 3316 break; 3317 3318 case CONNECTOR_TYPE_DISPLAY_PORT: 3319 slot_layout_info->connectors[j].connector_type = 3320 CONNECTOR_LAYOUT_TYPE_DP; 3321 slot_layout_info->connectors[j].length = 3322 CONNECTOR_SIZE_DP; 3323 break; 3324 3325 case CONNECTOR_TYPE_MINI_DISPLAY_PORT: 3326 slot_layout_info->connectors[j].connector_type = 3327 CONNECTOR_LAYOUT_TYPE_MINI_DP; 3328 slot_layout_info->connectors[j].length = 3329 CONNECTOR_SIZE_MINI_DP; 3330 break; 3331 3332 default: 3333 slot_layout_info->connectors[j].connector_type = 3334 CONNECTOR_LAYOUT_TYPE_UNKNOWN; 3335 slot_layout_info->connectors[j].length = 3336 CONNECTOR_SIZE_UNKNOWN; 3337 } 3338 3339 slot_layout_info->connectors[j].position = 3340 record->conn_info[j].position; 3341 slot_layout_info->connectors[j].connector_id = 3342 object_id_from_bios_object_id( 3343 record->conn_info[j].connectorobjid); 3344 } 3345 return result; 3346 } 3347 3348 static enum bp_result update_slot_layout_info_v2( 3349 struct dc_bios *dcb, 3350 unsigned int i, 3351 struct slot_layout_info *slot_layout_info) 3352 { 3353 unsigned int record_offset; 3354 struct atom_display_object_path_v3 *object; 3355 struct atom_bracket_layout_record_v2 *record; 3356 struct atom_common_record_header *record_header; 3357 static enum bp_result result; 3358 struct bios_parser *bp; 3359 struct object_info_table *tbl; 3360 struct display_object_info_table_v1_5 *v1_5; 3361 struct graphics_object_id connector_id; 3362 3363 record = NULL; 3364 record_header = NULL; 3365 result = BP_RESULT_NORECORD; 3366 3367 bp = BP_FROM_DCB(dcb); 3368 tbl = &bp->object_info_tbl; 3369 v1_5 = tbl->v1_5; 3370 3371 object = &v1_5->display_path[i]; 3372 record_offset = (unsigned int) 3373 (object->disp_recordoffset) + 3374 (unsigned int)(bp->object_info_tbl_offset); 3375 3376 for (;;) { 3377 3378 record_header = (struct atom_common_record_header *) 3379 GET_IMAGE(struct atom_common_record_header, 3380 record_offset); 3381 if (record_header == NULL) { 3382 result = BP_RESULT_BADBIOSTABLE; 3383 break; 3384 } 3385 3386 /* the end of the list */ 3387 if (record_header->record_type == ATOM_RECORD_END_TYPE || 3388 record_header->record_size == 0) { 3389 break; 3390 } 3391 3392 if (record_header->record_type == 3393 ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE && 3394 sizeof(struct atom_bracket_layout_record_v2) 3395 <= record_header->record_size) { 3396 record = (struct atom_bracket_layout_record_v2 *) 3397 (record_header); 3398 result = BP_RESULT_OK; 3399 break; 3400 } 3401 3402 record_offset += record_header->record_size; 3403 } 3404 3405 /* return if the record not found */ 3406 if (result != BP_RESULT_OK) 3407 return result; 3408 3409 /* get slot sizes */ 3410 connector_id = object_id_from_bios_object_id(object->display_objid); 3411 3412 slot_layout_info->length = record->bracketlen; 3413 slot_layout_info->width = record->bracketwidth; 3414 slot_layout_info->num_of_connectors = v1_5->number_of_path; 3415 slot_layout_info->connectors[i].position = record->conn_num; 3416 slot_layout_info->connectors[i].connector_id = connector_id; 3417 3418 switch (connector_id.id) { 3419 case CONNECTOR_ID_SINGLE_LINK_DVID: 3420 case CONNECTOR_ID_DUAL_LINK_DVID: 3421 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DVI_D; 3422 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DVI; 3423 break; 3424 3425 case CONNECTOR_ID_HDMI_TYPE_A: 3426 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_HDMI; 3427 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_HDMI; 3428 break; 3429 3430 case CONNECTOR_ID_DISPLAY_PORT: 3431 case CONNECTOR_ID_USBC: 3432 if (record->mini_type == MINI_TYPE_NORMAL) { 3433 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DP; 3434 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DP; 3435 } else { 3436 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_MINI_DP; 3437 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_MINI_DP; 3438 } 3439 break; 3440 3441 default: 3442 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_UNKNOWN; 3443 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_UNKNOWN; 3444 } 3445 return result; 3446 } 3447 3448 static enum bp_result get_bracket_layout_record( 3449 struct dc_bios *dcb, 3450 unsigned int bracket_layout_id, 3451 struct slot_layout_info *slot_layout_info) 3452 { 3453 unsigned int i; 3454 struct bios_parser *bp = BP_FROM_DCB(dcb); 3455 static enum bp_result result; 3456 struct object_info_table *tbl; 3457 struct display_object_info_table_v1_4 *v1_4; 3458 struct display_object_info_table_v1_5 *v1_5; 3459 3460 if (slot_layout_info == NULL) { 3461 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n"); 3462 return BP_RESULT_BADINPUT; 3463 } 3464 3465 tbl = &bp->object_info_tbl; 3466 v1_4 = tbl->v1_4; 3467 v1_5 = tbl->v1_5; 3468 3469 result = BP_RESULT_NORECORD; 3470 switch (bp->object_info_tbl.revision.minor) { 3471 case 4: 3472 default: 3473 for (i = 0; i < v1_4->number_of_path; ++i) { 3474 if (bracket_layout_id == v1_4->display_path[i].display_objid) { 3475 result = update_slot_layout_info(dcb, i, slot_layout_info); 3476 break; 3477 } 3478 } 3479 break; 3480 case 5: 3481 for (i = 0; i < v1_5->number_of_path; ++i) 3482 result = update_slot_layout_info_v2(dcb, i, slot_layout_info); 3483 break; 3484 } 3485 3486 return result; 3487 } 3488 3489 static enum bp_result bios_get_board_layout_info( 3490 struct dc_bios *dcb, 3491 struct board_layout_info *board_layout_info) 3492 { 3493 unsigned int i; 3494 struct bios_parser *bp; 3495 static enum bp_result record_result; 3496 unsigned int max_slots; 3497 3498 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = { 3499 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1, 3500 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2, 3501 0, 0 3502 }; 3503 3504 bp = BP_FROM_DCB(dcb); 3505 3506 if (board_layout_info == NULL) { 3507 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n"); 3508 return BP_RESULT_BADINPUT; 3509 } 3510 3511 board_layout_info->num_of_slots = 0; 3512 max_slots = MAX_BOARD_SLOTS; 3513 3514 // Assume single slot on v1_5 3515 if (bp->object_info_tbl.revision.minor == 5) { 3516 max_slots = 1; 3517 } 3518 3519 for (i = 0; i < max_slots; ++i) { 3520 record_result = get_bracket_layout_record(dcb, 3521 slot_index_to_vbios_id[i], 3522 &board_layout_info->slots[i]); 3523 3524 if (record_result == BP_RESULT_NORECORD && i > 0) 3525 break; /* no more slots present in bios */ 3526 else if (record_result != BP_RESULT_OK) 3527 return record_result; /* fail */ 3528 3529 ++board_layout_info->num_of_slots; 3530 } 3531 3532 /* all data is valid */ 3533 board_layout_info->is_number_of_slots_valid = 1; 3534 board_layout_info->is_slots_size_valid = 1; 3535 board_layout_info->is_connector_offsets_valid = 1; 3536 board_layout_info->is_connector_lengths_valid = 1; 3537 3538 return BP_RESULT_OK; 3539 } 3540 3541 3542 static uint16_t bios_parser_pack_data_tables( 3543 struct dc_bios *dcb, 3544 void *dst) 3545 { 3546 (void)dcb; 3547 (void)dst; 3548 // TODO: There is data bytes alignment issue, disable it for now. 3549 return 0; 3550 } 3551 3552 static struct atom_dc_golden_table_v1 *bios_get_golden_table( 3553 struct bios_parser *bp, 3554 uint32_t rev_major, 3555 uint32_t rev_minor, 3556 uint16_t *dc_golden_table_ver) 3557 { 3558 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL; 3559 uint32_t dc_golden_offset = 0; 3560 *dc_golden_table_ver = 0; 3561 3562 if (!DATA_TABLES(dce_info)) 3563 return NULL; 3564 3565 /* ver.4.4 or higher */ 3566 switch (rev_major) { 3567 case 4: 3568 switch (rev_minor) { 3569 case 4: 3570 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 3571 DATA_TABLES(dce_info)); 3572 if (!disp_cntl_tbl_4_4) 3573 return NULL; 3574 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset; 3575 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver; 3576 break; 3577 case 5: 3578 default: 3579 /* For atom_display_controller_info_v4_5 there is no need to get golden table from 3580 * dc_golden_table_offset as all these fields previously in golden table used for AUX 3581 * pre-charge settings are now available directly in atom_display_controller_info_v4_5. 3582 */ 3583 break; 3584 } 3585 break; 3586 } 3587 3588 if (!dc_golden_offset) 3589 return NULL; 3590 3591 if (*dc_golden_table_ver != 1) 3592 return NULL; 3593 3594 return GET_IMAGE(struct atom_dc_golden_table_v1, 3595 dc_golden_offset); 3596 } 3597 3598 static enum bp_result bios_get_atom_dc_golden_table( 3599 struct dc_bios *dcb) 3600 { 3601 struct bios_parser *bp = BP_FROM_DCB(dcb); 3602 enum bp_result result = BP_RESULT_OK; 3603 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL; 3604 struct atom_common_table_header *header; 3605 struct atom_data_revision tbl_revision; 3606 uint16_t dc_golden_table_ver = 0; 3607 3608 header = GET_IMAGE(struct atom_common_table_header, 3609 DATA_TABLES(dce_info)); 3610 if (!header) 3611 return BP_RESULT_UNSUPPORTED; 3612 3613 get_atom_data_table_revision(header, &tbl_revision); 3614 3615 atom_dc_golden_table = bios_get_golden_table(bp, 3616 tbl_revision.major, 3617 tbl_revision.minor, 3618 &dc_golden_table_ver); 3619 3620 if (!atom_dc_golden_table) 3621 return BP_RESULT_UNSUPPORTED; 3622 3623 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver; 3624 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val; 3625 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val; 3626 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val; 3627 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val; 3628 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val; 3629 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val; 3630 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val; 3631 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val; 3632 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val; 3633 3634 return result; 3635 } 3636 3637 3638 static const struct dc_vbios_funcs vbios_funcs = { 3639 .get_connectors_number = bios_parser_get_connectors_number, 3640 3641 .get_connector_id = bios_parser_get_connector_id, 3642 3643 .get_src_obj = bios_parser_get_src_obj, 3644 3645 .get_i2c_info = bios_parser_get_i2c_info, 3646 3647 .get_hpd_info = bios_parser_get_hpd_info, 3648 3649 .get_device_tag = bios_parser_get_device_tag, 3650 3651 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, 3652 3653 .get_ss_entry_number = bios_parser_get_ss_entry_number, 3654 3655 .get_embedded_panel_info = bios_parser_get_embedded_panel_info, 3656 3657 .get_gpio_pin_info = bios_parser_get_gpio_pin_info, 3658 3659 .get_encoder_cap_info = bios_parser_get_encoder_cap_info, 3660 3661 .is_device_id_supported = bios_parser_is_device_id_supported, 3662 3663 .is_accelerated_mode = bios_parser_is_accelerated_mode, 3664 3665 .set_scratch_critical_state = bios_parser_set_scratch_critical_state, 3666 3667 3668 /* COMMANDS */ 3669 .encoder_control = bios_parser_encoder_control, 3670 3671 .transmitter_control = bios_parser_transmitter_control, 3672 3673 .enable_crtc = bios_parser_enable_crtc, 3674 3675 .set_pixel_clock = bios_parser_set_pixel_clock, 3676 3677 .set_dce_clock = bios_parser_set_dce_clock, 3678 3679 .program_crtc_timing = bios_parser_program_crtc_timing, 3680 3681 .enable_disp_power_gating = bios_parser_enable_disp_power_gating, 3682 3683 .bios_parser_destroy = firmware_parser_destroy, 3684 3685 .get_board_layout_info = bios_get_board_layout_info, 3686 .pack_data_tables = bios_parser_pack_data_tables, 3687 3688 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table, 3689 3690 .enable_lvtma_control = bios_parser_enable_lvtma_control, 3691 3692 .get_soc_bb_info = bios_parser_get_soc_bb_info, 3693 3694 .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info, 3695 3696 .get_lttpr_caps = bios_parser_get_lttpr_caps, 3697 3698 .get_lttpr_interop = bios_parser_get_lttpr_interop, 3699 3700 .get_connector_speed_cap_info = bios_parser_get_connector_speed_cap_info, 3701 }; 3702 3703 static bool bios_parser2_construct( 3704 struct bios_parser *bp, 3705 struct bp_init_data *init, 3706 enum dce_version dce_version) 3707 { 3708 uint16_t *rom_header_offset = NULL; 3709 struct atom_rom_header_v2_2 *rom_header = NULL; 3710 struct display_object_info_table_v1_4 *object_info_tbl; 3711 struct atom_data_revision tbl_rev = {0}; 3712 3713 if (!init) 3714 return false; 3715 3716 if (!init->bios) 3717 return false; 3718 3719 bp->base.funcs = &vbios_funcs; 3720 bp->base.bios = init->bios; 3721 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT; 3722 3723 bp->base.ctx = init->ctx; 3724 3725 bp->base.bios_local_image = NULL; 3726 3727 rom_header_offset = 3728 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 3729 3730 if (!rom_header_offset) 3731 return false; 3732 3733 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 3734 3735 if (!rom_header) 3736 return false; 3737 3738 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 3739 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 3740 return false; 3741 3742 bp->master_data_tbl = 3743 GET_IMAGE(struct atom_master_data_table_v2_1, 3744 rom_header->masterdatatable_offset); 3745 3746 if (!bp->master_data_tbl) 3747 return false; 3748 3749 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo); 3750 3751 if (!bp->object_info_tbl_offset) 3752 return false; 3753 3754 object_info_tbl = 3755 GET_IMAGE(struct display_object_info_table_v1_4, 3756 bp->object_info_tbl_offset); 3757 3758 if (!object_info_tbl) 3759 return false; 3760 3761 get_atom_data_table_revision(&object_info_tbl->table_header, 3762 &bp->object_info_tbl.revision); 3763 3764 if (bp->object_info_tbl.revision.major == 1 3765 && bp->object_info_tbl.revision.minor == 4) { 3766 struct display_object_info_table_v1_4 *tbl_v1_4; 3767 3768 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4, 3769 bp->object_info_tbl_offset); 3770 if (!tbl_v1_4) 3771 return false; 3772 3773 bp->object_info_tbl.v1_4 = tbl_v1_4; 3774 } else if (bp->object_info_tbl.revision.major == 1 3775 && bp->object_info_tbl.revision.minor == 5) { 3776 struct display_object_info_table_v1_5 *tbl_v1_5; 3777 3778 tbl_v1_5 = GET_IMAGE(struct display_object_info_table_v1_5, 3779 bp->object_info_tbl_offset); 3780 if (!tbl_v1_5) 3781 return false; 3782 3783 bp->object_info_tbl.v1_5 = tbl_v1_5; 3784 } else { 3785 ASSERT(0); 3786 return false; 3787 } 3788 3789 dal_firmware_parser_init_cmd_tbl(bp); 3790 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version); 3791 3792 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); 3793 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK; 3794 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info); 3795 bios_parser_get_soc_bb_info(&bp->base, &bp->base.bb_info); 3796 return true; 3797 } 3798 3799 struct dc_bios *firmware_parser_create( 3800 struct bp_init_data *init, 3801 enum dce_version dce_version) 3802 { 3803 struct bios_parser *bp; 3804 3805 bp = kzalloc_obj(struct bios_parser); 3806 if (!bp) 3807 return NULL; 3808 3809 if (bios_parser2_construct(bp, init, dce_version)) 3810 return &bp->base; 3811 3812 kfree(bp); 3813 return NULL; 3814 } 3815 3816 3817