1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2024 ROHM Semiconductors
4 *
5 * ROHM BD96801 PMIC driver
6 *
7 * This version of the "BD86801 scalable PMIC"'s driver supports only very
8 * basic set of the PMIC features. Most notably, there is no support for
9 * the ERRB interrupt and the configurations which should be done when the
10 * PMIC is in STBY mode.
11 *
12 * Supporting the ERRB interrupt would require dropping the regmap-IRQ
13 * usage or working around (or accepting a presense of) a naming conflict
14 * in debugFS IRQs.
15 *
16 * Being able to reliably do the configurations like changing the
17 * regulator safety limits (like limits for the over/under -voltages, over
18 * current, thermal protection) would require the configuring driver to be
19 * synchronized with entity causing the PMIC state transitions. Eg, one
20 * should be able to ensure the PMIC is in STBY state when the
21 * configurations are applied to the hardware. How and when the PMIC state
22 * transitions are to be done is likely to be very system specific, as will
23 * be the need to configure these safety limits. Hence it's not simple to
24 * come up with a generic solution.
25 *
26 * Users who require the ERRB handling and STBY state configurations can
27 * have a look at the original RFC:
28 * https://lore.kernel.org/all/cover.1712920132.git.mazziesaccount@gmail.com/
29 * which implements a workaround to debugFS naming conflict and some of
30 * the safety limit configurations - but leaves the state change handling
31 * and synchronization to be implemented.
32 *
33 * It would be great to hear (and receive a patch!) if you implement the
34 * STBY configuration support or a proper fix to the debugFS naming
35 * conflict in your downstream driver ;)
36 */
37
38 #include <linux/i2c.h>
39 #include <linux/interrupt.h>
40 #include <linux/mfd/core.h>
41 #include <linux/module.h>
42 #include <linux/property.h>
43 #include <linux/regmap.h>
44 #include <linux/types.h>
45
46 #include <linux/mfd/rohm-bd96801.h>
47 #include <linux/mfd/rohm-generic.h>
48
49 static const struct resource regulator_intb_irqs[] = {
50 DEFINE_RES_IRQ_NAMED(BD96801_TW_STAT, "bd96801-core-thermal"),
51
52 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPH_STAT, "bd96801-buck1-overcurr-h"),
53 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPL_STAT, "bd96801-buck1-overcurr-l"),
54 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPN_STAT, "bd96801-buck1-overcurr-n"),
55 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OVD_STAT, "bd96801-buck1-overvolt"),
56 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_UVD_STAT, "bd96801-buck1-undervolt"),
57 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_TW_CH_STAT, "bd96801-buck1-thermal"),
58
59 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPH_STAT, "bd96801-buck2-overcurr-h"),
60 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPL_STAT, "bd96801-buck2-overcurr-l"),
61 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPN_STAT, "bd96801-buck2-overcurr-n"),
62 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OVD_STAT, "bd96801-buck2-overvolt"),
63 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_UVD_STAT, "bd96801-buck2-undervolt"),
64 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_TW_CH_STAT, "bd96801-buck2-thermal"),
65
66 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPH_STAT, "bd96801-buck3-overcurr-h"),
67 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPL_STAT, "bd96801-buck3-overcurr-l"),
68 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPN_STAT, "bd96801-buck3-overcurr-n"),
69 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OVD_STAT, "bd96801-buck3-overvolt"),
70 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_UVD_STAT, "bd96801-buck3-undervolt"),
71 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_TW_CH_STAT, "bd96801-buck3-thermal"),
72
73 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPH_STAT, "bd96801-buck4-overcurr-h"),
74 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPL_STAT, "bd96801-buck4-overcurr-l"),
75 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPN_STAT, "bd96801-buck4-overcurr-n"),
76 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OVD_STAT, "bd96801-buck4-overvolt"),
77 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_UVD_STAT, "bd96801-buck4-undervolt"),
78 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_TW_CH_STAT, "bd96801-buck4-thermal"),
79
80 DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OCPH_STAT, "bd96801-ldo5-overcurr"),
81 DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OVD_STAT, "bd96801-ldo5-overvolt"),
82 DEFINE_RES_IRQ_NAMED(BD96801_LDO5_UVD_STAT, "bd96801-ldo5-undervolt"),
83
84 DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OCPH_STAT, "bd96801-ldo6-overcurr"),
85 DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OVD_STAT, "bd96801-ldo6-overvolt"),
86 DEFINE_RES_IRQ_NAMED(BD96801_LDO6_UVD_STAT, "bd96801-ldo6-undervolt"),
87
88 DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OCPH_STAT, "bd96801-ldo7-overcurr"),
89 DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OVD_STAT, "bd96801-ldo7-overvolt"),
90 DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVD_STAT, "bd96801-ldo7-undervolt"),
91 };
92
93 static const struct resource wdg_intb_irqs[] = {
94 DEFINE_RES_IRQ_NAMED(BD96801_WDT_ERR_STAT, "bd96801-wdg"),
95 };
96
97 static struct mfd_cell bd96801_cells[] = {
98 {
99 .name = "bd96801-wdt",
100 .resources = wdg_intb_irqs,
101 .num_resources = ARRAY_SIZE(wdg_intb_irqs),
102 }, {
103 .name = "bd96801-regulator",
104 .resources = regulator_intb_irqs,
105 .num_resources = ARRAY_SIZE(regulator_intb_irqs),
106 },
107 };
108
109 static const struct regmap_range bd96801_volatile_ranges[] = {
110 /* Status registers */
111 regmap_reg_range(BD96801_REG_WD_FEED, BD96801_REG_WD_FAILCOUNT),
112 regmap_reg_range(BD96801_REG_WD_ASK, BD96801_REG_WD_ASK),
113 regmap_reg_range(BD96801_REG_WD_STATUS, BD96801_REG_WD_STATUS),
114 regmap_reg_range(BD96801_REG_PMIC_STATE, BD96801_REG_INT_LDO7_INTB),
115 /* Registers which do not update value unless PMIC is in STBY */
116 regmap_reg_range(BD96801_REG_SSCG_CTRL, BD96801_REG_SHD_INTB),
117 regmap_reg_range(BD96801_REG_BUCK_OVP, BD96801_REG_BOOT_OVERTIME),
118 /*
119 * LDO control registers have single bit (LDO MODE) which does not
120 * change when we write it unless PMIC is in STBY. It's safer to not
121 * cache it.
122 */
123 regmap_reg_range(BD96801_LDO5_VOL_LVL_REG, BD96801_LDO7_VOL_LVL_REG),
124 };
125
126 static const struct regmap_access_table volatile_regs = {
127 .yes_ranges = bd96801_volatile_ranges,
128 .n_yes_ranges = ARRAY_SIZE(bd96801_volatile_ranges),
129 };
130
131 static const struct regmap_irq bd96801_intb_irqs[] = {
132 /* STATUS SYSTEM INTB */
133 REGMAP_IRQ_REG(BD96801_TW_STAT, 0, BD96801_TW_STAT_MASK),
134 REGMAP_IRQ_REG(BD96801_WDT_ERR_STAT, 0, BD96801_WDT_ERR_STAT_MASK),
135 REGMAP_IRQ_REG(BD96801_I2C_ERR_STAT, 0, BD96801_I2C_ERR_STAT_MASK),
136 REGMAP_IRQ_REG(BD96801_CHIP_IF_ERR_STAT, 0, BD96801_CHIP_IF_ERR_STAT_MASK),
137 /* STATUS BUCK1 INTB */
138 REGMAP_IRQ_REG(BD96801_BUCK1_OCPH_STAT, 1, BD96801_BUCK_OCPH_STAT_MASK),
139 REGMAP_IRQ_REG(BD96801_BUCK1_OCPL_STAT, 1, BD96801_BUCK_OCPL_STAT_MASK),
140 REGMAP_IRQ_REG(BD96801_BUCK1_OCPN_STAT, 1, BD96801_BUCK_OCPN_STAT_MASK),
141 REGMAP_IRQ_REG(BD96801_BUCK1_OVD_STAT, 1, BD96801_BUCK_OVD_STAT_MASK),
142 REGMAP_IRQ_REG(BD96801_BUCK1_UVD_STAT, 1, BD96801_BUCK_UVD_STAT_MASK),
143 REGMAP_IRQ_REG(BD96801_BUCK1_TW_CH_STAT, 1, BD96801_BUCK_TW_CH_STAT_MASK),
144 /* BUCK 2 INTB */
145 REGMAP_IRQ_REG(BD96801_BUCK2_OCPH_STAT, 2, BD96801_BUCK_OCPH_STAT_MASK),
146 REGMAP_IRQ_REG(BD96801_BUCK2_OCPL_STAT, 2, BD96801_BUCK_OCPL_STAT_MASK),
147 REGMAP_IRQ_REG(BD96801_BUCK2_OCPN_STAT, 2, BD96801_BUCK_OCPN_STAT_MASK),
148 REGMAP_IRQ_REG(BD96801_BUCK2_OVD_STAT, 2, BD96801_BUCK_OVD_STAT_MASK),
149 REGMAP_IRQ_REG(BD96801_BUCK2_UVD_STAT, 2, BD96801_BUCK_UVD_STAT_MASK),
150 REGMAP_IRQ_REG(BD96801_BUCK2_TW_CH_STAT, 2, BD96801_BUCK_TW_CH_STAT_MASK),
151 /* BUCK 3 INTB */
152 REGMAP_IRQ_REG(BD96801_BUCK3_OCPH_STAT, 3, BD96801_BUCK_OCPH_STAT_MASK),
153 REGMAP_IRQ_REG(BD96801_BUCK3_OCPL_STAT, 3, BD96801_BUCK_OCPL_STAT_MASK),
154 REGMAP_IRQ_REG(BD96801_BUCK3_OCPN_STAT, 3, BD96801_BUCK_OCPN_STAT_MASK),
155 REGMAP_IRQ_REG(BD96801_BUCK3_OVD_STAT, 3, BD96801_BUCK_OVD_STAT_MASK),
156 REGMAP_IRQ_REG(BD96801_BUCK3_UVD_STAT, 3, BD96801_BUCK_UVD_STAT_MASK),
157 REGMAP_IRQ_REG(BD96801_BUCK3_TW_CH_STAT, 3, BD96801_BUCK_TW_CH_STAT_MASK),
158 /* BUCK 4 INTB */
159 REGMAP_IRQ_REG(BD96801_BUCK4_OCPH_STAT, 4, BD96801_BUCK_OCPH_STAT_MASK),
160 REGMAP_IRQ_REG(BD96801_BUCK4_OCPL_STAT, 4, BD96801_BUCK_OCPL_STAT_MASK),
161 REGMAP_IRQ_REG(BD96801_BUCK4_OCPN_STAT, 4, BD96801_BUCK_OCPN_STAT_MASK),
162 REGMAP_IRQ_REG(BD96801_BUCK4_OVD_STAT, 4, BD96801_BUCK_OVD_STAT_MASK),
163 REGMAP_IRQ_REG(BD96801_BUCK4_UVD_STAT, 4, BD96801_BUCK_UVD_STAT_MASK),
164 REGMAP_IRQ_REG(BD96801_BUCK4_TW_CH_STAT, 4, BD96801_BUCK_TW_CH_STAT_MASK),
165 /* LDO5 INTB */
166 REGMAP_IRQ_REG(BD96801_LDO5_OCPH_STAT, 5, BD96801_LDO_OCPH_STAT_MASK),
167 REGMAP_IRQ_REG(BD96801_LDO5_OVD_STAT, 5, BD96801_LDO_OVD_STAT_MASK),
168 REGMAP_IRQ_REG(BD96801_LDO5_UVD_STAT, 5, BD96801_LDO_UVD_STAT_MASK),
169 /* LDO6 INTB */
170 REGMAP_IRQ_REG(BD96801_LDO6_OCPH_STAT, 6, BD96801_LDO_OCPH_STAT_MASK),
171 REGMAP_IRQ_REG(BD96801_LDO6_OVD_STAT, 6, BD96801_LDO_OVD_STAT_MASK),
172 REGMAP_IRQ_REG(BD96801_LDO6_UVD_STAT, 6, BD96801_LDO_UVD_STAT_MASK),
173 /* LDO7 INTB */
174 REGMAP_IRQ_REG(BD96801_LDO7_OCPH_STAT, 7, BD96801_LDO_OCPH_STAT_MASK),
175 REGMAP_IRQ_REG(BD96801_LDO7_OVD_STAT, 7, BD96801_LDO_OVD_STAT_MASK),
176 REGMAP_IRQ_REG(BD96801_LDO7_UVD_STAT, 7, BD96801_LDO_UVD_STAT_MASK),
177 };
178
179 static struct regmap_irq_chip bd96801_irq_chip_intb = {
180 .name = "bd96801-irq-intb",
181 .main_status = BD96801_REG_INT_MAIN,
182 .num_main_regs = 1,
183 .irqs = &bd96801_intb_irqs[0],
184 .num_irqs = ARRAY_SIZE(bd96801_intb_irqs),
185 .status_base = BD96801_REG_INT_SYS_INTB,
186 .mask_base = BD96801_REG_MASK_SYS_INTB,
187 .ack_base = BD96801_REG_INT_SYS_INTB,
188 .init_ack_masked = true,
189 .num_regs = 8,
190 .irq_reg_stride = 1,
191 };
192
193 static const struct regmap_config bd96801_regmap_config = {
194 .reg_bits = 8,
195 .val_bits = 8,
196 .volatile_table = &volatile_regs,
197 .cache_type = REGCACHE_RBTREE,
198 };
199
bd96801_i2c_probe(struct i2c_client * i2c)200 static int bd96801_i2c_probe(struct i2c_client *i2c)
201 {
202 struct regmap_irq_chip_data *intb_irq_data;
203 const struct fwnode_handle *fwnode;
204 struct irq_domain *intb_domain;
205 struct regmap *regmap;
206 int ret, intb_irq;
207
208 fwnode = dev_fwnode(&i2c->dev);
209 if (!fwnode)
210 return dev_err_probe(&i2c->dev, -EINVAL, "Failed to find fwnode\n");
211
212 intb_irq = fwnode_irq_get_byname(fwnode, "intb");
213 if (intb_irq < 0)
214 return dev_err_probe(&i2c->dev, intb_irq, "INTB IRQ not configured\n");
215
216 regmap = devm_regmap_init_i2c(i2c, &bd96801_regmap_config);
217 if (IS_ERR(regmap))
218 return dev_err_probe(&i2c->dev, PTR_ERR(regmap),
219 "Regmap initialization failed\n");
220
221 ret = regmap_write(regmap, BD96801_LOCK_REG, BD96801_UNLOCK);
222 if (ret)
223 return dev_err_probe(&i2c->dev, ret, "Failed to unlock PMIC\n");
224
225 ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, intb_irq,
226 IRQF_ONESHOT, 0, &bd96801_irq_chip_intb,
227 &intb_irq_data);
228 if (ret)
229 return dev_err_probe(&i2c->dev, ret, "Failed to add INTB IRQ chip\n");
230
231 intb_domain = regmap_irq_get_domain(intb_irq_data);
232
233 ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO,
234 bd96801_cells,
235 ARRAY_SIZE(bd96801_cells), NULL, 0,
236 intb_domain);
237 if (ret)
238 dev_err(&i2c->dev, "Failed to create subdevices\n");
239
240 return ret;
241 }
242
243 static const struct of_device_id bd96801_of_match[] = {
244 { .compatible = "rohm,bd96801", },
245 { }
246 };
247 MODULE_DEVICE_TABLE(of, bd96801_of_match);
248
249 static struct i2c_driver bd96801_i2c_driver = {
250 .driver = {
251 .name = "rohm-bd96801",
252 .of_match_table = bd96801_of_match,
253 },
254 .probe = bd96801_i2c_probe,
255 };
256
bd96801_i2c_init(void)257 static int __init bd96801_i2c_init(void)
258 {
259 return i2c_add_driver(&bd96801_i2c_driver);
260 }
261
262 /* Initialise early so consumer devices can complete system boot */
263 subsys_initcall(bd96801_i2c_init);
264
bd96801_i2c_exit(void)265 static void __exit bd96801_i2c_exit(void)
266 {
267 i2c_del_driver(&bd96801_i2c_driver);
268 }
269 module_exit(bd96801_i2c_exit);
270
271 MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
272 MODULE_DESCRIPTION("ROHM BD96801 Power Management IC driver");
273 MODULE_LICENSE("GPL");
274