1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Broadcom GENET (Gigabit Ethernet) controller driver
4 *
5 * Copyright (c) 2014-2025 Broadcom
6 */
7
8 #define pr_fmt(fmt) "bcmgenet: " fmt
9
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/sched.h>
14 #include <linux/types.h>
15 #include <linux/fcntl.h>
16 #include <linux/interrupt.h>
17 #include <linux/string.h>
18 #include <linux/if_ether.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/delay.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/pm.h>
25 #include <linux/clk.h>
26 #include <net/arp.h>
27
28 #include <linux/mii.h>
29 #include <linux/ethtool.h>
30 #include <linux/netdevice.h>
31 #include <linux/inetdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/ipv6.h>
37 #include <linux/phy.h>
38 #include <linux/platform_data/bcmgenet.h>
39
40 #include <linux/unaligned.h>
41
42 #include "bcmgenet.h"
43
44 /* Default highest priority queue for multi queue support */
45 #define GENET_Q1_PRIORITY 0
46 #define GENET_Q0_PRIORITY 1
47
48 #define GENET_Q0_RX_BD_CNT \
49 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
50 #define GENET_Q0_TX_BD_CNT \
51 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
52
53 #define RX_BUF_LENGTH 2048
54 #define SKB_ALIGNMENT 32
55
56 /* Tx/Rx DMA register offset, skip 256 descriptors */
57 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
58 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
59
60 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
61 TOTAL_DESC * DMA_DESC_SIZE)
62
63 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
64 TOTAL_DESC * DMA_DESC_SIZE)
65
66 /* Forward declarations */
67 static void bcmgenet_set_rx_mode(struct net_device *dev);
68
bcmgenet_writel(u32 value,void __iomem * offset)69 static inline void bcmgenet_writel(u32 value, void __iomem *offset)
70 {
71 /* MIPS chips strapped for BE will automagically configure the
72 * peripheral registers for CPU-native byte order.
73 */
74 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
75 __raw_writel(value, offset);
76 else
77 writel_relaxed(value, offset);
78 }
79
bcmgenet_readl(void __iomem * offset)80 static inline u32 bcmgenet_readl(void __iomem *offset)
81 {
82 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
83 return __raw_readl(offset);
84 else
85 return readl_relaxed(offset);
86 }
87
dmadesc_set_length_status(struct bcmgenet_priv * priv,void __iomem * d,u32 value)88 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
89 void __iomem *d, u32 value)
90 {
91 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
92 }
93
dmadesc_set_addr(struct bcmgenet_priv * priv,void __iomem * d,dma_addr_t addr)94 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
95 void __iomem *d,
96 dma_addr_t addr)
97 {
98 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
99
100 /* Register writes to GISB bus can take couple hundred nanoseconds
101 * and are done for each packet, save these expensive writes unless
102 * the platform is explicitly configured for 64-bits/LPAE.
103 */
104 #ifdef CONFIG_PHYS_ADDR_T_64BIT
105 if (bcmgenet_has_40bits(priv))
106 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
107 #endif
108 }
109
110 /* Combined address + length/status setter */
dmadesc_set(struct bcmgenet_priv * priv,void __iomem * d,dma_addr_t addr,u32 val)111 static inline void dmadesc_set(struct bcmgenet_priv *priv,
112 void __iomem *d, dma_addr_t addr, u32 val)
113 {
114 dmadesc_set_addr(priv, d, addr);
115 dmadesc_set_length_status(priv, d, val);
116 }
117
118 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
119
120 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
121 NETIF_MSG_LINK)
122
bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv * priv)123 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
124 {
125 if (GENET_IS_V1(priv))
126 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
127 else
128 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
129 }
130
bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv * priv,u32 val)131 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
132 {
133 if (GENET_IS_V1(priv))
134 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
135 else
136 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
137 }
138
139 /* These macros are defined to deal with register map change
140 * between GENET1.1 and GENET2. Only those currently being used
141 * by driver are defined.
142 */
bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv * priv)143 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
144 {
145 if (GENET_IS_V1(priv))
146 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
147 else
148 return bcmgenet_readl(priv->base +
149 priv->hw_params->tbuf_offset + TBUF_CTRL);
150 }
151
bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv * priv,u32 val)152 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
153 {
154 if (GENET_IS_V1(priv))
155 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
156 else
157 bcmgenet_writel(val, priv->base +
158 priv->hw_params->tbuf_offset + TBUF_CTRL);
159 }
160
bcmgenet_bp_mc_get(struct bcmgenet_priv * priv)161 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
162 {
163 if (GENET_IS_V1(priv))
164 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
165 else
166 return bcmgenet_readl(priv->base +
167 priv->hw_params->tbuf_offset + TBUF_BP_MC);
168 }
169
bcmgenet_bp_mc_set(struct bcmgenet_priv * priv,u32 val)170 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
171 {
172 if (GENET_IS_V1(priv))
173 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
174 else
175 bcmgenet_writel(val, priv->base +
176 priv->hw_params->tbuf_offset + TBUF_BP_MC);
177 }
178
179 /* RX/TX DMA register accessors */
180 enum dma_reg {
181 DMA_RING_CFG = 0,
182 DMA_CTRL,
183 DMA_STATUS,
184 DMA_SCB_BURST_SIZE,
185 DMA_ARB_CTRL,
186 DMA_PRIORITY_0,
187 DMA_PRIORITY_1,
188 DMA_PRIORITY_2,
189 DMA_INDEX2RING_0,
190 DMA_INDEX2RING_1,
191 DMA_INDEX2RING_2,
192 DMA_INDEX2RING_3,
193 DMA_INDEX2RING_4,
194 DMA_INDEX2RING_5,
195 DMA_INDEX2RING_6,
196 DMA_INDEX2RING_7,
197 DMA_RING0_TIMEOUT,
198 DMA_RING1_TIMEOUT,
199 DMA_RING2_TIMEOUT,
200 DMA_RING3_TIMEOUT,
201 DMA_RING4_TIMEOUT,
202 DMA_RING5_TIMEOUT,
203 DMA_RING6_TIMEOUT,
204 DMA_RING7_TIMEOUT,
205 DMA_RING8_TIMEOUT,
206 DMA_RING9_TIMEOUT,
207 DMA_RING10_TIMEOUT,
208 DMA_RING11_TIMEOUT,
209 DMA_RING12_TIMEOUT,
210 DMA_RING13_TIMEOUT,
211 DMA_RING14_TIMEOUT,
212 DMA_RING15_TIMEOUT,
213 DMA_RING16_TIMEOUT,
214 };
215
216 static const u8 bcmgenet_dma_regs_v3plus[] = {
217 [DMA_RING_CFG] = 0x00,
218 [DMA_CTRL] = 0x04,
219 [DMA_STATUS] = 0x08,
220 [DMA_SCB_BURST_SIZE] = 0x0C,
221 [DMA_ARB_CTRL] = 0x2C,
222 [DMA_PRIORITY_0] = 0x30,
223 [DMA_PRIORITY_1] = 0x34,
224 [DMA_PRIORITY_2] = 0x38,
225 [DMA_RING0_TIMEOUT] = 0x2C,
226 [DMA_RING1_TIMEOUT] = 0x30,
227 [DMA_RING2_TIMEOUT] = 0x34,
228 [DMA_RING3_TIMEOUT] = 0x38,
229 [DMA_RING4_TIMEOUT] = 0x3c,
230 [DMA_RING5_TIMEOUT] = 0x40,
231 [DMA_RING6_TIMEOUT] = 0x44,
232 [DMA_RING7_TIMEOUT] = 0x48,
233 [DMA_RING8_TIMEOUT] = 0x4c,
234 [DMA_RING9_TIMEOUT] = 0x50,
235 [DMA_RING10_TIMEOUT] = 0x54,
236 [DMA_RING11_TIMEOUT] = 0x58,
237 [DMA_RING12_TIMEOUT] = 0x5c,
238 [DMA_RING13_TIMEOUT] = 0x60,
239 [DMA_RING14_TIMEOUT] = 0x64,
240 [DMA_RING15_TIMEOUT] = 0x68,
241 [DMA_RING16_TIMEOUT] = 0x6C,
242 [DMA_INDEX2RING_0] = 0x70,
243 [DMA_INDEX2RING_1] = 0x74,
244 [DMA_INDEX2RING_2] = 0x78,
245 [DMA_INDEX2RING_3] = 0x7C,
246 [DMA_INDEX2RING_4] = 0x80,
247 [DMA_INDEX2RING_5] = 0x84,
248 [DMA_INDEX2RING_6] = 0x88,
249 [DMA_INDEX2RING_7] = 0x8C,
250 };
251
252 static const u8 bcmgenet_dma_regs_v2[] = {
253 [DMA_RING_CFG] = 0x00,
254 [DMA_CTRL] = 0x04,
255 [DMA_STATUS] = 0x08,
256 [DMA_SCB_BURST_SIZE] = 0x0C,
257 [DMA_ARB_CTRL] = 0x30,
258 [DMA_PRIORITY_0] = 0x34,
259 [DMA_PRIORITY_1] = 0x38,
260 [DMA_PRIORITY_2] = 0x3C,
261 [DMA_RING0_TIMEOUT] = 0x2C,
262 [DMA_RING1_TIMEOUT] = 0x30,
263 [DMA_RING2_TIMEOUT] = 0x34,
264 [DMA_RING3_TIMEOUT] = 0x38,
265 [DMA_RING4_TIMEOUT] = 0x3c,
266 [DMA_RING5_TIMEOUT] = 0x40,
267 [DMA_RING6_TIMEOUT] = 0x44,
268 [DMA_RING7_TIMEOUT] = 0x48,
269 [DMA_RING8_TIMEOUT] = 0x4c,
270 [DMA_RING9_TIMEOUT] = 0x50,
271 [DMA_RING10_TIMEOUT] = 0x54,
272 [DMA_RING11_TIMEOUT] = 0x58,
273 [DMA_RING12_TIMEOUT] = 0x5c,
274 [DMA_RING13_TIMEOUT] = 0x60,
275 [DMA_RING14_TIMEOUT] = 0x64,
276 [DMA_RING15_TIMEOUT] = 0x68,
277 [DMA_RING16_TIMEOUT] = 0x6C,
278 };
279
280 static const u8 bcmgenet_dma_regs_v1[] = {
281 [DMA_CTRL] = 0x00,
282 [DMA_STATUS] = 0x04,
283 [DMA_SCB_BURST_SIZE] = 0x0C,
284 [DMA_ARB_CTRL] = 0x30,
285 [DMA_PRIORITY_0] = 0x34,
286 [DMA_PRIORITY_1] = 0x38,
287 [DMA_PRIORITY_2] = 0x3C,
288 [DMA_RING0_TIMEOUT] = 0x2C,
289 [DMA_RING1_TIMEOUT] = 0x30,
290 [DMA_RING2_TIMEOUT] = 0x34,
291 [DMA_RING3_TIMEOUT] = 0x38,
292 [DMA_RING4_TIMEOUT] = 0x3c,
293 [DMA_RING5_TIMEOUT] = 0x40,
294 [DMA_RING6_TIMEOUT] = 0x44,
295 [DMA_RING7_TIMEOUT] = 0x48,
296 [DMA_RING8_TIMEOUT] = 0x4c,
297 [DMA_RING9_TIMEOUT] = 0x50,
298 [DMA_RING10_TIMEOUT] = 0x54,
299 [DMA_RING11_TIMEOUT] = 0x58,
300 [DMA_RING12_TIMEOUT] = 0x5c,
301 [DMA_RING13_TIMEOUT] = 0x60,
302 [DMA_RING14_TIMEOUT] = 0x64,
303 [DMA_RING15_TIMEOUT] = 0x68,
304 [DMA_RING16_TIMEOUT] = 0x6C,
305 };
306
307 /* Set at runtime once bcmgenet version is known */
308 static const u8 *bcmgenet_dma_regs;
309
dev_to_priv(struct device * dev)310 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
311 {
312 return netdev_priv(dev_get_drvdata(dev));
313 }
314
bcmgenet_tdma_readl(struct bcmgenet_priv * priv,enum dma_reg r)315 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
316 enum dma_reg r)
317 {
318 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
319 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
320 }
321
bcmgenet_tdma_writel(struct bcmgenet_priv * priv,u32 val,enum dma_reg r)322 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
323 u32 val, enum dma_reg r)
324 {
325 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
326 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
327 }
328
bcmgenet_rdma_readl(struct bcmgenet_priv * priv,enum dma_reg r)329 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
330 enum dma_reg r)
331 {
332 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
333 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
334 }
335
bcmgenet_rdma_writel(struct bcmgenet_priv * priv,u32 val,enum dma_reg r)336 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
337 u32 val, enum dma_reg r)
338 {
339 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
340 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
341 }
342
343 /* RDMA/TDMA ring registers and accessors
344 * we merge the common fields and just prefix with T/D the registers
345 * having different meaning depending on the direction
346 */
347 enum dma_ring_reg {
348 TDMA_READ_PTR = 0,
349 RDMA_WRITE_PTR = TDMA_READ_PTR,
350 TDMA_READ_PTR_HI,
351 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
352 TDMA_CONS_INDEX,
353 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
354 TDMA_PROD_INDEX,
355 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
356 DMA_RING_BUF_SIZE,
357 DMA_START_ADDR,
358 DMA_START_ADDR_HI,
359 DMA_END_ADDR,
360 DMA_END_ADDR_HI,
361 DMA_MBUF_DONE_THRESH,
362 TDMA_FLOW_PERIOD,
363 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
364 TDMA_WRITE_PTR,
365 RDMA_READ_PTR = TDMA_WRITE_PTR,
366 TDMA_WRITE_PTR_HI,
367 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
368 };
369
370 /* GENET v4 supports 40-bits pointer addressing
371 * for obvious reasons the LO and HI word parts
372 * are contiguous, but this offsets the other
373 * registers.
374 */
375 static const u8 genet_dma_ring_regs_v4[] = {
376 [TDMA_READ_PTR] = 0x00,
377 [TDMA_READ_PTR_HI] = 0x04,
378 [TDMA_CONS_INDEX] = 0x08,
379 [TDMA_PROD_INDEX] = 0x0C,
380 [DMA_RING_BUF_SIZE] = 0x10,
381 [DMA_START_ADDR] = 0x14,
382 [DMA_START_ADDR_HI] = 0x18,
383 [DMA_END_ADDR] = 0x1C,
384 [DMA_END_ADDR_HI] = 0x20,
385 [DMA_MBUF_DONE_THRESH] = 0x24,
386 [TDMA_FLOW_PERIOD] = 0x28,
387 [TDMA_WRITE_PTR] = 0x2C,
388 [TDMA_WRITE_PTR_HI] = 0x30,
389 };
390
391 static const u8 genet_dma_ring_regs_v123[] = {
392 [TDMA_READ_PTR] = 0x00,
393 [TDMA_CONS_INDEX] = 0x04,
394 [TDMA_PROD_INDEX] = 0x08,
395 [DMA_RING_BUF_SIZE] = 0x0C,
396 [DMA_START_ADDR] = 0x10,
397 [DMA_END_ADDR] = 0x14,
398 [DMA_MBUF_DONE_THRESH] = 0x18,
399 [TDMA_FLOW_PERIOD] = 0x1C,
400 [TDMA_WRITE_PTR] = 0x20,
401 };
402
403 /* Set at runtime once GENET version is known */
404 static const u8 *genet_dma_ring_regs;
405
bcmgenet_tdma_ring_readl(struct bcmgenet_priv * priv,unsigned int ring,enum dma_ring_reg r)406 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
407 unsigned int ring,
408 enum dma_ring_reg r)
409 {
410 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
411 (DMA_RING_SIZE * ring) +
412 genet_dma_ring_regs[r]);
413 }
414
bcmgenet_tdma_ring_writel(struct bcmgenet_priv * priv,unsigned int ring,u32 val,enum dma_ring_reg r)415 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
416 unsigned int ring, u32 val,
417 enum dma_ring_reg r)
418 {
419 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
420 (DMA_RING_SIZE * ring) +
421 genet_dma_ring_regs[r]);
422 }
423
bcmgenet_rdma_ring_readl(struct bcmgenet_priv * priv,unsigned int ring,enum dma_ring_reg r)424 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
425 unsigned int ring,
426 enum dma_ring_reg r)
427 {
428 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
429 (DMA_RING_SIZE * ring) +
430 genet_dma_ring_regs[r]);
431 }
432
bcmgenet_rdma_ring_writel(struct bcmgenet_priv * priv,unsigned int ring,u32 val,enum dma_ring_reg r)433 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
434 unsigned int ring, u32 val,
435 enum dma_ring_reg r)
436 {
437 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
438 (DMA_RING_SIZE * ring) +
439 genet_dma_ring_regs[r]);
440 }
441
bcmgenet_hfb_enable_filter(struct bcmgenet_priv * priv,u32 f_index)442 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
443 {
444 u32 offset;
445 u32 reg;
446
447 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) {
448 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
449 reg |= (1 << ((f_index % 32) + RBUF_HFB_FILTER_EN_SHIFT)) |
450 RBUF_HFB_EN;
451 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
452 } else {
453 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
454 reg = bcmgenet_hfb_reg_readl(priv, offset);
455 reg |= (1 << (f_index % 32));
456 bcmgenet_hfb_reg_writel(priv, reg, offset);
457 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
458 reg |= RBUF_HFB_EN;
459 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
460 }
461 }
462
bcmgenet_hfb_disable_filter(struct bcmgenet_priv * priv,u32 f_index)463 static void bcmgenet_hfb_disable_filter(struct bcmgenet_priv *priv, u32 f_index)
464 {
465 u32 offset, reg, reg1;
466
467 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) {
468 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
469 reg &= ~(1 << ((f_index % 32) + RBUF_HFB_FILTER_EN_SHIFT));
470 if (!(reg & RBUF_HFB_FILTER_EN_MASK))
471 reg &= ~RBUF_HFB_EN;
472 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
473 } else {
474 offset = HFB_FLT_ENABLE_V3PLUS;
475 reg = bcmgenet_hfb_reg_readl(priv, offset);
476 reg1 = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32));
477 if (f_index < 32) {
478 reg1 &= ~(1 << (f_index % 32));
479 bcmgenet_hfb_reg_writel(priv, reg1, offset + sizeof(u32));
480 } else {
481 reg &= ~(1 << (f_index % 32));
482 bcmgenet_hfb_reg_writel(priv, reg, offset);
483 }
484 if (!reg && !reg1) {
485 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
486 reg &= ~RBUF_HFB_EN;
487 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
488 }
489 }
490 }
491
bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv * priv,u32 f_index,u32 rx_queue)492 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
493 u32 f_index, u32 rx_queue)
494 {
495 u32 offset;
496 u32 reg;
497
498 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
499 return;
500
501 offset = f_index / 8;
502 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
503 reg &= ~(0xF << (4 * (f_index % 8)));
504 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
505 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
506 }
507
bcmgenet_hfb_set_filter_length(struct bcmgenet_priv * priv,u32 f_index,u32 f_length)508 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
509 u32 f_index, u32 f_length)
510 {
511 u32 offset;
512 u32 reg;
513
514 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
515 offset = HFB_FLT_LEN_V2;
516 else
517 offset = HFB_FLT_LEN_V3PLUS;
518
519 offset += sizeof(u32) *
520 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4);
521 reg = bcmgenet_hfb_reg_readl(priv, offset);
522 reg &= ~(0xFF << (8 * (f_index % 4)));
523 reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
524 bcmgenet_hfb_reg_writel(priv, reg, offset);
525 }
526
bcmgenet_hfb_validate_mask(void * mask,size_t size)527 static int bcmgenet_hfb_validate_mask(void *mask, size_t size)
528 {
529 while (size) {
530 switch (*(unsigned char *)mask++) {
531 case 0x00:
532 case 0x0f:
533 case 0xf0:
534 case 0xff:
535 size--;
536 continue;
537 default:
538 return -EINVAL;
539 }
540 }
541
542 return 0;
543 }
544
545 #define VALIDATE_MASK(x) \
546 bcmgenet_hfb_validate_mask(&(x), sizeof(x))
547
bcmgenet_hfb_insert_data(struct bcmgenet_priv * priv,u32 f_index,u32 offset,void * val,void * mask,size_t size)548 static int bcmgenet_hfb_insert_data(struct bcmgenet_priv *priv, u32 f_index,
549 u32 offset, void *val, void *mask,
550 size_t size)
551 {
552 u32 index, tmp;
553
554 index = f_index * priv->hw_params->hfb_filter_size + offset / 2;
555 tmp = bcmgenet_hfb_readl(priv, index * sizeof(u32));
556
557 while (size--) {
558 if (offset++ & 1) {
559 tmp &= ~0x300FF;
560 tmp |= (*(unsigned char *)val++);
561 switch ((*(unsigned char *)mask++)) {
562 case 0xFF:
563 tmp |= 0x30000;
564 break;
565 case 0xF0:
566 tmp |= 0x20000;
567 break;
568 case 0x0F:
569 tmp |= 0x10000;
570 break;
571 }
572 bcmgenet_hfb_writel(priv, tmp, index++ * sizeof(u32));
573 if (size)
574 tmp = bcmgenet_hfb_readl(priv,
575 index * sizeof(u32));
576 } else {
577 tmp &= ~0xCFF00;
578 tmp |= (*(unsigned char *)val++) << 8;
579 switch ((*(unsigned char *)mask++)) {
580 case 0xFF:
581 tmp |= 0xC0000;
582 break;
583 case 0xF0:
584 tmp |= 0x80000;
585 break;
586 case 0x0F:
587 tmp |= 0x40000;
588 break;
589 }
590 if (!size)
591 bcmgenet_hfb_writel(priv, tmp, index * sizeof(u32));
592 }
593 }
594
595 return 0;
596 }
597
bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv * priv,struct bcmgenet_rxnfc_rule * rule)598 static void bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv *priv,
599 struct bcmgenet_rxnfc_rule *rule)
600 {
601 struct ethtool_rx_flow_spec *fs = &rule->fs;
602 u32 offset = 0, f_length = 0, f, q;
603 u8 val_8, mask_8;
604 __be16 val_16;
605 u16 mask_16;
606 size_t size;
607
608 f = fs->location + 1;
609 if (fs->flow_type & FLOW_MAC_EXT) {
610 bcmgenet_hfb_insert_data(priv, f, 0,
611 &fs->h_ext.h_dest, &fs->m_ext.h_dest,
612 sizeof(fs->h_ext.h_dest));
613 }
614
615 if (fs->flow_type & FLOW_EXT) {
616 if (fs->m_ext.vlan_etype ||
617 fs->m_ext.vlan_tci) {
618 bcmgenet_hfb_insert_data(priv, f, 12,
619 &fs->h_ext.vlan_etype,
620 &fs->m_ext.vlan_etype,
621 sizeof(fs->h_ext.vlan_etype));
622 bcmgenet_hfb_insert_data(priv, f, 14,
623 &fs->h_ext.vlan_tci,
624 &fs->m_ext.vlan_tci,
625 sizeof(fs->h_ext.vlan_tci));
626 offset += VLAN_HLEN;
627 f_length += DIV_ROUND_UP(VLAN_HLEN, 2);
628 }
629 }
630
631 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
632 case ETHER_FLOW:
633 f_length += DIV_ROUND_UP(ETH_HLEN, 2);
634 bcmgenet_hfb_insert_data(priv, f, 0,
635 &fs->h_u.ether_spec.h_dest,
636 &fs->m_u.ether_spec.h_dest,
637 sizeof(fs->h_u.ether_spec.h_dest));
638 bcmgenet_hfb_insert_data(priv, f, ETH_ALEN,
639 &fs->h_u.ether_spec.h_source,
640 &fs->m_u.ether_spec.h_source,
641 sizeof(fs->h_u.ether_spec.h_source));
642 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset,
643 &fs->h_u.ether_spec.h_proto,
644 &fs->m_u.ether_spec.h_proto,
645 sizeof(fs->h_u.ether_spec.h_proto));
646 break;
647 case IP_USER_FLOW:
648 f_length += DIV_ROUND_UP(ETH_HLEN + 20, 2);
649 /* Specify IP Ether Type */
650 val_16 = htons(ETH_P_IP);
651 mask_16 = 0xFFFF;
652 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset,
653 &val_16, &mask_16, sizeof(val_16));
654 bcmgenet_hfb_insert_data(priv, f, 15 + offset,
655 &fs->h_u.usr_ip4_spec.tos,
656 &fs->m_u.usr_ip4_spec.tos,
657 sizeof(fs->h_u.usr_ip4_spec.tos));
658 bcmgenet_hfb_insert_data(priv, f, 23 + offset,
659 &fs->h_u.usr_ip4_spec.proto,
660 &fs->m_u.usr_ip4_spec.proto,
661 sizeof(fs->h_u.usr_ip4_spec.proto));
662 bcmgenet_hfb_insert_data(priv, f, 26 + offset,
663 &fs->h_u.usr_ip4_spec.ip4src,
664 &fs->m_u.usr_ip4_spec.ip4src,
665 sizeof(fs->h_u.usr_ip4_spec.ip4src));
666 bcmgenet_hfb_insert_data(priv, f, 30 + offset,
667 &fs->h_u.usr_ip4_spec.ip4dst,
668 &fs->m_u.usr_ip4_spec.ip4dst,
669 sizeof(fs->h_u.usr_ip4_spec.ip4dst));
670 if (!fs->m_u.usr_ip4_spec.l4_4_bytes)
671 break;
672
673 /* Only supports 20 byte IPv4 header */
674 val_8 = 0x45;
675 mask_8 = 0xFF;
676 bcmgenet_hfb_insert_data(priv, f, ETH_HLEN + offset,
677 &val_8, &mask_8,
678 sizeof(val_8));
679 size = sizeof(fs->h_u.usr_ip4_spec.l4_4_bytes);
680 bcmgenet_hfb_insert_data(priv, f,
681 ETH_HLEN + 20 + offset,
682 &fs->h_u.usr_ip4_spec.l4_4_bytes,
683 &fs->m_u.usr_ip4_spec.l4_4_bytes,
684 size);
685 f_length += DIV_ROUND_UP(size, 2);
686 break;
687 }
688
689 bcmgenet_hfb_set_filter_length(priv, f, 2 * f_length);
690 if (fs->ring_cookie == RX_CLS_FLOW_WAKE)
691 q = 0;
692 else if (fs->ring_cookie == RX_CLS_FLOW_DISC)
693 q = priv->hw_params->rx_queues + 1;
694 else
695 /* Other Rx rings are direct mapped here */
696 q = fs->ring_cookie;
697 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f, q);
698 bcmgenet_hfb_enable_filter(priv, f);
699 rule->state = BCMGENET_RXNFC_STATE_ENABLED;
700 }
701
702 /* bcmgenet_hfb_clear
703 *
704 * Clear Hardware Filter Block and disable all filtering.
705 */
bcmgenet_hfb_clear_filter(struct bcmgenet_priv * priv,u32 f_index)706 static void bcmgenet_hfb_clear_filter(struct bcmgenet_priv *priv, u32 f_index)
707 {
708 u32 base, i;
709
710 bcmgenet_hfb_set_filter_length(priv, f_index, 0);
711 base = f_index * priv->hw_params->hfb_filter_size;
712 for (i = 0; i < priv->hw_params->hfb_filter_size; i++)
713 bcmgenet_hfb_writel(priv, 0x0, (base + i) * sizeof(u32));
714 }
715
bcmgenet_hfb_clear(struct bcmgenet_priv * priv)716 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
717 {
718 u32 i;
719
720 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL);
721
722 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) {
723 bcmgenet_hfb_reg_writel(priv, 0,
724 HFB_FLT_ENABLE_V3PLUS);
725 bcmgenet_hfb_reg_writel(priv, 0,
726 HFB_FLT_ENABLE_V3PLUS + 4);
727 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
728 bcmgenet_rdma_writel(priv, 0, i);
729 }
730
731 for (i = 0; i < priv->hw_params->hfb_filter_cnt; i++)
732 bcmgenet_hfb_clear_filter(priv, i);
733
734 /* Enable filter 0 to send default flow to ring 0 */
735 bcmgenet_hfb_set_filter_length(priv, 0, 4);
736 bcmgenet_hfb_enable_filter(priv, 0);
737 }
738
bcmgenet_hfb_init(struct bcmgenet_priv * priv)739 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
740 {
741 int i;
742
743 INIT_LIST_HEAD(&priv->rxnfc_list);
744 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
745 INIT_LIST_HEAD(&priv->rxnfc_rules[i].list);
746 priv->rxnfc_rules[i].state = BCMGENET_RXNFC_STATE_UNUSED;
747 }
748
749 bcmgenet_hfb_clear(priv);
750 }
751
bcmgenet_begin(struct net_device * dev)752 static int bcmgenet_begin(struct net_device *dev)
753 {
754 struct bcmgenet_priv *priv = netdev_priv(dev);
755
756 /* Turn on the clock */
757 return clk_prepare_enable(priv->clk);
758 }
759
bcmgenet_complete(struct net_device * dev)760 static void bcmgenet_complete(struct net_device *dev)
761 {
762 struct bcmgenet_priv *priv = netdev_priv(dev);
763
764 /* Turn off the clock */
765 clk_disable_unprepare(priv->clk);
766 }
767
bcmgenet_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)768 static int bcmgenet_get_link_ksettings(struct net_device *dev,
769 struct ethtool_link_ksettings *cmd)
770 {
771 if (!netif_running(dev))
772 return -EINVAL;
773
774 if (!dev->phydev)
775 return -ENODEV;
776
777 phy_ethtool_ksettings_get(dev->phydev, cmd);
778
779 return 0;
780 }
781
bcmgenet_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)782 static int bcmgenet_set_link_ksettings(struct net_device *dev,
783 const struct ethtool_link_ksettings *cmd)
784 {
785 if (!netif_running(dev))
786 return -EINVAL;
787
788 if (!dev->phydev)
789 return -ENODEV;
790
791 return phy_ethtool_ksettings_set(dev->phydev, cmd);
792 }
793
bcmgenet_set_features(struct net_device * dev,netdev_features_t features)794 static int bcmgenet_set_features(struct net_device *dev,
795 netdev_features_t features)
796 {
797 struct bcmgenet_priv *priv = netdev_priv(dev);
798 u32 reg;
799 int ret;
800
801 ret = clk_prepare_enable(priv->clk);
802 if (ret)
803 return ret;
804
805 /* Make sure we reflect the value of CRC_CMD_FWD */
806 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
807 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
808
809 clk_disable_unprepare(priv->clk);
810
811 return ret;
812 }
813
bcmgenet_get_msglevel(struct net_device * dev)814 static u32 bcmgenet_get_msglevel(struct net_device *dev)
815 {
816 struct bcmgenet_priv *priv = netdev_priv(dev);
817
818 return priv->msg_enable;
819 }
820
bcmgenet_set_msglevel(struct net_device * dev,u32 level)821 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
822 {
823 struct bcmgenet_priv *priv = netdev_priv(dev);
824
825 priv->msg_enable = level;
826 }
827
bcmgenet_get_coalesce(struct net_device * dev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)828 static int bcmgenet_get_coalesce(struct net_device *dev,
829 struct ethtool_coalesce *ec,
830 struct kernel_ethtool_coalesce *kernel_coal,
831 struct netlink_ext_ack *extack)
832 {
833 struct bcmgenet_priv *priv = netdev_priv(dev);
834 struct bcmgenet_rx_ring *ring;
835 unsigned int i;
836
837 ec->tx_max_coalesced_frames =
838 bcmgenet_tdma_ring_readl(priv, 0, DMA_MBUF_DONE_THRESH);
839 ec->rx_max_coalesced_frames =
840 bcmgenet_rdma_ring_readl(priv, 0, DMA_MBUF_DONE_THRESH);
841 ec->rx_coalesce_usecs =
842 bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT) * 8192 / 1000;
843
844 for (i = 0; i <= priv->hw_params->rx_queues; i++) {
845 ring = &priv->rx_rings[i];
846 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
847 }
848
849 return 0;
850 }
851
bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring * ring,u32 usecs,u32 pkts)852 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring,
853 u32 usecs, u32 pkts)
854 {
855 struct bcmgenet_priv *priv = ring->priv;
856 unsigned int i = ring->index;
857 u32 reg;
858
859 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH);
860
861 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
862 reg &= ~DMA_TIMEOUT_MASK;
863 reg |= DIV_ROUND_UP(usecs * 1000, 8192);
864 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
865 }
866
bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring * ring,struct ethtool_coalesce * ec)867 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring,
868 struct ethtool_coalesce *ec)
869 {
870 struct dim_cq_moder moder;
871 u32 usecs, pkts;
872
873 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs;
874 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
875 usecs = ring->rx_coalesce_usecs;
876 pkts = ring->rx_max_coalesced_frames;
877
878 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) {
879 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode);
880 usecs = moder.usec;
881 pkts = moder.pkts;
882 }
883
884 ring->dim.use_dim = ec->use_adaptive_rx_coalesce;
885 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
886 }
887
bcmgenet_set_coalesce(struct net_device * dev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)888 static int bcmgenet_set_coalesce(struct net_device *dev,
889 struct ethtool_coalesce *ec,
890 struct kernel_ethtool_coalesce *kernel_coal,
891 struct netlink_ext_ack *extack)
892 {
893 struct bcmgenet_priv *priv = netdev_priv(dev);
894 unsigned int i;
895
896 /* Base system clock is 125Mhz, DMA timeout is this reference clock
897 * divided by 1024, which yields roughly 8.192us, our maximum value
898 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
899 */
900 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
901 ec->tx_max_coalesced_frames == 0 ||
902 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
903 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
904 return -EINVAL;
905
906 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
907 return -EINVAL;
908
909 /* GENET TDMA hardware does not support a configurable timeout, but will
910 * always generate an interrupt either after MBDONE packets have been
911 * transmitted, or when the ring is empty.
912 */
913
914 /* Program all TX queues with the same values, as there is no
915 * ethtool knob to do coalescing on a per-queue basis
916 */
917 for (i = 0; i <= priv->hw_params->tx_queues; i++)
918 bcmgenet_tdma_ring_writel(priv, i,
919 ec->tx_max_coalesced_frames,
920 DMA_MBUF_DONE_THRESH);
921
922 for (i = 0; i <= priv->hw_params->rx_queues; i++)
923 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec);
924
925 return 0;
926 }
927
bcmgenet_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * epause)928 static void bcmgenet_get_pauseparam(struct net_device *dev,
929 struct ethtool_pauseparam *epause)
930 {
931 struct bcmgenet_priv *priv;
932 u32 umac_cmd;
933
934 priv = netdev_priv(dev);
935
936 epause->autoneg = priv->autoneg_pause;
937
938 if (netif_carrier_ok(dev)) {
939 /* report active state when link is up */
940 umac_cmd = bcmgenet_umac_readl(priv, UMAC_CMD);
941 epause->tx_pause = !(umac_cmd & CMD_TX_PAUSE_IGNORE);
942 epause->rx_pause = !(umac_cmd & CMD_RX_PAUSE_IGNORE);
943 } else {
944 /* otherwise report stored settings */
945 epause->tx_pause = priv->tx_pause;
946 epause->rx_pause = priv->rx_pause;
947 }
948 }
949
bcmgenet_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * epause)950 static int bcmgenet_set_pauseparam(struct net_device *dev,
951 struct ethtool_pauseparam *epause)
952 {
953 struct bcmgenet_priv *priv = netdev_priv(dev);
954
955 if (!dev->phydev)
956 return -ENODEV;
957
958 if (!phy_validate_pause(dev->phydev, epause))
959 return -EINVAL;
960
961 priv->autoneg_pause = !!epause->autoneg;
962 priv->tx_pause = !!epause->tx_pause;
963 priv->rx_pause = !!epause->rx_pause;
964
965 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause);
966
967 return 0;
968 }
969
970 /* standard ethtool support functions. */
971 enum bcmgenet_stat_type {
972 BCMGENET_STAT_NETDEV = -1,
973 BCMGENET_STAT_MIB_RX,
974 BCMGENET_STAT_MIB_TX,
975 BCMGENET_STAT_RUNT,
976 BCMGENET_STAT_MISC,
977 BCMGENET_STAT_SOFT,
978 };
979
980 struct bcmgenet_stats {
981 char stat_string[ETH_GSTRING_LEN];
982 int stat_sizeof;
983 int stat_offset;
984 enum bcmgenet_stat_type type;
985 /* reg offset from UMAC base for misc counters */
986 u16 reg_offset;
987 };
988
989 #define STAT_NETDEV(m) { \
990 .stat_string = __stringify(m), \
991 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
992 .stat_offset = offsetof(struct net_device_stats, m), \
993 .type = BCMGENET_STAT_NETDEV, \
994 }
995
996 #define STAT_GENET_MIB(str, m, _type) { \
997 .stat_string = str, \
998 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
999 .stat_offset = offsetof(struct bcmgenet_priv, m), \
1000 .type = _type, \
1001 }
1002
1003 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
1004 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
1005 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
1006 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1007
1008 #define STAT_GENET_MISC(str, m, offset) { \
1009 .stat_string = str, \
1010 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
1011 .stat_offset = offsetof(struct bcmgenet_priv, m), \
1012 .type = BCMGENET_STAT_MISC, \
1013 .reg_offset = offset, \
1014 }
1015
1016 #define STAT_GENET_Q(num) \
1017 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
1018 tx_rings[num].packets), \
1019 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
1020 tx_rings[num].bytes), \
1021 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
1022 rx_rings[num].bytes), \
1023 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
1024 rx_rings[num].packets), \
1025 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
1026 rx_rings[num].errors), \
1027 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
1028 rx_rings[num].dropped)
1029
1030 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
1031 * between the end of TX stats and the beginning of the RX RUNT
1032 */
1033 #define BCMGENET_STAT_OFFSET 0xc
1034
1035 /* Hardware counters must be kept in sync because the order/offset
1036 * is important here (order in structure declaration = order in hardware)
1037 */
1038 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
1039 /* general stats */
1040 STAT_NETDEV(rx_packets),
1041 STAT_NETDEV(tx_packets),
1042 STAT_NETDEV(rx_bytes),
1043 STAT_NETDEV(tx_bytes),
1044 STAT_NETDEV(rx_errors),
1045 STAT_NETDEV(tx_errors),
1046 STAT_NETDEV(rx_dropped),
1047 STAT_NETDEV(tx_dropped),
1048 STAT_NETDEV(multicast),
1049 /* UniMAC RSV counters */
1050 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
1051 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
1052 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
1053 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
1054 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
1055 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
1056 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
1057 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
1058 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
1059 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
1060 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
1061 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
1062 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
1063 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
1064 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
1065 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
1066 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
1067 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
1068 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
1069 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
1070 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
1071 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
1072 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
1073 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
1074 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
1075 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
1076 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
1077 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
1078 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
1079 /* UniMAC TSV counters */
1080 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
1081 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
1082 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
1083 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
1084 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
1085 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
1086 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
1087 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
1088 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
1089 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
1090 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
1091 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
1092 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
1093 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
1094 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
1095 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
1096 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
1097 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
1098 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
1099 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
1100 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
1101 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
1102 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
1103 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
1104 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
1105 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
1106 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
1107 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
1108 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
1109 /* UniMAC RUNT counters */
1110 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
1111 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
1112 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
1113 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
1114 /* Misc UniMAC counters */
1115 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
1116 UMAC_RBUF_OVFL_CNT_V1),
1117 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
1118 UMAC_RBUF_ERR_CNT_V1),
1119 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
1120 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
1121 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
1122 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
1123 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb),
1124 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed",
1125 mib.tx_realloc_tsb_failed),
1126 /* Per TX queues */
1127 STAT_GENET_Q(0),
1128 STAT_GENET_Q(1),
1129 STAT_GENET_Q(2),
1130 STAT_GENET_Q(3),
1131 STAT_GENET_Q(4),
1132 };
1133
1134 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
1135
bcmgenet_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1136 static void bcmgenet_get_drvinfo(struct net_device *dev,
1137 struct ethtool_drvinfo *info)
1138 {
1139 strscpy(info->driver, "bcmgenet", sizeof(info->driver));
1140 }
1141
bcmgenet_get_sset_count(struct net_device * dev,int string_set)1142 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
1143 {
1144 switch (string_set) {
1145 case ETH_SS_STATS:
1146 return BCMGENET_STATS_LEN;
1147 default:
1148 return -EOPNOTSUPP;
1149 }
1150 }
1151
bcmgenet_get_strings(struct net_device * dev,u32 stringset,u8 * data)1152 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
1153 u8 *data)
1154 {
1155 const char *str;
1156 int i;
1157
1158 switch (stringset) {
1159 case ETH_SS_STATS:
1160 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1161 str = bcmgenet_gstrings_stats[i].stat_string;
1162 ethtool_puts(&data, str);
1163 }
1164 break;
1165 }
1166 }
1167
bcmgenet_update_stat_misc(struct bcmgenet_priv * priv,u16 offset)1168 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
1169 {
1170 u16 new_offset;
1171 u32 val;
1172
1173 switch (offset) {
1174 case UMAC_RBUF_OVFL_CNT_V1:
1175 if (GENET_IS_V2(priv))
1176 new_offset = RBUF_OVFL_CNT_V2;
1177 else
1178 new_offset = RBUF_OVFL_CNT_V3PLUS;
1179
1180 val = bcmgenet_rbuf_readl(priv, new_offset);
1181 /* clear if overflowed */
1182 if (val == ~0)
1183 bcmgenet_rbuf_writel(priv, 0, new_offset);
1184 break;
1185 case UMAC_RBUF_ERR_CNT_V1:
1186 if (GENET_IS_V2(priv))
1187 new_offset = RBUF_ERR_CNT_V2;
1188 else
1189 new_offset = RBUF_ERR_CNT_V3PLUS;
1190
1191 val = bcmgenet_rbuf_readl(priv, new_offset);
1192 /* clear if overflowed */
1193 if (val == ~0)
1194 bcmgenet_rbuf_writel(priv, 0, new_offset);
1195 break;
1196 default:
1197 val = bcmgenet_umac_readl(priv, offset);
1198 /* clear if overflowed */
1199 if (val == ~0)
1200 bcmgenet_umac_writel(priv, 0, offset);
1201 break;
1202 }
1203
1204 return val;
1205 }
1206
bcmgenet_update_mib_counters(struct bcmgenet_priv * priv)1207 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
1208 {
1209 int i, j = 0;
1210
1211 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1212 const struct bcmgenet_stats *s;
1213 u8 offset = 0;
1214 u32 val = 0;
1215 char *p;
1216
1217 s = &bcmgenet_gstrings_stats[i];
1218 switch (s->type) {
1219 case BCMGENET_STAT_NETDEV:
1220 case BCMGENET_STAT_SOFT:
1221 continue;
1222 case BCMGENET_STAT_RUNT:
1223 offset += BCMGENET_STAT_OFFSET;
1224 fallthrough;
1225 case BCMGENET_STAT_MIB_TX:
1226 offset += BCMGENET_STAT_OFFSET;
1227 fallthrough;
1228 case BCMGENET_STAT_MIB_RX:
1229 val = bcmgenet_umac_readl(priv,
1230 UMAC_MIB_START + j + offset);
1231 offset = 0; /* Reset Offset */
1232 break;
1233 case BCMGENET_STAT_MISC:
1234 if (GENET_IS_V1(priv)) {
1235 val = bcmgenet_umac_readl(priv, s->reg_offset);
1236 /* clear if overflowed */
1237 if (val == ~0)
1238 bcmgenet_umac_writel(priv, 0,
1239 s->reg_offset);
1240 } else {
1241 val = bcmgenet_update_stat_misc(priv,
1242 s->reg_offset);
1243 }
1244 break;
1245 }
1246
1247 j += s->stat_sizeof;
1248 p = (char *)priv + s->stat_offset;
1249 *(u32 *)p = val;
1250 }
1251 }
1252
bcmgenet_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)1253 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
1254 struct ethtool_stats *stats,
1255 u64 *data)
1256 {
1257 struct bcmgenet_priv *priv = netdev_priv(dev);
1258 int i;
1259
1260 if (netif_running(dev))
1261 bcmgenet_update_mib_counters(priv);
1262
1263 dev->netdev_ops->ndo_get_stats(dev);
1264
1265 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1266 const struct bcmgenet_stats *s;
1267 char *p;
1268
1269 s = &bcmgenet_gstrings_stats[i];
1270 if (s->type == BCMGENET_STAT_NETDEV)
1271 p = (char *)&dev->stats;
1272 else
1273 p = (char *)priv;
1274 p += s->stat_offset;
1275 if (sizeof(unsigned long) != sizeof(u32) &&
1276 s->stat_sizeof == sizeof(unsigned long))
1277 data[i] = *(unsigned long *)p;
1278 else
1279 data[i] = *(u32 *)p;
1280 }
1281 }
1282
bcmgenet_eee_enable_set(struct net_device * dev,bool enable,bool tx_lpi_enabled)1283 void bcmgenet_eee_enable_set(struct net_device *dev, bool enable,
1284 bool tx_lpi_enabled)
1285 {
1286 struct bcmgenet_priv *priv = netdev_priv(dev);
1287 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
1288 u32 reg;
1289
1290 if (enable && !priv->clk_eee_enabled) {
1291 clk_prepare_enable(priv->clk_eee);
1292 priv->clk_eee_enabled = true;
1293 }
1294
1295 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1296 if (enable)
1297 reg |= EEE_EN;
1298 else
1299 reg &= ~EEE_EN;
1300 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1301
1302 /* Enable EEE and switch to a 27Mhz clock automatically */
1303 reg = bcmgenet_readl(priv->base + off);
1304 if (tx_lpi_enabled)
1305 reg |= TBUF_EEE_EN | TBUF_PM_EN;
1306 else
1307 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
1308 bcmgenet_writel(reg, priv->base + off);
1309
1310 /* Do the same for thing for RBUF */
1311 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1312 if (enable)
1313 reg |= RBUF_EEE_EN | RBUF_PM_EN;
1314 else
1315 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1316 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1317
1318 if (!enable && priv->clk_eee_enabled) {
1319 clk_disable_unprepare(priv->clk_eee);
1320 priv->clk_eee_enabled = false;
1321 }
1322
1323 priv->eee.eee_enabled = enable;
1324 priv->eee.tx_lpi_enabled = tx_lpi_enabled;
1325 }
1326
bcmgenet_get_eee(struct net_device * dev,struct ethtool_keee * e)1327 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_keee *e)
1328 {
1329 struct bcmgenet_priv *priv = netdev_priv(dev);
1330 struct ethtool_keee *p = &priv->eee;
1331
1332 if (GENET_IS_V1(priv))
1333 return -EOPNOTSUPP;
1334
1335 if (!dev->phydev)
1336 return -ENODEV;
1337
1338 e->tx_lpi_enabled = p->tx_lpi_enabled;
1339 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1340
1341 return phy_ethtool_get_eee(dev->phydev, e);
1342 }
1343
bcmgenet_set_eee(struct net_device * dev,struct ethtool_keee * e)1344 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_keee *e)
1345 {
1346 struct bcmgenet_priv *priv = netdev_priv(dev);
1347 struct ethtool_keee *p = &priv->eee;
1348 bool active;
1349
1350 if (GENET_IS_V1(priv))
1351 return -EOPNOTSUPP;
1352
1353 if (!dev->phydev)
1354 return -ENODEV;
1355
1356 p->eee_enabled = e->eee_enabled;
1357
1358 if (!p->eee_enabled) {
1359 bcmgenet_eee_enable_set(dev, false, false);
1360 } else {
1361 active = phy_init_eee(dev->phydev, false) >= 0;
1362 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1363 bcmgenet_eee_enable_set(dev, active, e->tx_lpi_enabled);
1364 }
1365
1366 return phy_ethtool_set_eee(dev->phydev, e);
1367 }
1368
bcmgenet_validate_flow(struct net_device * dev,struct ethtool_rxnfc * cmd)1369 static int bcmgenet_validate_flow(struct net_device *dev,
1370 struct ethtool_rxnfc *cmd)
1371 {
1372 struct ethtool_usrip4_spec *l4_mask;
1373 struct ethhdr *eth_mask;
1374
1375 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES &&
1376 cmd->fs.location != RX_CLS_LOC_ANY) {
1377 netdev_err(dev, "rxnfc: Invalid location (%d)\n",
1378 cmd->fs.location);
1379 return -EINVAL;
1380 }
1381
1382 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1383 case IP_USER_FLOW:
1384 l4_mask = &cmd->fs.m_u.usr_ip4_spec;
1385 /* don't allow mask which isn't valid */
1386 if (VALIDATE_MASK(l4_mask->ip4src) ||
1387 VALIDATE_MASK(l4_mask->ip4dst) ||
1388 VALIDATE_MASK(l4_mask->l4_4_bytes) ||
1389 VALIDATE_MASK(l4_mask->proto) ||
1390 VALIDATE_MASK(l4_mask->ip_ver) ||
1391 VALIDATE_MASK(l4_mask->tos)) {
1392 netdev_err(dev, "rxnfc: Unsupported mask\n");
1393 return -EINVAL;
1394 }
1395 break;
1396 case ETHER_FLOW:
1397 eth_mask = &cmd->fs.m_u.ether_spec;
1398 /* don't allow mask which isn't valid */
1399 if (VALIDATE_MASK(eth_mask->h_dest) ||
1400 VALIDATE_MASK(eth_mask->h_source) ||
1401 VALIDATE_MASK(eth_mask->h_proto)) {
1402 netdev_err(dev, "rxnfc: Unsupported mask\n");
1403 return -EINVAL;
1404 }
1405 break;
1406 default:
1407 netdev_err(dev, "rxnfc: Unsupported flow type (0x%x)\n",
1408 cmd->fs.flow_type);
1409 return -EINVAL;
1410 }
1411
1412 if ((cmd->fs.flow_type & FLOW_EXT)) {
1413 /* don't allow mask which isn't valid */
1414 if (VALIDATE_MASK(cmd->fs.m_ext.vlan_etype) ||
1415 VALIDATE_MASK(cmd->fs.m_ext.vlan_tci)) {
1416 netdev_err(dev, "rxnfc: Unsupported mask\n");
1417 return -EINVAL;
1418 }
1419 if (cmd->fs.m_ext.data[0] || cmd->fs.m_ext.data[1]) {
1420 netdev_err(dev, "rxnfc: user-def not supported\n");
1421 return -EINVAL;
1422 }
1423 }
1424
1425 if ((cmd->fs.flow_type & FLOW_MAC_EXT)) {
1426 /* don't allow mask which isn't valid */
1427 if (VALIDATE_MASK(cmd->fs.m_ext.h_dest)) {
1428 netdev_err(dev, "rxnfc: Unsupported mask\n");
1429 return -EINVAL;
1430 }
1431 }
1432
1433 return 0;
1434 }
1435
bcmgenet_insert_flow(struct net_device * dev,struct ethtool_rxnfc * cmd)1436 static int bcmgenet_insert_flow(struct net_device *dev,
1437 struct ethtool_rxnfc *cmd)
1438 {
1439 struct bcmgenet_priv *priv = netdev_priv(dev);
1440 struct bcmgenet_rxnfc_rule *loc_rule;
1441 int err, i;
1442
1443 if (priv->hw_params->hfb_filter_size < 128) {
1444 netdev_err(dev, "rxnfc: Not supported by this device\n");
1445 return -EINVAL;
1446 }
1447
1448 if (cmd->fs.ring_cookie > priv->hw_params->rx_queues &&
1449 cmd->fs.ring_cookie != RX_CLS_FLOW_WAKE &&
1450 cmd->fs.ring_cookie != RX_CLS_FLOW_DISC) {
1451 netdev_err(dev, "rxnfc: Unsupported action (%llu)\n",
1452 cmd->fs.ring_cookie);
1453 return -EINVAL;
1454 }
1455
1456 err = bcmgenet_validate_flow(dev, cmd);
1457 if (err)
1458 return err;
1459
1460 if (cmd->fs.location == RX_CLS_LOC_ANY) {
1461 list_for_each_entry(loc_rule, &priv->rxnfc_list, list) {
1462 cmd->fs.location = loc_rule->fs.location;
1463 err = memcmp(&loc_rule->fs, &cmd->fs,
1464 sizeof(struct ethtool_rx_flow_spec));
1465 if (!err)
1466 /* rule exists so return current location */
1467 return 0;
1468 }
1469 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
1470 loc_rule = &priv->rxnfc_rules[i];
1471 if (loc_rule->state == BCMGENET_RXNFC_STATE_UNUSED) {
1472 cmd->fs.location = i;
1473 break;
1474 }
1475 }
1476 if (i == MAX_NUM_OF_FS_RULES) {
1477 cmd->fs.location = RX_CLS_LOC_ANY;
1478 return -ENOSPC;
1479 }
1480 } else {
1481 loc_rule = &priv->rxnfc_rules[cmd->fs.location];
1482 }
1483 if (loc_rule->state == BCMGENET_RXNFC_STATE_ENABLED)
1484 bcmgenet_hfb_disable_filter(priv, cmd->fs.location + 1);
1485 if (loc_rule->state != BCMGENET_RXNFC_STATE_UNUSED) {
1486 list_del(&loc_rule->list);
1487 bcmgenet_hfb_clear_filter(priv, cmd->fs.location + 1);
1488 }
1489 loc_rule->state = BCMGENET_RXNFC_STATE_UNUSED;
1490 memcpy(&loc_rule->fs, &cmd->fs,
1491 sizeof(struct ethtool_rx_flow_spec));
1492
1493 bcmgenet_hfb_create_rxnfc_filter(priv, loc_rule);
1494
1495 list_add_tail(&loc_rule->list, &priv->rxnfc_list);
1496
1497 return 0;
1498 }
1499
bcmgenet_delete_flow(struct net_device * dev,struct ethtool_rxnfc * cmd)1500 static int bcmgenet_delete_flow(struct net_device *dev,
1501 struct ethtool_rxnfc *cmd)
1502 {
1503 struct bcmgenet_priv *priv = netdev_priv(dev);
1504 struct bcmgenet_rxnfc_rule *rule;
1505 int err = 0;
1506
1507 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1508 return -EINVAL;
1509
1510 rule = &priv->rxnfc_rules[cmd->fs.location];
1511 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) {
1512 err = -ENOENT;
1513 goto out;
1514 }
1515
1516 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED)
1517 bcmgenet_hfb_disable_filter(priv, cmd->fs.location + 1);
1518 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) {
1519 list_del(&rule->list);
1520 bcmgenet_hfb_clear_filter(priv, cmd->fs.location + 1);
1521 }
1522 rule->state = BCMGENET_RXNFC_STATE_UNUSED;
1523 memset(&rule->fs, 0, sizeof(struct ethtool_rx_flow_spec));
1524
1525 out:
1526 return err;
1527 }
1528
bcmgenet_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)1529 static int bcmgenet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1530 {
1531 struct bcmgenet_priv *priv = netdev_priv(dev);
1532 int err = 0;
1533
1534 switch (cmd->cmd) {
1535 case ETHTOOL_SRXCLSRLINS:
1536 err = bcmgenet_insert_flow(dev, cmd);
1537 break;
1538 case ETHTOOL_SRXCLSRLDEL:
1539 err = bcmgenet_delete_flow(dev, cmd);
1540 break;
1541 default:
1542 netdev_warn(priv->dev, "Unsupported ethtool command. (%d)\n",
1543 cmd->cmd);
1544 return -EINVAL;
1545 }
1546
1547 return err;
1548 }
1549
bcmgenet_get_flow(struct net_device * dev,struct ethtool_rxnfc * cmd,int loc)1550 static int bcmgenet_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1551 int loc)
1552 {
1553 struct bcmgenet_priv *priv = netdev_priv(dev);
1554 struct bcmgenet_rxnfc_rule *rule;
1555 int err = 0;
1556
1557 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1558 return -EINVAL;
1559
1560 rule = &priv->rxnfc_rules[loc];
1561 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED)
1562 err = -ENOENT;
1563 else
1564 memcpy(&cmd->fs, &rule->fs,
1565 sizeof(struct ethtool_rx_flow_spec));
1566
1567 return err;
1568 }
1569
bcmgenet_get_num_flows(struct bcmgenet_priv * priv)1570 static int bcmgenet_get_num_flows(struct bcmgenet_priv *priv)
1571 {
1572 struct list_head *pos;
1573 int res = 0;
1574
1575 list_for_each(pos, &priv->rxnfc_list)
1576 res++;
1577
1578 return res;
1579 }
1580
bcmgenet_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)1581 static int bcmgenet_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1582 u32 *rule_locs)
1583 {
1584 struct bcmgenet_priv *priv = netdev_priv(dev);
1585 struct bcmgenet_rxnfc_rule *rule;
1586 int err = 0;
1587 int i = 0;
1588
1589 switch (cmd->cmd) {
1590 case ETHTOOL_GRXRINGS:
1591 cmd->data = priv->hw_params->rx_queues ?: 1;
1592 break;
1593 case ETHTOOL_GRXCLSRLCNT:
1594 cmd->rule_cnt = bcmgenet_get_num_flows(priv);
1595 cmd->data = MAX_NUM_OF_FS_RULES | RX_CLS_LOC_SPECIAL;
1596 break;
1597 case ETHTOOL_GRXCLSRULE:
1598 err = bcmgenet_get_flow(dev, cmd, cmd->fs.location);
1599 break;
1600 case ETHTOOL_GRXCLSRLALL:
1601 list_for_each_entry(rule, &priv->rxnfc_list, list)
1602 if (i < cmd->rule_cnt)
1603 rule_locs[i++] = rule->fs.location;
1604 cmd->rule_cnt = i;
1605 cmd->data = MAX_NUM_OF_FS_RULES;
1606 break;
1607 default:
1608 err = -EOPNOTSUPP;
1609 break;
1610 }
1611
1612 return err;
1613 }
1614
1615 /* standard ethtool support functions. */
1616 static const struct ethtool_ops bcmgenet_ethtool_ops = {
1617 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
1618 ETHTOOL_COALESCE_MAX_FRAMES |
1619 ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
1620 .begin = bcmgenet_begin,
1621 .complete = bcmgenet_complete,
1622 .get_strings = bcmgenet_get_strings,
1623 .get_sset_count = bcmgenet_get_sset_count,
1624 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
1625 .get_drvinfo = bcmgenet_get_drvinfo,
1626 .get_link = ethtool_op_get_link,
1627 .get_msglevel = bcmgenet_get_msglevel,
1628 .set_msglevel = bcmgenet_set_msglevel,
1629 .get_wol = bcmgenet_get_wol,
1630 .set_wol = bcmgenet_set_wol,
1631 .get_eee = bcmgenet_get_eee,
1632 .set_eee = bcmgenet_set_eee,
1633 .nway_reset = phy_ethtool_nway_reset,
1634 .get_coalesce = bcmgenet_get_coalesce,
1635 .set_coalesce = bcmgenet_set_coalesce,
1636 .get_link_ksettings = bcmgenet_get_link_ksettings,
1637 .set_link_ksettings = bcmgenet_set_link_ksettings,
1638 .get_ts_info = ethtool_op_get_ts_info,
1639 .get_rxnfc = bcmgenet_get_rxnfc,
1640 .set_rxnfc = bcmgenet_set_rxnfc,
1641 .get_pauseparam = bcmgenet_get_pauseparam,
1642 .set_pauseparam = bcmgenet_set_pauseparam,
1643 };
1644
1645 /* Power down the unimac, based on mode. */
bcmgenet_power_down(struct bcmgenet_priv * priv,enum bcmgenet_power_mode mode)1646 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1647 enum bcmgenet_power_mode mode)
1648 {
1649 int ret = 0;
1650 u32 reg;
1651
1652 switch (mode) {
1653 case GENET_POWER_CABLE_SENSE:
1654 phy_detach(priv->dev->phydev);
1655 break;
1656
1657 case GENET_POWER_WOL_MAGIC:
1658 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1659 break;
1660
1661 case GENET_POWER_PASSIVE:
1662 /* Power down LED */
1663 if (bcmgenet_has_ext(priv)) {
1664 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1665 if (GENET_IS_V5(priv) && !bcmgenet_has_ephy_16nm(priv))
1666 reg |= EXT_PWR_DOWN_PHY_EN |
1667 EXT_PWR_DOWN_PHY_RD |
1668 EXT_PWR_DOWN_PHY_SD |
1669 EXT_PWR_DOWN_PHY_RX |
1670 EXT_PWR_DOWN_PHY_TX |
1671 EXT_IDDQ_GLBL_PWR;
1672 else
1673 reg |= EXT_PWR_DOWN_PHY;
1674
1675 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1676 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1677
1678 bcmgenet_phy_power_set(priv->dev, false);
1679 }
1680 break;
1681 default:
1682 break;
1683 }
1684
1685 return ret;
1686 }
1687
bcmgenet_power_up(struct bcmgenet_priv * priv,enum bcmgenet_power_mode mode)1688 static int bcmgenet_power_up(struct bcmgenet_priv *priv,
1689 enum bcmgenet_power_mode mode)
1690 {
1691 int ret = 0;
1692 u32 reg;
1693
1694 if (!bcmgenet_has_ext(priv))
1695 return ret;
1696
1697 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1698
1699 switch (mode) {
1700 case GENET_POWER_PASSIVE:
1701 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS |
1702 EXT_ENERGY_DET_MASK);
1703 if (GENET_IS_V5(priv) && !bcmgenet_has_ephy_16nm(priv)) {
1704 reg &= ~(EXT_PWR_DOWN_PHY_EN |
1705 EXT_PWR_DOWN_PHY_RD |
1706 EXT_PWR_DOWN_PHY_SD |
1707 EXT_PWR_DOWN_PHY_RX |
1708 EXT_PWR_DOWN_PHY_TX |
1709 EXT_IDDQ_GLBL_PWR);
1710 reg |= EXT_PHY_RESET;
1711 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1712 mdelay(1);
1713
1714 reg &= ~EXT_PHY_RESET;
1715 } else {
1716 reg &= ~EXT_PWR_DOWN_PHY;
1717 reg |= EXT_PWR_DN_EN_LD;
1718 }
1719 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1720 bcmgenet_phy_power_set(priv->dev, true);
1721 break;
1722
1723 case GENET_POWER_CABLE_SENSE:
1724 /* enable APD */
1725 if (!GENET_IS_V5(priv)) {
1726 reg |= EXT_PWR_DN_EN_LD;
1727 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1728 }
1729 break;
1730 case GENET_POWER_WOL_MAGIC:
1731 ret = bcmgenet_wol_power_up_cfg(priv, mode);
1732 break;
1733 default:
1734 break;
1735 }
1736
1737 return ret;
1738 }
1739
bcmgenet_get_txcb(struct bcmgenet_priv * priv,struct bcmgenet_tx_ring * ring)1740 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1741 struct bcmgenet_tx_ring *ring)
1742 {
1743 struct enet_cb *tx_cb_ptr;
1744
1745 tx_cb_ptr = ring->cbs;
1746 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1747
1748 /* Advancing local write pointer */
1749 if (ring->write_ptr == ring->end_ptr)
1750 ring->write_ptr = ring->cb_ptr;
1751 else
1752 ring->write_ptr++;
1753
1754 return tx_cb_ptr;
1755 }
1756
bcmgenet_put_txcb(struct bcmgenet_priv * priv,struct bcmgenet_tx_ring * ring)1757 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1758 struct bcmgenet_tx_ring *ring)
1759 {
1760 struct enet_cb *tx_cb_ptr;
1761
1762 tx_cb_ptr = ring->cbs;
1763 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1764
1765 /* Rewinding local write pointer */
1766 if (ring->write_ptr == ring->cb_ptr)
1767 ring->write_ptr = ring->end_ptr;
1768 else
1769 ring->write_ptr--;
1770
1771 return tx_cb_ptr;
1772 }
1773
bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring * ring)1774 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1775 {
1776 bcmgenet_intrl2_1_writel(ring->priv,
1777 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1778 INTRL2_CPU_MASK_SET);
1779 }
1780
bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring * ring)1781 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1782 {
1783 bcmgenet_intrl2_1_writel(ring->priv,
1784 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1785 INTRL2_CPU_MASK_CLEAR);
1786 }
1787
bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring * ring)1788 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1789 {
1790 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1791 INTRL2_CPU_MASK_CLEAR);
1792 }
1793
bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring * ring)1794 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1795 {
1796 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1797 INTRL2_CPU_MASK_SET);
1798 }
1799
1800 /* Simple helper to free a transmit control block's resources
1801 * Returns an skb when the last transmit control block associated with the
1802 * skb is freed. The skb should be freed by the caller if necessary.
1803 */
bcmgenet_free_tx_cb(struct device * dev,struct enet_cb * cb)1804 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1805 struct enet_cb *cb)
1806 {
1807 struct sk_buff *skb;
1808
1809 skb = cb->skb;
1810
1811 if (skb) {
1812 cb->skb = NULL;
1813 if (cb == GENET_CB(skb)->first_cb)
1814 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1815 dma_unmap_len(cb, dma_len),
1816 DMA_TO_DEVICE);
1817 else
1818 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1819 dma_unmap_len(cb, dma_len),
1820 DMA_TO_DEVICE);
1821 dma_unmap_addr_set(cb, dma_addr, 0);
1822
1823 if (cb == GENET_CB(skb)->last_cb)
1824 return skb;
1825
1826 } else if (dma_unmap_addr(cb, dma_addr)) {
1827 dma_unmap_page(dev,
1828 dma_unmap_addr(cb, dma_addr),
1829 dma_unmap_len(cb, dma_len),
1830 DMA_TO_DEVICE);
1831 dma_unmap_addr_set(cb, dma_addr, 0);
1832 }
1833
1834 return NULL;
1835 }
1836
1837 /* Simple helper to free a receive control block's resources */
bcmgenet_free_rx_cb(struct device * dev,struct enet_cb * cb)1838 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1839 struct enet_cb *cb)
1840 {
1841 struct sk_buff *skb;
1842
1843 skb = cb->skb;
1844 cb->skb = NULL;
1845
1846 if (dma_unmap_addr(cb, dma_addr)) {
1847 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1848 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1849 dma_unmap_addr_set(cb, dma_addr, 0);
1850 }
1851
1852 return skb;
1853 }
1854
1855 /* Unlocked version of the reclaim routine */
__bcmgenet_tx_reclaim(struct net_device * dev,struct bcmgenet_tx_ring * ring)1856 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1857 struct bcmgenet_tx_ring *ring)
1858 {
1859 struct bcmgenet_priv *priv = netdev_priv(dev);
1860 unsigned int txbds_processed = 0;
1861 unsigned int bytes_compl = 0;
1862 unsigned int pkts_compl = 0;
1863 unsigned int txbds_ready;
1864 unsigned int c_index;
1865 struct sk_buff *skb;
1866
1867 /* Clear status before servicing to reduce spurious interrupts */
1868 bcmgenet_intrl2_1_writel(priv, (1 << ring->index), INTRL2_CPU_CLEAR);
1869
1870 /* Compute how many buffers are transmitted since last xmit call */
1871 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1872 & DMA_C_INDEX_MASK;
1873 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1874
1875 netif_dbg(priv, tx_done, dev,
1876 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1877 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1878
1879 /* Reclaim transmitted buffers */
1880 while (txbds_processed < txbds_ready) {
1881 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1882 &priv->tx_cbs[ring->clean_ptr]);
1883 if (skb) {
1884 pkts_compl++;
1885 bytes_compl += GENET_CB(skb)->bytes_sent;
1886 dev_consume_skb_any(skb);
1887 }
1888
1889 txbds_processed++;
1890 if (likely(ring->clean_ptr < ring->end_ptr))
1891 ring->clean_ptr++;
1892 else
1893 ring->clean_ptr = ring->cb_ptr;
1894 }
1895
1896 ring->free_bds += txbds_processed;
1897 ring->c_index = c_index;
1898
1899 ring->packets += pkts_compl;
1900 ring->bytes += bytes_compl;
1901
1902 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->index),
1903 pkts_compl, bytes_compl);
1904
1905 return txbds_processed;
1906 }
1907
bcmgenet_tx_reclaim(struct net_device * dev,struct bcmgenet_tx_ring * ring,bool all)1908 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1909 struct bcmgenet_tx_ring *ring,
1910 bool all)
1911 {
1912 struct bcmgenet_priv *priv = netdev_priv(dev);
1913 struct device *kdev = &priv->pdev->dev;
1914 unsigned int released, drop, wr_ptr;
1915 struct enet_cb *cb_ptr;
1916 struct sk_buff *skb;
1917
1918 spin_lock_bh(&ring->lock);
1919 released = __bcmgenet_tx_reclaim(dev, ring);
1920 if (all) {
1921 skb = NULL;
1922 drop = (ring->prod_index - ring->c_index) & DMA_C_INDEX_MASK;
1923 released += drop;
1924 ring->prod_index = ring->c_index & DMA_C_INDEX_MASK;
1925 while (drop--) {
1926 cb_ptr = bcmgenet_put_txcb(priv, ring);
1927 skb = cb_ptr->skb;
1928 bcmgenet_free_tx_cb(kdev, cb_ptr);
1929 if (skb && cb_ptr == GENET_CB(skb)->first_cb) {
1930 dev_consume_skb_any(skb);
1931 skb = NULL;
1932 }
1933 }
1934 if (skb)
1935 dev_consume_skb_any(skb);
1936 bcmgenet_tdma_ring_writel(priv, ring->index,
1937 ring->prod_index, TDMA_PROD_INDEX);
1938 wr_ptr = ring->write_ptr * WORDS_PER_BD(priv);
1939 bcmgenet_tdma_ring_writel(priv, ring->index, wr_ptr,
1940 TDMA_WRITE_PTR);
1941 }
1942 spin_unlock_bh(&ring->lock);
1943
1944 return released;
1945 }
1946
bcmgenet_tx_poll(struct napi_struct * napi,int budget)1947 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1948 {
1949 struct bcmgenet_tx_ring *ring =
1950 container_of(napi, struct bcmgenet_tx_ring, napi);
1951 unsigned int work_done = 0;
1952 struct netdev_queue *txq;
1953
1954 spin_lock(&ring->lock);
1955 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1956 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1957 txq = netdev_get_tx_queue(ring->priv->dev, ring->index);
1958 netif_tx_wake_queue(txq);
1959 }
1960 spin_unlock(&ring->lock);
1961
1962 if (work_done == 0) {
1963 napi_complete(napi);
1964 bcmgenet_tx_ring_int_enable(ring);
1965
1966 return 0;
1967 }
1968
1969 return budget;
1970 }
1971
bcmgenet_tx_reclaim_all(struct net_device * dev)1972 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1973 {
1974 struct bcmgenet_priv *priv = netdev_priv(dev);
1975 int i = 0;
1976
1977 do {
1978 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i++], true);
1979 } while (i <= priv->hw_params->tx_queues && netif_is_multiqueue(dev));
1980 }
1981
1982 /* Reallocate the SKB to put enough headroom in front of it and insert
1983 * the transmit checksum offsets in the descriptors
1984 */
bcmgenet_add_tsb(struct net_device * dev,struct sk_buff * skb)1985 static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev,
1986 struct sk_buff *skb)
1987 {
1988 struct bcmgenet_priv *priv = netdev_priv(dev);
1989 struct status_64 *status = NULL;
1990 struct sk_buff *new_skb;
1991 u16 offset;
1992 u8 ip_proto;
1993 __be16 ip_ver;
1994 u32 tx_csum_info;
1995
1996 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1997 /* If 64 byte status block enabled, must make sure skb has
1998 * enough headroom for us to insert 64B status block.
1999 */
2000 new_skb = skb_realloc_headroom(skb, sizeof(*status));
2001 if (!new_skb) {
2002 dev_kfree_skb_any(skb);
2003 priv->mib.tx_realloc_tsb_failed++;
2004 dev->stats.tx_dropped++;
2005 return NULL;
2006 }
2007 dev_consume_skb_any(skb);
2008 skb = new_skb;
2009 priv->mib.tx_realloc_tsb++;
2010 }
2011
2012 skb_push(skb, sizeof(*status));
2013 status = (struct status_64 *)skb->data;
2014
2015 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2016 ip_ver = skb->protocol;
2017 switch (ip_ver) {
2018 case htons(ETH_P_IP):
2019 ip_proto = ip_hdr(skb)->protocol;
2020 break;
2021 case htons(ETH_P_IPV6):
2022 ip_proto = ipv6_hdr(skb)->nexthdr;
2023 break;
2024 default:
2025 /* don't use UDP flag */
2026 ip_proto = 0;
2027 break;
2028 }
2029
2030 offset = skb_checksum_start_offset(skb) - sizeof(*status);
2031 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
2032 (offset + skb->csum_offset) |
2033 STATUS_TX_CSUM_LV;
2034
2035 /* Set the special UDP flag for UDP */
2036 if (ip_proto == IPPROTO_UDP)
2037 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
2038
2039 status->tx_csum_info = tx_csum_info;
2040 }
2041
2042 return skb;
2043 }
2044
bcmgenet_hide_tsb(struct sk_buff * skb)2045 static void bcmgenet_hide_tsb(struct sk_buff *skb)
2046 {
2047 __skb_pull(skb, sizeof(struct status_64));
2048 }
2049
bcmgenet_xmit(struct sk_buff * skb,struct net_device * dev)2050 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
2051 {
2052 struct bcmgenet_priv *priv = netdev_priv(dev);
2053 struct device *kdev = &priv->pdev->dev;
2054 struct bcmgenet_tx_ring *ring = NULL;
2055 struct enet_cb *tx_cb_ptr;
2056 struct netdev_queue *txq;
2057 int nr_frags, index;
2058 dma_addr_t mapping;
2059 unsigned int size;
2060 skb_frag_t *frag;
2061 u32 len_stat;
2062 int ret;
2063 int i;
2064
2065 index = skb_get_queue_mapping(skb);
2066 /* Mapping strategy:
2067 * queue_mapping = 0, unclassified, packet xmited through ring 0
2068 * queue_mapping = 1, goes to ring 1. (highest priority queue)
2069 * queue_mapping = 2, goes to ring 2.
2070 * queue_mapping = 3, goes to ring 3.
2071 * queue_mapping = 4, goes to ring 4.
2072 */
2073 ring = &priv->tx_rings[index];
2074 txq = netdev_get_tx_queue(dev, index);
2075
2076 nr_frags = skb_shinfo(skb)->nr_frags;
2077
2078 spin_lock(&ring->lock);
2079 if (ring->free_bds <= (nr_frags + 1)) {
2080 if (!netif_tx_queue_stopped(txq))
2081 netif_tx_stop_queue(txq);
2082 ret = NETDEV_TX_BUSY;
2083 goto out;
2084 }
2085
2086 /* Retain how many bytes will be sent on the wire, without TSB inserted
2087 * by transmit checksum offload
2088 */
2089 GENET_CB(skb)->bytes_sent = skb->len;
2090
2091 /* add the Transmit Status Block */
2092 skb = bcmgenet_add_tsb(dev, skb);
2093 if (!skb) {
2094 ret = NETDEV_TX_OK;
2095 goto out;
2096 }
2097
2098 for (i = 0; i <= nr_frags; i++) {
2099 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
2100
2101 BUG_ON(!tx_cb_ptr);
2102
2103 if (!i) {
2104 /* Transmit single SKB or head of fragment list */
2105 GENET_CB(skb)->first_cb = tx_cb_ptr;
2106 size = skb_headlen(skb);
2107 mapping = dma_map_single(kdev, skb->data, size,
2108 DMA_TO_DEVICE);
2109 } else {
2110 /* xmit fragment */
2111 frag = &skb_shinfo(skb)->frags[i - 1];
2112 size = skb_frag_size(frag);
2113 mapping = skb_frag_dma_map(kdev, frag, 0, size,
2114 DMA_TO_DEVICE);
2115 }
2116
2117 ret = dma_mapping_error(kdev, mapping);
2118 if (ret) {
2119 priv->mib.tx_dma_failed++;
2120 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
2121 ret = NETDEV_TX_OK;
2122 goto out_unmap_frags;
2123 }
2124 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
2125 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
2126
2127 tx_cb_ptr->skb = skb;
2128
2129 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
2130 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
2131
2132 /* Note: if we ever change from DMA_TX_APPEND_CRC below we
2133 * will need to restore software padding of "runt" packets
2134 */
2135 len_stat |= DMA_TX_APPEND_CRC;
2136
2137 if (!i) {
2138 len_stat |= DMA_SOP;
2139 if (skb->ip_summed == CHECKSUM_PARTIAL)
2140 len_stat |= DMA_TX_DO_CSUM;
2141 }
2142 if (i == nr_frags)
2143 len_stat |= DMA_EOP;
2144
2145 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
2146 }
2147
2148 GENET_CB(skb)->last_cb = tx_cb_ptr;
2149
2150 bcmgenet_hide_tsb(skb);
2151 skb_tx_timestamp(skb);
2152
2153 /* Decrement total BD count and advance our write pointer */
2154 ring->free_bds -= nr_frags + 1;
2155 ring->prod_index += nr_frags + 1;
2156 ring->prod_index &= DMA_P_INDEX_MASK;
2157
2158 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
2159
2160 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
2161 netif_tx_stop_queue(txq);
2162
2163 if (!netdev_xmit_more() || netif_xmit_stopped(txq))
2164 /* Packets are ready, update producer index */
2165 bcmgenet_tdma_ring_writel(priv, ring->index,
2166 ring->prod_index, TDMA_PROD_INDEX);
2167 out:
2168 spin_unlock(&ring->lock);
2169
2170 return ret;
2171
2172 out_unmap_frags:
2173 /* Back up for failed control block mapping */
2174 bcmgenet_put_txcb(priv, ring);
2175
2176 /* Unmap successfully mapped control blocks */
2177 while (i-- > 0) {
2178 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
2179 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
2180 }
2181
2182 dev_kfree_skb(skb);
2183 goto out;
2184 }
2185
bcmgenet_rx_refill(struct bcmgenet_priv * priv,struct enet_cb * cb)2186 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
2187 struct enet_cb *cb)
2188 {
2189 struct device *kdev = &priv->pdev->dev;
2190 struct sk_buff *skb;
2191 struct sk_buff *rx_skb;
2192 dma_addr_t mapping;
2193
2194 /* Allocate a new Rx skb */
2195 skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT,
2196 GFP_ATOMIC | __GFP_NOWARN);
2197 if (!skb) {
2198 priv->mib.alloc_rx_buff_failed++;
2199 netif_err(priv, rx_err, priv->dev,
2200 "%s: Rx skb allocation failed\n", __func__);
2201 return NULL;
2202 }
2203
2204 /* DMA-map the new Rx skb */
2205 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
2206 DMA_FROM_DEVICE);
2207 if (dma_mapping_error(kdev, mapping)) {
2208 priv->mib.rx_dma_failed++;
2209 dev_kfree_skb_any(skb);
2210 netif_err(priv, rx_err, priv->dev,
2211 "%s: Rx skb DMA mapping failed\n", __func__);
2212 return NULL;
2213 }
2214
2215 /* Grab the current Rx skb from the ring and DMA-unmap it */
2216 rx_skb = bcmgenet_free_rx_cb(kdev, cb);
2217
2218 /* Put the new Rx skb on the ring */
2219 cb->skb = skb;
2220 dma_unmap_addr_set(cb, dma_addr, mapping);
2221 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
2222 dmadesc_set_addr(priv, cb->bd_addr, mapping);
2223
2224 /* Return the current Rx skb to caller */
2225 return rx_skb;
2226 }
2227
2228 /* bcmgenet_desc_rx - descriptor based rx process.
2229 * this could be called from bottom half, or from NAPI polling method.
2230 */
bcmgenet_desc_rx(struct bcmgenet_rx_ring * ring,unsigned int budget)2231 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
2232 unsigned int budget)
2233 {
2234 struct bcmgenet_priv *priv = ring->priv;
2235 struct net_device *dev = priv->dev;
2236 struct enet_cb *cb;
2237 struct sk_buff *skb;
2238 u32 dma_length_status;
2239 unsigned long dma_flag;
2240 int len;
2241 unsigned int rxpktprocessed = 0, rxpkttoprocess;
2242 unsigned int bytes_processed = 0;
2243 unsigned int p_index, mask;
2244 unsigned int discards;
2245
2246 /* Clear status before servicing to reduce spurious interrupts */
2247 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
2248 bcmgenet_intrl2_1_writel(priv, mask, INTRL2_CPU_CLEAR);
2249
2250 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
2251
2252 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
2253 DMA_P_INDEX_DISCARD_CNT_MASK;
2254 if (discards > ring->old_discards) {
2255 discards = discards - ring->old_discards;
2256 ring->errors += discards;
2257 ring->old_discards += discards;
2258
2259 /* Clear HW register when we reach 75% of maximum 0xFFFF */
2260 if (ring->old_discards >= 0xC000) {
2261 ring->old_discards = 0;
2262 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
2263 RDMA_PROD_INDEX);
2264 }
2265 }
2266
2267 p_index &= DMA_P_INDEX_MASK;
2268 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
2269
2270 netif_dbg(priv, rx_status, dev,
2271 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
2272
2273 while ((rxpktprocessed < rxpkttoprocess) &&
2274 (rxpktprocessed < budget)) {
2275 struct status_64 *status;
2276 __be16 rx_csum;
2277
2278 cb = &priv->rx_cbs[ring->read_ptr];
2279 skb = bcmgenet_rx_refill(priv, cb);
2280
2281 if (unlikely(!skb)) {
2282 ring->dropped++;
2283 goto next;
2284 }
2285
2286 status = (struct status_64 *)skb->data;
2287 dma_length_status = status->length_status;
2288 if (dev->features & NETIF_F_RXCSUM) {
2289 rx_csum = (__force __be16)(status->rx_csum & 0xffff);
2290 if (rx_csum) {
2291 skb->csum = (__force __wsum)ntohs(rx_csum);
2292 skb->ip_summed = CHECKSUM_COMPLETE;
2293 }
2294 }
2295
2296 /* DMA flags and length are still valid no matter how
2297 * we got the Receive Status Vector (64B RSB or register)
2298 */
2299 dma_flag = dma_length_status & 0xffff;
2300 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
2301
2302 netif_dbg(priv, rx_status, dev,
2303 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
2304 __func__, p_index, ring->c_index,
2305 ring->read_ptr, dma_length_status);
2306
2307 if (unlikely(len > RX_BUF_LENGTH)) {
2308 netif_err(priv, rx_status, dev, "oversized packet\n");
2309 dev->stats.rx_length_errors++;
2310 dev->stats.rx_errors++;
2311 dev_kfree_skb_any(skb);
2312 goto next;
2313 }
2314
2315 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
2316 netif_err(priv, rx_status, dev,
2317 "dropping fragmented packet!\n");
2318 ring->errors++;
2319 dev_kfree_skb_any(skb);
2320 goto next;
2321 }
2322
2323 /* report errors */
2324 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
2325 DMA_RX_OV |
2326 DMA_RX_NO |
2327 DMA_RX_LG |
2328 DMA_RX_RXER))) {
2329 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
2330 (unsigned int)dma_flag);
2331 if (dma_flag & DMA_RX_CRC_ERROR)
2332 dev->stats.rx_crc_errors++;
2333 if (dma_flag & DMA_RX_OV)
2334 dev->stats.rx_over_errors++;
2335 if (dma_flag & DMA_RX_NO)
2336 dev->stats.rx_frame_errors++;
2337 if (dma_flag & DMA_RX_LG)
2338 dev->stats.rx_length_errors++;
2339 dev->stats.rx_errors++;
2340 dev_kfree_skb_any(skb);
2341 goto next;
2342 } /* error packet */
2343
2344 skb_put(skb, len);
2345
2346 /* remove RSB and hardware 2bytes added for IP alignment */
2347 skb_pull(skb, 66);
2348 len -= 66;
2349
2350 if (priv->crc_fwd_en) {
2351 skb_trim(skb, len - ETH_FCS_LEN);
2352 len -= ETH_FCS_LEN;
2353 }
2354
2355 bytes_processed += len;
2356
2357 /*Finish setting up the received SKB and send it to the kernel*/
2358 skb->protocol = eth_type_trans(skb, priv->dev);
2359 ring->packets++;
2360 ring->bytes += len;
2361 if (dma_flag & DMA_RX_MULT)
2362 dev->stats.multicast++;
2363
2364 /* Notify kernel */
2365 napi_gro_receive(&ring->napi, skb);
2366 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
2367
2368 next:
2369 rxpktprocessed++;
2370 if (likely(ring->read_ptr < ring->end_ptr))
2371 ring->read_ptr++;
2372 else
2373 ring->read_ptr = ring->cb_ptr;
2374
2375 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
2376 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
2377 }
2378
2379 ring->dim.bytes = bytes_processed;
2380 ring->dim.packets = rxpktprocessed;
2381
2382 return rxpktprocessed;
2383 }
2384
2385 /* Rx NAPI polling method */
bcmgenet_rx_poll(struct napi_struct * napi,int budget)2386 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
2387 {
2388 struct bcmgenet_rx_ring *ring = container_of(napi,
2389 struct bcmgenet_rx_ring, napi);
2390 struct dim_sample dim_sample = {};
2391 unsigned int work_done;
2392
2393 work_done = bcmgenet_desc_rx(ring, budget);
2394
2395 if (work_done < budget) {
2396 napi_complete_done(napi, work_done);
2397 bcmgenet_rx_ring_int_enable(ring);
2398 }
2399
2400 if (ring->dim.use_dim) {
2401 dim_update_sample(ring->dim.event_ctr, ring->dim.packets,
2402 ring->dim.bytes, &dim_sample);
2403 net_dim(&ring->dim.dim, &dim_sample);
2404 }
2405
2406 return work_done;
2407 }
2408
bcmgenet_dim_work(struct work_struct * work)2409 static void bcmgenet_dim_work(struct work_struct *work)
2410 {
2411 struct dim *dim = container_of(work, struct dim, work);
2412 struct bcmgenet_net_dim *ndim =
2413 container_of(dim, struct bcmgenet_net_dim, dim);
2414 struct bcmgenet_rx_ring *ring =
2415 container_of(ndim, struct bcmgenet_rx_ring, dim);
2416 struct dim_cq_moder cur_profile =
2417 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
2418
2419 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts);
2420 dim->state = DIM_START_MEASURE;
2421 }
2422
2423 /* Assign skb to RX DMA descriptor. */
bcmgenet_alloc_rx_buffers(struct bcmgenet_priv * priv,struct bcmgenet_rx_ring * ring)2424 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
2425 struct bcmgenet_rx_ring *ring)
2426 {
2427 struct enet_cb *cb;
2428 struct sk_buff *skb;
2429 int i;
2430
2431 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2432
2433 /* loop here for each buffer needing assign */
2434 for (i = 0; i < ring->size; i++) {
2435 cb = ring->cbs + i;
2436 skb = bcmgenet_rx_refill(priv, cb);
2437 if (skb)
2438 dev_consume_skb_any(skb);
2439 if (!cb->skb)
2440 return -ENOMEM;
2441 }
2442
2443 return 0;
2444 }
2445
bcmgenet_free_rx_buffers(struct bcmgenet_priv * priv)2446 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
2447 {
2448 struct sk_buff *skb;
2449 struct enet_cb *cb;
2450 int i;
2451
2452 for (i = 0; i < priv->num_rx_bds; i++) {
2453 cb = &priv->rx_cbs[i];
2454
2455 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
2456 if (skb)
2457 dev_consume_skb_any(skb);
2458 }
2459 }
2460
umac_enable_set(struct bcmgenet_priv * priv,u32 mask,bool enable)2461 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
2462 {
2463 u32 reg;
2464
2465 spin_lock_bh(&priv->reg_lock);
2466 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2467 if (reg & CMD_SW_RESET) {
2468 spin_unlock_bh(&priv->reg_lock);
2469 return;
2470 }
2471 if (enable)
2472 reg |= mask;
2473 else
2474 reg &= ~mask;
2475 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2476 spin_unlock_bh(&priv->reg_lock);
2477
2478 /* UniMAC stops on a packet boundary, wait for a full-size packet
2479 * to be processed
2480 */
2481 if (enable == 0)
2482 usleep_range(1000, 2000);
2483 }
2484
reset_umac(struct bcmgenet_priv * priv)2485 static void reset_umac(struct bcmgenet_priv *priv)
2486 {
2487 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
2488 bcmgenet_rbuf_ctrl_set(priv, 0);
2489 udelay(10);
2490
2491 /* issue soft reset and disable MAC while updating its registers */
2492 spin_lock_bh(&priv->reg_lock);
2493 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
2494 udelay(2);
2495 spin_unlock_bh(&priv->reg_lock);
2496 }
2497
bcmgenet_intr_disable(struct bcmgenet_priv * priv)2498 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
2499 {
2500 /* Mask all interrupts.*/
2501 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2502 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2503 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2504 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2505 }
2506
bcmgenet_link_intr_enable(struct bcmgenet_priv * priv)2507 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
2508 {
2509 u32 int0_enable = 0;
2510
2511 /* Monitor cable plug/unplugged event for internal PHY, external PHY
2512 * and MoCA PHY
2513 */
2514 if (priv->internal_phy) {
2515 int0_enable |= UMAC_IRQ_LINK_EVENT;
2516 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
2517 int0_enable |= UMAC_IRQ_PHY_DET_R;
2518 } else if (priv->ext_phy) {
2519 int0_enable |= UMAC_IRQ_LINK_EVENT;
2520 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2521 if (bcmgenet_has_moca_link_det(priv))
2522 int0_enable |= UMAC_IRQ_LINK_EVENT;
2523 }
2524 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2525 }
2526
init_umac(struct bcmgenet_priv * priv)2527 static void init_umac(struct bcmgenet_priv *priv)
2528 {
2529 struct device *kdev = &priv->pdev->dev;
2530 u32 reg;
2531 u32 int0_enable = 0;
2532
2533 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
2534
2535 reset_umac(priv);
2536
2537 /* clear tx/rx counter */
2538 bcmgenet_umac_writel(priv,
2539 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
2540 UMAC_MIB_CTRL);
2541 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
2542
2543 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2544
2545 /* init tx registers, enable TSB */
2546 reg = bcmgenet_tbuf_ctrl_get(priv);
2547 reg |= TBUF_64B_EN;
2548 bcmgenet_tbuf_ctrl_set(priv, reg);
2549
2550 /* init rx registers, enable ip header optimization and RSB */
2551 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
2552 reg |= RBUF_ALIGN_2B | RBUF_64B_EN;
2553 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2554
2555 /* enable rx checksumming */
2556 reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
2557 reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS;
2558 /* If UniMAC forwards CRC, we need to skip over it to get
2559 * a valid CHK bit to be set in the per-packet status word
2560 */
2561 if (priv->crc_fwd_en)
2562 reg |= RBUF_SKIP_FCS;
2563 else
2564 reg &= ~RBUF_SKIP_FCS;
2565 bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL);
2566
2567 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2568 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2569
2570 bcmgenet_intr_disable(priv);
2571
2572 /* Configure backpressure vectors for MoCA */
2573 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2574 reg = bcmgenet_bp_mc_get(priv);
2575 reg |= BIT(priv->hw_params->bp_in_en_shift);
2576
2577 /* bp_mask: back pressure mask */
2578 if (netif_is_multiqueue(priv->dev))
2579 reg |= priv->hw_params->bp_in_mask;
2580 else
2581 reg &= ~priv->hw_params->bp_in_mask;
2582 bcmgenet_bp_mc_set(priv, reg);
2583 }
2584
2585 /* Enable MDIO interrupts on GENET v3+ */
2586 if (bcmgenet_has_mdio_intr(priv))
2587 int0_enable |= UMAC_IRQ_MDIO_EVENT;
2588
2589 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2590
2591 dev_dbg(kdev, "done init umac\n");
2592 }
2593
bcmgenet_init_dim(struct bcmgenet_rx_ring * ring,void (* cb)(struct work_struct * work))2594 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring,
2595 void (*cb)(struct work_struct *work))
2596 {
2597 struct bcmgenet_net_dim *dim = &ring->dim;
2598
2599 INIT_WORK(&dim->dim.work, cb);
2600 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2601 dim->event_ctr = 0;
2602 dim->packets = 0;
2603 dim->bytes = 0;
2604 }
2605
bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring * ring)2606 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring)
2607 {
2608 struct bcmgenet_net_dim *dim = &ring->dim;
2609 struct dim_cq_moder moder;
2610 u32 usecs, pkts;
2611
2612 usecs = ring->rx_coalesce_usecs;
2613 pkts = ring->rx_max_coalesced_frames;
2614
2615 /* If DIM was enabled, re-apply default parameters */
2616 if (dim->use_dim) {
2617 moder = net_dim_get_def_rx_moderation(dim->dim.mode);
2618 usecs = moder.usec;
2619 pkts = moder.pkts;
2620 }
2621
2622 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
2623 }
2624
2625 /* Initialize a Tx ring along with corresponding hardware registers */
bcmgenet_init_tx_ring(struct bcmgenet_priv * priv,unsigned int index,unsigned int size,unsigned int start_ptr,unsigned int end_ptr)2626 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2627 unsigned int index, unsigned int size,
2628 unsigned int start_ptr, unsigned int end_ptr)
2629 {
2630 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2631 u32 words_per_bd = WORDS_PER_BD(priv);
2632 u32 flow_period_val = 0;
2633
2634 spin_lock_init(&ring->lock);
2635 ring->priv = priv;
2636 ring->index = index;
2637 ring->cbs = priv->tx_cbs + start_ptr;
2638 ring->size = size;
2639 ring->clean_ptr = start_ptr;
2640 ring->c_index = 0;
2641 ring->free_bds = size;
2642 ring->write_ptr = start_ptr;
2643 ring->cb_ptr = start_ptr;
2644 ring->end_ptr = end_ptr - 1;
2645 ring->prod_index = 0;
2646
2647 /* Set flow period for ring != 0 */
2648 if (index)
2649 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2650
2651 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2652 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2653 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2654 /* Disable rate control for now */
2655 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2656 TDMA_FLOW_PERIOD);
2657 bcmgenet_tdma_ring_writel(priv, index,
2658 ((size << DMA_RING_SIZE_SHIFT) |
2659 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2660
2661 /* Set start and end address, read and write pointers */
2662 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2663 DMA_START_ADDR);
2664 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2665 TDMA_READ_PTR);
2666 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2667 TDMA_WRITE_PTR);
2668 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2669 DMA_END_ADDR);
2670
2671 /* Initialize Tx NAPI */
2672 netif_napi_add_tx(priv->dev, &ring->napi, bcmgenet_tx_poll);
2673 }
2674
2675 /* Initialize a RDMA ring */
bcmgenet_init_rx_ring(struct bcmgenet_priv * priv,unsigned int index,unsigned int size,unsigned int start_ptr,unsigned int end_ptr)2676 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2677 unsigned int index, unsigned int size,
2678 unsigned int start_ptr, unsigned int end_ptr)
2679 {
2680 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2681 u32 words_per_bd = WORDS_PER_BD(priv);
2682 int ret;
2683
2684 ring->priv = priv;
2685 ring->index = index;
2686 ring->cbs = priv->rx_cbs + start_ptr;
2687 ring->size = size;
2688 ring->c_index = 0;
2689 ring->read_ptr = start_ptr;
2690 ring->cb_ptr = start_ptr;
2691 ring->end_ptr = end_ptr - 1;
2692
2693 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2694 if (ret)
2695 return ret;
2696
2697 bcmgenet_init_dim(ring, bcmgenet_dim_work);
2698 bcmgenet_init_rx_coalesce(ring);
2699
2700 /* Initialize Rx NAPI */
2701 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll);
2702
2703 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2704 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2705 bcmgenet_rdma_ring_writel(priv, index,
2706 ((size << DMA_RING_SIZE_SHIFT) |
2707 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2708 bcmgenet_rdma_ring_writel(priv, index,
2709 (DMA_FC_THRESH_LO <<
2710 DMA_XOFF_THRESHOLD_SHIFT) |
2711 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2712
2713 /* Set start and end address, read and write pointers */
2714 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2715 DMA_START_ADDR);
2716 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2717 RDMA_READ_PTR);
2718 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2719 RDMA_WRITE_PTR);
2720 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2721 DMA_END_ADDR);
2722
2723 return ret;
2724 }
2725
bcmgenet_enable_tx_napi(struct bcmgenet_priv * priv)2726 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2727 {
2728 unsigned int i;
2729 struct bcmgenet_tx_ring *ring;
2730
2731 for (i = 0; i <= priv->hw_params->tx_queues; ++i) {
2732 ring = &priv->tx_rings[i];
2733 napi_enable(&ring->napi);
2734 bcmgenet_tx_ring_int_enable(ring);
2735 }
2736 }
2737
bcmgenet_disable_tx_napi(struct bcmgenet_priv * priv)2738 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2739 {
2740 unsigned int i;
2741 struct bcmgenet_tx_ring *ring;
2742
2743 for (i = 0; i <= priv->hw_params->tx_queues; ++i) {
2744 ring = &priv->tx_rings[i];
2745 napi_disable(&ring->napi);
2746 }
2747 }
2748
bcmgenet_fini_tx_napi(struct bcmgenet_priv * priv)2749 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2750 {
2751 unsigned int i;
2752 struct bcmgenet_tx_ring *ring;
2753
2754 for (i = 0; i <= priv->hw_params->tx_queues; ++i) {
2755 ring = &priv->tx_rings[i];
2756 netif_napi_del(&ring->napi);
2757 }
2758 }
2759
bcmgenet_tdma_disable(struct bcmgenet_priv * priv)2760 static int bcmgenet_tdma_disable(struct bcmgenet_priv *priv)
2761 {
2762 int timeout = 0;
2763 u32 reg, mask;
2764
2765 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2766 mask = (1 << (priv->hw_params->tx_queues + 1)) - 1;
2767 mask = (mask << DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2768 reg &= ~mask;
2769 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2770
2771 /* Check DMA status register to confirm DMA is disabled */
2772 while (timeout++ < DMA_TIMEOUT_VAL) {
2773 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2774 if ((reg & mask) == mask)
2775 return 0;
2776
2777 udelay(1);
2778 }
2779
2780 return -ETIMEDOUT;
2781 }
2782
bcmgenet_rdma_disable(struct bcmgenet_priv * priv)2783 static int bcmgenet_rdma_disable(struct bcmgenet_priv *priv)
2784 {
2785 int timeout = 0;
2786 u32 reg, mask;
2787
2788 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2789 mask = (1 << (priv->hw_params->rx_queues + 1)) - 1;
2790 mask = (mask << DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2791 reg &= ~mask;
2792 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2793
2794 /* Check DMA status register to confirm DMA is disabled */
2795 while (timeout++ < DMA_TIMEOUT_VAL) {
2796 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2797 if ((reg & mask) == mask)
2798 return 0;
2799
2800 udelay(1);
2801 }
2802
2803 return -ETIMEDOUT;
2804 }
2805
2806 /* Initialize Tx queues
2807 *
2808 * Queues 1-4 are priority-based, each one has 32 descriptors,
2809 * with queue 1 being the highest priority queue.
2810 *
2811 * Queue 0 is the default Tx queue with
2812 * GENET_Q0_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2813 *
2814 * The transmit control block pool is then partitioned as follows:
2815 * - Tx queue 0 uses tx_cbs[0..127]
2816 * - Tx queue 1 uses tx_cbs[128..159]
2817 * - Tx queue 2 uses tx_cbs[160..191]
2818 * - Tx queue 3 uses tx_cbs[192..223]
2819 * - Tx queue 4 uses tx_cbs[224..255]
2820 */
bcmgenet_init_tx_queues(struct net_device * dev)2821 static void bcmgenet_init_tx_queues(struct net_device *dev)
2822 {
2823 struct bcmgenet_priv *priv = netdev_priv(dev);
2824 unsigned int start = 0, end = GENET_Q0_TX_BD_CNT;
2825 u32 i, ring_mask, dma_priority[3] = {0, 0, 0};
2826
2827 /* Enable strict priority arbiter mode */
2828 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2829
2830 /* Initialize Tx priority queues */
2831 for (i = 0; i <= priv->hw_params->tx_queues; i++) {
2832 bcmgenet_init_tx_ring(priv, i, end - start, start, end);
2833 start = end;
2834 end += priv->hw_params->tx_bds_per_q;
2835 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2836 (i ? GENET_Q1_PRIORITY : GENET_Q0_PRIORITY)
2837 << DMA_PRIO_REG_SHIFT(i);
2838 }
2839
2840 /* Set Tx queue priorities */
2841 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2842 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2843 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2844
2845 /* Configure Tx queues as descriptor rings */
2846 ring_mask = (1 << (priv->hw_params->tx_queues + 1)) - 1;
2847 bcmgenet_tdma_writel(priv, ring_mask, DMA_RING_CFG);
2848
2849 /* Enable Tx rings */
2850 ring_mask <<= DMA_RING_BUF_EN_SHIFT;
2851 bcmgenet_tdma_writel(priv, ring_mask, DMA_CTRL);
2852 }
2853
bcmgenet_enable_rx_napi(struct bcmgenet_priv * priv)2854 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2855 {
2856 unsigned int i;
2857 struct bcmgenet_rx_ring *ring;
2858
2859 for (i = 0; i <= priv->hw_params->rx_queues; ++i) {
2860 ring = &priv->rx_rings[i];
2861 napi_enable(&ring->napi);
2862 bcmgenet_rx_ring_int_enable(ring);
2863 }
2864 }
2865
bcmgenet_disable_rx_napi(struct bcmgenet_priv * priv)2866 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2867 {
2868 unsigned int i;
2869 struct bcmgenet_rx_ring *ring;
2870
2871 for (i = 0; i <= priv->hw_params->rx_queues; ++i) {
2872 ring = &priv->rx_rings[i];
2873 napi_disable(&ring->napi);
2874 cancel_work_sync(&ring->dim.dim.work);
2875 }
2876 }
2877
bcmgenet_fini_rx_napi(struct bcmgenet_priv * priv)2878 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2879 {
2880 unsigned int i;
2881 struct bcmgenet_rx_ring *ring;
2882
2883 for (i = 0; i <= priv->hw_params->rx_queues; ++i) {
2884 ring = &priv->rx_rings[i];
2885 netif_napi_del(&ring->napi);
2886 }
2887 }
2888
2889 /* Initialize Rx queues
2890 *
2891 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2892 * used to direct traffic to these queues.
2893 *
2894 * Queue 0 is also the default Rx queue with GENET_Q0_RX_BD_CNT descriptors.
2895 */
bcmgenet_init_rx_queues(struct net_device * dev)2896 static int bcmgenet_init_rx_queues(struct net_device *dev)
2897 {
2898 struct bcmgenet_priv *priv = netdev_priv(dev);
2899 unsigned int start = 0, end = GENET_Q0_RX_BD_CNT;
2900 u32 i, ring_mask;
2901 int ret;
2902
2903 /* Initialize Rx priority queues */
2904 for (i = 0; i <= priv->hw_params->rx_queues; i++) {
2905 ret = bcmgenet_init_rx_ring(priv, i, end - start, start, end);
2906 if (ret)
2907 return ret;
2908
2909 start = end;
2910 end += priv->hw_params->rx_bds_per_q;
2911 }
2912
2913 /* Configure Rx queues as descriptor rings */
2914 ring_mask = (1 << (priv->hw_params->rx_queues + 1)) - 1;
2915 bcmgenet_rdma_writel(priv, ring_mask, DMA_RING_CFG);
2916
2917 /* Enable Rx rings */
2918 ring_mask <<= DMA_RING_BUF_EN_SHIFT;
2919 bcmgenet_rdma_writel(priv, ring_mask, DMA_CTRL);
2920
2921 return 0;
2922 }
2923
bcmgenet_dma_teardown(struct bcmgenet_priv * priv)2924 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2925 {
2926 int ret = 0;
2927
2928 /* Disable TDMA to stop add more frames in TX DMA */
2929 if (-ETIMEDOUT == bcmgenet_tdma_disable(priv)) {
2930 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2931 ret = -ETIMEDOUT;
2932 }
2933
2934 /* Wait 10ms for packet drain in both tx and rx dma */
2935 usleep_range(10000, 20000);
2936
2937 /* Disable RDMA */
2938 if (-ETIMEDOUT == bcmgenet_rdma_disable(priv)) {
2939 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2940 ret = -ETIMEDOUT;
2941 }
2942
2943 return ret;
2944 }
2945
bcmgenet_fini_dma(struct bcmgenet_priv * priv)2946 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2947 {
2948 struct netdev_queue *txq;
2949 int i;
2950
2951 bcmgenet_fini_rx_napi(priv);
2952 bcmgenet_fini_tx_napi(priv);
2953
2954 for (i = 0; i <= priv->hw_params->tx_queues; i++) {
2955 txq = netdev_get_tx_queue(priv->dev, i);
2956 netdev_tx_reset_queue(txq);
2957 }
2958
2959 bcmgenet_free_rx_buffers(priv);
2960 kfree(priv->rx_cbs);
2961 kfree(priv->tx_cbs);
2962 }
2963
2964 /* init_edma: Initialize DMA control register */
bcmgenet_init_dma(struct bcmgenet_priv * priv,bool flush_rx)2965 static int bcmgenet_init_dma(struct bcmgenet_priv *priv, bool flush_rx)
2966 {
2967 struct enet_cb *cb;
2968 unsigned int i;
2969 int ret;
2970 u32 reg;
2971
2972 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2973
2974 /* Disable TX DMA */
2975 ret = bcmgenet_tdma_disable(priv);
2976 if (ret) {
2977 netdev_err(priv->dev, "failed to halt Tx DMA\n");
2978 return ret;
2979 }
2980
2981 /* Disable RX DMA */
2982 ret = bcmgenet_rdma_disable(priv);
2983 if (ret) {
2984 netdev_err(priv->dev, "failed to halt Rx DMA\n");
2985 return ret;
2986 }
2987
2988 /* Flush TX queues */
2989 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2990 udelay(10);
2991 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2992
2993 if (flush_rx) {
2994 reg = bcmgenet_rbuf_ctrl_get(priv);
2995 bcmgenet_rbuf_ctrl_set(priv, reg | BIT(0));
2996 udelay(10);
2997 bcmgenet_rbuf_ctrl_set(priv, reg);
2998 udelay(10);
2999 }
3000
3001 /* Initialize common Rx ring structures */
3002 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
3003 priv->num_rx_bds = TOTAL_DESC;
3004 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
3005 GFP_KERNEL);
3006 if (!priv->rx_cbs)
3007 return -ENOMEM;
3008
3009 for (i = 0; i < priv->num_rx_bds; i++) {
3010 cb = priv->rx_cbs + i;
3011 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
3012 }
3013
3014 /* Initialize common TX ring structures */
3015 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
3016 priv->num_tx_bds = TOTAL_DESC;
3017 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
3018 GFP_KERNEL);
3019 if (!priv->tx_cbs) {
3020 kfree(priv->rx_cbs);
3021 return -ENOMEM;
3022 }
3023
3024 for (i = 0; i < priv->num_tx_bds; i++) {
3025 cb = priv->tx_cbs + i;
3026 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
3027 }
3028
3029 /* Init rDma */
3030 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length,
3031 DMA_SCB_BURST_SIZE);
3032
3033 /* Initialize Rx queues */
3034 ret = bcmgenet_init_rx_queues(priv->dev);
3035 if (ret) {
3036 netdev_err(priv->dev, "failed to initialize Rx queues\n");
3037 bcmgenet_free_rx_buffers(priv);
3038 kfree(priv->rx_cbs);
3039 kfree(priv->tx_cbs);
3040 return ret;
3041 }
3042
3043 /* Init tDma */
3044 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length,
3045 DMA_SCB_BURST_SIZE);
3046
3047 /* Initialize Tx queues */
3048 bcmgenet_init_tx_queues(priv->dev);
3049
3050 /* Enable RX/TX DMA */
3051 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3052 reg |= DMA_EN;
3053 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3054
3055 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3056 reg |= DMA_EN;
3057 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3058
3059 return 0;
3060 }
3061
3062 /* Interrupt bottom half */
bcmgenet_irq_task(struct work_struct * work)3063 static void bcmgenet_irq_task(struct work_struct *work)
3064 {
3065 unsigned int status;
3066 struct bcmgenet_priv *priv = container_of(
3067 work, struct bcmgenet_priv, bcmgenet_irq_work);
3068
3069 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
3070
3071 spin_lock_irq(&priv->lock);
3072 status = priv->irq0_stat;
3073 priv->irq0_stat = 0;
3074 spin_unlock_irq(&priv->lock);
3075
3076 if (status & UMAC_IRQ_PHY_DET_R &&
3077 priv->dev->phydev->autoneg != AUTONEG_ENABLE) {
3078 phy_init_hw(priv->dev->phydev);
3079 genphy_config_aneg(priv->dev->phydev);
3080 }
3081
3082 /* Link UP/DOWN event */
3083 if (status & UMAC_IRQ_LINK_EVENT)
3084 phy_mac_interrupt(priv->dev->phydev);
3085
3086 }
3087
3088 /* bcmgenet_isr1: handle Rx and Tx queues */
bcmgenet_isr1(int irq,void * dev_id)3089 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
3090 {
3091 struct bcmgenet_priv *priv = dev_id;
3092 struct bcmgenet_rx_ring *rx_ring;
3093 struct bcmgenet_tx_ring *tx_ring;
3094 unsigned int index, status;
3095
3096 /* Read irq status */
3097 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
3098 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3099
3100 /* clear interrupts */
3101 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
3102
3103 netif_dbg(priv, intr, priv->dev,
3104 "%s: IRQ=0x%x\n", __func__, status);
3105
3106 /* Check Rx priority queue interrupts */
3107 for (index = 0; index <= priv->hw_params->rx_queues; index++) {
3108 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
3109 continue;
3110
3111 rx_ring = &priv->rx_rings[index];
3112 rx_ring->dim.event_ctr++;
3113
3114 if (likely(napi_schedule_prep(&rx_ring->napi))) {
3115 bcmgenet_rx_ring_int_disable(rx_ring);
3116 __napi_schedule_irqoff(&rx_ring->napi);
3117 }
3118 }
3119
3120 /* Check Tx priority queue interrupts */
3121 for (index = 0; index <= priv->hw_params->tx_queues; index++) {
3122 if (!(status & BIT(index)))
3123 continue;
3124
3125 tx_ring = &priv->tx_rings[index];
3126
3127 if (likely(napi_schedule_prep(&tx_ring->napi))) {
3128 bcmgenet_tx_ring_int_disable(tx_ring);
3129 __napi_schedule_irqoff(&tx_ring->napi);
3130 }
3131 }
3132
3133 return IRQ_HANDLED;
3134 }
3135
3136 /* bcmgenet_isr0: handle other stuff */
bcmgenet_isr0(int irq,void * dev_id)3137 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
3138 {
3139 struct bcmgenet_priv *priv = dev_id;
3140 unsigned int status;
3141 unsigned long flags;
3142
3143 /* Read irq status */
3144 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
3145 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3146
3147 /* clear interrupts */
3148 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
3149
3150 netif_dbg(priv, intr, priv->dev,
3151 "IRQ=0x%x\n", status);
3152
3153 if (bcmgenet_has_mdio_intr(priv) && status & UMAC_IRQ_MDIO_EVENT)
3154 wake_up(&priv->wq);
3155
3156 /* all other interested interrupts handled in bottom half */
3157 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R);
3158 if (status) {
3159 /* Save irq status for bottom-half processing. */
3160 spin_lock_irqsave(&priv->lock, flags);
3161 priv->irq0_stat |= status;
3162 spin_unlock_irqrestore(&priv->lock, flags);
3163
3164 schedule_work(&priv->bcmgenet_irq_work);
3165 }
3166
3167 return IRQ_HANDLED;
3168 }
3169
bcmgenet_wol_isr(int irq,void * dev_id)3170 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
3171 {
3172 /* Acknowledge the interrupt */
3173 return IRQ_HANDLED;
3174 }
3175
bcmgenet_umac_reset(struct bcmgenet_priv * priv)3176 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
3177 {
3178 u32 reg;
3179
3180 reg = bcmgenet_rbuf_ctrl_get(priv);
3181 reg |= BIT(1);
3182 bcmgenet_rbuf_ctrl_set(priv, reg);
3183 udelay(10);
3184
3185 reg &= ~BIT(1);
3186 bcmgenet_rbuf_ctrl_set(priv, reg);
3187 udelay(10);
3188 }
3189
bcmgenet_set_hw_addr(struct bcmgenet_priv * priv,const unsigned char * addr)3190 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
3191 const unsigned char *addr)
3192 {
3193 bcmgenet_umac_writel(priv, get_unaligned_be32(&addr[0]), UMAC_MAC0);
3194 bcmgenet_umac_writel(priv, get_unaligned_be16(&addr[4]), UMAC_MAC1);
3195 }
3196
bcmgenet_get_hw_addr(struct bcmgenet_priv * priv,unsigned char * addr)3197 static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv,
3198 unsigned char *addr)
3199 {
3200 u32 addr_tmp;
3201
3202 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0);
3203 put_unaligned_be32(addr_tmp, &addr[0]);
3204 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1);
3205 put_unaligned_be16(addr_tmp, &addr[4]);
3206 }
3207
bcmgenet_netif_start(struct net_device * dev)3208 static void bcmgenet_netif_start(struct net_device *dev)
3209 {
3210 struct bcmgenet_priv *priv = netdev_priv(dev);
3211
3212 /* Start the network engine */
3213 netif_addr_lock_bh(dev);
3214 bcmgenet_set_rx_mode(dev);
3215 netif_addr_unlock_bh(dev);
3216 bcmgenet_enable_rx_napi(priv);
3217
3218 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
3219
3220 bcmgenet_enable_tx_napi(priv);
3221
3222 /* Monitor link interrupts now */
3223 bcmgenet_link_intr_enable(priv);
3224
3225 phy_start(dev->phydev);
3226 }
3227
bcmgenet_open(struct net_device * dev)3228 static int bcmgenet_open(struct net_device *dev)
3229 {
3230 struct bcmgenet_priv *priv = netdev_priv(dev);
3231 int ret;
3232
3233 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
3234
3235 /* Turn on the clock */
3236 clk_prepare_enable(priv->clk);
3237
3238 /* If this is an internal GPHY, power it back on now, before UniMAC is
3239 * brought out of reset as absolutely no UniMAC activity is allowed
3240 */
3241 if (priv->internal_phy)
3242 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3243
3244 /* take MAC out of reset */
3245 bcmgenet_umac_reset(priv);
3246
3247 init_umac(priv);
3248
3249 /* Apply features again in case we changed them while interface was
3250 * down
3251 */
3252 bcmgenet_set_features(dev, dev->features);
3253
3254 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3255
3256 /* HFB init */
3257 bcmgenet_hfb_init(priv);
3258
3259 /* Reinitialize TDMA and RDMA and SW housekeeping */
3260 ret = bcmgenet_init_dma(priv, true);
3261 if (ret) {
3262 netdev_err(dev, "failed to initialize DMA\n");
3263 goto err_clk_disable;
3264 }
3265
3266 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
3267 dev->name, priv);
3268 if (ret < 0) {
3269 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
3270 goto err_fini_dma;
3271 }
3272
3273 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
3274 dev->name, priv);
3275 if (ret < 0) {
3276 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
3277 goto err_irq0;
3278 }
3279
3280 ret = bcmgenet_mii_probe(dev);
3281 if (ret) {
3282 netdev_err(dev, "failed to connect to PHY\n");
3283 goto err_irq1;
3284 }
3285
3286 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause);
3287
3288 bcmgenet_netif_start(dev);
3289
3290 netif_tx_start_all_queues(dev);
3291
3292 return 0;
3293
3294 err_irq1:
3295 free_irq(priv->irq1, priv);
3296 err_irq0:
3297 free_irq(priv->irq0, priv);
3298 err_fini_dma:
3299 bcmgenet_dma_teardown(priv);
3300 bcmgenet_fini_dma(priv);
3301 err_clk_disable:
3302 if (priv->internal_phy)
3303 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3304 clk_disable_unprepare(priv->clk);
3305 return ret;
3306 }
3307
bcmgenet_netif_stop(struct net_device * dev,bool stop_phy)3308 static void bcmgenet_netif_stop(struct net_device *dev, bool stop_phy)
3309 {
3310 struct bcmgenet_priv *priv = netdev_priv(dev);
3311
3312 netif_tx_disable(dev);
3313
3314 /* Disable MAC receive */
3315 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL);
3316 umac_enable_set(priv, CMD_RX_EN, false);
3317
3318 if (stop_phy)
3319 phy_stop(dev->phydev);
3320
3321 bcmgenet_dma_teardown(priv);
3322
3323 /* Disable MAC transmit. TX DMA disabled must be done before this */
3324 umac_enable_set(priv, CMD_TX_EN, false);
3325
3326 bcmgenet_disable_tx_napi(priv);
3327 bcmgenet_disable_rx_napi(priv);
3328 bcmgenet_intr_disable(priv);
3329
3330 /* Wait for pending work items to complete. Since interrupts are
3331 * disabled no new work will be scheduled.
3332 */
3333 cancel_work_sync(&priv->bcmgenet_irq_work);
3334
3335 /* tx reclaim */
3336 bcmgenet_tx_reclaim_all(dev);
3337 bcmgenet_fini_dma(priv);
3338 }
3339
bcmgenet_close(struct net_device * dev)3340 static int bcmgenet_close(struct net_device *dev)
3341 {
3342 struct bcmgenet_priv *priv = netdev_priv(dev);
3343 int ret = 0;
3344
3345 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
3346
3347 bcmgenet_netif_stop(dev, false);
3348
3349 /* Really kill the PHY state machine and disconnect from it */
3350 phy_disconnect(dev->phydev);
3351
3352 free_irq(priv->irq0, priv);
3353 free_irq(priv->irq1, priv);
3354
3355 if (priv->internal_phy)
3356 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3357
3358 clk_disable_unprepare(priv->clk);
3359
3360 return ret;
3361 }
3362
bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring * ring)3363 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
3364 {
3365 struct bcmgenet_priv *priv = ring->priv;
3366 u32 p_index, c_index, intsts, intmsk;
3367 struct netdev_queue *txq;
3368 unsigned int free_bds;
3369 bool txq_stopped;
3370
3371 if (!netif_msg_tx_err(priv))
3372 return;
3373
3374 txq = netdev_get_tx_queue(priv->dev, ring->index);
3375
3376 spin_lock(&ring->lock);
3377 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3378 intmsk = 1 << ring->index;
3379 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3380 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3381 txq_stopped = netif_tx_queue_stopped(txq);
3382 free_bds = ring->free_bds;
3383 spin_unlock(&ring->lock);
3384
3385 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3386 "TX queue status: %s, interrupts: %s\n"
3387 "(sw)free_bds: %d (sw)size: %d\n"
3388 "(sw)p_index: %d (hw)p_index: %d\n"
3389 "(sw)c_index: %d (hw)c_index: %d\n"
3390 "(sw)clean_p: %d (sw)write_p: %d\n"
3391 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3392 ring->index, ring->index,
3393 txq_stopped ? "stopped" : "active",
3394 intsts & intmsk ? "enabled" : "disabled",
3395 free_bds, ring->size,
3396 ring->prod_index, p_index & DMA_P_INDEX_MASK,
3397 ring->c_index, c_index & DMA_C_INDEX_MASK,
3398 ring->clean_ptr, ring->write_ptr,
3399 ring->cb_ptr, ring->end_ptr);
3400 }
3401
bcmgenet_timeout(struct net_device * dev,unsigned int txqueue)3402 static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue)
3403 {
3404 struct bcmgenet_priv *priv = netdev_priv(dev);
3405 u32 int1_enable = 0;
3406 unsigned int q;
3407
3408 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3409
3410 for (q = 0; q <= priv->hw_params->tx_queues; q++)
3411 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3412
3413 bcmgenet_tx_reclaim_all(dev);
3414
3415 for (q = 0; q <= priv->hw_params->tx_queues; q++)
3416 int1_enable |= (1 << q);
3417
3418 /* Re-enable TX interrupts if disabled */
3419 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3420
3421 netif_trans_update(dev);
3422
3423 dev->stats.tx_errors++;
3424
3425 netif_tx_wake_all_queues(dev);
3426 }
3427
3428 #define MAX_MDF_FILTER 17
3429
bcmgenet_set_mdf_addr(struct bcmgenet_priv * priv,const unsigned char * addr,int * i)3430 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3431 const unsigned char *addr,
3432 int *i)
3433 {
3434 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3435 UMAC_MDF_ADDR + (*i * 4));
3436 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3437 addr[4] << 8 | addr[5],
3438 UMAC_MDF_ADDR + ((*i + 1) * 4));
3439 *i += 2;
3440 }
3441
bcmgenet_set_rx_mode(struct net_device * dev)3442 static void bcmgenet_set_rx_mode(struct net_device *dev)
3443 {
3444 struct bcmgenet_priv *priv = netdev_priv(dev);
3445 struct netdev_hw_addr *ha;
3446 int i, nfilter;
3447 u32 reg;
3448
3449 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3450
3451 /* Number of filters needed */
3452 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3453
3454 /*
3455 * Turn on promicuous mode for three scenarios
3456 * 1. IFF_PROMISC flag is set
3457 * 2. IFF_ALLMULTI flag is set
3458 * 3. The number of filters needed exceeds the number filters
3459 * supported by the hardware.
3460 */
3461 spin_lock(&priv->reg_lock);
3462 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3463 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3464 (nfilter > MAX_MDF_FILTER)) {
3465 reg |= CMD_PROMISC;
3466 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3467 spin_unlock(&priv->reg_lock);
3468 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3469 return;
3470 } else {
3471 reg &= ~CMD_PROMISC;
3472 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3473 spin_unlock(&priv->reg_lock);
3474 }
3475
3476 /* update MDF filter */
3477 i = 0;
3478 /* Broadcast */
3479 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
3480 /* my own address.*/
3481 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
3482
3483 /* Unicast */
3484 netdev_for_each_uc_addr(ha, dev)
3485 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3486
3487 /* Multicast */
3488 netdev_for_each_mc_addr(ha, dev)
3489 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3490
3491 /* Enable filters */
3492 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3493 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3494 }
3495
3496 /* Set the hardware MAC address. */
bcmgenet_set_mac_addr(struct net_device * dev,void * p)3497 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3498 {
3499 struct sockaddr *addr = p;
3500
3501 /* Setting the MAC address at the hardware level is not possible
3502 * without disabling the UniMAC RX/TX enable bits.
3503 */
3504 if (netif_running(dev))
3505 return -EBUSY;
3506
3507 eth_hw_addr_set(dev, addr->sa_data);
3508
3509 return 0;
3510 }
3511
bcmgenet_get_stats(struct net_device * dev)3512 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3513 {
3514 struct bcmgenet_priv *priv = netdev_priv(dev);
3515 unsigned long tx_bytes = 0, tx_packets = 0;
3516 unsigned long rx_bytes = 0, rx_packets = 0;
3517 unsigned long rx_errors = 0, rx_dropped = 0;
3518 struct bcmgenet_tx_ring *tx_ring;
3519 struct bcmgenet_rx_ring *rx_ring;
3520 unsigned int q;
3521
3522 for (q = 0; q <= priv->hw_params->tx_queues; q++) {
3523 tx_ring = &priv->tx_rings[q];
3524 tx_bytes += tx_ring->bytes;
3525 tx_packets += tx_ring->packets;
3526 }
3527
3528 for (q = 0; q <= priv->hw_params->rx_queues; q++) {
3529 rx_ring = &priv->rx_rings[q];
3530
3531 rx_bytes += rx_ring->bytes;
3532 rx_packets += rx_ring->packets;
3533 rx_errors += rx_ring->errors;
3534 rx_dropped += rx_ring->dropped;
3535 }
3536
3537 dev->stats.tx_bytes = tx_bytes;
3538 dev->stats.tx_packets = tx_packets;
3539 dev->stats.rx_bytes = rx_bytes;
3540 dev->stats.rx_packets = rx_packets;
3541 dev->stats.rx_errors = rx_errors;
3542 dev->stats.rx_missed_errors = rx_errors;
3543 dev->stats.rx_dropped = rx_dropped;
3544 return &dev->stats;
3545 }
3546
bcmgenet_change_carrier(struct net_device * dev,bool new_carrier)3547 static int bcmgenet_change_carrier(struct net_device *dev, bool new_carrier)
3548 {
3549 struct bcmgenet_priv *priv = netdev_priv(dev);
3550
3551 if (!dev->phydev || !phy_is_pseudo_fixed_link(dev->phydev) ||
3552 priv->phy_interface != PHY_INTERFACE_MODE_MOCA)
3553 return -EOPNOTSUPP;
3554
3555 if (new_carrier)
3556 netif_carrier_on(dev);
3557 else
3558 netif_carrier_off(dev);
3559
3560 return 0;
3561 }
3562
3563 static const struct net_device_ops bcmgenet_netdev_ops = {
3564 .ndo_open = bcmgenet_open,
3565 .ndo_stop = bcmgenet_close,
3566 .ndo_start_xmit = bcmgenet_xmit,
3567 .ndo_tx_timeout = bcmgenet_timeout,
3568 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3569 .ndo_set_mac_address = bcmgenet_set_mac_addr,
3570 .ndo_eth_ioctl = phy_do_ioctl_running,
3571 .ndo_set_features = bcmgenet_set_features,
3572 .ndo_get_stats = bcmgenet_get_stats,
3573 .ndo_change_carrier = bcmgenet_change_carrier,
3574 };
3575
3576 /* GENET hardware parameters/characteristics */
3577 static const struct bcmgenet_hw_params bcmgenet_hw_params_v1 = {
3578 .tx_queues = 0,
3579 .tx_bds_per_q = 0,
3580 .rx_queues = 0,
3581 .rx_bds_per_q = 0,
3582 .bp_in_en_shift = 16,
3583 .bp_in_mask = 0xffff,
3584 .hfb_filter_cnt = 16,
3585 .hfb_filter_size = 64,
3586 .qtag_mask = 0x1F,
3587 .hfb_offset = 0x1000,
3588 .hfb_reg_offset = GENET_RBUF_OFF + RBUF_HFB_CTRL_V1,
3589 .rdma_offset = 0x2000,
3590 .tdma_offset = 0x3000,
3591 .words_per_bd = 2,
3592 };
3593
3594 static const struct bcmgenet_hw_params bcmgenet_hw_params_v2 = {
3595 .tx_queues = 4,
3596 .tx_bds_per_q = 32,
3597 .rx_queues = 0,
3598 .rx_bds_per_q = 0,
3599 .bp_in_en_shift = 16,
3600 .bp_in_mask = 0xffff,
3601 .hfb_filter_cnt = 16,
3602 .hfb_filter_size = 64,
3603 .qtag_mask = 0x1F,
3604 .tbuf_offset = 0x0600,
3605 .hfb_offset = 0x1000,
3606 .hfb_reg_offset = 0x2000,
3607 .rdma_offset = 0x3000,
3608 .tdma_offset = 0x4000,
3609 .words_per_bd = 2,
3610 };
3611
3612 static const struct bcmgenet_hw_params bcmgenet_hw_params_v3 = {
3613 .tx_queues = 4,
3614 .tx_bds_per_q = 32,
3615 .rx_queues = 0,
3616 .rx_bds_per_q = 0,
3617 .bp_in_en_shift = 17,
3618 .bp_in_mask = 0x1ffff,
3619 .hfb_filter_cnt = 48,
3620 .hfb_filter_size = 128,
3621 .qtag_mask = 0x3F,
3622 .tbuf_offset = 0x0600,
3623 .hfb_offset = 0x8000,
3624 .hfb_reg_offset = 0xfc00,
3625 .rdma_offset = 0x10000,
3626 .tdma_offset = 0x11000,
3627 .words_per_bd = 2,
3628 };
3629
3630 static const struct bcmgenet_hw_params bcmgenet_hw_params_v4 = {
3631 .tx_queues = 4,
3632 .tx_bds_per_q = 32,
3633 .rx_queues = 0,
3634 .rx_bds_per_q = 0,
3635 .bp_in_en_shift = 17,
3636 .bp_in_mask = 0x1ffff,
3637 .hfb_filter_cnt = 48,
3638 .hfb_filter_size = 128,
3639 .qtag_mask = 0x3F,
3640 .tbuf_offset = 0x0600,
3641 .hfb_offset = 0x8000,
3642 .hfb_reg_offset = 0xfc00,
3643 .rdma_offset = 0x2000,
3644 .tdma_offset = 0x4000,
3645 .words_per_bd = 3,
3646 };
3647
3648 /* Infer hardware parameters from the detected GENET version */
bcmgenet_set_hw_params(struct bcmgenet_priv * priv)3649 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3650 {
3651 const struct bcmgenet_hw_params *params;
3652 u32 reg;
3653 u8 major;
3654 u16 gphy_rev;
3655
3656 /* default to latest values */
3657 params = &bcmgenet_hw_params_v4;
3658 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3659 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3660 if (GENET_IS_V3(priv)) {
3661 params = &bcmgenet_hw_params_v3;
3662 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3663 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3664 } else if (GENET_IS_V2(priv)) {
3665 params = &bcmgenet_hw_params_v2;
3666 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3667 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3668 } else if (GENET_IS_V1(priv)) {
3669 params = &bcmgenet_hw_params_v1;
3670 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3671 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3672 }
3673 priv->hw_params = params;
3674
3675 /* Read GENET HW version */
3676 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3677 major = (reg >> 24 & 0x0f);
3678 if (major == 6 || major == 7)
3679 major = 5;
3680 else if (major == 5)
3681 major = 4;
3682 else if (major == 0)
3683 major = 1;
3684 if (major != priv->version) {
3685 dev_err(&priv->pdev->dev,
3686 "GENET version mismatch, got: %d, configured for: %d\n",
3687 major, priv->version);
3688 }
3689
3690 /* Print the GENET core version */
3691 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3692 major, (reg >> 16) & 0x0f, reg & 0xffff);
3693
3694 /* Store the integrated PHY revision for the MDIO probing function
3695 * to pass this information to the PHY driver. The PHY driver expects
3696 * to find the PHY major revision in bits 15:8 while the GENET register
3697 * stores that information in bits 7:0, account for that.
3698 *
3699 * On newer chips, starting with PHY revision G0, a new scheme is
3700 * deployed similar to the Starfighter 2 switch with GPHY major
3701 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3702 * is reserved as well as special value 0x01ff, we have a small
3703 * heuristic to check for the new GPHY revision and re-arrange things
3704 * so the GPHY driver is happy.
3705 */
3706 gphy_rev = reg & 0xffff;
3707
3708 if (GENET_IS_V5(priv)) {
3709 /* The EPHY revision should come from the MDIO registers of
3710 * the PHY not from GENET.
3711 */
3712 if (gphy_rev != 0) {
3713 pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3714 gphy_rev);
3715 }
3716 /* This is reserved so should require special treatment */
3717 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3718 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3719 return;
3720 /* This is the good old scheme, just GPHY major, no minor nor patch */
3721 } else if ((gphy_rev & 0xf0) != 0) {
3722 priv->gphy_rev = gphy_rev << 8;
3723 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3724 } else if ((gphy_rev & 0xff00) != 0) {
3725 priv->gphy_rev = gphy_rev;
3726 }
3727
3728 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3729 if (!bcmgenet_has_40bits(priv))
3730 pr_warn("GENET does not support 40-bits PA\n");
3731 #endif
3732
3733 pr_debug("Configuration for version: %d\n"
3734 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3735 "BP << en: %2d, BP msk: 0x%05x\n"
3736 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3737 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3738 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3739 "Words/BD: %d\n",
3740 priv->version,
3741 params->tx_queues, params->tx_bds_per_q,
3742 params->rx_queues, params->rx_bds_per_q,
3743 params->bp_in_en_shift, params->bp_in_mask,
3744 params->hfb_filter_cnt, params->qtag_mask,
3745 params->tbuf_offset, params->hfb_offset,
3746 params->hfb_reg_offset,
3747 params->rdma_offset, params->tdma_offset,
3748 params->words_per_bd);
3749 }
3750
3751 struct bcmgenet_plat_data {
3752 enum bcmgenet_version version;
3753 u32 dma_max_burst_length;
3754 u32 flags;
3755 };
3756
3757 static const struct bcmgenet_plat_data v1_plat_data = {
3758 .version = GENET_V1,
3759 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3760 };
3761
3762 static const struct bcmgenet_plat_data v2_plat_data = {
3763 .version = GENET_V2,
3764 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3765 .flags = GENET_HAS_EXT,
3766 };
3767
3768 static const struct bcmgenet_plat_data v3_plat_data = {
3769 .version = GENET_V3,
3770 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3771 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3772 GENET_HAS_MOCA_LINK_DET,
3773 };
3774
3775 static const struct bcmgenet_plat_data v4_plat_data = {
3776 .version = GENET_V4,
3777 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3778 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3779 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3780 };
3781
3782 static const struct bcmgenet_plat_data v5_plat_data = {
3783 .version = GENET_V5,
3784 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3785 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3786 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3787 };
3788
3789 static const struct bcmgenet_plat_data bcm2711_plat_data = {
3790 .version = GENET_V5,
3791 .dma_max_burst_length = 0x08,
3792 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3793 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3794 };
3795
3796 static const struct bcmgenet_plat_data bcm7712_plat_data = {
3797 .version = GENET_V5,
3798 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3799 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3800 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET |
3801 GENET_HAS_EPHY_16NM,
3802 };
3803
3804 static const struct of_device_id bcmgenet_match[] = {
3805 { .compatible = "brcm,genet-v1", .data = &v1_plat_data },
3806 { .compatible = "brcm,genet-v2", .data = &v2_plat_data },
3807 { .compatible = "brcm,genet-v3", .data = &v3_plat_data },
3808 { .compatible = "brcm,genet-v4", .data = &v4_plat_data },
3809 { .compatible = "brcm,genet-v5", .data = &v5_plat_data },
3810 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data },
3811 { .compatible = "brcm,bcm7712-genet-v5", .data = &bcm7712_plat_data },
3812 { },
3813 };
3814 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3815
bcmgenet_probe(struct platform_device * pdev)3816 static int bcmgenet_probe(struct platform_device *pdev)
3817 {
3818 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3819 const struct bcmgenet_plat_data *pdata;
3820 struct bcmgenet_priv *priv;
3821 struct net_device *dev;
3822 unsigned int i;
3823 int err = -EIO;
3824
3825 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3826 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3827 GENET_MAX_MQ_CNT + 1);
3828 if (!dev) {
3829 dev_err(&pdev->dev, "can't allocate net device\n");
3830 return -ENOMEM;
3831 }
3832
3833 priv = netdev_priv(dev);
3834 priv->irq0 = platform_get_irq(pdev, 0);
3835 if (priv->irq0 < 0) {
3836 err = priv->irq0;
3837 goto err;
3838 }
3839 priv->irq1 = platform_get_irq(pdev, 1);
3840 if (priv->irq1 < 0) {
3841 err = priv->irq1;
3842 goto err;
3843 }
3844 priv->wol_irq = platform_get_irq_optional(pdev, 2);
3845 if (priv->wol_irq == -EPROBE_DEFER) {
3846 err = priv->wol_irq;
3847 goto err;
3848 }
3849
3850 priv->base = devm_platform_ioremap_resource(pdev, 0);
3851 if (IS_ERR(priv->base)) {
3852 err = PTR_ERR(priv->base);
3853 goto err;
3854 }
3855
3856 spin_lock_init(&priv->reg_lock);
3857 spin_lock_init(&priv->lock);
3858
3859 /* Set default pause parameters */
3860 priv->autoneg_pause = 1;
3861 priv->tx_pause = 1;
3862 priv->rx_pause = 1;
3863
3864 SET_NETDEV_DEV(dev, &pdev->dev);
3865 dev_set_drvdata(&pdev->dev, dev);
3866 dev->watchdog_timeo = 2 * HZ;
3867 dev->ethtool_ops = &bcmgenet_ethtool_ops;
3868 dev->netdev_ops = &bcmgenet_netdev_ops;
3869
3870 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3871
3872 /* Set default features */
3873 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM |
3874 NETIF_F_RXCSUM;
3875 dev->hw_features |= dev->features;
3876 dev->vlan_features |= dev->features;
3877
3878 /* Request the WOL interrupt and advertise suspend if available */
3879 priv->wol_irq_disabled = true;
3880 if (priv->wol_irq > 0) {
3881 err = devm_request_irq(&pdev->dev, priv->wol_irq,
3882 bcmgenet_wol_isr, 0, dev->name, priv);
3883 if (!err)
3884 device_set_wakeup_capable(&pdev->dev, 1);
3885 }
3886
3887 /* Set the needed headroom to account for any possible
3888 * features enabling/disabling at runtime
3889 */
3890 dev->needed_headroom += 64;
3891
3892 priv->dev = dev;
3893 priv->pdev = pdev;
3894
3895 pdata = device_get_match_data(&pdev->dev);
3896 if (pdata) {
3897 priv->version = pdata->version;
3898 priv->dma_max_burst_length = pdata->dma_max_burst_length;
3899 priv->flags = pdata->flags;
3900 } else {
3901 priv->version = pd->genet_version;
3902 priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH;
3903 }
3904
3905 priv->clk = devm_clk_get_optional(&priv->pdev->dev, "enet");
3906 if (IS_ERR(priv->clk)) {
3907 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n");
3908 err = PTR_ERR(priv->clk);
3909 goto err;
3910 }
3911
3912 err = clk_prepare_enable(priv->clk);
3913 if (err)
3914 goto err;
3915
3916 bcmgenet_set_hw_params(priv);
3917
3918 err = -EIO;
3919 if (bcmgenet_has_40bits(priv))
3920 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
3921 if (err)
3922 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3923 if (err)
3924 goto err_clk_disable;
3925
3926 /* Mii wait queue */
3927 init_waitqueue_head(&priv->wq);
3928 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3929 priv->rx_buf_len = RX_BUF_LENGTH;
3930 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3931
3932 priv->clk_wol = devm_clk_get_optional(&priv->pdev->dev, "enet-wol");
3933 if (IS_ERR(priv->clk_wol)) {
3934 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n");
3935 err = PTR_ERR(priv->clk_wol);
3936 goto err_clk_disable;
3937 }
3938
3939 priv->clk_eee = devm_clk_get_optional(&priv->pdev->dev, "enet-eee");
3940 if (IS_ERR(priv->clk_eee)) {
3941 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n");
3942 err = PTR_ERR(priv->clk_eee);
3943 goto err_clk_disable;
3944 }
3945
3946 /* If this is an internal GPHY, power it on now, before UniMAC is
3947 * brought out of reset as absolutely no UniMAC activity is allowed
3948 */
3949 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL)
3950 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3951
3952 if (pd && !IS_ERR_OR_NULL(pd->mac_address))
3953 eth_hw_addr_set(dev, pd->mac_address);
3954 else
3955 if (device_get_ethdev_address(&pdev->dev, dev))
3956 if (has_acpi_companion(&pdev->dev)) {
3957 u8 addr[ETH_ALEN];
3958
3959 bcmgenet_get_hw_addr(priv, addr);
3960 eth_hw_addr_set(dev, addr);
3961 }
3962
3963 if (!is_valid_ether_addr(dev->dev_addr)) {
3964 dev_warn(&pdev->dev, "using random Ethernet MAC\n");
3965 eth_hw_addr_random(dev);
3966 }
3967
3968 reset_umac(priv);
3969
3970 err = bcmgenet_mii_init(dev);
3971 if (err)
3972 goto err_clk_disable;
3973
3974 /* setup number of real queues + 1 */
3975 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3976 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3977
3978 /* Set default coalescing parameters */
3979 for (i = 0; i <= priv->hw_params->rx_queues; i++)
3980 priv->rx_rings[i].rx_max_coalesced_frames = 1;
3981
3982 /* libphy will determine the link state */
3983 netif_carrier_off(dev);
3984
3985 /* Turn off the main clock, WOL clock is handled separately */
3986 clk_disable_unprepare(priv->clk);
3987
3988 err = register_netdev(dev);
3989 if (err) {
3990 bcmgenet_mii_exit(dev);
3991 goto err;
3992 }
3993
3994 return err;
3995
3996 err_clk_disable:
3997 clk_disable_unprepare(priv->clk);
3998 err:
3999 free_netdev(dev);
4000 return err;
4001 }
4002
bcmgenet_remove(struct platform_device * pdev)4003 static void bcmgenet_remove(struct platform_device *pdev)
4004 {
4005 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
4006
4007 dev_set_drvdata(&pdev->dev, NULL);
4008 unregister_netdev(priv->dev);
4009 bcmgenet_mii_exit(priv->dev);
4010 free_netdev(priv->dev);
4011 }
4012
bcmgenet_shutdown(struct platform_device * pdev)4013 static void bcmgenet_shutdown(struct platform_device *pdev)
4014 {
4015 bcmgenet_remove(pdev);
4016 }
4017
4018 #ifdef CONFIG_PM_SLEEP
bcmgenet_resume_noirq(struct device * d)4019 static int bcmgenet_resume_noirq(struct device *d)
4020 {
4021 struct net_device *dev = dev_get_drvdata(d);
4022 struct bcmgenet_priv *priv = netdev_priv(dev);
4023 int ret;
4024 u32 reg;
4025
4026 if (!netif_running(dev))
4027 return 0;
4028
4029 /* Turn on the clock */
4030 ret = clk_prepare_enable(priv->clk);
4031 if (ret)
4032 return ret;
4033
4034 if (device_may_wakeup(d) && priv->wolopts) {
4035 /* Account for Wake-on-LAN events and clear those events
4036 * (Some devices need more time between enabling the clocks
4037 * and the interrupt register reflecting the wake event so
4038 * read the register twice)
4039 */
4040 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT);
4041 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT);
4042 if (reg & UMAC_IRQ_WAKE_EVENT)
4043 pm_wakeup_event(&priv->pdev->dev, 0);
4044
4045 /* From WOL-enabled suspend, switch to regular clock */
4046 if (!bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC))
4047 return 0;
4048
4049 /* Failed so fall through to reset MAC */
4050 }
4051
4052 /* If this is an internal GPHY, power it back on now, before UniMAC is
4053 * brought out of reset as absolutely no UniMAC activity is allowed
4054 */
4055 if (priv->internal_phy)
4056 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
4057
4058 /* take MAC out of reset */
4059 bcmgenet_umac_reset(priv);
4060
4061 return 0;
4062 }
4063
bcmgenet_resume(struct device * d)4064 static int bcmgenet_resume(struct device *d)
4065 {
4066 struct net_device *dev = dev_get_drvdata(d);
4067 struct bcmgenet_priv *priv = netdev_priv(dev);
4068 struct bcmgenet_rxnfc_rule *rule;
4069 int ret;
4070 u32 reg;
4071
4072 if (!netif_running(dev))
4073 return 0;
4074
4075 if (device_may_wakeup(d) && priv->wolopts) {
4076 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
4077 if (reg & CMD_RX_EN) {
4078 /* Successfully exited WoL, just resume data flows */
4079 list_for_each_entry(rule, &priv->rxnfc_list, list)
4080 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED)
4081 bcmgenet_hfb_enable_filter(priv,
4082 rule->fs.location + 1);
4083 bcmgenet_hfb_enable_filter(priv, 0);
4084 bcmgenet_set_rx_mode(dev);
4085 bcmgenet_enable_rx_napi(priv);
4086
4087 /* Reinitialize Tx flows */
4088 bcmgenet_tdma_disable(priv);
4089 bcmgenet_init_tx_queues(priv->dev);
4090 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
4091 reg |= DMA_EN;
4092 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
4093 bcmgenet_enable_tx_napi(priv);
4094
4095 bcmgenet_link_intr_enable(priv);
4096 phy_start_machine(dev->phydev);
4097
4098 netif_device_attach(dev);
4099 enable_irq(priv->irq1);
4100 return 0;
4101 }
4102 /* MAC was reset so complete bcmgenet_netif_stop() */
4103 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, false);
4104 bcmgenet_rdma_disable(priv);
4105 bcmgenet_intr_disable(priv);
4106 bcmgenet_fini_dma(priv);
4107 enable_irq(priv->irq1);
4108 }
4109
4110 init_umac(priv);
4111
4112 phy_init_hw(dev->phydev);
4113
4114 /* Speed settings must be restored */
4115 genphy_config_aneg(dev->phydev);
4116 bcmgenet_mii_config(priv->dev, false);
4117
4118 /* Restore enabled features */
4119 bcmgenet_set_features(dev, dev->features);
4120
4121 bcmgenet_set_hw_addr(priv, dev->dev_addr);
4122
4123 /* Restore hardware filters */
4124 bcmgenet_hfb_clear(priv);
4125 list_for_each_entry(rule, &priv->rxnfc_list, list)
4126 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED)
4127 bcmgenet_hfb_create_rxnfc_filter(priv, rule);
4128
4129 /* Reinitialize TDMA and RDMA and SW housekeeping */
4130 ret = bcmgenet_init_dma(priv, false);
4131 if (ret) {
4132 netdev_err(dev, "failed to initialize DMA\n");
4133 goto out_clk_disable;
4134 }
4135
4136 if (!device_may_wakeup(d))
4137 phy_resume(dev->phydev);
4138
4139 bcmgenet_netif_start(dev);
4140
4141 netif_device_attach(dev);
4142
4143 return 0;
4144
4145 out_clk_disable:
4146 if (priv->internal_phy)
4147 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
4148 clk_disable_unprepare(priv->clk);
4149 return ret;
4150 }
4151
bcmgenet_suspend(struct device * d)4152 static int bcmgenet_suspend(struct device *d)
4153 {
4154 struct net_device *dev = dev_get_drvdata(d);
4155 struct bcmgenet_priv *priv = netdev_priv(dev);
4156 struct bcmgenet_rxnfc_rule *rule;
4157 u32 reg, hfb_enable = 0;
4158
4159 if (!netif_running(dev))
4160 return 0;
4161
4162 netif_device_detach(dev);
4163
4164 if (device_may_wakeup(d) && priv->wolopts) {
4165 netif_tx_disable(dev);
4166
4167 /* Suspend non-wake Rx data flows */
4168 if (priv->wolopts & WAKE_FILTER)
4169 list_for_each_entry(rule, &priv->rxnfc_list, list)
4170 if (rule->fs.ring_cookie == RX_CLS_FLOW_WAKE &&
4171 rule->state == BCMGENET_RXNFC_STATE_ENABLED)
4172 hfb_enable |= 1 << rule->fs.location;
4173 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
4174 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) {
4175 reg &= ~RBUF_HFB_FILTER_EN_MASK;
4176 reg |= hfb_enable << (RBUF_HFB_FILTER_EN_SHIFT + 1);
4177 } else {
4178 bcmgenet_hfb_reg_writel(priv, hfb_enable << 1,
4179 HFB_FLT_ENABLE_V3PLUS + 4);
4180 }
4181 if (!hfb_enable)
4182 reg &= ~RBUF_HFB_EN;
4183 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
4184
4185 /* Clear any old filter matches so only new matches wake */
4186 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
4187 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
4188
4189 if (-ETIMEDOUT == bcmgenet_tdma_disable(priv))
4190 netdev_warn(priv->dev,
4191 "Timed out while disabling TX DMA\n");
4192
4193 bcmgenet_disable_tx_napi(priv);
4194 bcmgenet_disable_rx_napi(priv);
4195 disable_irq(priv->irq1);
4196 bcmgenet_tx_reclaim_all(dev);
4197 bcmgenet_fini_tx_napi(priv);
4198 } else {
4199 /* Teardown the interface */
4200 bcmgenet_netif_stop(dev, true);
4201 }
4202
4203 return 0;
4204 }
4205
bcmgenet_suspend_noirq(struct device * d)4206 static int bcmgenet_suspend_noirq(struct device *d)
4207 {
4208 struct net_device *dev = dev_get_drvdata(d);
4209 struct bcmgenet_priv *priv = netdev_priv(dev);
4210 int ret = 0;
4211
4212 if (!netif_running(dev))
4213 return 0;
4214
4215 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
4216 if (device_may_wakeup(d) && priv->wolopts)
4217 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
4218 else if (priv->internal_phy)
4219 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
4220
4221 /* Let the framework handle resumption and leave the clocks on */
4222 if (ret)
4223 return ret;
4224
4225 /* Turn off the clocks */
4226 clk_disable_unprepare(priv->clk);
4227
4228 return 0;
4229 }
4230 #else
4231 #define bcmgenet_suspend NULL
4232 #define bcmgenet_suspend_noirq NULL
4233 #define bcmgenet_resume NULL
4234 #define bcmgenet_resume_noirq NULL
4235 #endif /* CONFIG_PM_SLEEP */
4236
4237 static const struct dev_pm_ops bcmgenet_pm_ops = {
4238 .suspend = bcmgenet_suspend,
4239 .suspend_noirq = bcmgenet_suspend_noirq,
4240 .resume = bcmgenet_resume,
4241 .resume_noirq = bcmgenet_resume_noirq,
4242 };
4243
4244 static const struct acpi_device_id genet_acpi_match[] = {
4245 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data },
4246 { },
4247 };
4248 MODULE_DEVICE_TABLE(acpi, genet_acpi_match);
4249
4250 static struct platform_driver bcmgenet_driver = {
4251 .probe = bcmgenet_probe,
4252 .remove = bcmgenet_remove,
4253 .shutdown = bcmgenet_shutdown,
4254 .driver = {
4255 .name = "bcmgenet",
4256 .of_match_table = bcmgenet_match,
4257 .pm = &bcmgenet_pm_ops,
4258 .acpi_match_table = genet_acpi_match,
4259 },
4260 };
4261 module_platform_driver(bcmgenet_driver);
4262
4263 MODULE_AUTHOR("Broadcom Corporation");
4264 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
4265 MODULE_ALIAS("platform:bcmgenet");
4266 MODULE_LICENSE("GPL");
4267 MODULE_SOFTDEP("pre: mdio-bcm-unimac");
4268