xref: /linux/drivers/net/ethernet/broadcom/genet/bcmgenet.c (revision bc9ff192a6c940d9a26e21a0a82f2667067aaf5f)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Broadcom GENET (Gigabit Ethernet) controller driver
4  *
5  * Copyright (c) 2014-2025 Broadcom
6  */
7 
8 #define pr_fmt(fmt)				"bcmgenet: " fmt
9 
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/sched.h>
14 #include <linux/types.h>
15 #include <linux/fcntl.h>
16 #include <linux/interrupt.h>
17 #include <linux/string.h>
18 #include <linux/if_ether.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/delay.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/pm.h>
25 #include <linux/clk.h>
26 #include <net/arp.h>
27 
28 #include <linux/mii.h>
29 #include <linux/ethtool.h>
30 #include <linux/netdevice.h>
31 #include <linux/inetdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/ipv6.h>
37 #include <linux/phy.h>
38 #include <linux/platform_data/bcmgenet.h>
39 
40 #include <linux/unaligned.h>
41 
42 #include "bcmgenet.h"
43 
44 /* Default highest priority queue for multi queue support */
45 #define GENET_Q1_PRIORITY	0
46 #define GENET_Q0_PRIORITY	1
47 
48 #define GENET_Q0_RX_BD_CNT	\
49 	(TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
50 #define GENET_Q0_TX_BD_CNT	\
51 	(TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
52 
53 #define RX_BUF_LENGTH		2048
54 #define SKB_ALIGNMENT		32
55 
56 /* Tx/Rx DMA register offset, skip 256 descriptors */
57 #define WORDS_PER_BD(p)		(p->hw_params->words_per_bd)
58 #define DMA_DESC_SIZE		(WORDS_PER_BD(priv) * sizeof(u32))
59 
60 #define GENET_TDMA_REG_OFF	(priv->hw_params->tdma_offset + \
61 				TOTAL_DESC * DMA_DESC_SIZE)
62 
63 #define GENET_RDMA_REG_OFF	(priv->hw_params->rdma_offset + \
64 				TOTAL_DESC * DMA_DESC_SIZE)
65 
66 /* Forward declarations */
67 static void bcmgenet_set_rx_mode(struct net_device *dev);
68 
bcmgenet_writel(u32 value,void __iomem * offset)69 static inline void bcmgenet_writel(u32 value, void __iomem *offset)
70 {
71 	/* MIPS chips strapped for BE will automagically configure the
72 	 * peripheral registers for CPU-native byte order.
73 	 */
74 	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
75 		__raw_writel(value, offset);
76 	else
77 		writel_relaxed(value, offset);
78 }
79 
bcmgenet_readl(void __iomem * offset)80 static inline u32 bcmgenet_readl(void __iomem *offset)
81 {
82 	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
83 		return __raw_readl(offset);
84 	else
85 		return readl_relaxed(offset);
86 }
87 
dmadesc_set_length_status(struct bcmgenet_priv * priv,void __iomem * d,u32 value)88 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
89 					     void __iomem *d, u32 value)
90 {
91 	bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
92 }
93 
dmadesc_set_addr(struct bcmgenet_priv * priv,void __iomem * d,dma_addr_t addr)94 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
95 				    void __iomem *d,
96 				    dma_addr_t addr)
97 {
98 	bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
99 
100 	/* Register writes to GISB bus can take couple hundred nanoseconds
101 	 * and are done for each packet, save these expensive writes unless
102 	 * the platform is explicitly configured for 64-bits/LPAE.
103 	 */
104 #ifdef CONFIG_PHYS_ADDR_T_64BIT
105 	if (bcmgenet_has_40bits(priv))
106 		bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
107 #endif
108 }
109 
110 /* Combined address + length/status setter */
dmadesc_set(struct bcmgenet_priv * priv,void __iomem * d,dma_addr_t addr,u32 val)111 static inline void dmadesc_set(struct bcmgenet_priv *priv,
112 			       void __iomem *d, dma_addr_t addr, u32 val)
113 {
114 	dmadesc_set_addr(priv, d, addr);
115 	dmadesc_set_length_status(priv, d, val);
116 }
117 
118 #define GENET_VER_FMT	"%1d.%1d EPHY: 0x%04x"
119 
120 #define GENET_MSG_DEFAULT	(NETIF_MSG_DRV | NETIF_MSG_PROBE | \
121 				NETIF_MSG_LINK)
122 
bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv * priv)123 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
124 {
125 	if (GENET_IS_V1(priv))
126 		return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
127 	else
128 		return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
129 }
130 
bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv * priv,u32 val)131 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
132 {
133 	if (GENET_IS_V1(priv))
134 		bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
135 	else
136 		bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
137 }
138 
139 /* These macros are defined to deal with register map change
140  * between GENET1.1 and GENET2. Only those currently being used
141  * by driver are defined.
142  */
bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv * priv)143 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
144 {
145 	if (GENET_IS_V1(priv))
146 		return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
147 	else
148 		return bcmgenet_readl(priv->base +
149 				      priv->hw_params->tbuf_offset + TBUF_CTRL);
150 }
151 
bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv * priv,u32 val)152 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
153 {
154 	if (GENET_IS_V1(priv))
155 		bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
156 	else
157 		bcmgenet_writel(val, priv->base +
158 				priv->hw_params->tbuf_offset + TBUF_CTRL);
159 }
160 
bcmgenet_bp_mc_get(struct bcmgenet_priv * priv)161 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
162 {
163 	if (GENET_IS_V1(priv))
164 		return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
165 	else
166 		return bcmgenet_readl(priv->base +
167 				      priv->hw_params->tbuf_offset + TBUF_BP_MC);
168 }
169 
bcmgenet_bp_mc_set(struct bcmgenet_priv * priv,u32 val)170 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
171 {
172 	if (GENET_IS_V1(priv))
173 		bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
174 	else
175 		bcmgenet_writel(val, priv->base +
176 				priv->hw_params->tbuf_offset + TBUF_BP_MC);
177 }
178 
179 /* RX/TX DMA register accessors */
180 enum dma_reg {
181 	DMA_RING_CFG = 0,
182 	DMA_CTRL,
183 	DMA_STATUS,
184 	DMA_SCB_BURST_SIZE,
185 	DMA_ARB_CTRL,
186 	DMA_PRIORITY_0,
187 	DMA_PRIORITY_1,
188 	DMA_PRIORITY_2,
189 	DMA_INDEX2RING_0,
190 	DMA_INDEX2RING_1,
191 	DMA_INDEX2RING_2,
192 	DMA_INDEX2RING_3,
193 	DMA_INDEX2RING_4,
194 	DMA_INDEX2RING_5,
195 	DMA_INDEX2RING_6,
196 	DMA_INDEX2RING_7,
197 	DMA_RING0_TIMEOUT,
198 	DMA_RING1_TIMEOUT,
199 	DMA_RING2_TIMEOUT,
200 	DMA_RING3_TIMEOUT,
201 	DMA_RING4_TIMEOUT,
202 	DMA_RING5_TIMEOUT,
203 	DMA_RING6_TIMEOUT,
204 	DMA_RING7_TIMEOUT,
205 	DMA_RING8_TIMEOUT,
206 	DMA_RING9_TIMEOUT,
207 	DMA_RING10_TIMEOUT,
208 	DMA_RING11_TIMEOUT,
209 	DMA_RING12_TIMEOUT,
210 	DMA_RING13_TIMEOUT,
211 	DMA_RING14_TIMEOUT,
212 	DMA_RING15_TIMEOUT,
213 	DMA_RING16_TIMEOUT,
214 };
215 
216 static const u8 bcmgenet_dma_regs_v3plus[] = {
217 	[DMA_RING_CFG]		= 0x00,
218 	[DMA_CTRL]		= 0x04,
219 	[DMA_STATUS]		= 0x08,
220 	[DMA_SCB_BURST_SIZE]	= 0x0C,
221 	[DMA_ARB_CTRL]		= 0x2C,
222 	[DMA_PRIORITY_0]	= 0x30,
223 	[DMA_PRIORITY_1]	= 0x34,
224 	[DMA_PRIORITY_2]	= 0x38,
225 	[DMA_RING0_TIMEOUT]	= 0x2C,
226 	[DMA_RING1_TIMEOUT]	= 0x30,
227 	[DMA_RING2_TIMEOUT]	= 0x34,
228 	[DMA_RING3_TIMEOUT]	= 0x38,
229 	[DMA_RING4_TIMEOUT]	= 0x3c,
230 	[DMA_RING5_TIMEOUT]	= 0x40,
231 	[DMA_RING6_TIMEOUT]	= 0x44,
232 	[DMA_RING7_TIMEOUT]	= 0x48,
233 	[DMA_RING8_TIMEOUT]	= 0x4c,
234 	[DMA_RING9_TIMEOUT]	= 0x50,
235 	[DMA_RING10_TIMEOUT]	= 0x54,
236 	[DMA_RING11_TIMEOUT]	= 0x58,
237 	[DMA_RING12_TIMEOUT]	= 0x5c,
238 	[DMA_RING13_TIMEOUT]	= 0x60,
239 	[DMA_RING14_TIMEOUT]	= 0x64,
240 	[DMA_RING15_TIMEOUT]	= 0x68,
241 	[DMA_RING16_TIMEOUT]	= 0x6C,
242 	[DMA_INDEX2RING_0]	= 0x70,
243 	[DMA_INDEX2RING_1]	= 0x74,
244 	[DMA_INDEX2RING_2]	= 0x78,
245 	[DMA_INDEX2RING_3]	= 0x7C,
246 	[DMA_INDEX2RING_4]	= 0x80,
247 	[DMA_INDEX2RING_5]	= 0x84,
248 	[DMA_INDEX2RING_6]	= 0x88,
249 	[DMA_INDEX2RING_7]	= 0x8C,
250 };
251 
252 static const u8 bcmgenet_dma_regs_v2[] = {
253 	[DMA_RING_CFG]		= 0x00,
254 	[DMA_CTRL]		= 0x04,
255 	[DMA_STATUS]		= 0x08,
256 	[DMA_SCB_BURST_SIZE]	= 0x0C,
257 	[DMA_ARB_CTRL]		= 0x30,
258 	[DMA_PRIORITY_0]	= 0x34,
259 	[DMA_PRIORITY_1]	= 0x38,
260 	[DMA_PRIORITY_2]	= 0x3C,
261 	[DMA_RING0_TIMEOUT]	= 0x2C,
262 	[DMA_RING1_TIMEOUT]	= 0x30,
263 	[DMA_RING2_TIMEOUT]	= 0x34,
264 	[DMA_RING3_TIMEOUT]	= 0x38,
265 	[DMA_RING4_TIMEOUT]	= 0x3c,
266 	[DMA_RING5_TIMEOUT]	= 0x40,
267 	[DMA_RING6_TIMEOUT]	= 0x44,
268 	[DMA_RING7_TIMEOUT]	= 0x48,
269 	[DMA_RING8_TIMEOUT]	= 0x4c,
270 	[DMA_RING9_TIMEOUT]	= 0x50,
271 	[DMA_RING10_TIMEOUT]	= 0x54,
272 	[DMA_RING11_TIMEOUT]	= 0x58,
273 	[DMA_RING12_TIMEOUT]	= 0x5c,
274 	[DMA_RING13_TIMEOUT]	= 0x60,
275 	[DMA_RING14_TIMEOUT]	= 0x64,
276 	[DMA_RING15_TIMEOUT]	= 0x68,
277 	[DMA_RING16_TIMEOUT]	= 0x6C,
278 };
279 
280 static const u8 bcmgenet_dma_regs_v1[] = {
281 	[DMA_CTRL]		= 0x00,
282 	[DMA_STATUS]		= 0x04,
283 	[DMA_SCB_BURST_SIZE]	= 0x0C,
284 	[DMA_ARB_CTRL]		= 0x30,
285 	[DMA_PRIORITY_0]	= 0x34,
286 	[DMA_PRIORITY_1]	= 0x38,
287 	[DMA_PRIORITY_2]	= 0x3C,
288 	[DMA_RING0_TIMEOUT]	= 0x2C,
289 	[DMA_RING1_TIMEOUT]	= 0x30,
290 	[DMA_RING2_TIMEOUT]	= 0x34,
291 	[DMA_RING3_TIMEOUT]	= 0x38,
292 	[DMA_RING4_TIMEOUT]	= 0x3c,
293 	[DMA_RING5_TIMEOUT]	= 0x40,
294 	[DMA_RING6_TIMEOUT]	= 0x44,
295 	[DMA_RING7_TIMEOUT]	= 0x48,
296 	[DMA_RING8_TIMEOUT]	= 0x4c,
297 	[DMA_RING9_TIMEOUT]	= 0x50,
298 	[DMA_RING10_TIMEOUT]	= 0x54,
299 	[DMA_RING11_TIMEOUT]	= 0x58,
300 	[DMA_RING12_TIMEOUT]	= 0x5c,
301 	[DMA_RING13_TIMEOUT]	= 0x60,
302 	[DMA_RING14_TIMEOUT]	= 0x64,
303 	[DMA_RING15_TIMEOUT]	= 0x68,
304 	[DMA_RING16_TIMEOUT]	= 0x6C,
305 };
306 
307 /* Set at runtime once bcmgenet version is known */
308 static const u8 *bcmgenet_dma_regs;
309 
dev_to_priv(struct device * dev)310 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
311 {
312 	return netdev_priv(dev_get_drvdata(dev));
313 }
314 
bcmgenet_tdma_readl(struct bcmgenet_priv * priv,enum dma_reg r)315 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
316 				      enum dma_reg r)
317 {
318 	return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
319 			      DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
320 }
321 
bcmgenet_tdma_writel(struct bcmgenet_priv * priv,u32 val,enum dma_reg r)322 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
323 					u32 val, enum dma_reg r)
324 {
325 	bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
326 			DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
327 }
328 
bcmgenet_rdma_readl(struct bcmgenet_priv * priv,enum dma_reg r)329 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
330 				      enum dma_reg r)
331 {
332 	return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
333 			      DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
334 }
335 
bcmgenet_rdma_writel(struct bcmgenet_priv * priv,u32 val,enum dma_reg r)336 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
337 					u32 val, enum dma_reg r)
338 {
339 	bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
340 			DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
341 }
342 
343 /* RDMA/TDMA ring registers and accessors
344  * we merge the common fields and just prefix with T/D the registers
345  * having different meaning depending on the direction
346  */
347 enum dma_ring_reg {
348 	TDMA_READ_PTR = 0,
349 	RDMA_WRITE_PTR = TDMA_READ_PTR,
350 	TDMA_READ_PTR_HI,
351 	RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
352 	TDMA_CONS_INDEX,
353 	RDMA_PROD_INDEX = TDMA_CONS_INDEX,
354 	TDMA_PROD_INDEX,
355 	RDMA_CONS_INDEX = TDMA_PROD_INDEX,
356 	DMA_RING_BUF_SIZE,
357 	DMA_START_ADDR,
358 	DMA_START_ADDR_HI,
359 	DMA_END_ADDR,
360 	DMA_END_ADDR_HI,
361 	DMA_MBUF_DONE_THRESH,
362 	TDMA_FLOW_PERIOD,
363 	RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
364 	TDMA_WRITE_PTR,
365 	RDMA_READ_PTR = TDMA_WRITE_PTR,
366 	TDMA_WRITE_PTR_HI,
367 	RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
368 };
369 
370 /* GENET v4 supports 40-bits pointer addressing
371  * for obvious reasons the LO and HI word parts
372  * are contiguous, but this offsets the other
373  * registers.
374  */
375 static const u8 genet_dma_ring_regs_v4[] = {
376 	[TDMA_READ_PTR]			= 0x00,
377 	[TDMA_READ_PTR_HI]		= 0x04,
378 	[TDMA_CONS_INDEX]		= 0x08,
379 	[TDMA_PROD_INDEX]		= 0x0C,
380 	[DMA_RING_BUF_SIZE]		= 0x10,
381 	[DMA_START_ADDR]		= 0x14,
382 	[DMA_START_ADDR_HI]		= 0x18,
383 	[DMA_END_ADDR]			= 0x1C,
384 	[DMA_END_ADDR_HI]		= 0x20,
385 	[DMA_MBUF_DONE_THRESH]		= 0x24,
386 	[TDMA_FLOW_PERIOD]		= 0x28,
387 	[TDMA_WRITE_PTR]		= 0x2C,
388 	[TDMA_WRITE_PTR_HI]		= 0x30,
389 };
390 
391 static const u8 genet_dma_ring_regs_v123[] = {
392 	[TDMA_READ_PTR]			= 0x00,
393 	[TDMA_CONS_INDEX]		= 0x04,
394 	[TDMA_PROD_INDEX]		= 0x08,
395 	[DMA_RING_BUF_SIZE]		= 0x0C,
396 	[DMA_START_ADDR]		= 0x10,
397 	[DMA_END_ADDR]			= 0x14,
398 	[DMA_MBUF_DONE_THRESH]		= 0x18,
399 	[TDMA_FLOW_PERIOD]		= 0x1C,
400 	[TDMA_WRITE_PTR]		= 0x20,
401 };
402 
403 /* Set at runtime once GENET version is known */
404 static const u8 *genet_dma_ring_regs;
405 
bcmgenet_tdma_ring_readl(struct bcmgenet_priv * priv,unsigned int ring,enum dma_ring_reg r)406 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
407 					   unsigned int ring,
408 					   enum dma_ring_reg r)
409 {
410 	return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
411 			      (DMA_RING_SIZE * ring) +
412 			      genet_dma_ring_regs[r]);
413 }
414 
bcmgenet_tdma_ring_writel(struct bcmgenet_priv * priv,unsigned int ring,u32 val,enum dma_ring_reg r)415 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
416 					     unsigned int ring, u32 val,
417 					     enum dma_ring_reg r)
418 {
419 	bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
420 			(DMA_RING_SIZE * ring) +
421 			genet_dma_ring_regs[r]);
422 }
423 
bcmgenet_rdma_ring_readl(struct bcmgenet_priv * priv,unsigned int ring,enum dma_ring_reg r)424 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
425 					   unsigned int ring,
426 					   enum dma_ring_reg r)
427 {
428 	return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
429 			      (DMA_RING_SIZE * ring) +
430 			      genet_dma_ring_regs[r]);
431 }
432 
bcmgenet_rdma_ring_writel(struct bcmgenet_priv * priv,unsigned int ring,u32 val,enum dma_ring_reg r)433 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
434 					     unsigned int ring, u32 val,
435 					     enum dma_ring_reg r)
436 {
437 	bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
438 			(DMA_RING_SIZE * ring) +
439 			genet_dma_ring_regs[r]);
440 }
441 
bcmgenet_hfb_enable_filter(struct bcmgenet_priv * priv,u32 f_index)442 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
443 {
444 	u32 offset;
445 	u32 reg;
446 
447 	if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) {
448 		reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
449 		reg |= (1 << ((f_index % 32) + RBUF_HFB_FILTER_EN_SHIFT)) |
450 			RBUF_HFB_EN;
451 		bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
452 	} else {
453 		offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
454 		reg = bcmgenet_hfb_reg_readl(priv, offset);
455 		reg |= (1 << (f_index % 32));
456 		bcmgenet_hfb_reg_writel(priv, reg, offset);
457 		reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
458 		reg |= RBUF_HFB_EN;
459 		bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
460 	}
461 }
462 
bcmgenet_hfb_disable_filter(struct bcmgenet_priv * priv,u32 f_index)463 static void bcmgenet_hfb_disable_filter(struct bcmgenet_priv *priv, u32 f_index)
464 {
465 	u32 offset, reg, reg1;
466 
467 	if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) {
468 		reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
469 		reg &= ~(1 << ((f_index % 32) + RBUF_HFB_FILTER_EN_SHIFT));
470 		if (!(reg & RBUF_HFB_FILTER_EN_MASK))
471 			reg &= ~RBUF_HFB_EN;
472 		bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
473 	} else {
474 		offset = HFB_FLT_ENABLE_V3PLUS;
475 		reg = bcmgenet_hfb_reg_readl(priv, offset);
476 		reg1 = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32));
477 		if  (f_index < 32) {
478 			reg1 &= ~(1 << (f_index % 32));
479 			bcmgenet_hfb_reg_writel(priv, reg1, offset + sizeof(u32));
480 		} else {
481 			reg &= ~(1 << (f_index % 32));
482 			bcmgenet_hfb_reg_writel(priv, reg, offset);
483 		}
484 		if (!reg && !reg1) {
485 			reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
486 			reg &= ~RBUF_HFB_EN;
487 			bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
488 		}
489 	}
490 }
491 
bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv * priv,u32 f_index,u32 rx_queue)492 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
493 						     u32 f_index, u32 rx_queue)
494 {
495 	u32 offset;
496 	u32 reg;
497 
498 	if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
499 		return;
500 
501 	offset = f_index / 8;
502 	reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
503 	reg &= ~(0xF << (4 * (f_index % 8)));
504 	reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
505 	bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
506 }
507 
bcmgenet_hfb_set_filter_length(struct bcmgenet_priv * priv,u32 f_index,u32 f_length)508 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
509 					   u32 f_index, u32 f_length)
510 {
511 	u32 offset;
512 	u32 reg;
513 
514 	if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
515 		offset = HFB_FLT_LEN_V2;
516 	else
517 		offset = HFB_FLT_LEN_V3PLUS;
518 
519 	offset += sizeof(u32) *
520 		  ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4);
521 	reg = bcmgenet_hfb_reg_readl(priv, offset);
522 	reg &= ~(0xFF << (8 * (f_index % 4)));
523 	reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
524 	bcmgenet_hfb_reg_writel(priv, reg, offset);
525 }
526 
bcmgenet_hfb_validate_mask(void * mask,size_t size)527 static int bcmgenet_hfb_validate_mask(void *mask, size_t size)
528 {
529 	while (size) {
530 		switch (*(unsigned char *)mask++) {
531 		case 0x00:
532 		case 0x0f:
533 		case 0xf0:
534 		case 0xff:
535 			size--;
536 			continue;
537 		default:
538 			return -EINVAL;
539 		}
540 	}
541 
542 	return 0;
543 }
544 
545 #define VALIDATE_MASK(x) \
546 	bcmgenet_hfb_validate_mask(&(x), sizeof(x))
547 
bcmgenet_hfb_insert_data(struct bcmgenet_priv * priv,u32 f_index,u32 offset,void * val,void * mask,size_t size)548 static int bcmgenet_hfb_insert_data(struct bcmgenet_priv *priv, u32 f_index,
549 				    u32 offset, void *val, void *mask,
550 				    size_t size)
551 {
552 	u32 index, tmp;
553 
554 	index = f_index * priv->hw_params->hfb_filter_size + offset / 2;
555 	tmp = bcmgenet_hfb_readl(priv, index * sizeof(u32));
556 
557 	while (size--) {
558 		if (offset++ & 1) {
559 			tmp &= ~0x300FF;
560 			tmp |= (*(unsigned char *)val++);
561 			switch ((*(unsigned char *)mask++)) {
562 			case 0xFF:
563 				tmp |= 0x30000;
564 				break;
565 			case 0xF0:
566 				tmp |= 0x20000;
567 				break;
568 			case 0x0F:
569 				tmp |= 0x10000;
570 				break;
571 			}
572 			bcmgenet_hfb_writel(priv, tmp, index++ * sizeof(u32));
573 			if (size)
574 				tmp = bcmgenet_hfb_readl(priv,
575 							 index * sizeof(u32));
576 		} else {
577 			tmp &= ~0xCFF00;
578 			tmp |= (*(unsigned char *)val++) << 8;
579 			switch ((*(unsigned char *)mask++)) {
580 			case 0xFF:
581 				tmp |= 0xC0000;
582 				break;
583 			case 0xF0:
584 				tmp |= 0x80000;
585 				break;
586 			case 0x0F:
587 				tmp |= 0x40000;
588 				break;
589 			}
590 			if (!size)
591 				bcmgenet_hfb_writel(priv, tmp, index * sizeof(u32));
592 		}
593 	}
594 
595 	return 0;
596 }
597 
bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv * priv,struct bcmgenet_rxnfc_rule * rule)598 static void bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv *priv,
599 					     struct bcmgenet_rxnfc_rule *rule)
600 {
601 	struct ethtool_rx_flow_spec *fs = &rule->fs;
602 	u32 offset = 0, f_length = 0, f, q;
603 	u8 val_8, mask_8;
604 	__be16 val_16;
605 	u16 mask_16;
606 	size_t size;
607 
608 	f = fs->location + 1;
609 	if (fs->flow_type & FLOW_MAC_EXT) {
610 		bcmgenet_hfb_insert_data(priv, f, 0,
611 					 &fs->h_ext.h_dest, &fs->m_ext.h_dest,
612 					 sizeof(fs->h_ext.h_dest));
613 	}
614 
615 	if (fs->flow_type & FLOW_EXT) {
616 		if (fs->m_ext.vlan_etype ||
617 		    fs->m_ext.vlan_tci) {
618 			bcmgenet_hfb_insert_data(priv, f, 12,
619 						 &fs->h_ext.vlan_etype,
620 						 &fs->m_ext.vlan_etype,
621 						 sizeof(fs->h_ext.vlan_etype));
622 			bcmgenet_hfb_insert_data(priv, f, 14,
623 						 &fs->h_ext.vlan_tci,
624 						 &fs->m_ext.vlan_tci,
625 						 sizeof(fs->h_ext.vlan_tci));
626 			offset += VLAN_HLEN;
627 			f_length += DIV_ROUND_UP(VLAN_HLEN, 2);
628 		}
629 	}
630 
631 	switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
632 	case ETHER_FLOW:
633 		f_length += DIV_ROUND_UP(ETH_HLEN, 2);
634 		bcmgenet_hfb_insert_data(priv, f, 0,
635 					 &fs->h_u.ether_spec.h_dest,
636 					 &fs->m_u.ether_spec.h_dest,
637 					 sizeof(fs->h_u.ether_spec.h_dest));
638 		bcmgenet_hfb_insert_data(priv, f, ETH_ALEN,
639 					 &fs->h_u.ether_spec.h_source,
640 					 &fs->m_u.ether_spec.h_source,
641 					 sizeof(fs->h_u.ether_spec.h_source));
642 		bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset,
643 					 &fs->h_u.ether_spec.h_proto,
644 					 &fs->m_u.ether_spec.h_proto,
645 					 sizeof(fs->h_u.ether_spec.h_proto));
646 		break;
647 	case IP_USER_FLOW:
648 		f_length += DIV_ROUND_UP(ETH_HLEN + 20, 2);
649 		/* Specify IP Ether Type */
650 		val_16 = htons(ETH_P_IP);
651 		mask_16 = 0xFFFF;
652 		bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset,
653 					 &val_16, &mask_16, sizeof(val_16));
654 		bcmgenet_hfb_insert_data(priv, f, 15 + offset,
655 					 &fs->h_u.usr_ip4_spec.tos,
656 					 &fs->m_u.usr_ip4_spec.tos,
657 					 sizeof(fs->h_u.usr_ip4_spec.tos));
658 		bcmgenet_hfb_insert_data(priv, f, 23 + offset,
659 					 &fs->h_u.usr_ip4_spec.proto,
660 					 &fs->m_u.usr_ip4_spec.proto,
661 					 sizeof(fs->h_u.usr_ip4_spec.proto));
662 		bcmgenet_hfb_insert_data(priv, f, 26 + offset,
663 					 &fs->h_u.usr_ip4_spec.ip4src,
664 					 &fs->m_u.usr_ip4_spec.ip4src,
665 					 sizeof(fs->h_u.usr_ip4_spec.ip4src));
666 		bcmgenet_hfb_insert_data(priv, f, 30 + offset,
667 					 &fs->h_u.usr_ip4_spec.ip4dst,
668 					 &fs->m_u.usr_ip4_spec.ip4dst,
669 					 sizeof(fs->h_u.usr_ip4_spec.ip4dst));
670 		if (!fs->m_u.usr_ip4_spec.l4_4_bytes)
671 			break;
672 
673 		/* Only supports 20 byte IPv4 header */
674 		val_8 = 0x45;
675 		mask_8 = 0xFF;
676 		bcmgenet_hfb_insert_data(priv, f, ETH_HLEN + offset,
677 					 &val_8, &mask_8,
678 					 sizeof(val_8));
679 		size = sizeof(fs->h_u.usr_ip4_spec.l4_4_bytes);
680 		bcmgenet_hfb_insert_data(priv, f,
681 					 ETH_HLEN + 20 + offset,
682 					 &fs->h_u.usr_ip4_spec.l4_4_bytes,
683 					 &fs->m_u.usr_ip4_spec.l4_4_bytes,
684 					 size);
685 		f_length += DIV_ROUND_UP(size, 2);
686 		break;
687 	}
688 
689 	bcmgenet_hfb_set_filter_length(priv, f, 2 * f_length);
690 	if (fs->ring_cookie == RX_CLS_FLOW_WAKE)
691 		q = 0;
692 	else if (fs->ring_cookie == RX_CLS_FLOW_DISC)
693 		q = priv->hw_params->rx_queues + 1;
694 	else
695 		/* Other Rx rings are direct mapped here */
696 		q = fs->ring_cookie;
697 	bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f, q);
698 	bcmgenet_hfb_enable_filter(priv, f);
699 	rule->state = BCMGENET_RXNFC_STATE_ENABLED;
700 }
701 
702 /* bcmgenet_hfb_clear
703  *
704  * Clear Hardware Filter Block and disable all filtering.
705  */
bcmgenet_hfb_clear_filter(struct bcmgenet_priv * priv,u32 f_index)706 static void bcmgenet_hfb_clear_filter(struct bcmgenet_priv *priv, u32 f_index)
707 {
708 	u32 base, i;
709 
710 	bcmgenet_hfb_set_filter_length(priv, f_index, 0);
711 	base = f_index * priv->hw_params->hfb_filter_size;
712 	for (i = 0; i < priv->hw_params->hfb_filter_size; i++)
713 		bcmgenet_hfb_writel(priv, 0x0, (base + i) * sizeof(u32));
714 }
715 
bcmgenet_hfb_clear(struct bcmgenet_priv * priv)716 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
717 {
718 	u32 i;
719 
720 	bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL);
721 
722 	if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) {
723 		bcmgenet_hfb_reg_writel(priv, 0,
724 					HFB_FLT_ENABLE_V3PLUS);
725 		bcmgenet_hfb_reg_writel(priv, 0,
726 					HFB_FLT_ENABLE_V3PLUS + 4);
727 		for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
728 			bcmgenet_rdma_writel(priv, 0, i);
729 	}
730 
731 	for (i = 0; i < priv->hw_params->hfb_filter_cnt; i++)
732 		bcmgenet_hfb_clear_filter(priv, i);
733 
734 	/* Enable filter 0 to send default flow to ring 0 */
735 	bcmgenet_hfb_set_filter_length(priv, 0, 4);
736 	bcmgenet_hfb_enable_filter(priv, 0);
737 }
738 
bcmgenet_hfb_init(struct bcmgenet_priv * priv)739 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
740 {
741 	int i;
742 
743 	INIT_LIST_HEAD(&priv->rxnfc_list);
744 	for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
745 		INIT_LIST_HEAD(&priv->rxnfc_rules[i].list);
746 		priv->rxnfc_rules[i].state = BCMGENET_RXNFC_STATE_UNUSED;
747 	}
748 
749 	bcmgenet_hfb_clear(priv);
750 }
751 
bcmgenet_begin(struct net_device * dev)752 static int bcmgenet_begin(struct net_device *dev)
753 {
754 	struct bcmgenet_priv *priv = netdev_priv(dev);
755 
756 	/* Turn on the clock */
757 	return clk_prepare_enable(priv->clk);
758 }
759 
bcmgenet_complete(struct net_device * dev)760 static void bcmgenet_complete(struct net_device *dev)
761 {
762 	struct bcmgenet_priv *priv = netdev_priv(dev);
763 
764 	/* Turn off the clock */
765 	clk_disable_unprepare(priv->clk);
766 }
767 
bcmgenet_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)768 static int bcmgenet_get_link_ksettings(struct net_device *dev,
769 				       struct ethtool_link_ksettings *cmd)
770 {
771 	if (!netif_running(dev))
772 		return -EINVAL;
773 
774 	if (!dev->phydev)
775 		return -ENODEV;
776 
777 	phy_ethtool_ksettings_get(dev->phydev, cmd);
778 
779 	return 0;
780 }
781 
bcmgenet_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)782 static int bcmgenet_set_link_ksettings(struct net_device *dev,
783 				       const struct ethtool_link_ksettings *cmd)
784 {
785 	if (!netif_running(dev))
786 		return -EINVAL;
787 
788 	if (!dev->phydev)
789 		return -ENODEV;
790 
791 	return phy_ethtool_ksettings_set(dev->phydev, cmd);
792 }
793 
bcmgenet_set_features(struct net_device * dev,netdev_features_t features)794 static int bcmgenet_set_features(struct net_device *dev,
795 				 netdev_features_t features)
796 {
797 	struct bcmgenet_priv *priv = netdev_priv(dev);
798 	u32 reg;
799 	int ret;
800 
801 	ret = clk_prepare_enable(priv->clk);
802 	if (ret)
803 		return ret;
804 
805 	/* Make sure we reflect the value of CRC_CMD_FWD */
806 	reg = bcmgenet_umac_readl(priv, UMAC_CMD);
807 	priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
808 
809 	clk_disable_unprepare(priv->clk);
810 
811 	return ret;
812 }
813 
bcmgenet_get_msglevel(struct net_device * dev)814 static u32 bcmgenet_get_msglevel(struct net_device *dev)
815 {
816 	struct bcmgenet_priv *priv = netdev_priv(dev);
817 
818 	return priv->msg_enable;
819 }
820 
bcmgenet_set_msglevel(struct net_device * dev,u32 level)821 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
822 {
823 	struct bcmgenet_priv *priv = netdev_priv(dev);
824 
825 	priv->msg_enable = level;
826 }
827 
bcmgenet_get_coalesce(struct net_device * dev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)828 static int bcmgenet_get_coalesce(struct net_device *dev,
829 				 struct ethtool_coalesce *ec,
830 				 struct kernel_ethtool_coalesce *kernel_coal,
831 				 struct netlink_ext_ack *extack)
832 {
833 	struct bcmgenet_priv *priv = netdev_priv(dev);
834 	struct bcmgenet_rx_ring *ring;
835 	unsigned int i;
836 
837 	ec->tx_max_coalesced_frames =
838 		bcmgenet_tdma_ring_readl(priv, 0, DMA_MBUF_DONE_THRESH);
839 	ec->rx_max_coalesced_frames =
840 		bcmgenet_rdma_ring_readl(priv, 0, DMA_MBUF_DONE_THRESH);
841 	ec->rx_coalesce_usecs =
842 		bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT) * 8192 / 1000;
843 
844 	for (i = 0; i <= priv->hw_params->rx_queues; i++) {
845 		ring = &priv->rx_rings[i];
846 		ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
847 	}
848 
849 	return 0;
850 }
851 
bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring * ring,u32 usecs,u32 pkts)852 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring,
853 				     u32 usecs, u32 pkts)
854 {
855 	struct bcmgenet_priv *priv = ring->priv;
856 	unsigned int i = ring->index;
857 	u32 reg;
858 
859 	bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH);
860 
861 	reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
862 	reg &= ~DMA_TIMEOUT_MASK;
863 	reg |= DIV_ROUND_UP(usecs * 1000, 8192);
864 	bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
865 }
866 
bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring * ring,struct ethtool_coalesce * ec)867 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring,
868 					  struct ethtool_coalesce *ec)
869 {
870 	struct dim_cq_moder moder;
871 	u32 usecs, pkts;
872 
873 	ring->rx_coalesce_usecs = ec->rx_coalesce_usecs;
874 	ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
875 	usecs = ring->rx_coalesce_usecs;
876 	pkts = ring->rx_max_coalesced_frames;
877 
878 	if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) {
879 		moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode);
880 		usecs = moder.usec;
881 		pkts = moder.pkts;
882 	}
883 
884 	ring->dim.use_dim = ec->use_adaptive_rx_coalesce;
885 	bcmgenet_set_rx_coalesce(ring, usecs, pkts);
886 }
887 
bcmgenet_set_coalesce(struct net_device * dev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)888 static int bcmgenet_set_coalesce(struct net_device *dev,
889 				 struct ethtool_coalesce *ec,
890 				 struct kernel_ethtool_coalesce *kernel_coal,
891 				 struct netlink_ext_ack *extack)
892 {
893 	struct bcmgenet_priv *priv = netdev_priv(dev);
894 	unsigned int i;
895 
896 	/* Base system clock is 125Mhz, DMA timeout is this reference clock
897 	 * divided by 1024, which yields roughly 8.192us, our maximum value
898 	 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
899 	 */
900 	if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
901 	    ec->tx_max_coalesced_frames == 0 ||
902 	    ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
903 	    ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
904 		return -EINVAL;
905 
906 	if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
907 		return -EINVAL;
908 
909 	/* GENET TDMA hardware does not support a configurable timeout, but will
910 	 * always generate an interrupt either after MBDONE packets have been
911 	 * transmitted, or when the ring is empty.
912 	 */
913 
914 	/* Program all TX queues with the same values, as there is no
915 	 * ethtool knob to do coalescing on a per-queue basis
916 	 */
917 	for (i = 0; i <= priv->hw_params->tx_queues; i++)
918 		bcmgenet_tdma_ring_writel(priv, i,
919 					  ec->tx_max_coalesced_frames,
920 					  DMA_MBUF_DONE_THRESH);
921 
922 	for (i = 0; i <= priv->hw_params->rx_queues; i++)
923 		bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec);
924 
925 	return 0;
926 }
927 
bcmgenet_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * epause)928 static void bcmgenet_get_pauseparam(struct net_device *dev,
929 				    struct ethtool_pauseparam *epause)
930 {
931 	struct bcmgenet_priv *priv;
932 	u32 umac_cmd;
933 
934 	priv = netdev_priv(dev);
935 
936 	epause->autoneg = priv->autoneg_pause;
937 
938 	if (netif_carrier_ok(dev)) {
939 		/* report active state when link is up */
940 		umac_cmd = bcmgenet_umac_readl(priv, UMAC_CMD);
941 		epause->tx_pause = !(umac_cmd & CMD_TX_PAUSE_IGNORE);
942 		epause->rx_pause = !(umac_cmd & CMD_RX_PAUSE_IGNORE);
943 	} else {
944 		/* otherwise report stored settings */
945 		epause->tx_pause = priv->tx_pause;
946 		epause->rx_pause = priv->rx_pause;
947 	}
948 }
949 
bcmgenet_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * epause)950 static int bcmgenet_set_pauseparam(struct net_device *dev,
951 				   struct ethtool_pauseparam *epause)
952 {
953 	struct bcmgenet_priv *priv = netdev_priv(dev);
954 
955 	if (!dev->phydev)
956 		return -ENODEV;
957 
958 	if (!phy_validate_pause(dev->phydev, epause))
959 		return -EINVAL;
960 
961 	priv->autoneg_pause = !!epause->autoneg;
962 	priv->tx_pause = !!epause->tx_pause;
963 	priv->rx_pause = !!epause->rx_pause;
964 
965 	bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause);
966 
967 	return 0;
968 }
969 
970 /* standard ethtool support functions. */
971 enum bcmgenet_stat_type {
972 	BCMGENET_STAT_RTNL = -1,
973 	BCMGENET_STAT_MIB_RX,
974 	BCMGENET_STAT_MIB_TX,
975 	BCMGENET_STAT_RUNT,
976 	BCMGENET_STAT_MISC,
977 	BCMGENET_STAT_SOFT,
978 	BCMGENET_STAT_SOFT64,
979 };
980 
981 struct bcmgenet_stats {
982 	char stat_string[ETH_GSTRING_LEN];
983 	int stat_sizeof;
984 	int stat_offset;
985 	enum bcmgenet_stat_type type;
986 	/* reg offset from UMAC base for misc counters */
987 	u16 reg_offset;
988 	/* sync for u64 stats counters */
989 	int syncp_offset;
990 };
991 
992 #define STAT_RTNL(m) { \
993 	.stat_string = __stringify(m), \
994 	.stat_sizeof = sizeof(((struct rtnl_link_stats64 *)0)->m), \
995 	.stat_offset = offsetof(struct rtnl_link_stats64, m), \
996 	.type = BCMGENET_STAT_RTNL, \
997 }
998 
999 #define STAT_GENET_MIB(str, m, _type) { \
1000 	.stat_string = str, \
1001 	.stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
1002 	.stat_offset = offsetof(struct bcmgenet_priv, m), \
1003 	.type = _type, \
1004 }
1005 
1006 #define STAT_GENET_SOFT_MIB64(str, s, m) { \
1007 	.stat_string = str, \
1008 	.stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->s.m), \
1009 	.stat_offset = offsetof(struct bcmgenet_priv, s.m), \
1010 	.type = BCMGENET_STAT_SOFT64, \
1011 	.syncp_offset = offsetof(struct bcmgenet_priv, s.syncp), \
1012 }
1013 
1014 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
1015 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
1016 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
1017 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1018 
1019 #define STAT_GENET_MISC(str, m, offset) { \
1020 	.stat_string = str, \
1021 	.stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
1022 	.stat_offset = offsetof(struct bcmgenet_priv, m), \
1023 	.type = BCMGENET_STAT_MISC, \
1024 	.reg_offset = offset, \
1025 }
1026 
1027 #define STAT_GENET_Q(num) \
1028 	STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_packets", \
1029 			tx_rings[num].stats64, packets), \
1030 	STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_bytes", \
1031 			tx_rings[num].stats64, bytes), \
1032 	STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_errors", \
1033 			tx_rings[num].stats64, errors), \
1034 	STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_dropped", \
1035 			tx_rings[num].stats64, dropped), \
1036 	STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_bytes", \
1037 			rx_rings[num].stats64, bytes),	 \
1038 	STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_packets", \
1039 			rx_rings[num].stats64, packets), \
1040 	STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_errors", \
1041 			rx_rings[num].stats64, errors), \
1042 	STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_dropped", \
1043 			rx_rings[num].stats64, dropped), \
1044 	STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_multicast", \
1045 			rx_rings[num].stats64, multicast), \
1046 	STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_missed", \
1047 			rx_rings[num].stats64, missed), \
1048 	STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_length_errors", \
1049 			rx_rings[num].stats64, length_errors), \
1050 	STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_over_errors", \
1051 			rx_rings[num].stats64, over_errors), \
1052 	STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_crc_errors", \
1053 			rx_rings[num].stats64, crc_errors), \
1054 	STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_frame_errors", \
1055 			rx_rings[num].stats64, frame_errors), \
1056 	STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_fragmented_errors", \
1057 			rx_rings[num].stats64, fragmented_errors), \
1058 	STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_broadcast", \
1059 			rx_rings[num].stats64, broadcast)
1060 
1061 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
1062  * between the end of TX stats and the beginning of the RX RUNT
1063  */
1064 #define BCMGENET_STAT_OFFSET	0xc
1065 
1066 /* Hardware counters must be kept in sync because the order/offset
1067  * is important here (order in structure declaration = order in hardware)
1068  */
1069 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
1070 	/* general stats */
1071 	STAT_RTNL(rx_packets),
1072 	STAT_RTNL(tx_packets),
1073 	STAT_RTNL(rx_bytes),
1074 	STAT_RTNL(tx_bytes),
1075 	STAT_RTNL(rx_errors),
1076 	STAT_RTNL(tx_errors),
1077 	STAT_RTNL(rx_dropped),
1078 	STAT_RTNL(tx_dropped),
1079 	STAT_RTNL(multicast),
1080 	STAT_RTNL(rx_missed_errors),
1081 	STAT_RTNL(rx_length_errors),
1082 	STAT_RTNL(rx_over_errors),
1083 	STAT_RTNL(rx_crc_errors),
1084 	STAT_RTNL(rx_frame_errors),
1085 	/* UniMAC RSV counters */
1086 	STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
1087 	STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
1088 	STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
1089 	STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
1090 	STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
1091 	STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
1092 	STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
1093 	STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
1094 	STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
1095 	STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
1096 	STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
1097 	STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
1098 	STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
1099 	STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
1100 	STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
1101 	STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
1102 	STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
1103 	STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
1104 	STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
1105 	STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
1106 	STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
1107 	STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
1108 	STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
1109 	STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
1110 	STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
1111 	STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
1112 	STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
1113 	STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
1114 	STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
1115 	/* UniMAC TSV counters */
1116 	STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
1117 	STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
1118 	STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
1119 	STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
1120 	STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
1121 	STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
1122 	STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
1123 	STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
1124 	STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
1125 	STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
1126 	STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
1127 	STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
1128 	STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
1129 	STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
1130 	STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
1131 	STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
1132 	STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
1133 	STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
1134 	STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
1135 	STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
1136 	STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
1137 	STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
1138 	STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
1139 	STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
1140 	STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
1141 	STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
1142 	STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
1143 	STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
1144 	STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
1145 	/* UniMAC RUNT counters */
1146 	STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
1147 	STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
1148 	STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
1149 	STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
1150 	/* Misc UniMAC counters */
1151 	STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
1152 			UMAC_RBUF_OVFL_CNT_V1),
1153 	STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
1154 			UMAC_RBUF_ERR_CNT_V1),
1155 	STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
1156 	STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
1157 	STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
1158 	STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
1159 	STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb),
1160 	STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed",
1161 			    mib.tx_realloc_tsb_failed),
1162 	/* Per TX queues */
1163 	STAT_GENET_Q(0),
1164 	STAT_GENET_Q(1),
1165 	STAT_GENET_Q(2),
1166 	STAT_GENET_Q(3),
1167 	STAT_GENET_Q(4),
1168 };
1169 
1170 #define BCMGENET_STATS_LEN	ARRAY_SIZE(bcmgenet_gstrings_stats)
1171 
1172 #define BCMGENET_STATS64_ADD(stats, m, v) \
1173 	do { \
1174 		u64_stats_update_begin(&stats->syncp); \
1175 		u64_stats_add(&stats->m, v); \
1176 		u64_stats_update_end(&stats->syncp); \
1177 	} while (0)
1178 
1179 #define BCMGENET_STATS64_INC(stats, m) \
1180 	do { \
1181 		u64_stats_update_begin(&stats->syncp); \
1182 		u64_stats_inc(&stats->m); \
1183 		u64_stats_update_end(&stats->syncp); \
1184 	} while (0)
1185 
bcmgenet_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1186 static void bcmgenet_get_drvinfo(struct net_device *dev,
1187 				 struct ethtool_drvinfo *info)
1188 {
1189 	strscpy(info->driver, "bcmgenet", sizeof(info->driver));
1190 }
1191 
bcmgenet_get_sset_count(struct net_device * dev,int string_set)1192 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
1193 {
1194 	switch (string_set) {
1195 	case ETH_SS_STATS:
1196 		return BCMGENET_STATS_LEN;
1197 	default:
1198 		return -EOPNOTSUPP;
1199 	}
1200 }
1201 
bcmgenet_get_strings(struct net_device * dev,u32 stringset,u8 * data)1202 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
1203 				 u8 *data)
1204 {
1205 	const char *str;
1206 	int i;
1207 
1208 	switch (stringset) {
1209 	case ETH_SS_STATS:
1210 		for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1211 			str = bcmgenet_gstrings_stats[i].stat_string;
1212 			ethtool_puts(&data, str);
1213 		}
1214 		break;
1215 	}
1216 }
1217 
bcmgenet_update_stat_misc(struct bcmgenet_priv * priv,u16 offset)1218 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
1219 {
1220 	u16 new_offset;
1221 	u32 val;
1222 
1223 	switch (offset) {
1224 	case UMAC_RBUF_OVFL_CNT_V1:
1225 		if (GENET_IS_V2(priv))
1226 			new_offset = RBUF_OVFL_CNT_V2;
1227 		else
1228 			new_offset = RBUF_OVFL_CNT_V3PLUS;
1229 
1230 		val = bcmgenet_rbuf_readl(priv,	new_offset);
1231 		/* clear if overflowed */
1232 		if (val == ~0)
1233 			bcmgenet_rbuf_writel(priv, 0, new_offset);
1234 		break;
1235 	case UMAC_RBUF_ERR_CNT_V1:
1236 		if (GENET_IS_V2(priv))
1237 			new_offset = RBUF_ERR_CNT_V2;
1238 		else
1239 			new_offset = RBUF_ERR_CNT_V3PLUS;
1240 
1241 		val = bcmgenet_rbuf_readl(priv,	new_offset);
1242 		/* clear if overflowed */
1243 		if (val == ~0)
1244 			bcmgenet_rbuf_writel(priv, 0, new_offset);
1245 		break;
1246 	default:
1247 		val = bcmgenet_umac_readl(priv, offset);
1248 		/* clear if overflowed */
1249 		if (val == ~0)
1250 			bcmgenet_umac_writel(priv, 0, offset);
1251 		break;
1252 	}
1253 
1254 	return val;
1255 }
1256 
bcmgenet_update_mib_counters(struct bcmgenet_priv * priv)1257 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
1258 {
1259 	int i, j = 0;
1260 
1261 	for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1262 		const struct bcmgenet_stats *s;
1263 		u8 offset = 0;
1264 		u32 val = 0;
1265 		char *p;
1266 
1267 		s = &bcmgenet_gstrings_stats[i];
1268 		switch (s->type) {
1269 		case BCMGENET_STAT_RTNL:
1270 		case BCMGENET_STAT_SOFT:
1271 		case BCMGENET_STAT_SOFT64:
1272 			continue;
1273 		case BCMGENET_STAT_RUNT:
1274 			offset += BCMGENET_STAT_OFFSET;
1275 			fallthrough;
1276 		case BCMGENET_STAT_MIB_TX:
1277 			offset += BCMGENET_STAT_OFFSET;
1278 			fallthrough;
1279 		case BCMGENET_STAT_MIB_RX:
1280 			val = bcmgenet_umac_readl(priv,
1281 						  UMAC_MIB_START + j + offset);
1282 			offset = 0;	/* Reset Offset */
1283 			break;
1284 		case BCMGENET_STAT_MISC:
1285 			if (GENET_IS_V1(priv)) {
1286 				val = bcmgenet_umac_readl(priv, s->reg_offset);
1287 				/* clear if overflowed */
1288 				if (val == ~0)
1289 					bcmgenet_umac_writel(priv, 0,
1290 							     s->reg_offset);
1291 			} else {
1292 				val = bcmgenet_update_stat_misc(priv,
1293 								s->reg_offset);
1294 			}
1295 			break;
1296 		}
1297 
1298 		j += s->stat_sizeof;
1299 		p = (char *)priv + s->stat_offset;
1300 		*(u32 *)p = val;
1301 	}
1302 }
1303 
bcmgenet_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)1304 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
1305 				       struct ethtool_stats *stats,
1306 				       u64 *data)
1307 {
1308 	struct bcmgenet_priv *priv = netdev_priv(dev);
1309 	struct rtnl_link_stats64 stats64;
1310 	struct u64_stats_sync *syncp;
1311 	unsigned int start;
1312 	int i;
1313 
1314 	if (netif_running(dev))
1315 		bcmgenet_update_mib_counters(priv);
1316 
1317 	dev_get_stats(dev, &stats64);
1318 
1319 	for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1320 		const struct bcmgenet_stats *s;
1321 		char *p;
1322 
1323 		s = &bcmgenet_gstrings_stats[i];
1324 		p = (char *)priv;
1325 
1326 		if (s->type == BCMGENET_STAT_SOFT64) {
1327 			syncp = (struct u64_stats_sync *)(p + s->syncp_offset);
1328 			do {
1329 				start = u64_stats_fetch_begin(syncp);
1330 				data[i] = u64_stats_read((u64_stats_t *)(p + s->stat_offset));
1331 			} while (u64_stats_fetch_retry(syncp, start));
1332 		} else {
1333 			if (s->type == BCMGENET_STAT_RTNL)
1334 				p = (char *)&stats64;
1335 
1336 			p += s->stat_offset;
1337 			if (sizeof(unsigned long) != sizeof(u32) &&
1338 				s->stat_sizeof == sizeof(unsigned long))
1339 				data[i] = *(unsigned long *)p;
1340 			else
1341 				data[i] = *(u32 *)p;
1342 		}
1343 	}
1344 }
1345 
bcmgenet_eee_enable_set(struct net_device * dev,bool enable,bool tx_lpi_enabled)1346 void bcmgenet_eee_enable_set(struct net_device *dev, bool enable,
1347 			     bool tx_lpi_enabled)
1348 {
1349 	struct bcmgenet_priv *priv = netdev_priv(dev);
1350 	u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
1351 	u32 reg;
1352 
1353 	if (enable && !priv->clk_eee_enabled) {
1354 		clk_prepare_enable(priv->clk_eee);
1355 		priv->clk_eee_enabled = true;
1356 	}
1357 
1358 	reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1359 	if (enable)
1360 		reg |= EEE_EN;
1361 	else
1362 		reg &= ~EEE_EN;
1363 	bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1364 
1365 	/* Enable EEE and switch to a 27Mhz clock automatically */
1366 	reg = bcmgenet_readl(priv->base + off);
1367 	if (tx_lpi_enabled)
1368 		reg |= TBUF_EEE_EN | TBUF_PM_EN;
1369 	else
1370 		reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
1371 	bcmgenet_writel(reg, priv->base + off);
1372 
1373 	/* Do the same for thing for RBUF */
1374 	reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1375 	if (enable)
1376 		reg |= RBUF_EEE_EN | RBUF_PM_EN;
1377 	else
1378 		reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1379 	bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1380 
1381 	if (!enable && priv->clk_eee_enabled) {
1382 		clk_disable_unprepare(priv->clk_eee);
1383 		priv->clk_eee_enabled = false;
1384 	}
1385 
1386 	priv->eee.eee_enabled = enable;
1387 	priv->eee.tx_lpi_enabled = tx_lpi_enabled;
1388 }
1389 
bcmgenet_get_eee(struct net_device * dev,struct ethtool_keee * e)1390 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_keee *e)
1391 {
1392 	struct bcmgenet_priv *priv = netdev_priv(dev);
1393 	struct ethtool_keee *p = &priv->eee;
1394 
1395 	if (GENET_IS_V1(priv))
1396 		return -EOPNOTSUPP;
1397 
1398 	if (!dev->phydev)
1399 		return -ENODEV;
1400 
1401 	e->tx_lpi_enabled = p->tx_lpi_enabled;
1402 	e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1403 
1404 	return phy_ethtool_get_eee(dev->phydev, e);
1405 }
1406 
bcmgenet_set_eee(struct net_device * dev,struct ethtool_keee * e)1407 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_keee *e)
1408 {
1409 	struct bcmgenet_priv *priv = netdev_priv(dev);
1410 	struct ethtool_keee *p = &priv->eee;
1411 	bool active;
1412 
1413 	if (GENET_IS_V1(priv))
1414 		return -EOPNOTSUPP;
1415 
1416 	if (!dev->phydev)
1417 		return -ENODEV;
1418 
1419 	p->eee_enabled = e->eee_enabled;
1420 
1421 	if (!p->eee_enabled) {
1422 		bcmgenet_eee_enable_set(dev, false, false);
1423 	} else {
1424 		active = phy_init_eee(dev->phydev, false) >= 0;
1425 		bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1426 		bcmgenet_eee_enable_set(dev, active, e->tx_lpi_enabled);
1427 	}
1428 
1429 	return phy_ethtool_set_eee(dev->phydev, e);
1430 }
1431 
bcmgenet_validate_flow(struct net_device * dev,struct ethtool_rxnfc * cmd)1432 static int bcmgenet_validate_flow(struct net_device *dev,
1433 				  struct ethtool_rxnfc *cmd)
1434 {
1435 	struct ethtool_usrip4_spec *l4_mask;
1436 	struct ethhdr *eth_mask;
1437 
1438 	if (cmd->fs.location >= MAX_NUM_OF_FS_RULES &&
1439 	    cmd->fs.location != RX_CLS_LOC_ANY) {
1440 		netdev_err(dev, "rxnfc: Invalid location (%d)\n",
1441 			   cmd->fs.location);
1442 		return -EINVAL;
1443 	}
1444 
1445 	switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1446 	case IP_USER_FLOW:
1447 		l4_mask = &cmd->fs.m_u.usr_ip4_spec;
1448 		/* don't allow mask which isn't valid */
1449 		if (VALIDATE_MASK(l4_mask->ip4src) ||
1450 		    VALIDATE_MASK(l4_mask->ip4dst) ||
1451 		    VALIDATE_MASK(l4_mask->l4_4_bytes) ||
1452 		    VALIDATE_MASK(l4_mask->proto) ||
1453 		    VALIDATE_MASK(l4_mask->ip_ver) ||
1454 		    VALIDATE_MASK(l4_mask->tos)) {
1455 			netdev_err(dev, "rxnfc: Unsupported mask\n");
1456 			return -EINVAL;
1457 		}
1458 		break;
1459 	case ETHER_FLOW:
1460 		eth_mask = &cmd->fs.m_u.ether_spec;
1461 		/* don't allow mask which isn't valid */
1462 		if (VALIDATE_MASK(eth_mask->h_dest) ||
1463 		    VALIDATE_MASK(eth_mask->h_source) ||
1464 		    VALIDATE_MASK(eth_mask->h_proto)) {
1465 			netdev_err(dev, "rxnfc: Unsupported mask\n");
1466 			return -EINVAL;
1467 		}
1468 		break;
1469 	default:
1470 		netdev_err(dev, "rxnfc: Unsupported flow type (0x%x)\n",
1471 			   cmd->fs.flow_type);
1472 		return -EINVAL;
1473 	}
1474 
1475 	if ((cmd->fs.flow_type & FLOW_EXT)) {
1476 		/* don't allow mask which isn't valid */
1477 		if (VALIDATE_MASK(cmd->fs.m_ext.vlan_etype) ||
1478 		    VALIDATE_MASK(cmd->fs.m_ext.vlan_tci)) {
1479 			netdev_err(dev, "rxnfc: Unsupported mask\n");
1480 			return -EINVAL;
1481 		}
1482 		if (cmd->fs.m_ext.data[0] || cmd->fs.m_ext.data[1]) {
1483 			netdev_err(dev, "rxnfc: user-def not supported\n");
1484 			return -EINVAL;
1485 		}
1486 	}
1487 
1488 	if ((cmd->fs.flow_type & FLOW_MAC_EXT)) {
1489 		/* don't allow mask which isn't valid */
1490 		if (VALIDATE_MASK(cmd->fs.m_ext.h_dest)) {
1491 			netdev_err(dev, "rxnfc: Unsupported mask\n");
1492 			return -EINVAL;
1493 		}
1494 	}
1495 
1496 	return 0;
1497 }
1498 
bcmgenet_insert_flow(struct net_device * dev,struct ethtool_rxnfc * cmd)1499 static int bcmgenet_insert_flow(struct net_device *dev,
1500 				struct ethtool_rxnfc *cmd)
1501 {
1502 	struct bcmgenet_priv *priv = netdev_priv(dev);
1503 	struct bcmgenet_rxnfc_rule *loc_rule;
1504 	int err, i;
1505 
1506 	if (priv->hw_params->hfb_filter_size < 128) {
1507 		netdev_err(dev, "rxnfc: Not supported by this device\n");
1508 		return -EINVAL;
1509 	}
1510 
1511 	if (cmd->fs.ring_cookie > priv->hw_params->rx_queues &&
1512 	    cmd->fs.ring_cookie != RX_CLS_FLOW_WAKE &&
1513 	    cmd->fs.ring_cookie != RX_CLS_FLOW_DISC) {
1514 		netdev_err(dev, "rxnfc: Unsupported action (%llu)\n",
1515 			   cmd->fs.ring_cookie);
1516 		return -EINVAL;
1517 	}
1518 
1519 	err = bcmgenet_validate_flow(dev, cmd);
1520 	if (err)
1521 		return err;
1522 
1523 	if (cmd->fs.location == RX_CLS_LOC_ANY) {
1524 		list_for_each_entry(loc_rule, &priv->rxnfc_list, list) {
1525 			cmd->fs.location = loc_rule->fs.location;
1526 			err = memcmp(&loc_rule->fs, &cmd->fs,
1527 				     sizeof(struct ethtool_rx_flow_spec));
1528 			if (!err)
1529 				/* rule exists so return current location */
1530 				return 0;
1531 		}
1532 		for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
1533 			loc_rule = &priv->rxnfc_rules[i];
1534 			if (loc_rule->state == BCMGENET_RXNFC_STATE_UNUSED) {
1535 				cmd->fs.location = i;
1536 				break;
1537 			}
1538 		}
1539 		if (i == MAX_NUM_OF_FS_RULES) {
1540 			cmd->fs.location = RX_CLS_LOC_ANY;
1541 			return -ENOSPC;
1542 		}
1543 	} else {
1544 		loc_rule = &priv->rxnfc_rules[cmd->fs.location];
1545 	}
1546 	if (loc_rule->state == BCMGENET_RXNFC_STATE_ENABLED)
1547 		bcmgenet_hfb_disable_filter(priv, cmd->fs.location + 1);
1548 	if (loc_rule->state != BCMGENET_RXNFC_STATE_UNUSED) {
1549 		list_del(&loc_rule->list);
1550 		bcmgenet_hfb_clear_filter(priv, cmd->fs.location + 1);
1551 	}
1552 	loc_rule->state = BCMGENET_RXNFC_STATE_UNUSED;
1553 	memcpy(&loc_rule->fs, &cmd->fs,
1554 	       sizeof(struct ethtool_rx_flow_spec));
1555 
1556 	bcmgenet_hfb_create_rxnfc_filter(priv, loc_rule);
1557 
1558 	list_add_tail(&loc_rule->list, &priv->rxnfc_list);
1559 
1560 	return 0;
1561 }
1562 
bcmgenet_delete_flow(struct net_device * dev,struct ethtool_rxnfc * cmd)1563 static int bcmgenet_delete_flow(struct net_device *dev,
1564 				struct ethtool_rxnfc *cmd)
1565 {
1566 	struct bcmgenet_priv *priv = netdev_priv(dev);
1567 	struct bcmgenet_rxnfc_rule *rule;
1568 	int err = 0;
1569 
1570 	if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1571 		return -EINVAL;
1572 
1573 	rule = &priv->rxnfc_rules[cmd->fs.location];
1574 	if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) {
1575 		err =  -ENOENT;
1576 		goto out;
1577 	}
1578 
1579 	if (rule->state == BCMGENET_RXNFC_STATE_ENABLED)
1580 		bcmgenet_hfb_disable_filter(priv, cmd->fs.location + 1);
1581 	if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) {
1582 		list_del(&rule->list);
1583 		bcmgenet_hfb_clear_filter(priv, cmd->fs.location + 1);
1584 	}
1585 	rule->state = BCMGENET_RXNFC_STATE_UNUSED;
1586 	memset(&rule->fs, 0, sizeof(struct ethtool_rx_flow_spec));
1587 
1588 out:
1589 	return err;
1590 }
1591 
bcmgenet_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)1592 static int bcmgenet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1593 {
1594 	struct bcmgenet_priv *priv = netdev_priv(dev);
1595 	int err = 0;
1596 
1597 	switch (cmd->cmd) {
1598 	case ETHTOOL_SRXCLSRLINS:
1599 		err = bcmgenet_insert_flow(dev, cmd);
1600 		break;
1601 	case ETHTOOL_SRXCLSRLDEL:
1602 		err = bcmgenet_delete_flow(dev, cmd);
1603 		break;
1604 	default:
1605 		netdev_warn(priv->dev, "Unsupported ethtool command. (%d)\n",
1606 			    cmd->cmd);
1607 		return -EINVAL;
1608 	}
1609 
1610 	return err;
1611 }
1612 
bcmgenet_get_flow(struct net_device * dev,struct ethtool_rxnfc * cmd,int loc)1613 static int bcmgenet_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1614 			     int loc)
1615 {
1616 	struct bcmgenet_priv *priv = netdev_priv(dev);
1617 	struct bcmgenet_rxnfc_rule *rule;
1618 	int err = 0;
1619 
1620 	if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1621 		return -EINVAL;
1622 
1623 	rule = &priv->rxnfc_rules[loc];
1624 	if (rule->state == BCMGENET_RXNFC_STATE_UNUSED)
1625 		err = -ENOENT;
1626 	else
1627 		memcpy(&cmd->fs, &rule->fs,
1628 		       sizeof(struct ethtool_rx_flow_spec));
1629 
1630 	return err;
1631 }
1632 
bcmgenet_get_num_flows(struct bcmgenet_priv * priv)1633 static int bcmgenet_get_num_flows(struct bcmgenet_priv *priv)
1634 {
1635 	struct list_head *pos;
1636 	int res = 0;
1637 
1638 	list_for_each(pos, &priv->rxnfc_list)
1639 		res++;
1640 
1641 	return res;
1642 }
1643 
bcmgenet_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)1644 static int bcmgenet_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1645 			      u32 *rule_locs)
1646 {
1647 	struct bcmgenet_priv *priv = netdev_priv(dev);
1648 	struct bcmgenet_rxnfc_rule *rule;
1649 	int err = 0;
1650 	int i = 0;
1651 
1652 	switch (cmd->cmd) {
1653 	case ETHTOOL_GRXRINGS:
1654 		cmd->data = priv->hw_params->rx_queues ?: 1;
1655 		break;
1656 	case ETHTOOL_GRXCLSRLCNT:
1657 		cmd->rule_cnt = bcmgenet_get_num_flows(priv);
1658 		cmd->data = MAX_NUM_OF_FS_RULES | RX_CLS_LOC_SPECIAL;
1659 		break;
1660 	case ETHTOOL_GRXCLSRULE:
1661 		err = bcmgenet_get_flow(dev, cmd, cmd->fs.location);
1662 		break;
1663 	case ETHTOOL_GRXCLSRLALL:
1664 		list_for_each_entry(rule, &priv->rxnfc_list, list)
1665 			if (i < cmd->rule_cnt)
1666 				rule_locs[i++] = rule->fs.location;
1667 		cmd->rule_cnt = i;
1668 		cmd->data = MAX_NUM_OF_FS_RULES;
1669 		break;
1670 	default:
1671 		err = -EOPNOTSUPP;
1672 		break;
1673 	}
1674 
1675 	return err;
1676 }
1677 
1678 /* standard ethtool support functions. */
1679 static const struct ethtool_ops bcmgenet_ethtool_ops = {
1680 	.supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
1681 				     ETHTOOL_COALESCE_MAX_FRAMES |
1682 				     ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
1683 	.begin			= bcmgenet_begin,
1684 	.complete		= bcmgenet_complete,
1685 	.get_strings		= bcmgenet_get_strings,
1686 	.get_sset_count		= bcmgenet_get_sset_count,
1687 	.get_ethtool_stats	= bcmgenet_get_ethtool_stats,
1688 	.get_drvinfo		= bcmgenet_get_drvinfo,
1689 	.get_link		= ethtool_op_get_link,
1690 	.get_msglevel		= bcmgenet_get_msglevel,
1691 	.set_msglevel		= bcmgenet_set_msglevel,
1692 	.get_wol		= bcmgenet_get_wol,
1693 	.set_wol		= bcmgenet_set_wol,
1694 	.get_eee		= bcmgenet_get_eee,
1695 	.set_eee		= bcmgenet_set_eee,
1696 	.nway_reset		= phy_ethtool_nway_reset,
1697 	.get_coalesce		= bcmgenet_get_coalesce,
1698 	.set_coalesce		= bcmgenet_set_coalesce,
1699 	.get_link_ksettings	= bcmgenet_get_link_ksettings,
1700 	.set_link_ksettings	= bcmgenet_set_link_ksettings,
1701 	.get_ts_info		= ethtool_op_get_ts_info,
1702 	.get_rxnfc		= bcmgenet_get_rxnfc,
1703 	.set_rxnfc		= bcmgenet_set_rxnfc,
1704 	.get_pauseparam		= bcmgenet_get_pauseparam,
1705 	.set_pauseparam		= bcmgenet_set_pauseparam,
1706 };
1707 
1708 /* Power down the unimac, based on mode. */
bcmgenet_power_down(struct bcmgenet_priv * priv,enum bcmgenet_power_mode mode)1709 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1710 				enum bcmgenet_power_mode mode)
1711 {
1712 	int ret = 0;
1713 	u32 reg;
1714 
1715 	switch (mode) {
1716 	case GENET_POWER_CABLE_SENSE:
1717 		phy_detach(priv->dev->phydev);
1718 		break;
1719 
1720 	case GENET_POWER_WOL_MAGIC:
1721 		ret = bcmgenet_wol_power_down_cfg(priv, mode);
1722 		break;
1723 
1724 	case GENET_POWER_PASSIVE:
1725 		/* Power down LED */
1726 		if (bcmgenet_has_ext(priv)) {
1727 			reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1728 			if (GENET_IS_V5(priv) && !bcmgenet_has_ephy_16nm(priv))
1729 				reg |= EXT_PWR_DOWN_PHY_EN |
1730 				       EXT_PWR_DOWN_PHY_RD |
1731 				       EXT_PWR_DOWN_PHY_SD |
1732 				       EXT_PWR_DOWN_PHY_RX |
1733 				       EXT_PWR_DOWN_PHY_TX |
1734 				       EXT_IDDQ_GLBL_PWR;
1735 			else
1736 				reg |= EXT_PWR_DOWN_PHY;
1737 
1738 			reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1739 			bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1740 
1741 			bcmgenet_phy_power_set(priv->dev, false);
1742 		}
1743 		break;
1744 	default:
1745 		break;
1746 	}
1747 
1748 	return ret;
1749 }
1750 
bcmgenet_power_up(struct bcmgenet_priv * priv,enum bcmgenet_power_mode mode)1751 static int bcmgenet_power_up(struct bcmgenet_priv *priv,
1752 			     enum bcmgenet_power_mode mode)
1753 {
1754 	int ret = 0;
1755 	u32 reg;
1756 
1757 	if (!bcmgenet_has_ext(priv))
1758 		return ret;
1759 
1760 	reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1761 
1762 	switch (mode) {
1763 	case GENET_POWER_PASSIVE:
1764 		reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS |
1765 			 EXT_ENERGY_DET_MASK);
1766 		if (GENET_IS_V5(priv) && !bcmgenet_has_ephy_16nm(priv)) {
1767 			reg &= ~(EXT_PWR_DOWN_PHY_EN |
1768 				 EXT_PWR_DOWN_PHY_RD |
1769 				 EXT_PWR_DOWN_PHY_SD |
1770 				 EXT_PWR_DOWN_PHY_RX |
1771 				 EXT_PWR_DOWN_PHY_TX |
1772 				 EXT_IDDQ_GLBL_PWR);
1773 			reg |=   EXT_PHY_RESET;
1774 			bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1775 			mdelay(1);
1776 
1777 			reg &=  ~EXT_PHY_RESET;
1778 		} else {
1779 			reg &= ~EXT_PWR_DOWN_PHY;
1780 			reg |= EXT_PWR_DN_EN_LD;
1781 		}
1782 		bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1783 		bcmgenet_phy_power_set(priv->dev, true);
1784 		break;
1785 
1786 	case GENET_POWER_CABLE_SENSE:
1787 		/* enable APD */
1788 		if (!GENET_IS_V5(priv)) {
1789 			reg |= EXT_PWR_DN_EN_LD;
1790 			bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1791 		}
1792 		break;
1793 	case GENET_POWER_WOL_MAGIC:
1794 		ret = bcmgenet_wol_power_up_cfg(priv, mode);
1795 		break;
1796 	default:
1797 		break;
1798 	}
1799 
1800 	return ret;
1801 }
1802 
bcmgenet_get_txcb(struct bcmgenet_priv * priv,struct bcmgenet_tx_ring * ring)1803 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1804 					 struct bcmgenet_tx_ring *ring)
1805 {
1806 	struct enet_cb *tx_cb_ptr;
1807 
1808 	tx_cb_ptr = ring->cbs;
1809 	tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1810 
1811 	/* Advancing local write pointer */
1812 	if (ring->write_ptr == ring->end_ptr)
1813 		ring->write_ptr = ring->cb_ptr;
1814 	else
1815 		ring->write_ptr++;
1816 
1817 	return tx_cb_ptr;
1818 }
1819 
bcmgenet_put_txcb(struct bcmgenet_priv * priv,struct bcmgenet_tx_ring * ring)1820 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1821 					 struct bcmgenet_tx_ring *ring)
1822 {
1823 	struct enet_cb *tx_cb_ptr;
1824 
1825 	tx_cb_ptr = ring->cbs;
1826 	tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1827 
1828 	/* Rewinding local write pointer */
1829 	if (ring->write_ptr == ring->cb_ptr)
1830 		ring->write_ptr = ring->end_ptr;
1831 	else
1832 		ring->write_ptr--;
1833 
1834 	return tx_cb_ptr;
1835 }
1836 
bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring * ring)1837 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1838 {
1839 	bcmgenet_intrl2_1_writel(ring->priv,
1840 				 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1841 				 INTRL2_CPU_MASK_SET);
1842 }
1843 
bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring * ring)1844 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1845 {
1846 	bcmgenet_intrl2_1_writel(ring->priv,
1847 				 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1848 				 INTRL2_CPU_MASK_CLEAR);
1849 }
1850 
bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring * ring)1851 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1852 {
1853 	bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1854 				 INTRL2_CPU_MASK_CLEAR);
1855 }
1856 
bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring * ring)1857 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1858 {
1859 	bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1860 				 INTRL2_CPU_MASK_SET);
1861 }
1862 
1863 /* Simple helper to free a transmit control block's resources
1864  * Returns an skb when the last transmit control block associated with the
1865  * skb is freed.  The skb should be freed by the caller if necessary.
1866  */
bcmgenet_free_tx_cb(struct device * dev,struct enet_cb * cb)1867 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1868 					   struct enet_cb *cb)
1869 {
1870 	struct sk_buff *skb;
1871 
1872 	skb = cb->skb;
1873 
1874 	if (skb) {
1875 		cb->skb = NULL;
1876 		if (cb == GENET_CB(skb)->first_cb)
1877 			dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1878 					 dma_unmap_len(cb, dma_len),
1879 					 DMA_TO_DEVICE);
1880 		else
1881 			dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1882 				       dma_unmap_len(cb, dma_len),
1883 				       DMA_TO_DEVICE);
1884 		dma_unmap_addr_set(cb, dma_addr, 0);
1885 
1886 		if (cb == GENET_CB(skb)->last_cb)
1887 			return skb;
1888 
1889 	} else if (dma_unmap_addr(cb, dma_addr)) {
1890 		dma_unmap_page(dev,
1891 			       dma_unmap_addr(cb, dma_addr),
1892 			       dma_unmap_len(cb, dma_len),
1893 			       DMA_TO_DEVICE);
1894 		dma_unmap_addr_set(cb, dma_addr, 0);
1895 	}
1896 
1897 	return NULL;
1898 }
1899 
1900 /* Simple helper to free a receive control block's resources */
bcmgenet_free_rx_cb(struct device * dev,struct enet_cb * cb)1901 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1902 					   struct enet_cb *cb)
1903 {
1904 	struct sk_buff *skb;
1905 
1906 	skb = cb->skb;
1907 	cb->skb = NULL;
1908 
1909 	if (dma_unmap_addr(cb, dma_addr)) {
1910 		dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1911 				 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1912 		dma_unmap_addr_set(cb, dma_addr, 0);
1913 	}
1914 
1915 	return skb;
1916 }
1917 
1918 /* Unlocked version of the reclaim routine */
__bcmgenet_tx_reclaim(struct net_device * dev,struct bcmgenet_tx_ring * ring)1919 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1920 					  struct bcmgenet_tx_ring *ring)
1921 {
1922 	struct bcmgenet_tx_stats64 *stats = &ring->stats64;
1923 	struct bcmgenet_priv *priv = netdev_priv(dev);
1924 	unsigned int txbds_processed = 0;
1925 	unsigned int bytes_compl = 0;
1926 	unsigned int pkts_compl = 0;
1927 	unsigned int txbds_ready;
1928 	unsigned int c_index;
1929 	struct sk_buff *skb;
1930 
1931 	/* Clear status before servicing to reduce spurious interrupts */
1932 	bcmgenet_intrl2_1_writel(priv, (1 << ring->index), INTRL2_CPU_CLEAR);
1933 
1934 	/* Compute how many buffers are transmitted since last xmit call */
1935 	c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1936 		& DMA_C_INDEX_MASK;
1937 	txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1938 
1939 	netif_dbg(priv, tx_done, dev,
1940 		  "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1941 		  __func__, ring->index, ring->c_index, c_index, txbds_ready);
1942 
1943 	/* Reclaim transmitted buffers */
1944 	while (txbds_processed < txbds_ready) {
1945 		skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1946 					  &priv->tx_cbs[ring->clean_ptr]);
1947 		if (skb) {
1948 			pkts_compl++;
1949 			bytes_compl += GENET_CB(skb)->bytes_sent;
1950 			dev_consume_skb_any(skb);
1951 		}
1952 
1953 		txbds_processed++;
1954 		if (likely(ring->clean_ptr < ring->end_ptr))
1955 			ring->clean_ptr++;
1956 		else
1957 			ring->clean_ptr = ring->cb_ptr;
1958 	}
1959 
1960 	ring->free_bds += txbds_processed;
1961 	ring->c_index = c_index;
1962 
1963 	u64_stats_update_begin(&stats->syncp);
1964 	u64_stats_add(&stats->packets, pkts_compl);
1965 	u64_stats_add(&stats->bytes, bytes_compl);
1966 	u64_stats_update_end(&stats->syncp);
1967 
1968 	netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->index),
1969 				  pkts_compl, bytes_compl);
1970 
1971 	return txbds_processed;
1972 }
1973 
bcmgenet_tx_reclaim(struct net_device * dev,struct bcmgenet_tx_ring * ring,bool all)1974 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1975 				struct bcmgenet_tx_ring *ring,
1976 				bool all)
1977 {
1978 	struct bcmgenet_priv *priv = netdev_priv(dev);
1979 	struct device *kdev = &priv->pdev->dev;
1980 	unsigned int released, drop, wr_ptr;
1981 	struct enet_cb *cb_ptr;
1982 	struct sk_buff *skb;
1983 
1984 	spin_lock_bh(&ring->lock);
1985 	released = __bcmgenet_tx_reclaim(dev, ring);
1986 	if (all) {
1987 		skb = NULL;
1988 		drop = (ring->prod_index - ring->c_index) & DMA_C_INDEX_MASK;
1989 		released += drop;
1990 		ring->prod_index = ring->c_index & DMA_C_INDEX_MASK;
1991 		while (drop--) {
1992 			cb_ptr = bcmgenet_put_txcb(priv, ring);
1993 			skb = cb_ptr->skb;
1994 			bcmgenet_free_tx_cb(kdev, cb_ptr);
1995 			if (skb && cb_ptr == GENET_CB(skb)->first_cb) {
1996 				dev_consume_skb_any(skb);
1997 				skb = NULL;
1998 			}
1999 		}
2000 		if (skb)
2001 			dev_consume_skb_any(skb);
2002 		bcmgenet_tdma_ring_writel(priv, ring->index,
2003 					  ring->prod_index, TDMA_PROD_INDEX);
2004 		wr_ptr = ring->write_ptr * WORDS_PER_BD(priv);
2005 		bcmgenet_tdma_ring_writel(priv, ring->index, wr_ptr,
2006 					  TDMA_WRITE_PTR);
2007 	}
2008 	spin_unlock_bh(&ring->lock);
2009 
2010 	return released;
2011 }
2012 
bcmgenet_tx_poll(struct napi_struct * napi,int budget)2013 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
2014 {
2015 	struct bcmgenet_tx_ring *ring =
2016 		container_of(napi, struct bcmgenet_tx_ring, napi);
2017 	unsigned int work_done = 0;
2018 	struct netdev_queue *txq;
2019 
2020 	spin_lock(&ring->lock);
2021 	work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
2022 	if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
2023 		txq = netdev_get_tx_queue(ring->priv->dev, ring->index);
2024 		netif_tx_wake_queue(txq);
2025 	}
2026 	spin_unlock(&ring->lock);
2027 
2028 	if (work_done == 0) {
2029 		napi_complete(napi);
2030 		bcmgenet_tx_ring_int_enable(ring);
2031 
2032 		return 0;
2033 	}
2034 
2035 	return budget;
2036 }
2037 
bcmgenet_tx_reclaim_all(struct net_device * dev)2038 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
2039 {
2040 	struct bcmgenet_priv *priv = netdev_priv(dev);
2041 	int i = 0;
2042 
2043 	do {
2044 		bcmgenet_tx_reclaim(dev, &priv->tx_rings[i++], true);
2045 	} while (i <= priv->hw_params->tx_queues && netif_is_multiqueue(dev));
2046 }
2047 
2048 /* Reallocate the SKB to put enough headroom in front of it and insert
2049  * the transmit checksum offsets in the descriptors
2050  */
bcmgenet_add_tsb(struct net_device * dev,struct sk_buff * skb,struct bcmgenet_tx_ring * ring)2051 static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev,
2052 					struct sk_buff *skb,
2053 					struct bcmgenet_tx_ring *ring)
2054 {
2055 	struct bcmgenet_tx_stats64 *stats = &ring->stats64;
2056 	struct bcmgenet_priv *priv = netdev_priv(dev);
2057 	struct status_64 *status = NULL;
2058 	struct sk_buff *new_skb;
2059 	u16 offset;
2060 	u8 ip_proto;
2061 	__be16 ip_ver;
2062 	u32 tx_csum_info;
2063 
2064 	if (unlikely(skb_headroom(skb) < sizeof(*status))) {
2065 		/* If 64 byte status block enabled, must make sure skb has
2066 		 * enough headroom for us to insert 64B status block.
2067 		 */
2068 		new_skb = skb_realloc_headroom(skb, sizeof(*status));
2069 		if (!new_skb) {
2070 			dev_kfree_skb_any(skb);
2071 			priv->mib.tx_realloc_tsb_failed++;
2072 			BCMGENET_STATS64_INC(stats, dropped);
2073 			return NULL;
2074 		}
2075 		dev_consume_skb_any(skb);
2076 		skb = new_skb;
2077 		priv->mib.tx_realloc_tsb++;
2078 	}
2079 
2080 	skb_push(skb, sizeof(*status));
2081 	status = (struct status_64 *)skb->data;
2082 
2083 	if (skb->ip_summed  == CHECKSUM_PARTIAL) {
2084 		ip_ver = skb->protocol;
2085 		switch (ip_ver) {
2086 		case htons(ETH_P_IP):
2087 			ip_proto = ip_hdr(skb)->protocol;
2088 			break;
2089 		case htons(ETH_P_IPV6):
2090 			ip_proto = ipv6_hdr(skb)->nexthdr;
2091 			break;
2092 		default:
2093 			/* don't use UDP flag */
2094 			ip_proto = 0;
2095 			break;
2096 		}
2097 
2098 		offset = skb_checksum_start_offset(skb) - sizeof(*status);
2099 		tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
2100 				(offset + skb->csum_offset) |
2101 				STATUS_TX_CSUM_LV;
2102 
2103 		/* Set the special UDP flag for UDP */
2104 		if (ip_proto == IPPROTO_UDP)
2105 			tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
2106 
2107 		status->tx_csum_info = tx_csum_info;
2108 	}
2109 
2110 	return skb;
2111 }
2112 
bcmgenet_hide_tsb(struct sk_buff * skb)2113 static void bcmgenet_hide_tsb(struct sk_buff *skb)
2114 {
2115 	__skb_pull(skb, sizeof(struct status_64));
2116 }
2117 
bcmgenet_xmit(struct sk_buff * skb,struct net_device * dev)2118 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
2119 {
2120 	struct bcmgenet_priv *priv = netdev_priv(dev);
2121 	struct device *kdev = &priv->pdev->dev;
2122 	struct bcmgenet_tx_ring *ring = NULL;
2123 	struct enet_cb *tx_cb_ptr;
2124 	struct netdev_queue *txq;
2125 	int nr_frags, index;
2126 	dma_addr_t mapping;
2127 	unsigned int size;
2128 	skb_frag_t *frag;
2129 	u32 len_stat;
2130 	int ret;
2131 	int i;
2132 
2133 	index = skb_get_queue_mapping(skb);
2134 	/* Mapping strategy:
2135 	 * queue_mapping = 0, unclassified, packet xmited through ring 0
2136 	 * queue_mapping = 1, goes to ring 1. (highest priority queue)
2137 	 * queue_mapping = 2, goes to ring 2.
2138 	 * queue_mapping = 3, goes to ring 3.
2139 	 * queue_mapping = 4, goes to ring 4.
2140 	 */
2141 	ring = &priv->tx_rings[index];
2142 	txq = netdev_get_tx_queue(dev, index);
2143 
2144 	nr_frags = skb_shinfo(skb)->nr_frags;
2145 
2146 	spin_lock(&ring->lock);
2147 	if (ring->free_bds <= (nr_frags + 1)) {
2148 		if (!netif_tx_queue_stopped(txq))
2149 			netif_tx_stop_queue(txq);
2150 		ret = NETDEV_TX_BUSY;
2151 		goto out;
2152 	}
2153 
2154 	/* Retain how many bytes will be sent on the wire, without TSB inserted
2155 	 * by transmit checksum offload
2156 	 */
2157 	GENET_CB(skb)->bytes_sent = skb->len;
2158 
2159 	/* add the Transmit Status Block */
2160 	skb = bcmgenet_add_tsb(dev, skb, ring);
2161 	if (!skb) {
2162 		ret = NETDEV_TX_OK;
2163 		goto out;
2164 	}
2165 
2166 	for (i = 0; i <= nr_frags; i++) {
2167 		tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
2168 
2169 		BUG_ON(!tx_cb_ptr);
2170 
2171 		if (!i) {
2172 			/* Transmit single SKB or head of fragment list */
2173 			GENET_CB(skb)->first_cb = tx_cb_ptr;
2174 			size = skb_headlen(skb);
2175 			mapping = dma_map_single(kdev, skb->data, size,
2176 						 DMA_TO_DEVICE);
2177 		} else {
2178 			/* xmit fragment */
2179 			frag = &skb_shinfo(skb)->frags[i - 1];
2180 			size = skb_frag_size(frag);
2181 			mapping = skb_frag_dma_map(kdev, frag, 0, size,
2182 						   DMA_TO_DEVICE);
2183 		}
2184 
2185 		ret = dma_mapping_error(kdev, mapping);
2186 		if (ret) {
2187 			priv->mib.tx_dma_failed++;
2188 			netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
2189 			ret = NETDEV_TX_OK;
2190 			goto out_unmap_frags;
2191 		}
2192 		dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
2193 		dma_unmap_len_set(tx_cb_ptr, dma_len, size);
2194 
2195 		tx_cb_ptr->skb = skb;
2196 
2197 		len_stat = (size << DMA_BUFLENGTH_SHIFT) |
2198 			   (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
2199 
2200 		/* Note: if we ever change from DMA_TX_APPEND_CRC below we
2201 		 * will need to restore software padding of "runt" packets
2202 		 */
2203 		len_stat |= DMA_TX_APPEND_CRC;
2204 
2205 		if (!i) {
2206 			len_stat |= DMA_SOP;
2207 			if (skb->ip_summed == CHECKSUM_PARTIAL)
2208 				len_stat |= DMA_TX_DO_CSUM;
2209 		}
2210 		if (i == nr_frags)
2211 			len_stat |= DMA_EOP;
2212 
2213 		dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
2214 	}
2215 
2216 	GENET_CB(skb)->last_cb = tx_cb_ptr;
2217 
2218 	bcmgenet_hide_tsb(skb);
2219 	skb_tx_timestamp(skb);
2220 
2221 	/* Decrement total BD count and advance our write pointer */
2222 	ring->free_bds -= nr_frags + 1;
2223 	ring->prod_index += nr_frags + 1;
2224 	ring->prod_index &= DMA_P_INDEX_MASK;
2225 
2226 	netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
2227 
2228 	if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
2229 		netif_tx_stop_queue(txq);
2230 
2231 	if (!netdev_xmit_more() || netif_xmit_stopped(txq))
2232 		/* Packets are ready, update producer index */
2233 		bcmgenet_tdma_ring_writel(priv, ring->index,
2234 					  ring->prod_index, TDMA_PROD_INDEX);
2235 out:
2236 	spin_unlock(&ring->lock);
2237 
2238 	return ret;
2239 
2240 out_unmap_frags:
2241 	/* Back up for failed control block mapping */
2242 	bcmgenet_put_txcb(priv, ring);
2243 
2244 	/* Unmap successfully mapped control blocks */
2245 	while (i-- > 0) {
2246 		tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
2247 		bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
2248 	}
2249 
2250 	dev_kfree_skb(skb);
2251 	goto out;
2252 }
2253 
bcmgenet_rx_refill(struct bcmgenet_priv * priv,struct enet_cb * cb)2254 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
2255 					  struct enet_cb *cb)
2256 {
2257 	struct device *kdev = &priv->pdev->dev;
2258 	struct sk_buff *skb;
2259 	struct sk_buff *rx_skb;
2260 	dma_addr_t mapping;
2261 
2262 	/* Allocate a new Rx skb */
2263 	skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT,
2264 				 GFP_ATOMIC | __GFP_NOWARN);
2265 	if (!skb) {
2266 		priv->mib.alloc_rx_buff_failed++;
2267 		netif_err(priv, rx_err, priv->dev,
2268 			  "%s: Rx skb allocation failed\n", __func__);
2269 		return NULL;
2270 	}
2271 
2272 	/* DMA-map the new Rx skb */
2273 	mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
2274 				 DMA_FROM_DEVICE);
2275 	if (dma_mapping_error(kdev, mapping)) {
2276 		priv->mib.rx_dma_failed++;
2277 		dev_kfree_skb_any(skb);
2278 		netif_err(priv, rx_err, priv->dev,
2279 			  "%s: Rx skb DMA mapping failed\n", __func__);
2280 		return NULL;
2281 	}
2282 
2283 	/* Grab the current Rx skb from the ring and DMA-unmap it */
2284 	rx_skb = bcmgenet_free_rx_cb(kdev, cb);
2285 
2286 	/* Put the new Rx skb on the ring */
2287 	cb->skb = skb;
2288 	dma_unmap_addr_set(cb, dma_addr, mapping);
2289 	dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
2290 	dmadesc_set_addr(priv, cb->bd_addr, mapping);
2291 
2292 	/* Return the current Rx skb to caller */
2293 	return rx_skb;
2294 }
2295 
2296 /* bcmgenet_desc_rx - descriptor based rx process.
2297  * this could be called from bottom half, or from NAPI polling method.
2298  */
bcmgenet_desc_rx(struct bcmgenet_rx_ring * ring,unsigned int budget)2299 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
2300 				     unsigned int budget)
2301 {
2302 	struct bcmgenet_rx_stats64 *stats = &ring->stats64;
2303 	struct bcmgenet_priv *priv = ring->priv;
2304 	struct net_device *dev = priv->dev;
2305 	struct enet_cb *cb;
2306 	struct sk_buff *skb;
2307 	u32 dma_length_status;
2308 	unsigned long dma_flag;
2309 	int len;
2310 	unsigned int rxpktprocessed = 0, rxpkttoprocess;
2311 	unsigned int bytes_processed = 0;
2312 	unsigned int p_index, mask;
2313 	unsigned int discards;
2314 
2315 	/* Clear status before servicing to reduce spurious interrupts */
2316 	mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
2317 	bcmgenet_intrl2_1_writel(priv, mask, INTRL2_CPU_CLEAR);
2318 
2319 	p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
2320 
2321 	discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
2322 		   DMA_P_INDEX_DISCARD_CNT_MASK;
2323 	if (discards > ring->old_discards) {
2324 		discards = discards - ring->old_discards;
2325 		BCMGENET_STATS64_ADD(stats, missed, discards);
2326 		ring->old_discards += discards;
2327 
2328 		/* Clear HW register when we reach 75% of maximum 0xFFFF */
2329 		if (ring->old_discards >= 0xC000) {
2330 			ring->old_discards = 0;
2331 			bcmgenet_rdma_ring_writel(priv, ring->index, 0,
2332 						  RDMA_PROD_INDEX);
2333 		}
2334 	}
2335 
2336 	p_index &= DMA_P_INDEX_MASK;
2337 	rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
2338 
2339 	netif_dbg(priv, rx_status, dev,
2340 		  "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
2341 
2342 	while ((rxpktprocessed < rxpkttoprocess) &&
2343 	       (rxpktprocessed < budget)) {
2344 		struct status_64 *status;
2345 		__be16 rx_csum;
2346 
2347 		cb = &priv->rx_cbs[ring->read_ptr];
2348 		skb = bcmgenet_rx_refill(priv, cb);
2349 
2350 		if (unlikely(!skb)) {
2351 			BCMGENET_STATS64_INC(stats, dropped);
2352 			goto next;
2353 		}
2354 
2355 		status = (struct status_64 *)skb->data;
2356 		dma_length_status = status->length_status;
2357 		if (dev->features & NETIF_F_RXCSUM) {
2358 			rx_csum = (__force __be16)(status->rx_csum & 0xffff);
2359 			if (rx_csum) {
2360 				skb->csum = (__force __wsum)ntohs(rx_csum);
2361 				skb->ip_summed = CHECKSUM_COMPLETE;
2362 			}
2363 		}
2364 
2365 		/* DMA flags and length are still valid no matter how
2366 		 * we got the Receive Status Vector (64B RSB or register)
2367 		 */
2368 		dma_flag = dma_length_status & 0xffff;
2369 		len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
2370 
2371 		netif_dbg(priv, rx_status, dev,
2372 			  "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
2373 			  __func__, p_index, ring->c_index,
2374 			  ring->read_ptr, dma_length_status);
2375 
2376 		if (unlikely(len > RX_BUF_LENGTH)) {
2377 			netif_err(priv, rx_status, dev, "oversized packet\n");
2378 			BCMGENET_STATS64_INC(stats, length_errors);
2379 			dev_kfree_skb_any(skb);
2380 			goto next;
2381 		}
2382 
2383 		if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
2384 			netif_err(priv, rx_status, dev,
2385 				  "dropping fragmented packet!\n");
2386 			BCMGENET_STATS64_INC(stats, fragmented_errors);
2387 			dev_kfree_skb_any(skb);
2388 			goto next;
2389 		}
2390 
2391 		/* report errors */
2392 		if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
2393 						DMA_RX_OV |
2394 						DMA_RX_NO |
2395 						DMA_RX_LG |
2396 						DMA_RX_RXER))) {
2397 			netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
2398 				  (unsigned int)dma_flag);
2399 			u64_stats_update_begin(&stats->syncp);
2400 			if (dma_flag & DMA_RX_CRC_ERROR)
2401 				u64_stats_inc(&stats->crc_errors);
2402 			if (dma_flag & DMA_RX_OV)
2403 				u64_stats_inc(&stats->over_errors);
2404 			if (dma_flag & DMA_RX_NO)
2405 				u64_stats_inc(&stats->frame_errors);
2406 			if (dma_flag & DMA_RX_LG)
2407 				u64_stats_inc(&stats->length_errors);
2408 			if ((dma_flag & (DMA_RX_CRC_ERROR |
2409 						DMA_RX_OV |
2410 						DMA_RX_NO |
2411 						DMA_RX_LG |
2412 						DMA_RX_RXER)) == DMA_RX_RXER)
2413 				u64_stats_inc(&stats->errors);
2414 			u64_stats_update_end(&stats->syncp);
2415 			dev_kfree_skb_any(skb);
2416 			goto next;
2417 		} /* error packet */
2418 
2419 		skb_put(skb, len);
2420 
2421 		/* remove RSB and hardware 2bytes added for IP alignment */
2422 		skb_pull(skb, 66);
2423 		len -= 66;
2424 
2425 		if (priv->crc_fwd_en) {
2426 			skb_trim(skb, len - ETH_FCS_LEN);
2427 			len -= ETH_FCS_LEN;
2428 		}
2429 
2430 		bytes_processed += len;
2431 
2432 		/*Finish setting up the received SKB and send it to the kernel*/
2433 		skb->protocol = eth_type_trans(skb, priv->dev);
2434 
2435 		u64_stats_update_begin(&stats->syncp);
2436 		u64_stats_inc(&stats->packets);
2437 		u64_stats_add(&stats->bytes, len);
2438 		if (dma_flag & DMA_RX_MULT)
2439 			u64_stats_inc(&stats->multicast);
2440 		else if (dma_flag & DMA_RX_BRDCAST)
2441 			u64_stats_inc(&stats->broadcast);
2442 		u64_stats_update_end(&stats->syncp);
2443 
2444 		/* Notify kernel */
2445 		napi_gro_receive(&ring->napi, skb);
2446 		netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
2447 
2448 next:
2449 		rxpktprocessed++;
2450 		if (likely(ring->read_ptr < ring->end_ptr))
2451 			ring->read_ptr++;
2452 		else
2453 			ring->read_ptr = ring->cb_ptr;
2454 
2455 		ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
2456 		bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
2457 	}
2458 
2459 	ring->dim.bytes = bytes_processed;
2460 	ring->dim.packets = rxpktprocessed;
2461 
2462 	return rxpktprocessed;
2463 }
2464 
2465 /* Rx NAPI polling method */
bcmgenet_rx_poll(struct napi_struct * napi,int budget)2466 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
2467 {
2468 	struct bcmgenet_rx_ring *ring = container_of(napi,
2469 			struct bcmgenet_rx_ring, napi);
2470 	struct dim_sample dim_sample = {};
2471 	unsigned int work_done;
2472 
2473 	work_done = bcmgenet_desc_rx(ring, budget);
2474 
2475 	if (work_done < budget) {
2476 		napi_complete_done(napi, work_done);
2477 		bcmgenet_rx_ring_int_enable(ring);
2478 	}
2479 
2480 	if (ring->dim.use_dim) {
2481 		dim_update_sample(ring->dim.event_ctr, ring->dim.packets,
2482 				  ring->dim.bytes, &dim_sample);
2483 		net_dim(&ring->dim.dim, &dim_sample);
2484 	}
2485 
2486 	return work_done;
2487 }
2488 
bcmgenet_dim_work(struct work_struct * work)2489 static void bcmgenet_dim_work(struct work_struct *work)
2490 {
2491 	struct dim *dim = container_of(work, struct dim, work);
2492 	struct bcmgenet_net_dim *ndim =
2493 			container_of(dim, struct bcmgenet_net_dim, dim);
2494 	struct bcmgenet_rx_ring *ring =
2495 			container_of(ndim, struct bcmgenet_rx_ring, dim);
2496 	struct dim_cq_moder cur_profile =
2497 			net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
2498 
2499 	bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts);
2500 	dim->state = DIM_START_MEASURE;
2501 }
2502 
2503 /* Assign skb to RX DMA descriptor. */
bcmgenet_alloc_rx_buffers(struct bcmgenet_priv * priv,struct bcmgenet_rx_ring * ring)2504 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
2505 				     struct bcmgenet_rx_ring *ring)
2506 {
2507 	struct enet_cb *cb;
2508 	struct sk_buff *skb;
2509 	int i;
2510 
2511 	netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2512 
2513 	/* loop here for each buffer needing assign */
2514 	for (i = 0; i < ring->size; i++) {
2515 		cb = ring->cbs + i;
2516 		skb = bcmgenet_rx_refill(priv, cb);
2517 		if (skb)
2518 			dev_consume_skb_any(skb);
2519 		if (!cb->skb)
2520 			return -ENOMEM;
2521 	}
2522 
2523 	return 0;
2524 }
2525 
bcmgenet_free_rx_buffers(struct bcmgenet_priv * priv)2526 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
2527 {
2528 	struct sk_buff *skb;
2529 	struct enet_cb *cb;
2530 	int i;
2531 
2532 	for (i = 0; i < priv->num_rx_bds; i++) {
2533 		cb = &priv->rx_cbs[i];
2534 
2535 		skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
2536 		if (skb)
2537 			dev_consume_skb_any(skb);
2538 	}
2539 }
2540 
umac_enable_set(struct bcmgenet_priv * priv,u32 mask,bool enable)2541 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
2542 {
2543 	u32 reg;
2544 
2545 	spin_lock_bh(&priv->reg_lock);
2546 	reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2547 	if (reg & CMD_SW_RESET) {
2548 		spin_unlock_bh(&priv->reg_lock);
2549 		return;
2550 	}
2551 	if (enable)
2552 		reg |= mask;
2553 	else
2554 		reg &= ~mask;
2555 	bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2556 	spin_unlock_bh(&priv->reg_lock);
2557 
2558 	/* UniMAC stops on a packet boundary, wait for a full-size packet
2559 	 * to be processed
2560 	 */
2561 	if (enable == 0)
2562 		usleep_range(1000, 2000);
2563 }
2564 
reset_umac(struct bcmgenet_priv * priv)2565 static void reset_umac(struct bcmgenet_priv *priv)
2566 {
2567 	/* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
2568 	bcmgenet_rbuf_ctrl_set(priv, 0);
2569 	udelay(10);
2570 
2571 	/* issue soft reset and disable MAC while updating its registers */
2572 	spin_lock_bh(&priv->reg_lock);
2573 	bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
2574 	udelay(2);
2575 	spin_unlock_bh(&priv->reg_lock);
2576 }
2577 
bcmgenet_intr_disable(struct bcmgenet_priv * priv)2578 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
2579 {
2580 	/* Mask all interrupts.*/
2581 	bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2582 	bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2583 	bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2584 	bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2585 }
2586 
bcmgenet_link_intr_enable(struct bcmgenet_priv * priv)2587 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
2588 {
2589 	u32 int0_enable = 0;
2590 
2591 	/* Monitor cable plug/unplugged event for internal PHY, external PHY
2592 	 * and MoCA PHY
2593 	 */
2594 	if (priv->internal_phy) {
2595 		int0_enable |= UMAC_IRQ_LINK_EVENT;
2596 		if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
2597 			int0_enable |= UMAC_IRQ_PHY_DET_R;
2598 	} else if (priv->ext_phy) {
2599 		int0_enable |= UMAC_IRQ_LINK_EVENT;
2600 	} else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2601 		if (bcmgenet_has_moca_link_det(priv))
2602 			int0_enable |= UMAC_IRQ_LINK_EVENT;
2603 	}
2604 	bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2605 }
2606 
init_umac(struct bcmgenet_priv * priv)2607 static void init_umac(struct bcmgenet_priv *priv)
2608 {
2609 	struct device *kdev = &priv->pdev->dev;
2610 	u32 reg;
2611 	u32 int0_enable = 0;
2612 
2613 	dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
2614 
2615 	reset_umac(priv);
2616 
2617 	/* clear tx/rx counter */
2618 	bcmgenet_umac_writel(priv,
2619 			     MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
2620 			     UMAC_MIB_CTRL);
2621 	bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
2622 
2623 	bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2624 
2625 	/* init tx registers, enable TSB */
2626 	reg = bcmgenet_tbuf_ctrl_get(priv);
2627 	reg |= TBUF_64B_EN;
2628 	bcmgenet_tbuf_ctrl_set(priv, reg);
2629 
2630 	/* init rx registers, enable ip header optimization and RSB */
2631 	reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
2632 	reg |= RBUF_ALIGN_2B | RBUF_64B_EN;
2633 	bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2634 
2635 	/* enable rx checksumming */
2636 	reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
2637 	reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS;
2638 	/* If UniMAC forwards CRC, we need to skip over it to get
2639 	 * a valid CHK bit to be set in the per-packet status word
2640 	 */
2641 	if (priv->crc_fwd_en)
2642 		reg |= RBUF_SKIP_FCS;
2643 	else
2644 		reg &= ~RBUF_SKIP_FCS;
2645 	bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL);
2646 
2647 	if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2648 		bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2649 
2650 	bcmgenet_intr_disable(priv);
2651 
2652 	/* Configure backpressure vectors for MoCA */
2653 	if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2654 		reg = bcmgenet_bp_mc_get(priv);
2655 		reg |= BIT(priv->hw_params->bp_in_en_shift);
2656 
2657 		/* bp_mask: back pressure mask */
2658 		if (netif_is_multiqueue(priv->dev))
2659 			reg |= priv->hw_params->bp_in_mask;
2660 		else
2661 			reg &= ~priv->hw_params->bp_in_mask;
2662 		bcmgenet_bp_mc_set(priv, reg);
2663 	}
2664 
2665 	/* Enable MDIO interrupts on GENET v3+ */
2666 	if (bcmgenet_has_mdio_intr(priv))
2667 		int0_enable |= UMAC_IRQ_MDIO_EVENT;
2668 
2669 	bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2670 
2671 	dev_dbg(kdev, "done init umac\n");
2672 }
2673 
bcmgenet_init_dim(struct bcmgenet_rx_ring * ring,void (* cb)(struct work_struct * work))2674 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring,
2675 			      void (*cb)(struct work_struct *work))
2676 {
2677 	struct bcmgenet_net_dim *dim = &ring->dim;
2678 
2679 	INIT_WORK(&dim->dim.work, cb);
2680 	dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2681 	dim->event_ctr = 0;
2682 	dim->packets = 0;
2683 	dim->bytes = 0;
2684 }
2685 
bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring * ring)2686 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring)
2687 {
2688 	struct bcmgenet_net_dim *dim = &ring->dim;
2689 	struct dim_cq_moder moder;
2690 	u32 usecs, pkts;
2691 
2692 	usecs = ring->rx_coalesce_usecs;
2693 	pkts = ring->rx_max_coalesced_frames;
2694 
2695 	/* If DIM was enabled, re-apply default parameters */
2696 	if (dim->use_dim) {
2697 		moder = net_dim_get_def_rx_moderation(dim->dim.mode);
2698 		usecs = moder.usec;
2699 		pkts = moder.pkts;
2700 	}
2701 
2702 	bcmgenet_set_rx_coalesce(ring, usecs, pkts);
2703 }
2704 
2705 /* Initialize a Tx ring along with corresponding hardware registers */
bcmgenet_init_tx_ring(struct bcmgenet_priv * priv,unsigned int index,unsigned int size,unsigned int start_ptr,unsigned int end_ptr)2706 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2707 				  unsigned int index, unsigned int size,
2708 				  unsigned int start_ptr, unsigned int end_ptr)
2709 {
2710 	struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2711 	u32 words_per_bd = WORDS_PER_BD(priv);
2712 	u32 flow_period_val = 0;
2713 
2714 	spin_lock_init(&ring->lock);
2715 	ring->priv = priv;
2716 	ring->index = index;
2717 	ring->cbs = priv->tx_cbs + start_ptr;
2718 	ring->size = size;
2719 	ring->clean_ptr = start_ptr;
2720 	ring->c_index = 0;
2721 	ring->free_bds = size;
2722 	ring->write_ptr = start_ptr;
2723 	ring->cb_ptr = start_ptr;
2724 	ring->end_ptr = end_ptr - 1;
2725 	ring->prod_index = 0;
2726 
2727 	/* Set flow period for ring != 0 */
2728 	if (index)
2729 		flow_period_val = ENET_MAX_MTU_SIZE << 16;
2730 
2731 	bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2732 	bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2733 	bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2734 	/* Disable rate control for now */
2735 	bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2736 				  TDMA_FLOW_PERIOD);
2737 	bcmgenet_tdma_ring_writel(priv, index,
2738 				  ((size << DMA_RING_SIZE_SHIFT) |
2739 				   RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2740 
2741 	/* Set start and end address, read and write pointers */
2742 	bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2743 				  DMA_START_ADDR);
2744 	bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2745 				  TDMA_READ_PTR);
2746 	bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2747 				  TDMA_WRITE_PTR);
2748 	bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2749 				  DMA_END_ADDR);
2750 
2751 	/* Initialize Tx NAPI */
2752 	netif_napi_add_tx(priv->dev, &ring->napi, bcmgenet_tx_poll);
2753 }
2754 
2755 /* Initialize a RDMA ring */
bcmgenet_init_rx_ring(struct bcmgenet_priv * priv,unsigned int index,unsigned int size,unsigned int start_ptr,unsigned int end_ptr)2756 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2757 				 unsigned int index, unsigned int size,
2758 				 unsigned int start_ptr, unsigned int end_ptr)
2759 {
2760 	struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2761 	u32 words_per_bd = WORDS_PER_BD(priv);
2762 	int ret;
2763 
2764 	ring->priv = priv;
2765 	ring->index = index;
2766 	ring->cbs = priv->rx_cbs + start_ptr;
2767 	ring->size = size;
2768 	ring->c_index = 0;
2769 	ring->read_ptr = start_ptr;
2770 	ring->cb_ptr = start_ptr;
2771 	ring->end_ptr = end_ptr - 1;
2772 
2773 	ret = bcmgenet_alloc_rx_buffers(priv, ring);
2774 	if (ret)
2775 		return ret;
2776 
2777 	bcmgenet_init_dim(ring, bcmgenet_dim_work);
2778 	bcmgenet_init_rx_coalesce(ring);
2779 
2780 	/* Initialize Rx NAPI */
2781 	netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll);
2782 
2783 	bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2784 	bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2785 	bcmgenet_rdma_ring_writel(priv, index,
2786 				  ((size << DMA_RING_SIZE_SHIFT) |
2787 				   RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2788 	bcmgenet_rdma_ring_writel(priv, index,
2789 				  (DMA_FC_THRESH_LO <<
2790 				   DMA_XOFF_THRESHOLD_SHIFT) |
2791 				   DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2792 
2793 	/* Set start and end address, read and write pointers */
2794 	bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2795 				  DMA_START_ADDR);
2796 	bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2797 				  RDMA_READ_PTR);
2798 	bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2799 				  RDMA_WRITE_PTR);
2800 	bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2801 				  DMA_END_ADDR);
2802 
2803 	return ret;
2804 }
2805 
bcmgenet_enable_tx_napi(struct bcmgenet_priv * priv)2806 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2807 {
2808 	unsigned int i;
2809 	struct bcmgenet_tx_ring *ring;
2810 
2811 	for (i = 0; i <= priv->hw_params->tx_queues; ++i) {
2812 		ring = &priv->tx_rings[i];
2813 		napi_enable(&ring->napi);
2814 		bcmgenet_tx_ring_int_enable(ring);
2815 	}
2816 }
2817 
bcmgenet_disable_tx_napi(struct bcmgenet_priv * priv)2818 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2819 {
2820 	unsigned int i;
2821 	struct bcmgenet_tx_ring *ring;
2822 
2823 	for (i = 0; i <= priv->hw_params->tx_queues; ++i) {
2824 		ring = &priv->tx_rings[i];
2825 		napi_disable(&ring->napi);
2826 	}
2827 }
2828 
bcmgenet_fini_tx_napi(struct bcmgenet_priv * priv)2829 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2830 {
2831 	unsigned int i;
2832 	struct bcmgenet_tx_ring *ring;
2833 
2834 	for (i = 0; i <= priv->hw_params->tx_queues; ++i) {
2835 		ring = &priv->tx_rings[i];
2836 		netif_napi_del(&ring->napi);
2837 	}
2838 }
2839 
bcmgenet_tdma_disable(struct bcmgenet_priv * priv)2840 static int bcmgenet_tdma_disable(struct bcmgenet_priv *priv)
2841 {
2842 	int timeout = 0;
2843 	u32 reg, mask;
2844 
2845 	reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2846 	mask = (1 << (priv->hw_params->tx_queues + 1)) - 1;
2847 	mask = (mask << DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2848 	reg &= ~mask;
2849 	bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2850 
2851 	/* Check DMA status register to confirm DMA is disabled */
2852 	while (timeout++ < DMA_TIMEOUT_VAL) {
2853 		reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2854 		if ((reg & mask) == mask)
2855 			return 0;
2856 
2857 		udelay(1);
2858 	}
2859 
2860 	return -ETIMEDOUT;
2861 }
2862 
bcmgenet_rdma_disable(struct bcmgenet_priv * priv)2863 static int bcmgenet_rdma_disable(struct bcmgenet_priv *priv)
2864 {
2865 	int timeout = 0;
2866 	u32 reg, mask;
2867 
2868 	reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2869 	mask = (1 << (priv->hw_params->rx_queues + 1)) - 1;
2870 	mask = (mask << DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2871 	reg &= ~mask;
2872 	bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2873 
2874 	/* Check DMA status register to confirm DMA is disabled */
2875 	while (timeout++ < DMA_TIMEOUT_VAL) {
2876 		reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2877 		if ((reg & mask) == mask)
2878 			return 0;
2879 
2880 		udelay(1);
2881 	}
2882 
2883 	return -ETIMEDOUT;
2884 }
2885 
2886 /* Initialize Tx queues
2887  *
2888  * Queues 1-4 are priority-based, each one has 32 descriptors,
2889  * with queue 1 being the highest priority queue.
2890  *
2891  * Queue 0 is the default Tx queue with
2892  * GENET_Q0_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2893  *
2894  * The transmit control block pool is then partitioned as follows:
2895  * - Tx queue 0 uses tx_cbs[0..127]
2896  * - Tx queue 1 uses tx_cbs[128..159]
2897  * - Tx queue 2 uses tx_cbs[160..191]
2898  * - Tx queue 3 uses tx_cbs[192..223]
2899  * - Tx queue 4 uses tx_cbs[224..255]
2900  */
bcmgenet_init_tx_queues(struct net_device * dev)2901 static void bcmgenet_init_tx_queues(struct net_device *dev)
2902 {
2903 	struct bcmgenet_priv *priv = netdev_priv(dev);
2904 	unsigned int start = 0, end = GENET_Q0_TX_BD_CNT;
2905 	u32 i, ring_mask, dma_priority[3] = {0, 0, 0};
2906 
2907 	/* Enable strict priority arbiter mode */
2908 	bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2909 
2910 	/* Initialize Tx priority queues */
2911 	for (i = 0; i <= priv->hw_params->tx_queues; i++) {
2912 		bcmgenet_init_tx_ring(priv, i, end - start, start, end);
2913 		start = end;
2914 		end += priv->hw_params->tx_bds_per_q;
2915 		dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2916 			(i ? GENET_Q1_PRIORITY : GENET_Q0_PRIORITY)
2917 			<< DMA_PRIO_REG_SHIFT(i);
2918 	}
2919 
2920 	/* Set Tx queue priorities */
2921 	bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2922 	bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2923 	bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2924 
2925 	/* Configure Tx queues as descriptor rings */
2926 	ring_mask = (1 << (priv->hw_params->tx_queues + 1)) - 1;
2927 	bcmgenet_tdma_writel(priv, ring_mask, DMA_RING_CFG);
2928 
2929 	/* Enable Tx rings */
2930 	ring_mask <<= DMA_RING_BUF_EN_SHIFT;
2931 	bcmgenet_tdma_writel(priv, ring_mask, DMA_CTRL);
2932 }
2933 
bcmgenet_enable_rx_napi(struct bcmgenet_priv * priv)2934 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2935 {
2936 	unsigned int i;
2937 	struct bcmgenet_rx_ring *ring;
2938 
2939 	for (i = 0; i <= priv->hw_params->rx_queues; ++i) {
2940 		ring = &priv->rx_rings[i];
2941 		napi_enable(&ring->napi);
2942 		bcmgenet_rx_ring_int_enable(ring);
2943 	}
2944 }
2945 
bcmgenet_disable_rx_napi(struct bcmgenet_priv * priv)2946 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2947 {
2948 	unsigned int i;
2949 	struct bcmgenet_rx_ring *ring;
2950 
2951 	for (i = 0; i <= priv->hw_params->rx_queues; ++i) {
2952 		ring = &priv->rx_rings[i];
2953 		napi_disable(&ring->napi);
2954 		cancel_work_sync(&ring->dim.dim.work);
2955 	}
2956 }
2957 
bcmgenet_fini_rx_napi(struct bcmgenet_priv * priv)2958 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2959 {
2960 	unsigned int i;
2961 	struct bcmgenet_rx_ring *ring;
2962 
2963 	for (i = 0; i <= priv->hw_params->rx_queues; ++i) {
2964 		ring = &priv->rx_rings[i];
2965 		netif_napi_del(&ring->napi);
2966 	}
2967 }
2968 
2969 /* Initialize Rx queues
2970  *
2971  * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2972  * used to direct traffic to these queues.
2973  *
2974  * Queue 0 is also the default Rx queue with GENET_Q0_RX_BD_CNT descriptors.
2975  */
bcmgenet_init_rx_queues(struct net_device * dev)2976 static int bcmgenet_init_rx_queues(struct net_device *dev)
2977 {
2978 	struct bcmgenet_priv *priv = netdev_priv(dev);
2979 	unsigned int start = 0, end = GENET_Q0_RX_BD_CNT;
2980 	u32 i, ring_mask;
2981 	int ret;
2982 
2983 	/* Initialize Rx priority queues */
2984 	for (i = 0; i <= priv->hw_params->rx_queues; i++) {
2985 		ret = bcmgenet_init_rx_ring(priv, i, end - start, start, end);
2986 		if (ret)
2987 			return ret;
2988 
2989 		start = end;
2990 		end += priv->hw_params->rx_bds_per_q;
2991 	}
2992 
2993 	/* Configure Rx queues as descriptor rings */
2994 	ring_mask = (1 << (priv->hw_params->rx_queues + 1)) - 1;
2995 	bcmgenet_rdma_writel(priv, ring_mask, DMA_RING_CFG);
2996 
2997 	/* Enable Rx rings */
2998 	ring_mask <<= DMA_RING_BUF_EN_SHIFT;
2999 	bcmgenet_rdma_writel(priv, ring_mask, DMA_CTRL);
3000 
3001 	return 0;
3002 }
3003 
bcmgenet_dma_teardown(struct bcmgenet_priv * priv)3004 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
3005 {
3006 	int ret = 0;
3007 
3008 	/* Disable TDMA to stop add more frames in TX DMA */
3009 	if (-ETIMEDOUT == bcmgenet_tdma_disable(priv)) {
3010 		netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
3011 		ret = -ETIMEDOUT;
3012 	}
3013 
3014 	/* Wait 10ms for packet drain in both tx and rx dma */
3015 	usleep_range(10000, 20000);
3016 
3017 	/* Disable RDMA */
3018 	if (-ETIMEDOUT == bcmgenet_rdma_disable(priv)) {
3019 		netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
3020 		ret = -ETIMEDOUT;
3021 	}
3022 
3023 	return ret;
3024 }
3025 
bcmgenet_fini_dma(struct bcmgenet_priv * priv)3026 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
3027 {
3028 	struct netdev_queue *txq;
3029 	int i;
3030 
3031 	bcmgenet_fini_rx_napi(priv);
3032 	bcmgenet_fini_tx_napi(priv);
3033 
3034 	for (i = 0; i <= priv->hw_params->tx_queues; i++) {
3035 		txq = netdev_get_tx_queue(priv->dev, i);
3036 		netdev_tx_reset_queue(txq);
3037 	}
3038 
3039 	bcmgenet_free_rx_buffers(priv);
3040 	kfree(priv->rx_cbs);
3041 	kfree(priv->tx_cbs);
3042 }
3043 
3044 /* init_edma: Initialize DMA control register */
bcmgenet_init_dma(struct bcmgenet_priv * priv,bool flush_rx)3045 static int bcmgenet_init_dma(struct bcmgenet_priv *priv, bool flush_rx)
3046 {
3047 	struct enet_cb *cb;
3048 	unsigned int i;
3049 	int ret;
3050 	u32 reg;
3051 
3052 	netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
3053 
3054 	/* Disable TX DMA */
3055 	ret = bcmgenet_tdma_disable(priv);
3056 	if (ret) {
3057 		netdev_err(priv->dev, "failed to halt Tx DMA\n");
3058 		return ret;
3059 	}
3060 
3061 	/* Disable RX DMA */
3062 	ret = bcmgenet_rdma_disable(priv);
3063 	if (ret) {
3064 		netdev_err(priv->dev, "failed to halt Rx DMA\n");
3065 		return ret;
3066 	}
3067 
3068 	/* Flush TX queues */
3069 	bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
3070 	udelay(10);
3071 	bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
3072 
3073 	if (flush_rx) {
3074 		reg = bcmgenet_rbuf_ctrl_get(priv);
3075 		bcmgenet_rbuf_ctrl_set(priv, reg | BIT(0));
3076 		udelay(10);
3077 		bcmgenet_rbuf_ctrl_set(priv, reg);
3078 		udelay(10);
3079 	}
3080 
3081 	/* Initialize common Rx ring structures */
3082 	priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
3083 	priv->num_rx_bds = TOTAL_DESC;
3084 	priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
3085 			       GFP_KERNEL);
3086 	if (!priv->rx_cbs)
3087 		return -ENOMEM;
3088 
3089 	for (i = 0; i < priv->num_rx_bds; i++) {
3090 		cb = priv->rx_cbs + i;
3091 		cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
3092 	}
3093 
3094 	/* Initialize common TX ring structures */
3095 	priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
3096 	priv->num_tx_bds = TOTAL_DESC;
3097 	priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
3098 			       GFP_KERNEL);
3099 	if (!priv->tx_cbs) {
3100 		kfree(priv->rx_cbs);
3101 		return -ENOMEM;
3102 	}
3103 
3104 	for (i = 0; i < priv->num_tx_bds; i++) {
3105 		cb = priv->tx_cbs + i;
3106 		cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
3107 	}
3108 
3109 	/* Init rDma */
3110 	bcmgenet_rdma_writel(priv, priv->dma_max_burst_length,
3111 			     DMA_SCB_BURST_SIZE);
3112 
3113 	/* Initialize Rx queues */
3114 	ret = bcmgenet_init_rx_queues(priv->dev);
3115 	if (ret) {
3116 		netdev_err(priv->dev, "failed to initialize Rx queues\n");
3117 		bcmgenet_free_rx_buffers(priv);
3118 		kfree(priv->rx_cbs);
3119 		kfree(priv->tx_cbs);
3120 		return ret;
3121 	}
3122 
3123 	/* Init tDma */
3124 	bcmgenet_tdma_writel(priv, priv->dma_max_burst_length,
3125 			     DMA_SCB_BURST_SIZE);
3126 
3127 	/* Initialize Tx queues */
3128 	bcmgenet_init_tx_queues(priv->dev);
3129 
3130 	/* Enable RX/TX DMA */
3131 	reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3132 	reg |= DMA_EN;
3133 	bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3134 
3135 	reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3136 	reg |= DMA_EN;
3137 	bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3138 
3139 	return 0;
3140 }
3141 
3142 /* Interrupt bottom half */
bcmgenet_irq_task(struct work_struct * work)3143 static void bcmgenet_irq_task(struct work_struct *work)
3144 {
3145 	unsigned int status;
3146 	struct bcmgenet_priv *priv = container_of(
3147 			work, struct bcmgenet_priv, bcmgenet_irq_work);
3148 
3149 	netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
3150 
3151 	spin_lock_irq(&priv->lock);
3152 	status = priv->irq0_stat;
3153 	priv->irq0_stat = 0;
3154 	spin_unlock_irq(&priv->lock);
3155 
3156 	if (status & UMAC_IRQ_PHY_DET_R &&
3157 	    priv->dev->phydev->autoneg != AUTONEG_ENABLE) {
3158 		phy_init_hw(priv->dev->phydev);
3159 		genphy_config_aneg(priv->dev->phydev);
3160 	}
3161 
3162 	/* Link UP/DOWN event */
3163 	if (status & UMAC_IRQ_LINK_EVENT)
3164 		phy_mac_interrupt(priv->dev->phydev);
3165 
3166 }
3167 
3168 /* bcmgenet_isr1: handle Rx and Tx queues */
bcmgenet_isr1(int irq,void * dev_id)3169 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
3170 {
3171 	struct bcmgenet_priv *priv = dev_id;
3172 	struct bcmgenet_rx_ring *rx_ring;
3173 	struct bcmgenet_tx_ring *tx_ring;
3174 	unsigned int index, status;
3175 
3176 	/* Read irq status */
3177 	status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
3178 		~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3179 
3180 	/* clear interrupts */
3181 	bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
3182 
3183 	netif_dbg(priv, intr, priv->dev,
3184 		  "%s: IRQ=0x%x\n", __func__, status);
3185 
3186 	/* Check Rx priority queue interrupts */
3187 	for (index = 0; index <= priv->hw_params->rx_queues; index++) {
3188 		if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
3189 			continue;
3190 
3191 		rx_ring = &priv->rx_rings[index];
3192 		rx_ring->dim.event_ctr++;
3193 
3194 		if (likely(napi_schedule_prep(&rx_ring->napi))) {
3195 			bcmgenet_rx_ring_int_disable(rx_ring);
3196 			__napi_schedule_irqoff(&rx_ring->napi);
3197 		}
3198 	}
3199 
3200 	/* Check Tx priority queue interrupts */
3201 	for (index = 0; index <= priv->hw_params->tx_queues; index++) {
3202 		if (!(status & BIT(index)))
3203 			continue;
3204 
3205 		tx_ring = &priv->tx_rings[index];
3206 
3207 		if (likely(napi_schedule_prep(&tx_ring->napi))) {
3208 			bcmgenet_tx_ring_int_disable(tx_ring);
3209 			__napi_schedule_irqoff(&tx_ring->napi);
3210 		}
3211 	}
3212 
3213 	return IRQ_HANDLED;
3214 }
3215 
3216 /* bcmgenet_isr0: handle other stuff */
bcmgenet_isr0(int irq,void * dev_id)3217 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
3218 {
3219 	struct bcmgenet_priv *priv = dev_id;
3220 	unsigned int status;
3221 	unsigned long flags;
3222 
3223 	/* Read irq status */
3224 	status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
3225 		~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3226 
3227 	/* clear interrupts */
3228 	bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
3229 
3230 	netif_dbg(priv, intr, priv->dev,
3231 		  "IRQ=0x%x\n", status);
3232 
3233 	if (bcmgenet_has_mdio_intr(priv) && status & UMAC_IRQ_MDIO_EVENT)
3234 		wake_up(&priv->wq);
3235 
3236 	/* all other interested interrupts handled in bottom half */
3237 	status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R);
3238 	if (status) {
3239 		/* Save irq status for bottom-half processing. */
3240 		spin_lock_irqsave(&priv->lock, flags);
3241 		priv->irq0_stat |= status;
3242 		spin_unlock_irqrestore(&priv->lock, flags);
3243 
3244 		schedule_work(&priv->bcmgenet_irq_work);
3245 	}
3246 
3247 	return IRQ_HANDLED;
3248 }
3249 
bcmgenet_wol_isr(int irq,void * dev_id)3250 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
3251 {
3252 	/* Acknowledge the interrupt */
3253 	return IRQ_HANDLED;
3254 }
3255 
bcmgenet_umac_reset(struct bcmgenet_priv * priv)3256 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
3257 {
3258 	u32 reg;
3259 
3260 	reg = bcmgenet_rbuf_ctrl_get(priv);
3261 	reg |= BIT(1);
3262 	bcmgenet_rbuf_ctrl_set(priv, reg);
3263 	udelay(10);
3264 
3265 	reg &= ~BIT(1);
3266 	bcmgenet_rbuf_ctrl_set(priv, reg);
3267 	udelay(10);
3268 }
3269 
bcmgenet_set_hw_addr(struct bcmgenet_priv * priv,const unsigned char * addr)3270 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
3271 				 const unsigned char *addr)
3272 {
3273 	bcmgenet_umac_writel(priv, get_unaligned_be32(&addr[0]), UMAC_MAC0);
3274 	bcmgenet_umac_writel(priv, get_unaligned_be16(&addr[4]), UMAC_MAC1);
3275 }
3276 
bcmgenet_get_hw_addr(struct bcmgenet_priv * priv,unsigned char * addr)3277 static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv,
3278 				 unsigned char *addr)
3279 {
3280 	u32 addr_tmp;
3281 
3282 	addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0);
3283 	put_unaligned_be32(addr_tmp, &addr[0]);
3284 	addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1);
3285 	put_unaligned_be16(addr_tmp, &addr[4]);
3286 }
3287 
bcmgenet_netif_start(struct net_device * dev)3288 static void bcmgenet_netif_start(struct net_device *dev)
3289 {
3290 	struct bcmgenet_priv *priv = netdev_priv(dev);
3291 
3292 	/* Start the network engine */
3293 	netif_addr_lock_bh(dev);
3294 	bcmgenet_set_rx_mode(dev);
3295 	netif_addr_unlock_bh(dev);
3296 	bcmgenet_enable_rx_napi(priv);
3297 
3298 	umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
3299 
3300 	bcmgenet_enable_tx_napi(priv);
3301 
3302 	/* Monitor link interrupts now */
3303 	bcmgenet_link_intr_enable(priv);
3304 
3305 	phy_start(dev->phydev);
3306 }
3307 
bcmgenet_open(struct net_device * dev)3308 static int bcmgenet_open(struct net_device *dev)
3309 {
3310 	struct bcmgenet_priv *priv = netdev_priv(dev);
3311 	int ret;
3312 
3313 	netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
3314 
3315 	/* Turn on the clock */
3316 	clk_prepare_enable(priv->clk);
3317 
3318 	/* If this is an internal GPHY, power it back on now, before UniMAC is
3319 	 * brought out of reset as absolutely no UniMAC activity is allowed
3320 	 */
3321 	if (priv->internal_phy)
3322 		bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3323 
3324 	/* take MAC out of reset */
3325 	bcmgenet_umac_reset(priv);
3326 
3327 	init_umac(priv);
3328 
3329 	/* Apply features again in case we changed them while interface was
3330 	 * down
3331 	 */
3332 	bcmgenet_set_features(dev, dev->features);
3333 
3334 	bcmgenet_set_hw_addr(priv, dev->dev_addr);
3335 
3336 	/* HFB init */
3337 	bcmgenet_hfb_init(priv);
3338 
3339 	/* Reinitialize TDMA and RDMA and SW housekeeping */
3340 	ret = bcmgenet_init_dma(priv, true);
3341 	if (ret) {
3342 		netdev_err(dev, "failed to initialize DMA\n");
3343 		goto err_clk_disable;
3344 	}
3345 
3346 	ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
3347 			  dev->name, priv);
3348 	if (ret < 0) {
3349 		netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
3350 		goto err_fini_dma;
3351 	}
3352 
3353 	ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
3354 			  dev->name, priv);
3355 	if (ret < 0) {
3356 		netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
3357 		goto err_irq0;
3358 	}
3359 
3360 	ret = bcmgenet_mii_probe(dev);
3361 	if (ret) {
3362 		netdev_err(dev, "failed to connect to PHY\n");
3363 		goto err_irq1;
3364 	}
3365 
3366 	bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause);
3367 
3368 	bcmgenet_netif_start(dev);
3369 
3370 	netif_tx_start_all_queues(dev);
3371 
3372 	return 0;
3373 
3374 err_irq1:
3375 	free_irq(priv->irq1, priv);
3376 err_irq0:
3377 	free_irq(priv->irq0, priv);
3378 err_fini_dma:
3379 	bcmgenet_dma_teardown(priv);
3380 	bcmgenet_fini_dma(priv);
3381 err_clk_disable:
3382 	if (priv->internal_phy)
3383 		bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3384 	clk_disable_unprepare(priv->clk);
3385 	return ret;
3386 }
3387 
bcmgenet_netif_stop(struct net_device * dev,bool stop_phy)3388 static void bcmgenet_netif_stop(struct net_device *dev, bool stop_phy)
3389 {
3390 	struct bcmgenet_priv *priv = netdev_priv(dev);
3391 
3392 	netif_tx_disable(dev);
3393 
3394 	/* Disable MAC receive */
3395 	bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL);
3396 	umac_enable_set(priv, CMD_RX_EN, false);
3397 
3398 	if (stop_phy)
3399 		phy_stop(dev->phydev);
3400 
3401 	bcmgenet_dma_teardown(priv);
3402 
3403 	/* Disable MAC transmit. TX DMA disabled must be done before this */
3404 	umac_enable_set(priv, CMD_TX_EN, false);
3405 
3406 	bcmgenet_disable_tx_napi(priv);
3407 	bcmgenet_disable_rx_napi(priv);
3408 	bcmgenet_intr_disable(priv);
3409 
3410 	/* Wait for pending work items to complete. Since interrupts are
3411 	 * disabled no new work will be scheduled.
3412 	 */
3413 	cancel_work_sync(&priv->bcmgenet_irq_work);
3414 
3415 	/* tx reclaim */
3416 	bcmgenet_tx_reclaim_all(dev);
3417 	bcmgenet_fini_dma(priv);
3418 }
3419 
bcmgenet_close(struct net_device * dev)3420 static int bcmgenet_close(struct net_device *dev)
3421 {
3422 	struct bcmgenet_priv *priv = netdev_priv(dev);
3423 	int ret = 0;
3424 
3425 	netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
3426 
3427 	bcmgenet_netif_stop(dev, false);
3428 
3429 	/* Really kill the PHY state machine and disconnect from it */
3430 	phy_disconnect(dev->phydev);
3431 
3432 	free_irq(priv->irq0, priv);
3433 	free_irq(priv->irq1, priv);
3434 
3435 	if (priv->internal_phy)
3436 		ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3437 
3438 	clk_disable_unprepare(priv->clk);
3439 
3440 	return ret;
3441 }
3442 
bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring * ring)3443 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
3444 {
3445 	struct bcmgenet_priv *priv = ring->priv;
3446 	u32 p_index, c_index, intsts, intmsk;
3447 	struct netdev_queue *txq;
3448 	unsigned int free_bds;
3449 	bool txq_stopped;
3450 
3451 	if (!netif_msg_tx_err(priv))
3452 		return;
3453 
3454 	txq = netdev_get_tx_queue(priv->dev, ring->index);
3455 
3456 	spin_lock(&ring->lock);
3457 	intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3458 	intmsk = 1 << ring->index;
3459 	c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3460 	p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3461 	txq_stopped = netif_tx_queue_stopped(txq);
3462 	free_bds = ring->free_bds;
3463 	spin_unlock(&ring->lock);
3464 
3465 	netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3466 		  "TX queue status: %s, interrupts: %s\n"
3467 		  "(sw)free_bds: %d (sw)size: %d\n"
3468 		  "(sw)p_index: %d (hw)p_index: %d\n"
3469 		  "(sw)c_index: %d (hw)c_index: %d\n"
3470 		  "(sw)clean_p: %d (sw)write_p: %d\n"
3471 		  "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3472 		  ring->index, ring->index,
3473 		  txq_stopped ? "stopped" : "active",
3474 		  intsts & intmsk ? "enabled" : "disabled",
3475 		  free_bds, ring->size,
3476 		  ring->prod_index, p_index & DMA_P_INDEX_MASK,
3477 		  ring->c_index, c_index & DMA_C_INDEX_MASK,
3478 		  ring->clean_ptr, ring->write_ptr,
3479 		  ring->cb_ptr, ring->end_ptr);
3480 }
3481 
bcmgenet_timeout(struct net_device * dev,unsigned int txqueue)3482 static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue)
3483 {
3484 	struct bcmgenet_priv *priv = netdev_priv(dev);
3485 	u32 int1_enable = 0;
3486 	unsigned int q;
3487 
3488 	netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3489 
3490 	for (q = 0; q <= priv->hw_params->tx_queues; q++)
3491 		bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3492 
3493 	bcmgenet_tx_reclaim_all(dev);
3494 
3495 	for (q = 0; q <= priv->hw_params->tx_queues; q++)
3496 		int1_enable |= (1 << q);
3497 
3498 	/* Re-enable TX interrupts if disabled */
3499 	bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3500 
3501 	netif_trans_update(dev);
3502 
3503 	BCMGENET_STATS64_INC((&priv->tx_rings[txqueue].stats64), errors);
3504 
3505 	netif_tx_wake_all_queues(dev);
3506 }
3507 
3508 #define MAX_MDF_FILTER	17
3509 
bcmgenet_set_mdf_addr(struct bcmgenet_priv * priv,const unsigned char * addr,int * i)3510 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3511 					 const unsigned char *addr,
3512 					 int *i)
3513 {
3514 	bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3515 			     UMAC_MDF_ADDR + (*i * 4));
3516 	bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3517 			     addr[4] << 8 | addr[5],
3518 			     UMAC_MDF_ADDR + ((*i + 1) * 4));
3519 	*i += 2;
3520 }
3521 
bcmgenet_set_rx_mode(struct net_device * dev)3522 static void bcmgenet_set_rx_mode(struct net_device *dev)
3523 {
3524 	struct bcmgenet_priv *priv = netdev_priv(dev);
3525 	struct netdev_hw_addr *ha;
3526 	int i, nfilter;
3527 	u32 reg;
3528 
3529 	netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3530 
3531 	/* Number of filters needed */
3532 	nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3533 
3534 	/*
3535 	 * Turn on promicuous mode for three scenarios
3536 	 * 1. IFF_PROMISC flag is set
3537 	 * 2. IFF_ALLMULTI flag is set
3538 	 * 3. The number of filters needed exceeds the number filters
3539 	 *    supported by the hardware.
3540 	*/
3541 	spin_lock(&priv->reg_lock);
3542 	reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3543 	if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3544 	    (nfilter > MAX_MDF_FILTER)) {
3545 		reg |= CMD_PROMISC;
3546 		bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3547 		spin_unlock(&priv->reg_lock);
3548 		bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3549 		return;
3550 	} else {
3551 		reg &= ~CMD_PROMISC;
3552 		bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3553 		spin_unlock(&priv->reg_lock);
3554 	}
3555 
3556 	/* update MDF filter */
3557 	i = 0;
3558 	/* Broadcast */
3559 	bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
3560 	/* my own address.*/
3561 	bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
3562 
3563 	/* Unicast */
3564 	netdev_for_each_uc_addr(ha, dev)
3565 		bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3566 
3567 	/* Multicast */
3568 	netdev_for_each_mc_addr(ha, dev)
3569 		bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3570 
3571 	/* Enable filters */
3572 	reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3573 	bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3574 }
3575 
3576 /* Set the hardware MAC address. */
bcmgenet_set_mac_addr(struct net_device * dev,void * p)3577 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3578 {
3579 	struct sockaddr *addr = p;
3580 
3581 	/* Setting the MAC address at the hardware level is not possible
3582 	 * without disabling the UniMAC RX/TX enable bits.
3583 	 */
3584 	if (netif_running(dev))
3585 		return -EBUSY;
3586 
3587 	eth_hw_addr_set(dev, addr->sa_data);
3588 
3589 	return 0;
3590 }
3591 
bcmgenet_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * stats)3592 static void bcmgenet_get_stats64(struct net_device *dev,
3593 				 struct rtnl_link_stats64 *stats)
3594 {
3595 	struct bcmgenet_priv *priv = netdev_priv(dev);
3596 	struct bcmgenet_tx_stats64 *tx_stats;
3597 	struct bcmgenet_rx_stats64 *rx_stats;
3598 	u64 rx_length_errors, rx_over_errors;
3599 	u64 rx_missed, rx_fragmented_errors;
3600 	u64 rx_crc_errors, rx_frame_errors;
3601 	u64 tx_errors, tx_dropped;
3602 	u64 rx_errors, rx_dropped;
3603 	u64 tx_bytes, tx_packets;
3604 	u64 rx_bytes, rx_packets;
3605 	unsigned int start;
3606 	unsigned int q;
3607 	u64 multicast;
3608 
3609 	for (q = 0; q <= priv->hw_params->tx_queues; q++) {
3610 		tx_stats = &priv->tx_rings[q].stats64;
3611 		do {
3612 			start = u64_stats_fetch_begin(&tx_stats->syncp);
3613 			tx_bytes = u64_stats_read(&tx_stats->bytes);
3614 			tx_packets = u64_stats_read(&tx_stats->packets);
3615 			tx_errors = u64_stats_read(&tx_stats->errors);
3616 			tx_dropped = u64_stats_read(&tx_stats->dropped);
3617 		} while (u64_stats_fetch_retry(&tx_stats->syncp, start));
3618 
3619 		stats->tx_bytes += tx_bytes;
3620 		stats->tx_packets += tx_packets;
3621 		stats->tx_errors += tx_errors;
3622 		stats->tx_dropped += tx_dropped;
3623 	}
3624 
3625 	for (q = 0; q <= priv->hw_params->rx_queues; q++) {
3626 		rx_stats = &priv->rx_rings[q].stats64;
3627 		do {
3628 			start = u64_stats_fetch_begin(&rx_stats->syncp);
3629 			rx_bytes = u64_stats_read(&rx_stats->bytes);
3630 			rx_packets = u64_stats_read(&rx_stats->packets);
3631 			rx_errors = u64_stats_read(&rx_stats->errors);
3632 			rx_dropped = u64_stats_read(&rx_stats->dropped);
3633 			rx_missed = u64_stats_read(&rx_stats->missed);
3634 			rx_length_errors = u64_stats_read(&rx_stats->length_errors);
3635 			rx_over_errors = u64_stats_read(&rx_stats->over_errors);
3636 			rx_crc_errors = u64_stats_read(&rx_stats->crc_errors);
3637 			rx_frame_errors = u64_stats_read(&rx_stats->frame_errors);
3638 			rx_fragmented_errors = u64_stats_read(&rx_stats->fragmented_errors);
3639 			multicast = u64_stats_read(&rx_stats->multicast);
3640 		} while (u64_stats_fetch_retry(&rx_stats->syncp, start));
3641 
3642 		rx_errors += rx_length_errors;
3643 		rx_errors += rx_crc_errors;
3644 		rx_errors += rx_frame_errors;
3645 		rx_errors += rx_fragmented_errors;
3646 
3647 		stats->rx_bytes += rx_bytes;
3648 		stats->rx_packets += rx_packets;
3649 		stats->rx_errors += rx_errors;
3650 		stats->rx_dropped += rx_dropped;
3651 		stats->rx_missed_errors += rx_missed;
3652 		stats->rx_length_errors += rx_length_errors;
3653 		stats->rx_over_errors += rx_over_errors;
3654 		stats->rx_crc_errors += rx_crc_errors;
3655 		stats->rx_frame_errors += rx_frame_errors;
3656 		stats->multicast += multicast;
3657 	}
3658 }
3659 
bcmgenet_change_carrier(struct net_device * dev,bool new_carrier)3660 static int bcmgenet_change_carrier(struct net_device *dev, bool new_carrier)
3661 {
3662 	struct bcmgenet_priv *priv = netdev_priv(dev);
3663 
3664 	if (!dev->phydev || !phy_is_pseudo_fixed_link(dev->phydev) ||
3665 	    priv->phy_interface != PHY_INTERFACE_MODE_MOCA)
3666 		return -EOPNOTSUPP;
3667 
3668 	if (new_carrier)
3669 		netif_carrier_on(dev);
3670 	else
3671 		netif_carrier_off(dev);
3672 
3673 	return 0;
3674 }
3675 
3676 static const struct net_device_ops bcmgenet_netdev_ops = {
3677 	.ndo_open		= bcmgenet_open,
3678 	.ndo_stop		= bcmgenet_close,
3679 	.ndo_start_xmit		= bcmgenet_xmit,
3680 	.ndo_tx_timeout		= bcmgenet_timeout,
3681 	.ndo_set_rx_mode	= bcmgenet_set_rx_mode,
3682 	.ndo_set_mac_address	= bcmgenet_set_mac_addr,
3683 	.ndo_eth_ioctl		= phy_do_ioctl_running,
3684 	.ndo_set_features	= bcmgenet_set_features,
3685 	.ndo_get_stats64	= bcmgenet_get_stats64,
3686 	.ndo_change_carrier	= bcmgenet_change_carrier,
3687 };
3688 
3689 /* GENET hardware parameters/characteristics */
3690 static const struct bcmgenet_hw_params bcmgenet_hw_params_v1 = {
3691 	.tx_queues = 0,
3692 	.tx_bds_per_q = 0,
3693 	.rx_queues = 0,
3694 	.rx_bds_per_q = 0,
3695 	.bp_in_en_shift = 16,
3696 	.bp_in_mask = 0xffff,
3697 	.hfb_filter_cnt = 16,
3698 	.hfb_filter_size = 64,
3699 	.qtag_mask = 0x1F,
3700 	.hfb_offset = 0x1000,
3701 	.hfb_reg_offset = GENET_RBUF_OFF + RBUF_HFB_CTRL_V1,
3702 	.rdma_offset = 0x2000,
3703 	.tdma_offset = 0x3000,
3704 	.words_per_bd = 2,
3705 };
3706 
3707 static const struct bcmgenet_hw_params bcmgenet_hw_params_v2 = {
3708 	.tx_queues = 4,
3709 	.tx_bds_per_q = 32,
3710 	.rx_queues = 0,
3711 	.rx_bds_per_q = 0,
3712 	.bp_in_en_shift = 16,
3713 	.bp_in_mask = 0xffff,
3714 	.hfb_filter_cnt = 16,
3715 	.hfb_filter_size = 64,
3716 	.qtag_mask = 0x1F,
3717 	.tbuf_offset = 0x0600,
3718 	.hfb_offset = 0x1000,
3719 	.hfb_reg_offset = 0x2000,
3720 	.rdma_offset = 0x3000,
3721 	.tdma_offset = 0x4000,
3722 	.words_per_bd = 2,
3723 };
3724 
3725 static const struct bcmgenet_hw_params bcmgenet_hw_params_v3 = {
3726 	.tx_queues = 4,
3727 	.tx_bds_per_q = 32,
3728 	.rx_queues = 0,
3729 	.rx_bds_per_q = 0,
3730 	.bp_in_en_shift = 17,
3731 	.bp_in_mask = 0x1ffff,
3732 	.hfb_filter_cnt = 48,
3733 	.hfb_filter_size = 128,
3734 	.qtag_mask = 0x3F,
3735 	.tbuf_offset = 0x0600,
3736 	.hfb_offset = 0x8000,
3737 	.hfb_reg_offset = 0xfc00,
3738 	.rdma_offset = 0x10000,
3739 	.tdma_offset = 0x11000,
3740 	.words_per_bd = 2,
3741 };
3742 
3743 static const struct bcmgenet_hw_params bcmgenet_hw_params_v4 = {
3744 	.tx_queues = 4,
3745 	.tx_bds_per_q = 32,
3746 	.rx_queues = 0,
3747 	.rx_bds_per_q = 0,
3748 	.bp_in_en_shift = 17,
3749 	.bp_in_mask = 0x1ffff,
3750 	.hfb_filter_cnt = 48,
3751 	.hfb_filter_size = 128,
3752 	.qtag_mask = 0x3F,
3753 	.tbuf_offset = 0x0600,
3754 	.hfb_offset = 0x8000,
3755 	.hfb_reg_offset = 0xfc00,
3756 	.rdma_offset = 0x2000,
3757 	.tdma_offset = 0x4000,
3758 	.words_per_bd = 3,
3759 };
3760 
3761 /* Infer hardware parameters from the detected GENET version */
bcmgenet_set_hw_params(struct bcmgenet_priv * priv)3762 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3763 {
3764 	const struct bcmgenet_hw_params *params;
3765 	u32 reg;
3766 	u8 major;
3767 	u16 gphy_rev;
3768 
3769 	/* default to latest values */
3770 	params = &bcmgenet_hw_params_v4;
3771 	bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3772 	genet_dma_ring_regs = genet_dma_ring_regs_v4;
3773 	if (GENET_IS_V3(priv)) {
3774 		params = &bcmgenet_hw_params_v3;
3775 		bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3776 		genet_dma_ring_regs = genet_dma_ring_regs_v123;
3777 	} else if (GENET_IS_V2(priv)) {
3778 		params = &bcmgenet_hw_params_v2;
3779 		bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3780 		genet_dma_ring_regs = genet_dma_ring_regs_v123;
3781 	} else if (GENET_IS_V1(priv)) {
3782 		params = &bcmgenet_hw_params_v1;
3783 		bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3784 		genet_dma_ring_regs = genet_dma_ring_regs_v123;
3785 	}
3786 	priv->hw_params = params;
3787 
3788 	/* Read GENET HW version */
3789 	reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3790 	major = (reg >> 24 & 0x0f);
3791 	if (major == 6 || major == 7)
3792 		major = 5;
3793 	else if (major == 5)
3794 		major = 4;
3795 	else if (major == 0)
3796 		major = 1;
3797 	if (major != priv->version) {
3798 		dev_err(&priv->pdev->dev,
3799 			"GENET version mismatch, got: %d, configured for: %d\n",
3800 			major, priv->version);
3801 	}
3802 
3803 	/* Print the GENET core version */
3804 	dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3805 		 major, (reg >> 16) & 0x0f, reg & 0xffff);
3806 
3807 	/* Store the integrated PHY revision for the MDIO probing function
3808 	 * to pass this information to the PHY driver. The PHY driver expects
3809 	 * to find the PHY major revision in bits 15:8 while the GENET register
3810 	 * stores that information in bits 7:0, account for that.
3811 	 *
3812 	 * On newer chips, starting with PHY revision G0, a new scheme is
3813 	 * deployed similar to the Starfighter 2 switch with GPHY major
3814 	 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3815 	 * is reserved as well as special value 0x01ff, we have a small
3816 	 * heuristic to check for the new GPHY revision and re-arrange things
3817 	 * so the GPHY driver is happy.
3818 	 */
3819 	gphy_rev = reg & 0xffff;
3820 
3821 	if (GENET_IS_V5(priv)) {
3822 		/* The EPHY revision should come from the MDIO registers of
3823 		 * the PHY not from GENET.
3824 		 */
3825 		if (gphy_rev != 0) {
3826 			pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3827 				gphy_rev);
3828 		}
3829 	/* This is reserved so should require special treatment */
3830 	} else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3831 		pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3832 		return;
3833 	/* This is the good old scheme, just GPHY major, no minor nor patch */
3834 	} else if ((gphy_rev & 0xf0) != 0) {
3835 		priv->gphy_rev = gphy_rev << 8;
3836 	/* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3837 	} else if ((gphy_rev & 0xff00) != 0) {
3838 		priv->gphy_rev = gphy_rev;
3839 	}
3840 
3841 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3842 	if (!bcmgenet_has_40bits(priv))
3843 		pr_warn("GENET does not support 40-bits PA\n");
3844 #endif
3845 
3846 	pr_debug("Configuration for version: %d\n"
3847 		"TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3848 		"BP << en: %2d, BP msk: 0x%05x\n"
3849 		"HFB count: %2d, QTAQ msk: 0x%05x\n"
3850 		"TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3851 		"RDMA: 0x%05x, TDMA: 0x%05x\n"
3852 		"Words/BD: %d\n",
3853 		priv->version,
3854 		params->tx_queues, params->tx_bds_per_q,
3855 		params->rx_queues, params->rx_bds_per_q,
3856 		params->bp_in_en_shift, params->bp_in_mask,
3857 		params->hfb_filter_cnt, params->qtag_mask,
3858 		params->tbuf_offset, params->hfb_offset,
3859 		params->hfb_reg_offset,
3860 		params->rdma_offset, params->tdma_offset,
3861 		params->words_per_bd);
3862 }
3863 
3864 struct bcmgenet_plat_data {
3865 	enum bcmgenet_version version;
3866 	u32 dma_max_burst_length;
3867 	u32 flags;
3868 };
3869 
3870 static const struct bcmgenet_plat_data v1_plat_data = {
3871 	.version = GENET_V1,
3872 	.dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3873 };
3874 
3875 static const struct bcmgenet_plat_data v2_plat_data = {
3876 	.version = GENET_V2,
3877 	.dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3878 	.flags = GENET_HAS_EXT,
3879 };
3880 
3881 static const struct bcmgenet_plat_data v3_plat_data = {
3882 	.version = GENET_V3,
3883 	.dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3884 	.flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3885 		 GENET_HAS_MOCA_LINK_DET,
3886 };
3887 
3888 static const struct bcmgenet_plat_data v4_plat_data = {
3889 	.version = GENET_V4,
3890 	.dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3891 	.flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3892 		 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3893 };
3894 
3895 static const struct bcmgenet_plat_data v5_plat_data = {
3896 	.version = GENET_V5,
3897 	.dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3898 	.flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3899 		 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3900 };
3901 
3902 static const struct bcmgenet_plat_data bcm2711_plat_data = {
3903 	.version = GENET_V5,
3904 	.dma_max_burst_length = 0x08,
3905 	.flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3906 		 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3907 };
3908 
3909 static const struct bcmgenet_plat_data bcm7712_plat_data = {
3910 	.version = GENET_V5,
3911 	.dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3912 	.flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3913 		 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET |
3914 		 GENET_HAS_EPHY_16NM,
3915 };
3916 
3917 static const struct of_device_id bcmgenet_match[] = {
3918 	{ .compatible = "brcm,genet-v1", .data = &v1_plat_data },
3919 	{ .compatible = "brcm,genet-v2", .data = &v2_plat_data },
3920 	{ .compatible = "brcm,genet-v3", .data = &v3_plat_data },
3921 	{ .compatible = "brcm,genet-v4", .data = &v4_plat_data },
3922 	{ .compatible = "brcm,genet-v5", .data = &v5_plat_data },
3923 	{ .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data },
3924 	{ .compatible = "brcm,bcm7712-genet-v5", .data = &bcm7712_plat_data },
3925 	{ },
3926 };
3927 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3928 
bcmgenet_probe(struct platform_device * pdev)3929 static int bcmgenet_probe(struct platform_device *pdev)
3930 {
3931 	struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3932 	const struct bcmgenet_plat_data *pdata;
3933 	struct bcmgenet_priv *priv;
3934 	struct net_device *dev;
3935 	unsigned int i;
3936 	int err = -EIO;
3937 
3938 	/* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3939 	dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3940 				 GENET_MAX_MQ_CNT + 1);
3941 	if (!dev) {
3942 		dev_err(&pdev->dev, "can't allocate net device\n");
3943 		return -ENOMEM;
3944 	}
3945 
3946 	priv = netdev_priv(dev);
3947 	priv->irq0 = platform_get_irq(pdev, 0);
3948 	if (priv->irq0 < 0) {
3949 		err = priv->irq0;
3950 		goto err;
3951 	}
3952 	priv->irq1 = platform_get_irq(pdev, 1);
3953 	if (priv->irq1 < 0) {
3954 		err = priv->irq1;
3955 		goto err;
3956 	}
3957 	priv->wol_irq = platform_get_irq_optional(pdev, 2);
3958 	if (priv->wol_irq == -EPROBE_DEFER) {
3959 		err = priv->wol_irq;
3960 		goto err;
3961 	}
3962 
3963 	priv->base = devm_platform_ioremap_resource(pdev, 0);
3964 	if (IS_ERR(priv->base)) {
3965 		err = PTR_ERR(priv->base);
3966 		goto err;
3967 	}
3968 
3969 	spin_lock_init(&priv->reg_lock);
3970 	spin_lock_init(&priv->lock);
3971 
3972 	/* Set default pause parameters */
3973 	priv->autoneg_pause = 1;
3974 	priv->tx_pause = 1;
3975 	priv->rx_pause = 1;
3976 
3977 	SET_NETDEV_DEV(dev, &pdev->dev);
3978 	dev_set_drvdata(&pdev->dev, dev);
3979 	dev->watchdog_timeo = 2 * HZ;
3980 	dev->ethtool_ops = &bcmgenet_ethtool_ops;
3981 	dev->netdev_ops = &bcmgenet_netdev_ops;
3982 
3983 	priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3984 
3985 	/* Set default features */
3986 	dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM |
3987 			 NETIF_F_RXCSUM;
3988 	dev->hw_features |= dev->features;
3989 	dev->vlan_features |= dev->features;
3990 
3991 	/* Request the WOL interrupt and advertise suspend if available */
3992 	priv->wol_irq_disabled = true;
3993 	if (priv->wol_irq > 0) {
3994 		err = devm_request_irq(&pdev->dev, priv->wol_irq,
3995 				       bcmgenet_wol_isr, 0, dev->name, priv);
3996 		if (!err)
3997 			device_set_wakeup_capable(&pdev->dev, 1);
3998 	}
3999 
4000 	/* Set the needed headroom to account for any possible
4001 	 * features enabling/disabling at runtime
4002 	 */
4003 	dev->needed_headroom += 64;
4004 
4005 	priv->dev = dev;
4006 	priv->pdev = pdev;
4007 
4008 	pdata = device_get_match_data(&pdev->dev);
4009 	if (pdata) {
4010 		priv->version = pdata->version;
4011 		priv->dma_max_burst_length = pdata->dma_max_burst_length;
4012 		priv->flags = pdata->flags;
4013 	} else {
4014 		priv->version = pd->genet_version;
4015 		priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH;
4016 	}
4017 
4018 	priv->clk = devm_clk_get_optional(&priv->pdev->dev, "enet");
4019 	if (IS_ERR(priv->clk)) {
4020 		dev_dbg(&priv->pdev->dev, "failed to get enet clock\n");
4021 		err = PTR_ERR(priv->clk);
4022 		goto err;
4023 	}
4024 
4025 	err = clk_prepare_enable(priv->clk);
4026 	if (err)
4027 		goto err;
4028 
4029 	bcmgenet_set_hw_params(priv);
4030 
4031 	err = -EIO;
4032 	if (bcmgenet_has_40bits(priv))
4033 		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
4034 	if (err)
4035 		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4036 	if (err)
4037 		goto err_clk_disable;
4038 
4039 	/* Mii wait queue */
4040 	init_waitqueue_head(&priv->wq);
4041 	/* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
4042 	priv->rx_buf_len = RX_BUF_LENGTH;
4043 	INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
4044 
4045 	priv->clk_wol = devm_clk_get_optional(&priv->pdev->dev, "enet-wol");
4046 	if (IS_ERR(priv->clk_wol)) {
4047 		dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n");
4048 		err = PTR_ERR(priv->clk_wol);
4049 		goto err_clk_disable;
4050 	}
4051 
4052 	priv->clk_eee = devm_clk_get_optional(&priv->pdev->dev, "enet-eee");
4053 	if (IS_ERR(priv->clk_eee)) {
4054 		dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n");
4055 		err = PTR_ERR(priv->clk_eee);
4056 		goto err_clk_disable;
4057 	}
4058 
4059 	/* If this is an internal GPHY, power it on now, before UniMAC is
4060 	 * brought out of reset as absolutely no UniMAC activity is allowed
4061 	 */
4062 	if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL)
4063 		bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
4064 
4065 	if (pd && !IS_ERR_OR_NULL(pd->mac_address))
4066 		eth_hw_addr_set(dev, pd->mac_address);
4067 	else
4068 		if (device_get_ethdev_address(&pdev->dev, dev))
4069 			if (has_acpi_companion(&pdev->dev)) {
4070 				u8 addr[ETH_ALEN];
4071 
4072 				bcmgenet_get_hw_addr(priv, addr);
4073 				eth_hw_addr_set(dev, addr);
4074 			}
4075 
4076 	if (!is_valid_ether_addr(dev->dev_addr)) {
4077 		dev_warn(&pdev->dev, "using random Ethernet MAC\n");
4078 		eth_hw_addr_random(dev);
4079 	}
4080 
4081 	reset_umac(priv);
4082 
4083 	err = bcmgenet_mii_init(dev);
4084 	if (err)
4085 		goto err_clk_disable;
4086 
4087 	/* setup number of real queues + 1 */
4088 	netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
4089 	netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
4090 
4091 	/* Set default coalescing parameters */
4092 	for (i = 0; i <= priv->hw_params->rx_queues; i++)
4093 		priv->rx_rings[i].rx_max_coalesced_frames = 1;
4094 
4095 	/* Initialize u64 stats seq counter for 32bit machines */
4096 	for (i = 0; i <= priv->hw_params->rx_queues; i++)
4097 		u64_stats_init(&priv->rx_rings[i].stats64.syncp);
4098 	for (i = 0; i <= priv->hw_params->tx_queues; i++)
4099 		u64_stats_init(&priv->tx_rings[i].stats64.syncp);
4100 
4101 	/* libphy will determine the link state */
4102 	netif_carrier_off(dev);
4103 
4104 	/* Turn off the main clock, WOL clock is handled separately */
4105 	clk_disable_unprepare(priv->clk);
4106 
4107 	err = register_netdev(dev);
4108 	if (err) {
4109 		bcmgenet_mii_exit(dev);
4110 		goto err;
4111 	}
4112 
4113 	return err;
4114 
4115 err_clk_disable:
4116 	clk_disable_unprepare(priv->clk);
4117 err:
4118 	free_netdev(dev);
4119 	return err;
4120 }
4121 
bcmgenet_remove(struct platform_device * pdev)4122 static void bcmgenet_remove(struct platform_device *pdev)
4123 {
4124 	struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
4125 
4126 	dev_set_drvdata(&pdev->dev, NULL);
4127 	unregister_netdev(priv->dev);
4128 	bcmgenet_mii_exit(priv->dev);
4129 	free_netdev(priv->dev);
4130 }
4131 
bcmgenet_shutdown(struct platform_device * pdev)4132 static void bcmgenet_shutdown(struct platform_device *pdev)
4133 {
4134 	bcmgenet_remove(pdev);
4135 }
4136 
4137 #ifdef CONFIG_PM_SLEEP
bcmgenet_resume_noirq(struct device * d)4138 static int bcmgenet_resume_noirq(struct device *d)
4139 {
4140 	struct net_device *dev = dev_get_drvdata(d);
4141 	struct bcmgenet_priv *priv = netdev_priv(dev);
4142 	int ret;
4143 	u32 reg;
4144 
4145 	if (!netif_running(dev))
4146 		return 0;
4147 
4148 	/* Turn on the clock */
4149 	ret = clk_prepare_enable(priv->clk);
4150 	if (ret)
4151 		return ret;
4152 
4153 	if (device_may_wakeup(d) && priv->wolopts) {
4154 		/* Account for Wake-on-LAN events and clear those events
4155 		 * (Some devices need more time between enabling the clocks
4156 		 *  and the interrupt register reflecting the wake event so
4157 		 *  read the register twice)
4158 		 */
4159 		reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT);
4160 		reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT);
4161 		if (reg & UMAC_IRQ_WAKE_EVENT)
4162 			pm_wakeup_event(&priv->pdev->dev, 0);
4163 
4164 		/* From WOL-enabled suspend, switch to regular clock */
4165 		if (!bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC))
4166 			return 0;
4167 
4168 		/* Failed so fall through to reset MAC */
4169 	}
4170 
4171 	/* If this is an internal GPHY, power it back on now, before UniMAC is
4172 	 * brought out of reset as absolutely no UniMAC activity is allowed
4173 	 */
4174 	if (priv->internal_phy)
4175 		bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
4176 
4177 	/* take MAC out of reset */
4178 	bcmgenet_umac_reset(priv);
4179 
4180 	return 0;
4181 }
4182 
bcmgenet_resume(struct device * d)4183 static int bcmgenet_resume(struct device *d)
4184 {
4185 	struct net_device *dev = dev_get_drvdata(d);
4186 	struct bcmgenet_priv *priv = netdev_priv(dev);
4187 	struct bcmgenet_rxnfc_rule *rule;
4188 	int ret;
4189 	u32 reg;
4190 
4191 	if (!netif_running(dev))
4192 		return 0;
4193 
4194 	if (device_may_wakeup(d) && priv->wolopts) {
4195 		reg = bcmgenet_umac_readl(priv, UMAC_CMD);
4196 		if (reg & CMD_RX_EN) {
4197 			/* Successfully exited WoL, just resume data flows */
4198 			list_for_each_entry(rule, &priv->rxnfc_list, list)
4199 				if (rule->state == BCMGENET_RXNFC_STATE_ENABLED)
4200 					bcmgenet_hfb_enable_filter(priv,
4201 							rule->fs.location + 1);
4202 			bcmgenet_hfb_enable_filter(priv, 0);
4203 			bcmgenet_set_rx_mode(dev);
4204 			bcmgenet_enable_rx_napi(priv);
4205 
4206 			/* Reinitialize Tx flows */
4207 			bcmgenet_tdma_disable(priv);
4208 			bcmgenet_init_tx_queues(priv->dev);
4209 			reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
4210 			reg |= DMA_EN;
4211 			bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
4212 			bcmgenet_enable_tx_napi(priv);
4213 
4214 			bcmgenet_link_intr_enable(priv);
4215 			phy_start_machine(dev->phydev);
4216 
4217 			netif_device_attach(dev);
4218 			enable_irq(priv->irq1);
4219 			return 0;
4220 		}
4221 		/* MAC was reset so complete bcmgenet_netif_stop() */
4222 		umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, false);
4223 		bcmgenet_rdma_disable(priv);
4224 		bcmgenet_intr_disable(priv);
4225 		bcmgenet_fini_dma(priv);
4226 		enable_irq(priv->irq1);
4227 	}
4228 
4229 	init_umac(priv);
4230 
4231 	phy_init_hw(dev->phydev);
4232 
4233 	/* Speed settings must be restored */
4234 	genphy_config_aneg(dev->phydev);
4235 	bcmgenet_mii_config(priv->dev, false);
4236 
4237 	/* Restore enabled features */
4238 	bcmgenet_set_features(dev, dev->features);
4239 
4240 	bcmgenet_set_hw_addr(priv, dev->dev_addr);
4241 
4242 	/* Restore hardware filters */
4243 	bcmgenet_hfb_clear(priv);
4244 	list_for_each_entry(rule, &priv->rxnfc_list, list)
4245 		if (rule->state != BCMGENET_RXNFC_STATE_UNUSED)
4246 			bcmgenet_hfb_create_rxnfc_filter(priv, rule);
4247 
4248 	/* Reinitialize TDMA and RDMA and SW housekeeping */
4249 	ret = bcmgenet_init_dma(priv, false);
4250 	if (ret) {
4251 		netdev_err(dev, "failed to initialize DMA\n");
4252 		goto out_clk_disable;
4253 	}
4254 
4255 	if (!device_may_wakeup(d))
4256 		phy_resume(dev->phydev);
4257 
4258 	bcmgenet_netif_start(dev);
4259 
4260 	netif_device_attach(dev);
4261 
4262 	return 0;
4263 
4264 out_clk_disable:
4265 	if (priv->internal_phy)
4266 		bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
4267 	clk_disable_unprepare(priv->clk);
4268 	return ret;
4269 }
4270 
bcmgenet_suspend(struct device * d)4271 static int bcmgenet_suspend(struct device *d)
4272 {
4273 	struct net_device *dev = dev_get_drvdata(d);
4274 	struct bcmgenet_priv *priv = netdev_priv(dev);
4275 	struct bcmgenet_rxnfc_rule *rule;
4276 	u32 reg, hfb_enable = 0;
4277 
4278 	if (!netif_running(dev))
4279 		return 0;
4280 
4281 	netif_device_detach(dev);
4282 
4283 	if (device_may_wakeup(d) && priv->wolopts) {
4284 		netif_tx_disable(dev);
4285 
4286 		/* Suspend non-wake Rx data flows */
4287 		if (priv->wolopts & WAKE_FILTER)
4288 			list_for_each_entry(rule, &priv->rxnfc_list, list)
4289 				if (rule->fs.ring_cookie == RX_CLS_FLOW_WAKE &&
4290 				    rule->state == BCMGENET_RXNFC_STATE_ENABLED)
4291 					hfb_enable |= 1 << rule->fs.location;
4292 		reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
4293 		if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) {
4294 			reg &= ~RBUF_HFB_FILTER_EN_MASK;
4295 			reg |= hfb_enable << (RBUF_HFB_FILTER_EN_SHIFT + 1);
4296 		} else {
4297 			bcmgenet_hfb_reg_writel(priv, hfb_enable << 1,
4298 						HFB_FLT_ENABLE_V3PLUS + 4);
4299 		}
4300 		if (!hfb_enable)
4301 			reg &= ~RBUF_HFB_EN;
4302 		bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
4303 
4304 		/* Clear any old filter matches so only new matches wake */
4305 		bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
4306 		bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
4307 
4308 		if (-ETIMEDOUT == bcmgenet_tdma_disable(priv))
4309 			netdev_warn(priv->dev,
4310 				    "Timed out while disabling TX DMA\n");
4311 
4312 		bcmgenet_disable_tx_napi(priv);
4313 		bcmgenet_disable_rx_napi(priv);
4314 		disable_irq(priv->irq1);
4315 		bcmgenet_tx_reclaim_all(dev);
4316 		bcmgenet_fini_tx_napi(priv);
4317 	} else {
4318 		/* Teardown the interface */
4319 		bcmgenet_netif_stop(dev, true);
4320 	}
4321 
4322 	return 0;
4323 }
4324 
bcmgenet_suspend_noirq(struct device * d)4325 static int bcmgenet_suspend_noirq(struct device *d)
4326 {
4327 	struct net_device *dev = dev_get_drvdata(d);
4328 	struct bcmgenet_priv *priv = netdev_priv(dev);
4329 	int ret = 0;
4330 
4331 	if (!netif_running(dev))
4332 		return 0;
4333 
4334 	/* Prepare the device for Wake-on-LAN and switch to the slow clock */
4335 	if (device_may_wakeup(d) && priv->wolopts)
4336 		ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
4337 	else if (priv->internal_phy)
4338 		ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
4339 
4340 	/* Let the framework handle resumption and leave the clocks on */
4341 	if (ret)
4342 		return ret;
4343 
4344 	/* Turn off the clocks */
4345 	clk_disable_unprepare(priv->clk);
4346 
4347 	return 0;
4348 }
4349 #else
4350 #define bcmgenet_suspend	NULL
4351 #define bcmgenet_suspend_noirq	NULL
4352 #define bcmgenet_resume		NULL
4353 #define bcmgenet_resume_noirq	NULL
4354 #endif /* CONFIG_PM_SLEEP */
4355 
4356 static const struct dev_pm_ops bcmgenet_pm_ops = {
4357 	.suspend	= bcmgenet_suspend,
4358 	.suspend_noirq	= bcmgenet_suspend_noirq,
4359 	.resume		= bcmgenet_resume,
4360 	.resume_noirq	= bcmgenet_resume_noirq,
4361 };
4362 
4363 static const struct acpi_device_id genet_acpi_match[] = {
4364 	{ "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data },
4365 	{ },
4366 };
4367 MODULE_DEVICE_TABLE(acpi, genet_acpi_match);
4368 
4369 static struct platform_driver bcmgenet_driver = {
4370 	.probe	= bcmgenet_probe,
4371 	.remove = bcmgenet_remove,
4372 	.shutdown = bcmgenet_shutdown,
4373 	.driver	= {
4374 		.name	= "bcmgenet",
4375 		.of_match_table = bcmgenet_match,
4376 		.pm	= &bcmgenet_pm_ops,
4377 		.acpi_match_table = genet_acpi_match,
4378 	},
4379 };
4380 module_platform_driver(bcmgenet_driver);
4381 
4382 MODULE_AUTHOR("Broadcom Corporation");
4383 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
4384 MODULE_ALIAS("platform:bcmgenet");
4385 MODULE_LICENSE("GPL");
4386 MODULE_SOFTDEP("pre: mdio-bcm-unimac");
4387