1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Broadcom GENET MDIO routines
4 *
5 * Copyright (c) 2014-2024 Broadcom
6 */
7
8 #include <linux/acpi.h>
9 #include <linux/types.h>
10 #include <linux/delay.h>
11 #include <linux/wait.h>
12 #include <linux/mii.h>
13 #include <linux/ethtool.h>
14 #include <linux/bitops.h>
15 #include <linux/netdevice.h>
16 #include <linux/platform_device.h>
17 #include <linux/phy.h>
18 #include <linux/phy_fixed.h>
19 #include <linux/brcmphy.h>
20 #include <linux/of.h>
21 #include <linux/of_net.h>
22 #include <linux/of_mdio.h>
23 #include <linux/platform_data/bcmgenet.h>
24 #include <linux/platform_data/mdio-bcm-unimac.h>
25
26 #include "bcmgenet.h"
27
bcmgenet_mac_config(struct net_device * dev)28 static void bcmgenet_mac_config(struct net_device *dev)
29 {
30 struct bcmgenet_priv *priv = netdev_priv(dev);
31 struct phy_device *phydev = dev->phydev;
32 u32 reg, cmd_bits = 0;
33 bool active;
34
35 /* speed */
36 if (phydev->speed == SPEED_1000)
37 cmd_bits = CMD_SPEED_1000;
38 else if (phydev->speed == SPEED_100)
39 cmd_bits = CMD_SPEED_100;
40 else
41 cmd_bits = CMD_SPEED_10;
42 cmd_bits <<= CMD_SPEED_SHIFT;
43
44 /* duplex */
45 if (phydev->duplex != DUPLEX_FULL) {
46 cmd_bits |= CMD_HD_EN |
47 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
48 } else {
49 /* pause capability defaults to Symmetric */
50 if (priv->autoneg_pause) {
51 bool tx_pause = 0, rx_pause = 0;
52
53 if (phydev->autoneg)
54 phy_get_pause(phydev, &tx_pause, &rx_pause);
55
56 if (!tx_pause)
57 cmd_bits |= CMD_TX_PAUSE_IGNORE;
58 if (!rx_pause)
59 cmd_bits |= CMD_RX_PAUSE_IGNORE;
60 }
61
62 /* Manual override */
63 if (!priv->rx_pause)
64 cmd_bits |= CMD_RX_PAUSE_IGNORE;
65 if (!priv->tx_pause)
66 cmd_bits |= CMD_TX_PAUSE_IGNORE;
67 }
68
69 /* Program UMAC and RGMII block based on established
70 * link speed, duplex, and pause. The speed set in
71 * umac->cmd tell RGMII block which clock to use for
72 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
73 * Receive clock is provided by the PHY.
74 */
75 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
76 reg |= RGMII_LINK;
77 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
78
79 spin_lock_bh(&priv->reg_lock);
80 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
81 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
82 CMD_HD_EN |
83 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
84 reg |= cmd_bits;
85 if (reg & CMD_SW_RESET) {
86 reg &= ~CMD_SW_RESET;
87 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
88 udelay(2);
89 reg |= CMD_TX_EN | CMD_RX_EN;
90 }
91 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
92 spin_unlock_bh(&priv->reg_lock);
93
94 active = phy_init_eee(phydev, 0) >= 0;
95 bcmgenet_eee_enable_set(dev,
96 priv->eee.eee_enabled && active,
97 priv->eee.tx_lpi_enabled);
98 }
99
100 /* setup netdev link state when PHY link status change and
101 * update UMAC and RGMII block when link up
102 */
bcmgenet_mii_setup(struct net_device * dev)103 void bcmgenet_mii_setup(struct net_device *dev)
104 {
105 struct bcmgenet_priv *priv = netdev_priv(dev);
106 struct phy_device *phydev = dev->phydev;
107 u32 reg;
108
109 if (phydev->link) {
110 bcmgenet_mac_config(dev);
111 } else {
112 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
113 reg &= ~RGMII_LINK;
114 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
115 }
116
117 phy_print_status(phydev);
118 }
119
120
bcmgenet_fixed_phy_link_update(struct net_device * dev,struct fixed_phy_status * status)121 static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
122 struct fixed_phy_status *status)
123 {
124 struct bcmgenet_priv *priv;
125 u32 reg;
126
127 if (dev && dev->phydev && status) {
128 priv = netdev_priv(dev);
129 reg = bcmgenet_umac_readl(priv, UMAC_MODE);
130 status->link = !!(reg & MODE_LINK_STATUS);
131 }
132
133 return 0;
134 }
135
bcmgenet_phy_pause_set(struct net_device * dev,bool rx,bool tx)136 void bcmgenet_phy_pause_set(struct net_device *dev, bool rx, bool tx)
137 {
138 struct phy_device *phydev = dev->phydev;
139
140 linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising, rx);
141 linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising,
142 rx | tx);
143 phy_start_aneg(phydev);
144
145 mutex_lock(&phydev->lock);
146 if (phydev->link)
147 bcmgenet_mac_config(dev);
148 mutex_unlock(&phydev->lock);
149 }
150
bcmgenet_phy_power_set(struct net_device * dev,bool enable)151 void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
152 {
153 struct bcmgenet_priv *priv = netdev_priv(dev);
154 u32 reg = 0;
155
156 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
157 if (GENET_IS_V4(priv) || priv->ephy_16nm) {
158 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
159 if (enable) {
160 reg &= ~EXT_CK25_DIS;
161 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
162 mdelay(1);
163
164 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN |
165 EXT_CFG_IDDQ_GLOBAL_PWR);
166 reg |= EXT_GPHY_RESET;
167 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
168 mdelay(1);
169
170 reg &= ~EXT_GPHY_RESET;
171 } else {
172 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN |
173 EXT_GPHY_RESET | EXT_CFG_IDDQ_GLOBAL_PWR;
174 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
175 mdelay(1);
176 reg |= EXT_CK25_DIS;
177 }
178 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
179 udelay(60);
180 } else {
181 mdelay(1);
182 }
183 }
184
bcmgenet_moca_phy_setup(struct bcmgenet_priv * priv)185 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
186 {
187 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
188 fixed_phy_set_link_update(priv->dev->phydev,
189 bcmgenet_fixed_phy_link_update);
190 }
191
bcmgenet_mii_config(struct net_device * dev,bool init)192 int bcmgenet_mii_config(struct net_device *dev, bool init)
193 {
194 struct bcmgenet_priv *priv = netdev_priv(dev);
195 struct phy_device *phydev = dev->phydev;
196 struct device *kdev = &priv->pdev->dev;
197 const char *phy_name = NULL;
198 u32 id_mode_dis = 0;
199 u32 port_ctrl;
200 u32 reg;
201
202 switch (priv->phy_interface) {
203 case PHY_INTERFACE_MODE_INTERNAL:
204 phy_name = "internal PHY";
205 fallthrough;
206 case PHY_INTERFACE_MODE_MOCA:
207 /* Irrespective of the actually configured PHY speed (100 or
208 * 1000) GENETv4 only has an internal GPHY so we will just end
209 * up masking the Gigabit features from what we support, not
210 * switching to the EPHY
211 */
212 if (GENET_IS_V4(priv))
213 port_ctrl = PORT_MODE_INT_GPHY;
214 else
215 port_ctrl = PORT_MODE_INT_EPHY;
216
217 if (!phy_name) {
218 phy_name = "MoCA";
219 if (!GENET_IS_V5(priv))
220 port_ctrl |= LED_ACT_SOURCE_MAC;
221 bcmgenet_moca_phy_setup(priv);
222 }
223 break;
224
225 case PHY_INTERFACE_MODE_MII:
226 phy_name = "external MII";
227 phy_set_max_speed(phydev, SPEED_100);
228 port_ctrl = PORT_MODE_EXT_EPHY;
229 break;
230
231 case PHY_INTERFACE_MODE_REVMII:
232 phy_name = "external RvMII";
233 /* of_mdiobus_register took care of reading the 'max-speed'
234 * PHY property for us, effectively limiting the PHY supported
235 * capabilities, use that knowledge to also configure the
236 * Reverse MII interface correctly.
237 */
238 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
239 dev->phydev->supported))
240 port_ctrl = PORT_MODE_EXT_RVMII_50;
241 else
242 port_ctrl = PORT_MODE_EXT_RVMII_25;
243 break;
244
245 case PHY_INTERFACE_MODE_RGMII:
246 /* RGMII_NO_ID: TXC transitions at the same time as TXD
247 * (requires PCB or receiver-side delay)
248 *
249 * ID is implicitly disabled for 100Mbps (RG)MII operation.
250 */
251 phy_name = "external RGMII (no delay)";
252 id_mode_dis = BIT(16);
253 port_ctrl = PORT_MODE_EXT_GPHY;
254 break;
255
256 case PHY_INTERFACE_MODE_RGMII_TXID:
257 /* RGMII_TXID: Add 2ns delay on TXC (90 degree shift) */
258 phy_name = "external RGMII (TX delay)";
259 port_ctrl = PORT_MODE_EXT_GPHY;
260 break;
261
262 case PHY_INTERFACE_MODE_RGMII_RXID:
263 phy_name = "external RGMII (RX delay)";
264 port_ctrl = PORT_MODE_EXT_GPHY;
265 break;
266 default:
267 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
268 return -EINVAL;
269 }
270
271 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
272
273 priv->ext_phy = !priv->internal_phy &&
274 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
275
276 /* This is an external PHY (xMII), so we need to enable the RGMII
277 * block for the interface to work, unconditionally clear the
278 * Out-of-band disable since we do not need it.
279 */
280 mutex_lock(&phydev->lock);
281 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
282 reg &= ~OOB_DISABLE;
283 if (priv->ext_phy) {
284 reg &= ~ID_MODE_DIS;
285 reg |= id_mode_dis;
286 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
287 reg |= RGMII_MODE_EN_V123;
288 else
289 reg |= RGMII_MODE_EN;
290 }
291 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
292 mutex_unlock(&phydev->lock);
293
294 if (init)
295 dev_info(kdev, "configuring instance for %s\n", phy_name);
296
297 return 0;
298 }
299
bcmgenet_mii_probe(struct net_device * dev)300 int bcmgenet_mii_probe(struct net_device *dev)
301 {
302 struct bcmgenet_priv *priv = netdev_priv(dev);
303 struct device *kdev = &priv->pdev->dev;
304 struct device_node *dn = kdev->of_node;
305 phy_interface_t phy_iface = priv->phy_interface;
306 struct phy_device *phydev;
307 u32 phy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE |
308 PHY_BRCM_DIS_TXCRXC_NOENRGY |
309 PHY_BRCM_IDDQ_SUSPEND;
310 int ret;
311
312 /* Communicate the integrated PHY revision */
313 if (priv->internal_phy)
314 phy_flags = priv->gphy_rev;
315
316 /* This is an ugly quirk but we have not been correctly interpreting
317 * the phy_interface values and we have done that across different
318 * drivers, so at least we are consistent in our mistakes.
319 *
320 * When the Generic PHY driver is in use either the PHY has been
321 * strapped or programmed correctly by the boot loader so we should
322 * stick to our incorrect interpretation since we have validated it.
323 *
324 * Now when a dedicated PHY driver is in use, we need to reverse the
325 * meaning of the phy_interface_mode values to something that the PHY
326 * driver will interpret and act on such that we have two mistakes
327 * canceling themselves so to speak. We only do this for the two
328 * modes that GENET driver officially supports on Broadcom STB chips:
329 * PHY_INTERFACE_MODE_RGMII and PHY_INTERFACE_MODE_RGMII_TXID. Other
330 * modes are not *officially* supported with the boot loader and the
331 * scripted environment generating Device Tree blobs for those
332 * platforms.
333 *
334 * Note that internal PHY, MoCA and fixed-link configurations are not
335 * affected because they use different phy_interface_t values or the
336 * Generic PHY driver.
337 */
338 switch (priv->phy_interface) {
339 case PHY_INTERFACE_MODE_RGMII:
340 phy_iface = PHY_INTERFACE_MODE_RGMII_ID;
341 break;
342 case PHY_INTERFACE_MODE_RGMII_TXID:
343 phy_iface = PHY_INTERFACE_MODE_RGMII_RXID;
344 break;
345 default:
346 break;
347 }
348
349 if (dn) {
350 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
351 phy_flags, phy_iface);
352 if (!phydev) {
353 pr_err("could not attach to PHY\n");
354 return -ENODEV;
355 }
356 } else {
357 if (has_acpi_companion(kdev)) {
358 char mdio_bus_id[MII_BUS_ID_SIZE];
359 struct mii_bus *unimacbus;
360
361 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
362 UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
363
364 unimacbus = mdio_find_bus(mdio_bus_id);
365 if (!unimacbus) {
366 pr_err("Unable to find mii\n");
367 return -ENODEV;
368 }
369 phydev = phy_find_first(unimacbus);
370 put_device(&unimacbus->dev);
371 if (!phydev) {
372 pr_err("Unable to find PHY\n");
373 return -ENODEV;
374 }
375 } else {
376 phydev = dev->phydev;
377 }
378 phydev->dev_flags = phy_flags;
379
380 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
381 phy_iface);
382 if (ret) {
383 pr_err("could not attach to PHY\n");
384 return -ENODEV;
385 }
386 }
387
388 /* Configure port multiplexer based on what the probed PHY device since
389 * reading the 'max-speed' property determines the maximum supported
390 * PHY speed which is needed for bcmgenet_mii_config() to configure
391 * things appropriately.
392 */
393 ret = bcmgenet_mii_config(dev, true);
394 if (ret) {
395 phy_disconnect(dev->phydev);
396 return ret;
397 }
398
399 /* The internal PHY has its link interrupts routed to the
400 * Ethernet MAC ISRs. On GENETv5 there is a hardware issue
401 * that prevents the signaling of link UP interrupts when
402 * the link operates at 10Mbps, so fallback to polling for
403 * those versions of GENET.
404 */
405 if (priv->internal_phy && !GENET_IS_V5(priv))
406 dev->phydev->irq = PHY_MAC_INTERRUPT;
407
408 /* Indicate that the MAC is responsible for PHY PM */
409 dev->phydev->mac_managed_pm = true;
410
411 return 0;
412 }
413
bcmgenet_mii_of_find_mdio(struct bcmgenet_priv * priv)414 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv)
415 {
416 struct device_node *dn = priv->pdev->dev.of_node;
417 struct device *kdev = &priv->pdev->dev;
418 char *compat;
419
420 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
421 if (!compat)
422 return NULL;
423
424 priv->mdio_dn = of_get_compatible_child(dn, compat);
425 kfree(compat);
426 if (!priv->mdio_dn) {
427 dev_err(kdev, "unable to find MDIO bus node\n");
428 return NULL;
429 }
430
431 return priv->mdio_dn;
432 }
433
bcmgenet_mii_pdata_init(struct bcmgenet_priv * priv,struct unimac_mdio_pdata * ppd)434 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv,
435 struct unimac_mdio_pdata *ppd)
436 {
437 struct device *kdev = &priv->pdev->dev;
438 struct bcmgenet_platform_data *pd = kdev->platform_data;
439
440 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
441 /*
442 * Internal or external PHY with MDIO access
443 */
444 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
445 ppd->phy_mask = 1 << pd->phy_address;
446 else
447 ppd->phy_mask = 0;
448 }
449 }
450
bcmgenet_mii_wait(void * wait_func_data)451 static int bcmgenet_mii_wait(void *wait_func_data)
452 {
453 struct bcmgenet_priv *priv = wait_func_data;
454
455 wait_event_timeout(priv->wq,
456 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
457 & MDIO_START_BUSY),
458 HZ / 100);
459 return 0;
460 }
461
bcmgenet_mii_register(struct bcmgenet_priv * priv)462 static int bcmgenet_mii_register(struct bcmgenet_priv *priv)
463 {
464 struct platform_device *pdev = priv->pdev;
465 struct bcmgenet_platform_data *pdata = pdev->dev.platform_data;
466 struct device_node *dn = pdev->dev.of_node;
467 struct unimac_mdio_pdata ppd;
468 struct platform_device *ppdev;
469 struct resource *pres, res;
470 int id, ret;
471
472 pres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
473 if (!pres) {
474 dev_err(&pdev->dev, "Invalid resource\n");
475 return -EINVAL;
476 }
477 memset(&res, 0, sizeof(res));
478 memset(&ppd, 0, sizeof(ppd));
479
480 ppd.wait_func = bcmgenet_mii_wait;
481 ppd.wait_func_data = priv;
482 ppd.bus_name = "bcmgenet MII bus";
483 /* Pass a reference to our "main" clock which is used for MDIO
484 * transfers
485 */
486 ppd.clk = priv->clk;
487
488 /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD
489 * and is 2 * 32-bits word long, 8 bytes total.
490 */
491 res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD;
492 res.end = res.start + 8;
493 res.flags = IORESOURCE_MEM;
494
495 if (dn)
496 id = of_alias_get_id(dn, "eth");
497 else
498 id = pdev->id;
499
500 ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id);
501 if (!ppdev)
502 return -ENOMEM;
503
504 /* Retain this platform_device pointer for later cleanup */
505 priv->mii_pdev = ppdev;
506 ppdev->dev.parent = &pdev->dev;
507 if (dn)
508 ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv);
509 else if (pdata)
510 bcmgenet_mii_pdata_init(priv, &ppd);
511 else
512 ppd.phy_mask = ~0;
513
514 ret = platform_device_add_resources(ppdev, &res, 1);
515 if (ret)
516 goto out;
517
518 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
519 if (ret)
520 goto out;
521
522 ret = platform_device_add(ppdev);
523 if (ret)
524 goto out;
525
526 return 0;
527 out:
528 platform_device_put(ppdev);
529 return ret;
530 }
531
bcmgenet_phy_interface_init(struct bcmgenet_priv * priv)532 static int bcmgenet_phy_interface_init(struct bcmgenet_priv *priv)
533 {
534 struct device *kdev = &priv->pdev->dev;
535 int phy_mode = device_get_phy_mode(kdev);
536
537 if (phy_mode < 0) {
538 dev_err(kdev, "invalid PHY mode property\n");
539 return phy_mode;
540 }
541
542 priv->phy_interface = phy_mode;
543
544 /* We need to specifically look up whether this PHY interface is
545 * internal or not *before* we even try to probe the PHY driver
546 * over MDIO as we may have shut down the internal PHY for power
547 * saving purposes.
548 */
549 if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL)
550 priv->internal_phy = true;
551
552 return 0;
553 }
554
bcmgenet_mii_of_init(struct bcmgenet_priv * priv)555 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
556 {
557 struct device_node *dn = priv->pdev->dev.of_node;
558 struct phy_device *phydev;
559 int ret;
560
561 /* Fetch the PHY phandle */
562 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
563
564 /* In the case of a fixed PHY, the DT node associated
565 * to the PHY is the Ethernet MAC DT node.
566 */
567 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
568 ret = of_phy_register_fixed_link(dn);
569 if (ret)
570 return ret;
571
572 priv->phy_dn = of_node_get(dn);
573 }
574
575 /* Get the link mode */
576 ret = bcmgenet_phy_interface_init(priv);
577 if (ret)
578 return ret;
579
580 /* Make sure we initialize MoCA PHYs with a link down */
581 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
582 phydev = of_phy_find_device(dn);
583 if (phydev) {
584 phydev->link = 0;
585 put_device(&phydev->mdio.dev);
586 }
587 }
588
589 return 0;
590 }
591
bcmgenet_mii_pd_init(struct bcmgenet_priv * priv)592 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
593 {
594 struct device *kdev = &priv->pdev->dev;
595 struct bcmgenet_platform_data *pd = kdev->platform_data;
596 char phy_name[MII_BUS_ID_SIZE + 3];
597 char mdio_bus_id[MII_BUS_ID_SIZE];
598 struct phy_device *phydev;
599
600 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
601 UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
602
603 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
604 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
605 mdio_bus_id, pd->phy_address);
606
607 /*
608 * Internal or external PHY with MDIO access
609 */
610 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface);
611 if (IS_ERR(phydev)) {
612 dev_err(kdev, "failed to register PHY device\n");
613 return PTR_ERR(phydev);
614 }
615 } else {
616 /*
617 * MoCA port or no MDIO access.
618 * Use fixed PHY to represent the link layer.
619 */
620 struct fixed_phy_status fphy_status = {
621 .link = 1,
622 .speed = pd->phy_speed,
623 .duplex = pd->phy_duplex,
624 .pause = 0,
625 .asym_pause = 0,
626 };
627
628 phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
629 if (IS_ERR(phydev)) {
630 dev_err(kdev, "failed to register fixed PHY device\n");
631 return PTR_ERR(phydev);
632 }
633
634 /* Make sure we initialize MoCA PHYs with a link down */
635 phydev->link = 0;
636
637 }
638
639 priv->phy_interface = pd->phy_interface;
640
641 return 0;
642 }
643
bcmgenet_mii_bus_init(struct bcmgenet_priv * priv)644 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
645 {
646 struct device *kdev = &priv->pdev->dev;
647 struct device_node *dn = kdev->of_node;
648
649 if (dn)
650 return bcmgenet_mii_of_init(priv);
651 else if (has_acpi_companion(kdev))
652 return bcmgenet_phy_interface_init(priv);
653 else
654 return bcmgenet_mii_pd_init(priv);
655 }
656
bcmgenet_mii_init(struct net_device * dev)657 int bcmgenet_mii_init(struct net_device *dev)
658 {
659 struct bcmgenet_priv *priv = netdev_priv(dev);
660 int ret;
661
662 ret = bcmgenet_mii_register(priv);
663 if (ret)
664 return ret;
665
666 ret = bcmgenet_mii_bus_init(priv);
667 if (ret)
668 goto out;
669
670 return 0;
671
672 out:
673 bcmgenet_mii_exit(dev);
674 return ret;
675 }
676
bcmgenet_mii_exit(struct net_device * dev)677 void bcmgenet_mii_exit(struct net_device *dev)
678 {
679 struct bcmgenet_priv *priv = netdev_priv(dev);
680 struct device_node *dn = priv->pdev->dev.of_node;
681
682 if (of_phy_is_fixed_link(dn))
683 of_phy_deregister_fixed_link(dn);
684 of_node_put(priv->phy_dn);
685 platform_device_unregister(priv->mii_pdev);
686 }
687