1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom GENET MDIO routines 4 * 5 * Copyright (c) 2014-2025 Broadcom 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/types.h> 10 #include <linux/delay.h> 11 #include <linux/wait.h> 12 #include <linux/mii.h> 13 #include <linux/ethtool.h> 14 #include <linux/bitops.h> 15 #include <linux/netdevice.h> 16 #include <linux/platform_device.h> 17 #include <linux/phy.h> 18 #include <linux/phy_fixed.h> 19 #include <linux/brcmphy.h> 20 #include <linux/of.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <linux/platform_data/mdio-bcm-unimac.h> 24 25 #include "bcmgenet.h" 26 27 static void bcmgenet_mac_config(struct net_device *dev) 28 { 29 struct bcmgenet_priv *priv = netdev_priv(dev); 30 struct phy_device *phydev = dev->phydev; 31 u32 reg, cmd_bits = 0; 32 bool active; 33 34 /* speed */ 35 if (phydev->speed == SPEED_1000) 36 cmd_bits = CMD_SPEED_1000; 37 else if (phydev->speed == SPEED_100) 38 cmd_bits = CMD_SPEED_100; 39 else 40 cmd_bits = CMD_SPEED_10; 41 cmd_bits <<= CMD_SPEED_SHIFT; 42 43 /* duplex */ 44 if (phydev->duplex != DUPLEX_FULL) { 45 cmd_bits |= CMD_HD_EN | 46 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 47 } else { 48 /* pause capability defaults to Symmetric */ 49 if (priv->autoneg_pause) { 50 bool tx_pause = 0, rx_pause = 0; 51 52 if (phydev->autoneg) 53 phy_get_pause(phydev, &tx_pause, &rx_pause); 54 55 if (!tx_pause) 56 cmd_bits |= CMD_TX_PAUSE_IGNORE; 57 if (!rx_pause) 58 cmd_bits |= CMD_RX_PAUSE_IGNORE; 59 } 60 61 /* Manual override */ 62 if (!priv->rx_pause) 63 cmd_bits |= CMD_RX_PAUSE_IGNORE; 64 if (!priv->tx_pause) 65 cmd_bits |= CMD_TX_PAUSE_IGNORE; 66 } 67 68 /* Program UMAC and RGMII block based on established 69 * link speed, duplex, and pause. The speed set in 70 * umac->cmd tell RGMII block which clock to use for 71 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). 72 * Receive clock is provided by the PHY. 73 */ 74 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 75 reg |= RGMII_LINK; 76 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 77 78 spin_lock_bh(&priv->reg_lock); 79 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 80 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 81 CMD_HD_EN | 82 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); 83 reg |= cmd_bits; 84 if (reg & CMD_SW_RESET) { 85 reg &= ~CMD_SW_RESET; 86 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 87 udelay(2); 88 reg |= CMD_TX_EN | CMD_RX_EN; 89 } 90 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 91 spin_unlock_bh(&priv->reg_lock); 92 93 active = phy_init_eee(phydev, 0) >= 0; 94 bcmgenet_eee_enable_set(dev, 95 priv->eee.eee_enabled && active, 96 priv->eee.tx_lpi_enabled); 97 } 98 99 /* setup netdev link state when PHY link status change and 100 * update UMAC and RGMII block when link up 101 */ 102 void bcmgenet_mii_setup(struct net_device *dev) 103 { 104 struct bcmgenet_priv *priv = netdev_priv(dev); 105 struct phy_device *phydev = dev->phydev; 106 u32 reg; 107 108 if (phydev->link) { 109 bcmgenet_mac_config(dev); 110 } else { 111 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 112 reg &= ~RGMII_LINK; 113 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 114 } 115 116 phy_print_status(phydev); 117 } 118 119 120 static int bcmgenet_fixed_phy_link_update(struct net_device *dev, 121 struct fixed_phy_status *status) 122 { 123 struct bcmgenet_priv *priv; 124 u32 reg; 125 126 if (dev && dev->phydev && status) { 127 priv = netdev_priv(dev); 128 reg = bcmgenet_umac_readl(priv, UMAC_MODE); 129 status->link = !!(reg & MODE_LINK_STATUS); 130 } 131 132 return 0; 133 } 134 135 void bcmgenet_phy_pause_set(struct net_device *dev, bool rx, bool tx) 136 { 137 struct phy_device *phydev = dev->phydev; 138 139 linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising, rx); 140 linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising, 141 rx | tx); 142 phy_start_aneg(phydev); 143 144 mutex_lock(&phydev->lock); 145 if (phydev->link) 146 bcmgenet_mac_config(dev); 147 mutex_unlock(&phydev->lock); 148 } 149 150 void bcmgenet_phy_power_set(struct net_device *dev, bool enable) 151 { 152 struct bcmgenet_priv *priv = netdev_priv(dev); 153 u32 reg = 0; 154 155 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ 156 if (GENET_IS_V4(priv) || bcmgenet_has_ephy_16nm(priv)) { 157 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); 158 if (enable) { 159 reg &= ~EXT_CK25_DIS; 160 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 161 mdelay(1); 162 163 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | 164 EXT_CFG_IDDQ_GLOBAL_PWR); 165 reg |= EXT_GPHY_RESET; 166 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 167 mdelay(1); 168 169 reg &= ~EXT_GPHY_RESET; 170 } else { 171 reg |= EXT_GPHY_RESET; 172 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 173 mdelay(1); 174 175 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | 176 EXT_CFG_IDDQ_GLOBAL_PWR; 177 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 178 mdelay(1); 179 180 reg |= EXT_CK25_DIS; 181 } 182 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 183 udelay(60); 184 } else { 185 mdelay(1); 186 } 187 } 188 189 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) 190 { 191 if (bcmgenet_has_moca_link_det(priv)) 192 fixed_phy_set_link_update(priv->dev->phydev, 193 bcmgenet_fixed_phy_link_update); 194 } 195 196 int bcmgenet_mii_config(struct net_device *dev, bool init) 197 { 198 struct bcmgenet_priv *priv = netdev_priv(dev); 199 struct phy_device *phydev = dev->phydev; 200 struct device *kdev = &priv->pdev->dev; 201 const char *phy_name = NULL; 202 u32 id_mode_dis = 0; 203 u32 port_ctrl; 204 u32 reg; 205 206 switch (priv->phy_interface) { 207 case PHY_INTERFACE_MODE_INTERNAL: 208 phy_name = "internal PHY"; 209 fallthrough; 210 case PHY_INTERFACE_MODE_MOCA: 211 /* Irrespective of the actually configured PHY speed (100 or 212 * 1000) GENETv4 only has an internal GPHY so we will just end 213 * up masking the Gigabit features from what we support, not 214 * switching to the EPHY 215 */ 216 if (GENET_IS_V4(priv)) 217 port_ctrl = PORT_MODE_INT_GPHY; 218 else 219 port_ctrl = PORT_MODE_INT_EPHY; 220 221 if (!phy_name) { 222 phy_name = "MoCA"; 223 if (!GENET_IS_V5(priv)) 224 port_ctrl |= LED_ACT_SOURCE_MAC; 225 bcmgenet_moca_phy_setup(priv); 226 } 227 break; 228 229 case PHY_INTERFACE_MODE_MII: 230 phy_name = "external MII"; 231 phy_set_max_speed(phydev, SPEED_100); 232 port_ctrl = PORT_MODE_EXT_EPHY; 233 break; 234 235 case PHY_INTERFACE_MODE_REVMII: 236 phy_name = "external RvMII"; 237 /* of_mdiobus_register took care of reading the 'max-speed' 238 * PHY property for us, effectively limiting the PHY supported 239 * capabilities, use that knowledge to also configure the 240 * Reverse MII interface correctly. 241 */ 242 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 243 dev->phydev->supported)) 244 port_ctrl = PORT_MODE_EXT_RVMII_50; 245 else 246 port_ctrl = PORT_MODE_EXT_RVMII_25; 247 break; 248 249 case PHY_INTERFACE_MODE_RGMII: 250 /* RGMII_NO_ID: TXC transitions at the same time as TXD 251 * (requires PCB or receiver-side delay) 252 * 253 * ID is implicitly disabled for 100Mbps (RG)MII operation. 254 */ 255 phy_name = "external RGMII (no delay)"; 256 id_mode_dis = BIT(16); 257 port_ctrl = PORT_MODE_EXT_GPHY; 258 break; 259 260 case PHY_INTERFACE_MODE_RGMII_TXID: 261 /* RGMII_TXID: Add 2ns delay on TXC (90 degree shift) */ 262 phy_name = "external RGMII (TX delay)"; 263 port_ctrl = PORT_MODE_EXT_GPHY; 264 break; 265 266 case PHY_INTERFACE_MODE_RGMII_RXID: 267 phy_name = "external RGMII (RX delay)"; 268 port_ctrl = PORT_MODE_EXT_GPHY; 269 break; 270 default: 271 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); 272 return -EINVAL; 273 } 274 275 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 276 277 priv->ext_phy = !priv->internal_phy && 278 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); 279 280 /* This is an external PHY (xMII), so we need to enable the RGMII 281 * block for the interface to work, unconditionally clear the 282 * Out-of-band disable since we do not need it. 283 */ 284 mutex_lock(&phydev->lock); 285 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 286 reg &= ~OOB_DISABLE; 287 if (priv->ext_phy) { 288 reg &= ~ID_MODE_DIS; 289 reg |= id_mode_dis; 290 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 291 reg |= RGMII_MODE_EN_V123; 292 else 293 reg |= RGMII_MODE_EN; 294 } 295 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 296 mutex_unlock(&phydev->lock); 297 298 if (init) 299 dev_info(kdev, "configuring instance for %s\n", phy_name); 300 301 return 0; 302 } 303 304 int bcmgenet_mii_probe(struct net_device *dev) 305 { 306 struct bcmgenet_priv *priv = netdev_priv(dev); 307 struct device *kdev = &priv->pdev->dev; 308 struct device_node *dn = kdev->of_node; 309 phy_interface_t phy_iface = priv->phy_interface; 310 struct phy_device *phydev; 311 u32 phy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE | 312 PHY_BRCM_DIS_TXCRXC_NOENRGY | 313 PHY_BRCM_IDDQ_SUSPEND; 314 int ret; 315 316 /* Communicate the integrated PHY revision */ 317 if (priv->internal_phy) 318 phy_flags = priv->gphy_rev; 319 320 /* This is an ugly quirk but we have not been correctly interpreting 321 * the phy_interface values and we have done that across different 322 * drivers, so at least we are consistent in our mistakes. 323 * 324 * When the Generic PHY driver is in use either the PHY has been 325 * strapped or programmed correctly by the boot loader so we should 326 * stick to our incorrect interpretation since we have validated it. 327 * 328 * Now when a dedicated PHY driver is in use, we need to reverse the 329 * meaning of the phy_interface_mode values to something that the PHY 330 * driver will interpret and act on such that we have two mistakes 331 * canceling themselves so to speak. We only do this for the two 332 * modes that GENET driver officially supports on Broadcom STB chips: 333 * PHY_INTERFACE_MODE_RGMII and PHY_INTERFACE_MODE_RGMII_TXID. Other 334 * modes are not *officially* supported with the boot loader and the 335 * scripted environment generating Device Tree blobs for those 336 * platforms. 337 * 338 * Note that internal PHY, MoCA and fixed-link configurations are not 339 * affected because they use different phy_interface_t values or the 340 * Generic PHY driver. 341 */ 342 switch (priv->phy_interface) { 343 case PHY_INTERFACE_MODE_RGMII: 344 phy_iface = PHY_INTERFACE_MODE_RGMII_ID; 345 break; 346 case PHY_INTERFACE_MODE_RGMII_TXID: 347 phy_iface = PHY_INTERFACE_MODE_RGMII_RXID; 348 break; 349 default: 350 break; 351 } 352 353 if (dn) { 354 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, 355 phy_flags, phy_iface); 356 if (!phydev) { 357 pr_err("could not attach to PHY\n"); 358 return -ENODEV; 359 } 360 } else { 361 if (has_acpi_companion(kdev)) { 362 char mdio_bus_id[MII_BUS_ID_SIZE]; 363 struct mii_bus *unimacbus; 364 365 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d", 366 UNIMAC_MDIO_DRV_NAME, priv->pdev->id); 367 368 unimacbus = mdio_find_bus(mdio_bus_id); 369 if (!unimacbus) { 370 pr_err("Unable to find mii\n"); 371 return -ENODEV; 372 } 373 phydev = phy_find_first(unimacbus); 374 put_device(&unimacbus->dev); 375 if (!phydev) { 376 pr_err("Unable to find PHY\n"); 377 return -ENODEV; 378 } 379 } else { 380 phydev = dev->phydev; 381 } 382 phydev->dev_flags = phy_flags; 383 384 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup, 385 phy_iface); 386 if (ret) { 387 pr_err("could not attach to PHY\n"); 388 return -ENODEV; 389 } 390 } 391 392 /* Configure port multiplexer based on what the probed PHY device since 393 * reading the 'max-speed' property determines the maximum supported 394 * PHY speed which is needed for bcmgenet_mii_config() to configure 395 * things appropriately. 396 */ 397 ret = bcmgenet_mii_config(dev, true); 398 if (ret) { 399 phy_disconnect(dev->phydev); 400 return ret; 401 } 402 403 /* The internal PHY has its link interrupts routed to the 404 * Ethernet MAC ISRs. On GENETv5 there is a hardware issue 405 * that prevents the signaling of link UP interrupts when 406 * the link operates at 10Mbps, so fallback to polling for 407 * those versions of GENET. 408 */ 409 if (priv->internal_phy && !GENET_IS_V5(priv)) 410 dev->phydev->irq = PHY_MAC_INTERRUPT; 411 412 /* Indicate that the MAC is responsible for PHY PM */ 413 dev->phydev->mac_managed_pm = true; 414 415 return 0; 416 } 417 418 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv) 419 { 420 struct device_node *dn = priv->pdev->dev.of_node; 421 struct device *kdev = &priv->pdev->dev; 422 char *compat; 423 424 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); 425 if (!compat) 426 return NULL; 427 428 priv->mdio_dn = of_get_compatible_child(dn, compat); 429 kfree(compat); 430 if (!priv->mdio_dn) { 431 dev_err(kdev, "unable to find MDIO bus node\n"); 432 return NULL; 433 } 434 435 return priv->mdio_dn; 436 } 437 438 static int bcmgenet_mii_wait(void *wait_func_data) 439 { 440 struct bcmgenet_priv *priv = wait_func_data; 441 442 wait_event_timeout(priv->wq, 443 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) 444 & MDIO_START_BUSY), 445 HZ / 100); 446 return 0; 447 } 448 449 static int bcmgenet_mii_register(struct bcmgenet_priv *priv) 450 { 451 struct platform_device *pdev = priv->pdev; 452 struct device_node *dn = pdev->dev.of_node; 453 struct unimac_mdio_pdata ppd; 454 struct platform_device *ppdev; 455 struct resource *pres, res; 456 int id, ret; 457 458 pres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 459 if (!pres) { 460 dev_err(&pdev->dev, "Invalid resource\n"); 461 return -EINVAL; 462 } 463 memset(&res, 0, sizeof(res)); 464 memset(&ppd, 0, sizeof(ppd)); 465 466 ppd.wait_func = bcmgenet_mii_wait; 467 ppd.wait_func_data = priv; 468 ppd.bus_name = "bcmgenet MII bus"; 469 /* Pass a reference to our "main" clock which is used for MDIO 470 * transfers 471 */ 472 ppd.clk = priv->clk; 473 474 /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD 475 * and is 2 * 32-bits word long, 8 bytes total. 476 */ 477 res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD; 478 res.end = res.start + 8; 479 res.flags = IORESOURCE_MEM; 480 481 if (dn) 482 id = of_alias_get_id(dn, "eth"); 483 else 484 id = pdev->id; 485 486 ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id); 487 if (!ppdev) 488 return -ENOMEM; 489 490 /* Retain this platform_device pointer for later cleanup */ 491 priv->mii_pdev = ppdev; 492 ppdev->dev.parent = &pdev->dev; 493 if (dn) 494 ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv); 495 else 496 ppd.phy_mask = ~0; 497 498 ret = platform_device_add_resources(ppdev, &res, 1); 499 if (ret) 500 goto out; 501 502 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd)); 503 if (ret) 504 goto out; 505 506 ret = platform_device_add(ppdev); 507 if (ret) 508 goto out; 509 510 return 0; 511 out: 512 platform_device_put(ppdev); 513 return ret; 514 } 515 516 static int bcmgenet_phy_interface_init(struct bcmgenet_priv *priv) 517 { 518 struct device *kdev = &priv->pdev->dev; 519 int phy_mode = device_get_phy_mode(kdev); 520 521 if (phy_mode < 0) { 522 dev_err(kdev, "invalid PHY mode property\n"); 523 return phy_mode; 524 } 525 526 priv->phy_interface = phy_mode; 527 528 /* We need to specifically look up whether this PHY interface is 529 * internal or not *before* we even try to probe the PHY driver 530 * over MDIO as we may have shut down the internal PHY for power 531 * saving purposes. 532 */ 533 if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 534 priv->internal_phy = true; 535 536 return 0; 537 } 538 539 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) 540 { 541 struct device_node *dn = priv->pdev->dev.of_node; 542 struct phy_device *phydev; 543 int ret; 544 545 /* Fetch the PHY phandle */ 546 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); 547 548 /* In the case of a fixed PHY, the DT node associated 549 * to the PHY is the Ethernet MAC DT node. 550 */ 551 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { 552 ret = of_phy_register_fixed_link(dn); 553 if (ret) 554 return ret; 555 556 priv->phy_dn = of_node_get(dn); 557 } 558 559 /* Get the link mode */ 560 ret = bcmgenet_phy_interface_init(priv); 561 if (ret) 562 return ret; 563 564 /* Make sure we initialize MoCA PHYs with a link down */ 565 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 566 phydev = of_phy_find_device(dn); 567 if (phydev) { 568 phydev->link = 0; 569 put_device(&phydev->mdio.dev); 570 } 571 } 572 573 return 0; 574 } 575 576 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) 577 { 578 struct device *kdev = &priv->pdev->dev; 579 struct device_node *dn = kdev->of_node; 580 581 if (dn) 582 return bcmgenet_mii_of_init(priv); 583 else if (has_acpi_companion(kdev)) 584 return bcmgenet_phy_interface_init(priv); 585 else 586 return -EINVAL; 587 } 588 589 int bcmgenet_mii_init(struct net_device *dev) 590 { 591 struct bcmgenet_priv *priv = netdev_priv(dev); 592 int ret; 593 594 ret = bcmgenet_mii_register(priv); 595 if (ret) 596 return ret; 597 598 ret = bcmgenet_mii_bus_init(priv); 599 if (ret) 600 goto out; 601 602 return 0; 603 604 out: 605 bcmgenet_mii_exit(dev); 606 return ret; 607 } 608 609 void bcmgenet_mii_exit(struct net_device *dev) 610 { 611 struct bcmgenet_priv *priv = netdev_priv(dev); 612 struct device_node *dn = priv->pdev->dev.of_node; 613 614 if (of_phy_is_fixed_link(dn)) 615 of_phy_deregister_fixed_link(dn); 616 of_node_put(priv->phy_dn); 617 platform_device_unregister(priv->mii_pdev); 618 } 619