1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Broadcom GENET MDIO routines
4 *
5 * Copyright (c) 2014-2025 Broadcom
6 */
7
8 #include <linux/acpi.h>
9 #include <linux/types.h>
10 #include <linux/delay.h>
11 #include <linux/wait.h>
12 #include <linux/mii.h>
13 #include <linux/ethtool.h>
14 #include <linux/bitops.h>
15 #include <linux/netdevice.h>
16 #include <linux/platform_device.h>
17 #include <linux/phy.h>
18 #include <linux/phy_fixed.h>
19 #include <linux/brcmphy.h>
20 #include <linux/of.h>
21 #include <linux/of_net.h>
22 #include <linux/of_mdio.h>
23 #include <linux/platform_data/bcmgenet.h>
24 #include <linux/platform_data/mdio-bcm-unimac.h>
25
26 #include "bcmgenet.h"
27
bcmgenet_mac_config(struct net_device * dev)28 static void bcmgenet_mac_config(struct net_device *dev)
29 {
30 struct bcmgenet_priv *priv = netdev_priv(dev);
31 struct phy_device *phydev = dev->phydev;
32 u32 reg, cmd_bits = 0;
33 bool active;
34
35 /* speed */
36 if (phydev->speed == SPEED_1000)
37 cmd_bits = CMD_SPEED_1000;
38 else if (phydev->speed == SPEED_100)
39 cmd_bits = CMD_SPEED_100;
40 else
41 cmd_bits = CMD_SPEED_10;
42 cmd_bits <<= CMD_SPEED_SHIFT;
43
44 /* duplex */
45 if (phydev->duplex != DUPLEX_FULL) {
46 cmd_bits |= CMD_HD_EN |
47 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
48 } else {
49 /* pause capability defaults to Symmetric */
50 if (priv->autoneg_pause) {
51 bool tx_pause = 0, rx_pause = 0;
52
53 if (phydev->autoneg)
54 phy_get_pause(phydev, &tx_pause, &rx_pause);
55
56 if (!tx_pause)
57 cmd_bits |= CMD_TX_PAUSE_IGNORE;
58 if (!rx_pause)
59 cmd_bits |= CMD_RX_PAUSE_IGNORE;
60 }
61
62 /* Manual override */
63 if (!priv->rx_pause)
64 cmd_bits |= CMD_RX_PAUSE_IGNORE;
65 if (!priv->tx_pause)
66 cmd_bits |= CMD_TX_PAUSE_IGNORE;
67 }
68
69 /* Program UMAC and RGMII block based on established
70 * link speed, duplex, and pause. The speed set in
71 * umac->cmd tell RGMII block which clock to use for
72 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
73 * Receive clock is provided by the PHY.
74 */
75 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
76 reg |= RGMII_LINK;
77 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
78
79 spin_lock_bh(&priv->reg_lock);
80 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
81 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
82 CMD_HD_EN |
83 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
84 reg |= cmd_bits;
85 if (reg & CMD_SW_RESET) {
86 reg &= ~CMD_SW_RESET;
87 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
88 udelay(2);
89 reg |= CMD_TX_EN | CMD_RX_EN;
90 }
91 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
92 spin_unlock_bh(&priv->reg_lock);
93
94 active = phy_init_eee(phydev, 0) >= 0;
95 bcmgenet_eee_enable_set(dev,
96 priv->eee.eee_enabled && active,
97 priv->eee.tx_lpi_enabled);
98 }
99
100 /* setup netdev link state when PHY link status change and
101 * update UMAC and RGMII block when link up
102 */
bcmgenet_mii_setup(struct net_device * dev)103 void bcmgenet_mii_setup(struct net_device *dev)
104 {
105 struct bcmgenet_priv *priv = netdev_priv(dev);
106 struct phy_device *phydev = dev->phydev;
107 u32 reg;
108
109 if (phydev->link) {
110 bcmgenet_mac_config(dev);
111 } else {
112 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
113 reg &= ~RGMII_LINK;
114 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
115 }
116
117 phy_print_status(phydev);
118 }
119
120
bcmgenet_fixed_phy_link_update(struct net_device * dev,struct fixed_phy_status * status)121 static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
122 struct fixed_phy_status *status)
123 {
124 struct bcmgenet_priv *priv;
125 u32 reg;
126
127 if (dev && dev->phydev && status) {
128 priv = netdev_priv(dev);
129 reg = bcmgenet_umac_readl(priv, UMAC_MODE);
130 status->link = !!(reg & MODE_LINK_STATUS);
131 }
132
133 return 0;
134 }
135
bcmgenet_phy_pause_set(struct net_device * dev,bool rx,bool tx)136 void bcmgenet_phy_pause_set(struct net_device *dev, bool rx, bool tx)
137 {
138 struct phy_device *phydev = dev->phydev;
139
140 linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising, rx);
141 linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising,
142 rx | tx);
143 phy_start_aneg(phydev);
144
145 mutex_lock(&phydev->lock);
146 if (phydev->link)
147 bcmgenet_mac_config(dev);
148 mutex_unlock(&phydev->lock);
149 }
150
bcmgenet_phy_power_set(struct net_device * dev,bool enable)151 void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
152 {
153 struct bcmgenet_priv *priv = netdev_priv(dev);
154 u32 reg = 0;
155
156 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
157 if (GENET_IS_V4(priv) || bcmgenet_has_ephy_16nm(priv)) {
158 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
159 if (enable) {
160 reg &= ~EXT_CK25_DIS;
161 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
162 mdelay(1);
163
164 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN |
165 EXT_CFG_IDDQ_GLOBAL_PWR);
166 reg |= EXT_GPHY_RESET;
167 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
168 mdelay(1);
169
170 reg &= ~EXT_GPHY_RESET;
171 } else {
172 reg |= EXT_GPHY_RESET;
173 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
174 mdelay(1);
175
176 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN |
177 EXT_CFG_IDDQ_GLOBAL_PWR;
178 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
179 mdelay(1);
180
181 reg |= EXT_CK25_DIS;
182 }
183 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
184 udelay(60);
185 } else {
186 mdelay(1);
187 }
188 }
189
bcmgenet_moca_phy_setup(struct bcmgenet_priv * priv)190 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
191 {
192 if (bcmgenet_has_moca_link_det(priv))
193 fixed_phy_set_link_update(priv->dev->phydev,
194 bcmgenet_fixed_phy_link_update);
195 }
196
bcmgenet_mii_config(struct net_device * dev,bool init)197 int bcmgenet_mii_config(struct net_device *dev, bool init)
198 {
199 struct bcmgenet_priv *priv = netdev_priv(dev);
200 struct phy_device *phydev = dev->phydev;
201 struct device *kdev = &priv->pdev->dev;
202 const char *phy_name = NULL;
203 u32 id_mode_dis = 0;
204 u32 port_ctrl;
205 u32 reg;
206
207 switch (priv->phy_interface) {
208 case PHY_INTERFACE_MODE_INTERNAL:
209 phy_name = "internal PHY";
210 fallthrough;
211 case PHY_INTERFACE_MODE_MOCA:
212 /* Irrespective of the actually configured PHY speed (100 or
213 * 1000) GENETv4 only has an internal GPHY so we will just end
214 * up masking the Gigabit features from what we support, not
215 * switching to the EPHY
216 */
217 if (GENET_IS_V4(priv))
218 port_ctrl = PORT_MODE_INT_GPHY;
219 else
220 port_ctrl = PORT_MODE_INT_EPHY;
221
222 if (!phy_name) {
223 phy_name = "MoCA";
224 if (!GENET_IS_V5(priv))
225 port_ctrl |= LED_ACT_SOURCE_MAC;
226 bcmgenet_moca_phy_setup(priv);
227 }
228 break;
229
230 case PHY_INTERFACE_MODE_MII:
231 phy_name = "external MII";
232 phy_set_max_speed(phydev, SPEED_100);
233 port_ctrl = PORT_MODE_EXT_EPHY;
234 break;
235
236 case PHY_INTERFACE_MODE_REVMII:
237 phy_name = "external RvMII";
238 /* of_mdiobus_register took care of reading the 'max-speed'
239 * PHY property for us, effectively limiting the PHY supported
240 * capabilities, use that knowledge to also configure the
241 * Reverse MII interface correctly.
242 */
243 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
244 dev->phydev->supported))
245 port_ctrl = PORT_MODE_EXT_RVMII_50;
246 else
247 port_ctrl = PORT_MODE_EXT_RVMII_25;
248 break;
249
250 case PHY_INTERFACE_MODE_RGMII:
251 /* RGMII_NO_ID: TXC transitions at the same time as TXD
252 * (requires PCB or receiver-side delay)
253 *
254 * ID is implicitly disabled for 100Mbps (RG)MII operation.
255 */
256 phy_name = "external RGMII (no delay)";
257 id_mode_dis = BIT(16);
258 port_ctrl = PORT_MODE_EXT_GPHY;
259 break;
260
261 case PHY_INTERFACE_MODE_RGMII_TXID:
262 /* RGMII_TXID: Add 2ns delay on TXC (90 degree shift) */
263 phy_name = "external RGMII (TX delay)";
264 port_ctrl = PORT_MODE_EXT_GPHY;
265 break;
266
267 case PHY_INTERFACE_MODE_RGMII_RXID:
268 phy_name = "external RGMII (RX delay)";
269 port_ctrl = PORT_MODE_EXT_GPHY;
270 break;
271 default:
272 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
273 return -EINVAL;
274 }
275
276 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
277
278 priv->ext_phy = !priv->internal_phy &&
279 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
280
281 /* This is an external PHY (xMII), so we need to enable the RGMII
282 * block for the interface to work, unconditionally clear the
283 * Out-of-band disable since we do not need it.
284 */
285 mutex_lock(&phydev->lock);
286 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
287 reg &= ~OOB_DISABLE;
288 if (priv->ext_phy) {
289 reg &= ~ID_MODE_DIS;
290 reg |= id_mode_dis;
291 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
292 reg |= RGMII_MODE_EN_V123;
293 else
294 reg |= RGMII_MODE_EN;
295 }
296 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
297 mutex_unlock(&phydev->lock);
298
299 if (init)
300 dev_info(kdev, "configuring instance for %s\n", phy_name);
301
302 return 0;
303 }
304
bcmgenet_mii_probe(struct net_device * dev)305 int bcmgenet_mii_probe(struct net_device *dev)
306 {
307 struct bcmgenet_priv *priv = netdev_priv(dev);
308 struct device *kdev = &priv->pdev->dev;
309 struct device_node *dn = kdev->of_node;
310 phy_interface_t phy_iface = priv->phy_interface;
311 struct phy_device *phydev;
312 u32 phy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE |
313 PHY_BRCM_DIS_TXCRXC_NOENRGY |
314 PHY_BRCM_IDDQ_SUSPEND;
315 int ret;
316
317 /* Communicate the integrated PHY revision */
318 if (priv->internal_phy)
319 phy_flags = priv->gphy_rev;
320
321 /* This is an ugly quirk but we have not been correctly interpreting
322 * the phy_interface values and we have done that across different
323 * drivers, so at least we are consistent in our mistakes.
324 *
325 * When the Generic PHY driver is in use either the PHY has been
326 * strapped or programmed correctly by the boot loader so we should
327 * stick to our incorrect interpretation since we have validated it.
328 *
329 * Now when a dedicated PHY driver is in use, we need to reverse the
330 * meaning of the phy_interface_mode values to something that the PHY
331 * driver will interpret and act on such that we have two mistakes
332 * canceling themselves so to speak. We only do this for the two
333 * modes that GENET driver officially supports on Broadcom STB chips:
334 * PHY_INTERFACE_MODE_RGMII and PHY_INTERFACE_MODE_RGMII_TXID. Other
335 * modes are not *officially* supported with the boot loader and the
336 * scripted environment generating Device Tree blobs for those
337 * platforms.
338 *
339 * Note that internal PHY, MoCA and fixed-link configurations are not
340 * affected because they use different phy_interface_t values or the
341 * Generic PHY driver.
342 */
343 switch (priv->phy_interface) {
344 case PHY_INTERFACE_MODE_RGMII:
345 phy_iface = PHY_INTERFACE_MODE_RGMII_ID;
346 break;
347 case PHY_INTERFACE_MODE_RGMII_TXID:
348 phy_iface = PHY_INTERFACE_MODE_RGMII_RXID;
349 break;
350 default:
351 break;
352 }
353
354 if (dn) {
355 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
356 phy_flags, phy_iface);
357 if (!phydev) {
358 pr_err("could not attach to PHY\n");
359 return -ENODEV;
360 }
361 } else {
362 if (has_acpi_companion(kdev)) {
363 char mdio_bus_id[MII_BUS_ID_SIZE];
364 struct mii_bus *unimacbus;
365
366 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
367 UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
368
369 unimacbus = mdio_find_bus(mdio_bus_id);
370 if (!unimacbus) {
371 pr_err("Unable to find mii\n");
372 return -ENODEV;
373 }
374 phydev = phy_find_first(unimacbus);
375 put_device(&unimacbus->dev);
376 if (!phydev) {
377 pr_err("Unable to find PHY\n");
378 return -ENODEV;
379 }
380 } else {
381 phydev = dev->phydev;
382 }
383 phydev->dev_flags = phy_flags;
384
385 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
386 phy_iface);
387 if (ret) {
388 pr_err("could not attach to PHY\n");
389 return -ENODEV;
390 }
391 }
392
393 /* Configure port multiplexer based on what the probed PHY device since
394 * reading the 'max-speed' property determines the maximum supported
395 * PHY speed which is needed for bcmgenet_mii_config() to configure
396 * things appropriately.
397 */
398 ret = bcmgenet_mii_config(dev, true);
399 if (ret) {
400 phy_disconnect(dev->phydev);
401 return ret;
402 }
403
404 /* The internal PHY has its link interrupts routed to the
405 * Ethernet MAC ISRs. On GENETv5 there is a hardware issue
406 * that prevents the signaling of link UP interrupts when
407 * the link operates at 10Mbps, so fallback to polling for
408 * those versions of GENET.
409 */
410 if (priv->internal_phy && !GENET_IS_V5(priv))
411 dev->phydev->irq = PHY_MAC_INTERRUPT;
412
413 /* Indicate that the MAC is responsible for PHY PM */
414 dev->phydev->mac_managed_pm = true;
415
416 return 0;
417 }
418
bcmgenet_mii_of_find_mdio(struct bcmgenet_priv * priv)419 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv)
420 {
421 struct device_node *dn = priv->pdev->dev.of_node;
422 struct device *kdev = &priv->pdev->dev;
423 char *compat;
424
425 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
426 if (!compat)
427 return NULL;
428
429 priv->mdio_dn = of_get_compatible_child(dn, compat);
430 kfree(compat);
431 if (!priv->mdio_dn) {
432 dev_err(kdev, "unable to find MDIO bus node\n");
433 return NULL;
434 }
435
436 return priv->mdio_dn;
437 }
438
bcmgenet_mii_pdata_init(struct bcmgenet_priv * priv,struct unimac_mdio_pdata * ppd)439 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv,
440 struct unimac_mdio_pdata *ppd)
441 {
442 struct device *kdev = &priv->pdev->dev;
443 struct bcmgenet_platform_data *pd = kdev->platform_data;
444
445 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
446 /*
447 * Internal or external PHY with MDIO access
448 */
449 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
450 ppd->phy_mask = 1 << pd->phy_address;
451 else
452 ppd->phy_mask = 0;
453 }
454 }
455
bcmgenet_mii_wait(void * wait_func_data)456 static int bcmgenet_mii_wait(void *wait_func_data)
457 {
458 struct bcmgenet_priv *priv = wait_func_data;
459
460 wait_event_timeout(priv->wq,
461 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
462 & MDIO_START_BUSY),
463 HZ / 100);
464 return 0;
465 }
466
bcmgenet_mii_register(struct bcmgenet_priv * priv)467 static int bcmgenet_mii_register(struct bcmgenet_priv *priv)
468 {
469 struct platform_device *pdev = priv->pdev;
470 struct bcmgenet_platform_data *pdata = pdev->dev.platform_data;
471 struct device_node *dn = pdev->dev.of_node;
472 struct unimac_mdio_pdata ppd;
473 struct platform_device *ppdev;
474 struct resource *pres, res;
475 int id, ret;
476
477 pres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
478 if (!pres) {
479 dev_err(&pdev->dev, "Invalid resource\n");
480 return -EINVAL;
481 }
482 memset(&res, 0, sizeof(res));
483 memset(&ppd, 0, sizeof(ppd));
484
485 ppd.wait_func = bcmgenet_mii_wait;
486 ppd.wait_func_data = priv;
487 ppd.bus_name = "bcmgenet MII bus";
488 /* Pass a reference to our "main" clock which is used for MDIO
489 * transfers
490 */
491 ppd.clk = priv->clk;
492
493 /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD
494 * and is 2 * 32-bits word long, 8 bytes total.
495 */
496 res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD;
497 res.end = res.start + 8;
498 res.flags = IORESOURCE_MEM;
499
500 if (dn)
501 id = of_alias_get_id(dn, "eth");
502 else
503 id = pdev->id;
504
505 ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id);
506 if (!ppdev)
507 return -ENOMEM;
508
509 /* Retain this platform_device pointer for later cleanup */
510 priv->mii_pdev = ppdev;
511 ppdev->dev.parent = &pdev->dev;
512 if (dn)
513 ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv);
514 else if (pdata)
515 bcmgenet_mii_pdata_init(priv, &ppd);
516 else
517 ppd.phy_mask = ~0;
518
519 ret = platform_device_add_resources(ppdev, &res, 1);
520 if (ret)
521 goto out;
522
523 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
524 if (ret)
525 goto out;
526
527 ret = platform_device_add(ppdev);
528 if (ret)
529 goto out;
530
531 return 0;
532 out:
533 platform_device_put(ppdev);
534 return ret;
535 }
536
bcmgenet_phy_interface_init(struct bcmgenet_priv * priv)537 static int bcmgenet_phy_interface_init(struct bcmgenet_priv *priv)
538 {
539 struct device *kdev = &priv->pdev->dev;
540 int phy_mode = device_get_phy_mode(kdev);
541
542 if (phy_mode < 0) {
543 dev_err(kdev, "invalid PHY mode property\n");
544 return phy_mode;
545 }
546
547 priv->phy_interface = phy_mode;
548
549 /* We need to specifically look up whether this PHY interface is
550 * internal or not *before* we even try to probe the PHY driver
551 * over MDIO as we may have shut down the internal PHY for power
552 * saving purposes.
553 */
554 if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL)
555 priv->internal_phy = true;
556
557 return 0;
558 }
559
bcmgenet_mii_of_init(struct bcmgenet_priv * priv)560 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
561 {
562 struct device_node *dn = priv->pdev->dev.of_node;
563 struct phy_device *phydev;
564 int ret;
565
566 /* Fetch the PHY phandle */
567 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
568
569 /* In the case of a fixed PHY, the DT node associated
570 * to the PHY is the Ethernet MAC DT node.
571 */
572 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
573 ret = of_phy_register_fixed_link(dn);
574 if (ret)
575 return ret;
576
577 priv->phy_dn = of_node_get(dn);
578 }
579
580 /* Get the link mode */
581 ret = bcmgenet_phy_interface_init(priv);
582 if (ret)
583 return ret;
584
585 /* Make sure we initialize MoCA PHYs with a link down */
586 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
587 phydev = of_phy_find_device(dn);
588 if (phydev) {
589 phydev->link = 0;
590 put_device(&phydev->mdio.dev);
591 }
592 }
593
594 return 0;
595 }
596
bcmgenet_mii_pd_init(struct bcmgenet_priv * priv)597 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
598 {
599 struct device *kdev = &priv->pdev->dev;
600 struct bcmgenet_platform_data *pd = kdev->platform_data;
601 char phy_name[MII_BUS_ID_SIZE + 3];
602 char mdio_bus_id[MII_BUS_ID_SIZE];
603 struct phy_device *phydev;
604
605 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
606 UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
607
608 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
609 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
610 mdio_bus_id, pd->phy_address);
611
612 /*
613 * Internal or external PHY with MDIO access
614 */
615 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface);
616 if (IS_ERR(phydev)) {
617 dev_err(kdev, "failed to register PHY device\n");
618 return PTR_ERR(phydev);
619 }
620 } else {
621 /*
622 * MoCA port or no MDIO access.
623 * Use fixed PHY to represent the link layer.
624 */
625 struct fixed_phy_status fphy_status = {
626 .link = 1,
627 .speed = pd->phy_speed,
628 .duplex = pd->phy_duplex,
629 .pause = 0,
630 .asym_pause = 0,
631 };
632
633 phydev = fixed_phy_register(&fphy_status, NULL);
634 if (IS_ERR(phydev)) {
635 dev_err(kdev, "failed to register fixed PHY device\n");
636 return PTR_ERR(phydev);
637 }
638
639 /* Make sure we initialize MoCA PHYs with a link down */
640 phydev->link = 0;
641
642 }
643
644 priv->phy_interface = pd->phy_interface;
645
646 return 0;
647 }
648
bcmgenet_mii_bus_init(struct bcmgenet_priv * priv)649 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
650 {
651 struct device *kdev = &priv->pdev->dev;
652 struct device_node *dn = kdev->of_node;
653
654 if (dn)
655 return bcmgenet_mii_of_init(priv);
656 else if (has_acpi_companion(kdev))
657 return bcmgenet_phy_interface_init(priv);
658 else
659 return bcmgenet_mii_pd_init(priv);
660 }
661
bcmgenet_mii_init(struct net_device * dev)662 int bcmgenet_mii_init(struct net_device *dev)
663 {
664 struct bcmgenet_priv *priv = netdev_priv(dev);
665 int ret;
666
667 ret = bcmgenet_mii_register(priv);
668 if (ret)
669 return ret;
670
671 ret = bcmgenet_mii_bus_init(priv);
672 if (ret)
673 goto out;
674
675 return 0;
676
677 out:
678 bcmgenet_mii_exit(dev);
679 return ret;
680 }
681
bcmgenet_mii_exit(struct net_device * dev)682 void bcmgenet_mii_exit(struct net_device *dev)
683 {
684 struct bcmgenet_priv *priv = netdev_priv(dev);
685 struct device_node *dn = priv->pdev->dev.of_node;
686
687 if (of_phy_is_fixed_link(dn))
688 of_phy_deregister_fixed_link(dn);
689 of_node_put(priv->phy_dn);
690 platform_device_unregister(priv->mii_pdev);
691 }
692