1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Broadcom BCM7038 style Level 1 interrupt controller driver
4 *
5 * Copyright (C) 2014 Broadcom Corporation
6 * Author: Kevin Cernekee
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/bitops.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/irqdomain.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_address.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/smp.h>
26 #include <linux/types.h>
27 #include <linux/irqchip.h>
28 #include <linux/irqchip/chained_irq.h>
29 #include <linux/syscore_ops.h>
30
31 #define IRQS_PER_WORD 32
32 #define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 4)
33 #define MAX_WORDS 8
34
35 struct bcm7038_l1_cpu;
36
37 struct bcm7038_l1_chip {
38 raw_spinlock_t lock;
39 unsigned int n_words;
40 struct irq_domain *domain;
41 struct bcm7038_l1_cpu *cpus[NR_CPUS];
42 #ifdef CONFIG_PM_SLEEP
43 struct list_head list;
44 u32 wake_mask[MAX_WORDS];
45 #endif
46 u32 irq_fwd_mask[MAX_WORDS];
47 u8 affinity[MAX_WORDS * IRQS_PER_WORD];
48 };
49
50 struct bcm7038_l1_cpu {
51 void __iomem *map_base;
52 u32 mask_cache[];
53 };
54
55 /*
56 * STATUS/MASK_STATUS/MASK_SET/MASK_CLEAR are packed one right after another:
57 *
58 * 7038:
59 * 0x1000_1400: W0_STATUS
60 * 0x1000_1404: W1_STATUS
61 * 0x1000_1408: W0_MASK_STATUS
62 * 0x1000_140c: W1_MASK_STATUS
63 * 0x1000_1410: W0_MASK_SET
64 * 0x1000_1414: W1_MASK_SET
65 * 0x1000_1418: W0_MASK_CLEAR
66 * 0x1000_141c: W1_MASK_CLEAR
67 *
68 * 7445:
69 * 0xf03e_1500: W0_STATUS
70 * 0xf03e_1504: W1_STATUS
71 * 0xf03e_1508: W2_STATUS
72 * 0xf03e_150c: W3_STATUS
73 * 0xf03e_1510: W4_STATUS
74 * 0xf03e_1514: W0_MASK_STATUS
75 * 0xf03e_1518: W1_MASK_STATUS
76 * [...]
77 */
78
reg_status(struct bcm7038_l1_chip * intc,unsigned int word)79 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc,
80 unsigned int word)
81 {
82 return (0 * intc->n_words + word) * sizeof(u32);
83 }
84
reg_mask_set(struct bcm7038_l1_chip * intc,unsigned int word)85 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc,
86 unsigned int word)
87 {
88 return (2 * intc->n_words + word) * sizeof(u32);
89 }
90
reg_mask_clr(struct bcm7038_l1_chip * intc,unsigned int word)91 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc,
92 unsigned int word)
93 {
94 return (3 * intc->n_words + word) * sizeof(u32);
95 }
96
l1_readl(void __iomem * reg)97 static inline u32 l1_readl(void __iomem *reg)
98 {
99 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
100 return ioread32be(reg);
101 else
102 return readl(reg);
103 }
104
l1_writel(u32 val,void __iomem * reg)105 static inline void l1_writel(u32 val, void __iomem *reg)
106 {
107 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
108 iowrite32be(val, reg);
109 else
110 writel(val, reg);
111 }
112
bcm7038_l1_irq_handle(struct irq_desc * desc)113 static void bcm7038_l1_irq_handle(struct irq_desc *desc)
114 {
115 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc);
116 struct bcm7038_l1_cpu *cpu;
117 struct irq_chip *chip = irq_desc_get_chip(desc);
118 unsigned int idx;
119
120 #if defined(CONFIG_SMP) && defined(CONFIG_MIPS)
121 cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
122 #else
123 cpu = intc->cpus[0];
124 #endif
125
126 chained_irq_enter(chip, desc);
127
128 for (idx = 0; idx < intc->n_words; idx++) {
129 int base = idx * IRQS_PER_WORD;
130 unsigned long pending, flags;
131 int hwirq;
132
133 raw_spin_lock_irqsave(&intc->lock, flags);
134 pending = l1_readl(cpu->map_base + reg_status(intc, idx)) &
135 ~cpu->mask_cache[idx];
136 raw_spin_unlock_irqrestore(&intc->lock, flags);
137
138 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD)
139 generic_handle_domain_irq(intc->domain, base + hwirq);
140 }
141
142 chained_irq_exit(chip, desc);
143 }
144
__bcm7038_l1_unmask(struct irq_data * d,unsigned int cpu_idx)145 static void __bcm7038_l1_unmask(struct irq_data *d, unsigned int cpu_idx)
146 {
147 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
148 u32 word = d->hwirq / IRQS_PER_WORD;
149 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
150
151 intc->cpus[cpu_idx]->mask_cache[word] &= ~mask;
152 l1_writel(mask, intc->cpus[cpu_idx]->map_base +
153 reg_mask_clr(intc, word));
154 }
155
__bcm7038_l1_mask(struct irq_data * d,unsigned int cpu_idx)156 static void __bcm7038_l1_mask(struct irq_data *d, unsigned int cpu_idx)
157 {
158 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
159 u32 word = d->hwirq / IRQS_PER_WORD;
160 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
161
162 intc->cpus[cpu_idx]->mask_cache[word] |= mask;
163 l1_writel(mask, intc->cpus[cpu_idx]->map_base +
164 reg_mask_set(intc, word));
165 }
166
bcm7038_l1_unmask(struct irq_data * d)167 static void bcm7038_l1_unmask(struct irq_data *d)
168 {
169 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
170 unsigned long flags;
171
172 raw_spin_lock_irqsave(&intc->lock, flags);
173 __bcm7038_l1_unmask(d, intc->affinity[d->hwirq]);
174 raw_spin_unlock_irqrestore(&intc->lock, flags);
175 }
176
bcm7038_l1_mask(struct irq_data * d)177 static void bcm7038_l1_mask(struct irq_data *d)
178 {
179 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
180 unsigned long flags;
181
182 raw_spin_lock_irqsave(&intc->lock, flags);
183 __bcm7038_l1_mask(d, intc->affinity[d->hwirq]);
184 raw_spin_unlock_irqrestore(&intc->lock, flags);
185 }
186
187 #if defined(CONFIG_MIPS) && defined(CONFIG_SMP)
bcm7038_l1_set_affinity(struct irq_data * d,const struct cpumask * dest,bool force)188 static int bcm7038_l1_set_affinity(struct irq_data *d,
189 const struct cpumask *dest,
190 bool force)
191 {
192 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
193 unsigned long flags;
194 irq_hw_number_t hw = d->hwirq;
195 u32 word = hw / IRQS_PER_WORD;
196 u32 mask = BIT(hw % IRQS_PER_WORD);
197 unsigned int first_cpu = cpumask_any_and(dest, cpu_online_mask);
198 bool was_disabled;
199
200 raw_spin_lock_irqsave(&intc->lock, flags);
201
202 was_disabled = !!(intc->cpus[intc->affinity[hw]]->mask_cache[word] &
203 mask);
204 __bcm7038_l1_mask(d, intc->affinity[hw]);
205 intc->affinity[hw] = first_cpu;
206 if (!was_disabled)
207 __bcm7038_l1_unmask(d, first_cpu);
208
209 raw_spin_unlock_irqrestore(&intc->lock, flags);
210 irq_data_update_effective_affinity(d, cpumask_of(first_cpu));
211
212 return 0;
213 }
214 #endif
215
bcm7038_l1_init_one(struct device_node * dn,unsigned int idx,struct bcm7038_l1_chip * intc)216 static int bcm7038_l1_init_one(struct device_node *dn, unsigned int idx,
217 struct bcm7038_l1_chip *intc)
218 {
219 struct resource res;
220 resource_size_t sz;
221 struct bcm7038_l1_cpu *cpu;
222 unsigned int i, n_words, parent_irq;
223 int ret;
224
225 if (of_address_to_resource(dn, idx, &res))
226 return -EINVAL;
227 sz = resource_size(&res);
228 n_words = sz / REG_BYTES_PER_IRQ_WORD;
229
230 if (n_words > MAX_WORDS)
231 return -EINVAL;
232 else if (!intc->n_words)
233 intc->n_words = n_words;
234 else if (intc->n_words != n_words)
235 return -EINVAL;
236
237 ret = of_property_read_u32_array(dn , "brcm,int-fwd-mask",
238 intc->irq_fwd_mask, n_words);
239 if (ret != 0 && ret != -EINVAL) {
240 /* property exists but has the wrong number of words */
241 pr_err("invalid brcm,int-fwd-mask property\n");
242 return -EINVAL;
243 }
244
245 cpu = intc->cpus[idx] = kzalloc(struct_size(cpu, mask_cache, n_words),
246 GFP_KERNEL);
247 if (!cpu)
248 return -ENOMEM;
249
250 cpu->map_base = ioremap(res.start, sz);
251 if (!cpu->map_base)
252 return -ENOMEM;
253
254 for (i = 0; i < n_words; i++) {
255 l1_writel(~intc->irq_fwd_mask[i],
256 cpu->map_base + reg_mask_set(intc, i));
257 l1_writel(intc->irq_fwd_mask[i],
258 cpu->map_base + reg_mask_clr(intc, i));
259 cpu->mask_cache[i] = ~intc->irq_fwd_mask[i];
260 }
261
262 parent_irq = irq_of_parse_and_map(dn, idx);
263 if (!parent_irq) {
264 pr_err("failed to map parent interrupt %d\n", parent_irq);
265 return -EINVAL;
266 }
267
268 if (of_property_read_bool(dn, "brcm,irq-can-wake"))
269 enable_irq_wake(parent_irq);
270
271 irq_set_chained_handler_and_data(parent_irq, bcm7038_l1_irq_handle,
272 intc);
273
274 return 0;
275 }
276
277 #ifdef CONFIG_PM_SLEEP
278 /*
279 * We keep a list of bcm7038_l1_chip used for suspend/resume. This hack is
280 * used because the struct chip_type suspend/resume hooks are not called
281 * unless chip_type is hooked onto a generic_chip. Since this driver does
282 * not use generic_chip, we need to manually hook our resume/suspend to
283 * syscore_ops.
284 */
285 static LIST_HEAD(bcm7038_l1_intcs_list);
286 static DEFINE_RAW_SPINLOCK(bcm7038_l1_intcs_lock);
287
bcm7038_l1_suspend(void * data)288 static int bcm7038_l1_suspend(void *data)
289 {
290 struct bcm7038_l1_chip *intc;
291 int boot_cpu, word;
292 u32 val;
293
294 /* Wakeup interrupt should only come from the boot cpu */
295 #if defined(CONFIG_SMP) && defined(CONFIG_MIPS)
296 boot_cpu = cpu_logical_map(0);
297 #else
298 boot_cpu = 0;
299 #endif
300
301 list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
302 for (word = 0; word < intc->n_words; word++) {
303 val = intc->wake_mask[word] | intc->irq_fwd_mask[word];
304 l1_writel(~val,
305 intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word));
306 l1_writel(val,
307 intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word));
308 }
309 }
310
311 return 0;
312 }
313
bcm7038_l1_resume(void * data)314 static void bcm7038_l1_resume(void *data)
315 {
316 struct bcm7038_l1_chip *intc;
317 int boot_cpu, word;
318
319 #if defined(CONFIG_SMP) && defined(CONFIG_MIPS)
320 boot_cpu = cpu_logical_map(0);
321 #else
322 boot_cpu = 0;
323 #endif
324
325 list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
326 for (word = 0; word < intc->n_words; word++) {
327 l1_writel(intc->cpus[boot_cpu]->mask_cache[word],
328 intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word));
329 l1_writel(~intc->cpus[boot_cpu]->mask_cache[word],
330 intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word));
331 }
332 }
333 }
334
335 static const struct syscore_ops bcm7038_l1_syscore_ops = {
336 .suspend = bcm7038_l1_suspend,
337 .resume = bcm7038_l1_resume,
338 };
339
340 static struct syscore bcm7038_l1_syscore = {
341 .ops = &bcm7038_l1_syscore_ops,
342 };
343
bcm7038_l1_set_wake(struct irq_data * d,unsigned int on)344 static int bcm7038_l1_set_wake(struct irq_data *d, unsigned int on)
345 {
346 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
347 unsigned long flags;
348 u32 word = d->hwirq / IRQS_PER_WORD;
349 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
350
351 raw_spin_lock_irqsave(&intc->lock, flags);
352 if (on)
353 intc->wake_mask[word] |= mask;
354 else
355 intc->wake_mask[word] &= ~mask;
356 raw_spin_unlock_irqrestore(&intc->lock, flags);
357
358 return 0;
359 }
360 #endif
361
362 static struct irq_chip bcm7038_l1_irq_chip = {
363 .name = "bcm7038-l1",
364 .irq_mask = bcm7038_l1_mask,
365 .irq_unmask = bcm7038_l1_unmask,
366 #if defined(CONFIG_SMP) && defined(CONFIG_MIPS)
367 .irq_set_affinity = bcm7038_l1_set_affinity,
368 #endif
369 #ifdef CONFIG_PM_SLEEP
370 .irq_set_wake = bcm7038_l1_set_wake,
371 #endif
372 };
373
bcm7038_l1_map(struct irq_domain * d,unsigned int virq,irq_hw_number_t hw_irq)374 static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq,
375 irq_hw_number_t hw_irq)
376 {
377 struct bcm7038_l1_chip *intc = d->host_data;
378 u32 mask = BIT(hw_irq % IRQS_PER_WORD);
379 u32 word = hw_irq / IRQS_PER_WORD;
380
381 if (intc->irq_fwd_mask[word] & mask)
382 return -EPERM;
383
384 irq_set_chip_and_handler(virq, &bcm7038_l1_irq_chip, handle_level_irq);
385 irq_set_chip_data(virq, d->host_data);
386 irqd_set_single_target(irq_get_irq_data(virq));
387 return 0;
388 }
389
390 static const struct irq_domain_ops bcm7038_l1_domain_ops = {
391 .xlate = irq_domain_xlate_onecell,
392 .map = bcm7038_l1_map,
393 };
394
bcm7038_l1_probe(struct platform_device * pdev,struct device_node * parent)395 static int bcm7038_l1_probe(struct platform_device *pdev, struct device_node *parent)
396 {
397 struct device_node *dn = pdev->dev.of_node;
398 struct bcm7038_l1_chip *intc;
399 int idx, ret;
400
401 intc = kzalloc(sizeof(*intc), GFP_KERNEL);
402 if (!intc)
403 return -ENOMEM;
404
405 raw_spin_lock_init(&intc->lock);
406 for_each_possible_cpu(idx) {
407 ret = bcm7038_l1_init_one(dn, idx, intc);
408 if (ret < 0) {
409 if (idx)
410 break;
411 pr_err("failed to remap intc L1 registers\n");
412 goto out_free;
413 }
414 }
415
416 intc->domain = irq_domain_create_linear(of_fwnode_handle(dn), IRQS_PER_WORD * intc->n_words,
417 &bcm7038_l1_domain_ops,
418 intc);
419 if (!intc->domain) {
420 ret = -ENOMEM;
421 goto out_unmap;
422 }
423
424 #ifdef CONFIG_PM_SLEEP
425 /* Add bcm7038_l1_chip into a list */
426 raw_spin_lock(&bcm7038_l1_intcs_lock);
427 list_add_tail(&intc->list, &bcm7038_l1_intcs_list);
428 raw_spin_unlock(&bcm7038_l1_intcs_lock);
429
430 if (list_is_singular(&bcm7038_l1_intcs_list))
431 register_syscore(&bcm7038_l1_syscore);
432 #endif
433
434 pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n",
435 dn, IRQS_PER_WORD * intc->n_words);
436
437 return 0;
438
439 out_unmap:
440 for_each_possible_cpu(idx) {
441 struct bcm7038_l1_cpu *cpu = intc->cpus[idx];
442
443 if (cpu) {
444 if (cpu->map_base)
445 iounmap(cpu->map_base);
446 kfree(cpu);
447 }
448 }
449 out_free:
450 kfree(intc);
451 return ret;
452 }
453
454 IRQCHIP_PLATFORM_DRIVER_BEGIN(bcm7038_l1)
455 IRQCHIP_MATCH("brcm,bcm7038-l1-intc", bcm7038_l1_probe)
456 IRQCHIP_PLATFORM_DRIVER_END(bcm7038_l1)
457 MODULE_DESCRIPTION("Broadcom STB 7038-style L1/L2 interrupt controller");
458 MODULE_LICENSE("GPL v2");
459