xref: /linux/arch/mips/bmips/setup.c (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7  * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
8  */
9 
10 #include <linux/init.h>
11 #include <linux/bitops.h>
12 #include <linux/memblock.h>
13 #include <linux/ioport.h>
14 #include <linux/kernel.h>
15 #include <linux/io.h>
16 #include <linux/of.h>
17 #include <linux/of_clk.h>
18 #include <linux/of_fdt.h>
19 #include <linux/libfdt.h>
20 #include <linux/smp.h>
21 #include <asm/addrspace.h>
22 #include <asm/bmips.h>
23 #include <asm/bootinfo.h>
24 #include <asm/cpu-type.h>
25 #include <asm/mipsregs.h>
26 #include <asm/prom.h>
27 #include <asm/smp-ops.h>
28 #include <asm/time.h>
29 #include <asm/traps.h>
30 #include <asm/fw/cfe/cfe_api.h>
31 
32 #define RELO_NORMAL_VEC		BIT(18)
33 
34 #define REG_BCM6328_OTP		((void __iomem *)CKSEG1ADDR(0x1000062c))
35 #define BCM6328_TP1_DISABLED	BIT(9)
36 
37 /*
38  * CBR addr doesn't change and we can cache it.
39  * For broken SoC/Bootloader CBR addr might also be provided via DT
40  * with "brcm,bmips-cbr-reg" in the "cpus" node.
41  */
42 void __iomem *bmips_cbr_addr __read_mostly;
43 
44 extern bool bmips_rac_flush_disable;
45 
46 static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
47 
48 struct bmips_quirk {
49 	const char		*compatible;
50 	void			(*quirk_fn)(void);
51 };
52 
kbase_setup(void)53 static void kbase_setup(void)
54 {
55 	__raw_writel(kbase | RELO_NORMAL_VEC,
56 		     BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1);
57 	ebase = kbase;
58 }
59 
bcm3384_viper_quirks(void)60 static void bcm3384_viper_quirks(void)
61 {
62 	/*
63 	 * Some experimental CM boxes are set up to let CM own the Viper TP0
64 	 * and let Linux own TP1.  This requires moving the kernel
65 	 * load address to a non-conflicting region (e.g. via
66 	 * CONFIG_PHYSICAL_START) and supplying an alternate DTB.
67 	 * If we detect this condition, we need to move the MIPS exception
68 	 * vectors up to an area that we own.
69 	 *
70 	 * This is distinct from the OTHER special case mentioned in
71 	 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our
72 	 * logical CPU#1).  For the Viper TP1 case, SMP is off limits.
73 	 *
74 	 * Also note that many BMIPS435x CPUs do not have a
75 	 * BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just
76 	 * write VMLINUX_LOAD_ADDRESS into that register on every SoC.
77 	 */
78 	board_ebase_setup = &kbase_setup;
79 	bmips_smp_enabled = 0;
80 }
81 
bcm63xx_fixup_cpu1(void)82 static void bcm63xx_fixup_cpu1(void)
83 {
84 	/*
85 	 * The bootloader has set up the CPU1 reset vector at
86 	 * 0xa000_0200.
87 	 * This conflicts with the special interrupt vector (IV).
88 	 * The bootloader has also set up CPU1 to respond to the wrong
89 	 * IPI interrupt.
90 	 * Here we will start up CPU1 in the background and ask it to
91 	 * reconfigure itself then go back to sleep.
92 	 */
93 	memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
94 	__sync();
95 	set_c0_cause(C_SW0);
96 	cpumask_set_cpu(1, &bmips_booted_mask);
97 }
98 
bcm6328_quirks(void)99 static void bcm6328_quirks(void)
100 {
101 	/* Check CPU1 status in OTP (it is usually disabled) */
102 	if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED)
103 		bmips_smp_enabled = 0;
104 	else
105 		bcm63xx_fixup_cpu1();
106 }
107 
bcm6358_quirks(void)108 static void bcm6358_quirks(void)
109 {
110 	/*
111 	 * BCM3368/BCM6358 need special handling for their shared TLB, so
112 	 * disable SMP for now
113 	 */
114 	bmips_smp_enabled = 0;
115 
116 	/*
117 	 * RAC flush causes kernel panics on BCM6358 when booting from TP1
118 	 * because the bootloader is not initializing it properly.
119 	 */
120 	bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) ||
121 				  !!bmips_cbr_addr;
122 }
123 
bcm6368_quirks(void)124 static void bcm6368_quirks(void)
125 {
126 	bcm63xx_fixup_cpu1();
127 }
128 
129 static const struct bmips_quirk bmips_quirk_list[] = {
130 	{ "brcm,bcm3368",		&bcm6358_quirks			},
131 	{ "brcm,bcm3384-viper",		&bcm3384_viper_quirks		},
132 	{ "brcm,bcm33843-viper",	&bcm3384_viper_quirks		},
133 	{ "brcm,bcm6328",		&bcm6328_quirks			},
134 	{ "brcm,bcm6358",		&bcm6358_quirks			},
135 	{ "brcm,bcm6362",		&bcm6368_quirks			},
136 	{ "brcm,bcm6368",		&bcm6368_quirks			},
137 	{ "brcm,bcm63168",		&bcm6368_quirks			},
138 	{ "brcm,bcm63268",		&bcm6368_quirks			},
139 	{ },
140 };
141 
bmips_init_cfe(void)142 static void __init bmips_init_cfe(void)
143 {
144 	cfe_seal = fw_arg3;
145 
146 	if (cfe_seal != CFE_EPTSEAL)
147 		return;
148 
149 	cfe_init(fw_arg0, fw_arg2);
150 }
151 
prom_init(void)152 void __init prom_init(void)
153 {
154 	/* Cache CBR addr before CPU/DMA setup */
155 	bmips_cbr_addr = BMIPS_GET_CBR();
156 	bmips_init_cfe();
157 	bmips_cpu_setup();
158 	register_bmips_smp_ops();
159 }
160 
get_system_type(void)161 const char *get_system_type(void)
162 {
163 	return "Generic BMIPS kernel";
164 }
165 
plat_time_init(void)166 void __init plat_time_init(void)
167 {
168 	struct device_node *np;
169 	u32 freq;
170 
171 	np = of_find_node_by_name(NULL, "cpus");
172 	if (!np)
173 		panic("missing 'cpus' DT node");
174 	if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
175 		panic("missing 'mips-hpt-frequency' property");
176 	of_node_put(np);
177 
178 	mips_hpt_frequency = freq;
179 }
180 
plat_mem_setup(void)181 void __init plat_mem_setup(void)
182 {
183 	void *dtb;
184 	const struct bmips_quirk *q;
185 
186 	set_io_port_base(0);
187 	ioport_resource.start = 0;
188 	ioport_resource.end = ~0;
189 
190 	/*
191 	 * intended to somewhat resemble ARM; see
192 	 * Documentation/arch/arm/booting.rst
193 	 */
194 	if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
195 		dtb = phys_to_virt(fw_arg2);
196 	else
197 		dtb = get_fdt();
198 
199 	if (!dtb)
200 		cfe_die("no dtb found");
201 
202 	__dt_setup_arch(dtb);
203 
204 	for (q = bmips_quirk_list; q->quirk_fn; q++) {
205 		if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
206 					     q->compatible)) {
207 			q->quirk_fn();
208 		}
209 	}
210 }
211 
device_tree_init(void)212 void __init device_tree_init(void)
213 {
214 	struct device_node *np;
215 	u32 addr;
216 
217 	unflatten_and_copy_device_tree();
218 
219 	/* Disable SMP boot unless both CPUs are listed in DT and !disabled */
220 	np = of_find_node_by_name(NULL, "cpus");
221 	if (!np)
222 		return;
223 
224 	if (of_get_available_child_count(np) <= 1)
225 		bmips_smp_enabled = 0;
226 
227 	/* Check if DT provide a CBR address */
228 	if (of_property_read_u32(np, "brcm,bmips-cbr-reg", &addr))
229 		goto exit;
230 
231 	/* Make sure CBR address is outside DRAM window */
232 	if (addr >= (u32)memblock_start_of_DRAM() &&
233 	    addr < (u32)memblock_end_of_DRAM()) {
234 		WARN(1, "DT CBR %x inside DRAM window. Ignoring DT CBR.\n",
235 		     addr);
236 		goto exit;
237 	}
238 
239 	bmips_cbr_addr = (void __iomem *)addr;
240 	/* Since CBR is provided by DT, enable RAC flush */
241 	bmips_rac_flush_disable = false;
242 
243 exit:
244 	of_node_put(np);
245 }
246 
plat_dev_init(void)247 static int __init plat_dev_init(void)
248 {
249 	of_clk_init(NULL);
250 	return 0;
251 }
252 
253 arch_initcall(plat_dev_init);
254