1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2022 Intel Corporation
4 */
5
6 #include "xe_gt.h"
7
8 #include <linux/minmax.h>
9
10 #include <drm/drm_managed.h>
11 #include <uapi/drm/xe_drm.h>
12
13 #include <generated/xe_wa_oob.h>
14
15 #include "instructions/xe_alu_commands.h"
16 #include "instructions/xe_gfxpipe_commands.h"
17 #include "instructions/xe_mi_commands.h"
18 #include "regs/xe_engine_regs.h"
19 #include "regs/xe_gt_regs.h"
20 #include "xe_assert.h"
21 #include "xe_bb.h"
22 #include "xe_bo.h"
23 #include "xe_device.h"
24 #include "xe_eu_stall.h"
25 #include "xe_exec_queue.h"
26 #include "xe_execlist.h"
27 #include "xe_force_wake.h"
28 #include "xe_ggtt.h"
29 #include "xe_gsc.h"
30 #include "xe_gt_ccs_mode.h"
31 #include "xe_gt_clock.h"
32 #include "xe_gt_freq.h"
33 #include "xe_gt_idle.h"
34 #include "xe_gt_mcr.h"
35 #include "xe_gt_pagefault.h"
36 #include "xe_gt_printk.h"
37 #include "xe_gt_sriov_pf.h"
38 #include "xe_gt_sriov_vf.h"
39 #include "xe_gt_sysfs.h"
40 #include "xe_gt_topology.h"
41 #include "xe_guc_exec_queue_types.h"
42 #include "xe_guc_pc.h"
43 #include "xe_guc_submit.h"
44 #include "xe_hw_fence.h"
45 #include "xe_hw_engine_class_sysfs.h"
46 #include "xe_irq.h"
47 #include "xe_lmtt.h"
48 #include "xe_lrc.h"
49 #include "xe_map.h"
50 #include "xe_migrate.h"
51 #include "xe_mmio.h"
52 #include "xe_pat.h"
53 #include "xe_pm.h"
54 #include "xe_mocs.h"
55 #include "xe_reg_sr.h"
56 #include "xe_ring_ops.h"
57 #include "xe_sa.h"
58 #include "xe_sched_job.h"
59 #include "xe_sriov.h"
60 #include "xe_tlb_inval.h"
61 #include "xe_tuning.h"
62 #include "xe_uc.h"
63 #include "xe_uc_fw.h"
64 #include "xe_vm.h"
65 #include "xe_wa.h"
66 #include "xe_wopcm.h"
67
gt_fini(struct drm_device * drm,void * arg)68 static void gt_fini(struct drm_device *drm, void *arg)
69 {
70 struct xe_gt *gt = arg;
71
72 destroy_workqueue(gt->ordered_wq);
73 }
74
xe_gt_alloc(struct xe_tile * tile)75 struct xe_gt *xe_gt_alloc(struct xe_tile *tile)
76 {
77 struct xe_gt *gt;
78 int err;
79
80 gt = drmm_kzalloc(&tile_to_xe(tile)->drm, sizeof(*gt), GFP_KERNEL);
81 if (!gt)
82 return ERR_PTR(-ENOMEM);
83
84 gt->tile = tile;
85 gt->ordered_wq = alloc_ordered_workqueue("gt-ordered-wq",
86 WQ_MEM_RECLAIM);
87
88 err = drmm_add_action_or_reset(>_to_xe(gt)->drm, gt_fini, gt);
89 if (err)
90 return ERR_PTR(err);
91
92 return gt;
93 }
94
xe_gt_sanitize(struct xe_gt * gt)95 void xe_gt_sanitize(struct xe_gt *gt)
96 {
97 /*
98 * FIXME: if xe_uc_sanitize is called here, on TGL driver will not
99 * reload
100 */
101 xe_guc_submit_disable(>->uc.guc);
102 }
103
xe_gt_enable_host_l2_vram(struct xe_gt * gt)104 static void xe_gt_enable_host_l2_vram(struct xe_gt *gt)
105 {
106 unsigned int fw_ref;
107 u32 reg;
108
109 if (!XE_GT_WA(gt, 16023588340))
110 return;
111
112 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
113 if (!fw_ref)
114 return;
115
116 if (xe_gt_is_main_type(gt)) {
117 reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL);
118 reg |= CG_DIS_CNTLBUS;
119 xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg);
120 }
121
122 xe_gt_mcr_multicast_write(gt, XEHPC_L3CLOS_MASK(3), 0xF);
123 xe_force_wake_put(gt_to_fw(gt), fw_ref);
124 }
125
xe_gt_disable_host_l2_vram(struct xe_gt * gt)126 static void xe_gt_disable_host_l2_vram(struct xe_gt *gt)
127 {
128 unsigned int fw_ref;
129 u32 reg;
130
131 if (!XE_GT_WA(gt, 16023588340))
132 return;
133
134 if (xe_gt_is_media_type(gt))
135 return;
136
137 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
138 if (!fw_ref)
139 return;
140
141 reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL);
142 reg &= ~CG_DIS_CNTLBUS;
143 xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg);
144
145 xe_force_wake_put(gt_to_fw(gt), fw_ref);
146 }
147
148 static void gt_reset_worker(struct work_struct *w);
149
emit_job_sync(struct xe_exec_queue * q,struct xe_bb * bb,long timeout_jiffies)150 static int emit_job_sync(struct xe_exec_queue *q, struct xe_bb *bb,
151 long timeout_jiffies)
152 {
153 struct xe_sched_job *job;
154 struct dma_fence *fence;
155 long timeout;
156
157 job = xe_bb_create_job(q, bb);
158 if (IS_ERR(job))
159 return PTR_ERR(job);
160
161 xe_sched_job_arm(job);
162 fence = dma_fence_get(&job->drm.s_fence->finished);
163 xe_sched_job_push(job);
164
165 timeout = dma_fence_wait_timeout(fence, false, timeout_jiffies);
166 dma_fence_put(fence);
167 if (timeout < 0)
168 return timeout;
169 else if (!timeout)
170 return -ETIME;
171
172 return 0;
173 }
174
emit_nop_job(struct xe_gt * gt,struct xe_exec_queue * q)175 static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q)
176 {
177 struct xe_bb *bb;
178 int ret;
179
180 bb = xe_bb_new(gt, 4, false);
181 if (IS_ERR(bb))
182 return PTR_ERR(bb);
183
184 ret = emit_job_sync(q, bb, HZ);
185 xe_bb_free(bb, NULL);
186
187 return ret;
188 }
189
emit_wa_job(struct xe_gt * gt,struct xe_exec_queue * q)190 static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
191 {
192 struct xe_reg_sr *sr = &q->hwe->reg_lrc;
193 struct xe_reg_sr_entry *entry;
194 int count_rmw = 0, count = 0, ret;
195 unsigned long idx;
196 struct xe_bb *bb;
197 size_t bb_len = 0;
198 u32 *cs;
199
200 /* count RMW registers as those will be handled separately */
201 xa_for_each(&sr->xa, idx, entry) {
202 if (entry->reg.masked || entry->clr_bits == ~0)
203 ++count;
204 else
205 ++count_rmw;
206 }
207
208 if (count)
209 bb_len += count * 2 + 1;
210
211 if (count_rmw)
212 bb_len += count_rmw * 20 + 7;
213
214 if (q->hwe->class == XE_ENGINE_CLASS_RENDER)
215 /*
216 * Big enough to emit all of the context's 3DSTATE via
217 * xe_lrc_emit_hwe_state_instructions()
218 */
219 bb_len += xe_gt_lrc_size(gt, q->hwe->class) / sizeof(u32);
220
221 xe_gt_dbg(gt, "LRC %s WA job: %zu dwords\n", q->hwe->name, bb_len);
222
223 bb = xe_bb_new(gt, bb_len, false);
224 if (IS_ERR(bb))
225 return PTR_ERR(bb);
226
227 cs = bb->cs;
228
229 if (count) {
230 /*
231 * Emit single LRI with all non RMW regs: 1 leading dw + 2dw per
232 * reg + 1
233 */
234
235 *cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count);
236
237 xa_for_each(&sr->xa, idx, entry) {
238 struct xe_reg reg = entry->reg;
239 u32 val;
240
241 if (reg.masked)
242 val = entry->clr_bits << 16;
243 else if (entry->clr_bits == ~0)
244 val = 0;
245 else
246 continue;
247
248 val |= entry->set_bits;
249
250 *cs++ = reg.addr;
251 *cs++ = val;
252 xe_gt_dbg(gt, "REG[0x%x] = 0x%08x", reg.addr, val);
253 }
254 }
255
256 if (count_rmw) {
257 /* Emit MI_MATH for each RMW reg: 20dw per reg + 7 trailing dw */
258
259 xa_for_each(&sr->xa, idx, entry) {
260 if (entry->reg.masked || entry->clr_bits == ~0)
261 continue;
262
263 *cs++ = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO;
264 *cs++ = entry->reg.addr;
265 *cs++ = CS_GPR_REG(0, 0).addr;
266
267 *cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(2) |
268 MI_LRI_LRM_CS_MMIO;
269 *cs++ = CS_GPR_REG(0, 1).addr;
270 *cs++ = entry->clr_bits;
271 *cs++ = CS_GPR_REG(0, 2).addr;
272 *cs++ = entry->set_bits;
273
274 *cs++ = MI_MATH(8);
275 *cs++ = CS_ALU_INSTR_LOAD(SRCA, REG0);
276 *cs++ = CS_ALU_INSTR_LOADINV(SRCB, REG1);
277 *cs++ = CS_ALU_INSTR_AND;
278 *cs++ = CS_ALU_INSTR_STORE(REG0, ACCU);
279 *cs++ = CS_ALU_INSTR_LOAD(SRCA, REG0);
280 *cs++ = CS_ALU_INSTR_LOAD(SRCB, REG2);
281 *cs++ = CS_ALU_INSTR_OR;
282 *cs++ = CS_ALU_INSTR_STORE(REG0, ACCU);
283
284 *cs++ = MI_LOAD_REGISTER_REG | MI_LRR_SRC_CS_MMIO;
285 *cs++ = CS_GPR_REG(0, 0).addr;
286 *cs++ = entry->reg.addr;
287
288 xe_gt_dbg(gt, "REG[%#x] = ~%#x|%#x\n",
289 entry->reg.addr, entry->clr_bits, entry->set_bits);
290 }
291
292 /* reset used GPR */
293 *cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(3) |
294 MI_LRI_LRM_CS_MMIO;
295 *cs++ = CS_GPR_REG(0, 0).addr;
296 *cs++ = 0;
297 *cs++ = CS_GPR_REG(0, 1).addr;
298 *cs++ = 0;
299 *cs++ = CS_GPR_REG(0, 2).addr;
300 *cs++ = 0;
301 }
302
303 cs = xe_lrc_emit_hwe_state_instructions(q, cs);
304
305 bb->len = cs - bb->cs;
306
307 ret = emit_job_sync(q, bb, HZ);
308
309 xe_bb_free(bb, NULL);
310
311 return ret;
312 }
313
xe_gt_record_default_lrcs(struct xe_gt * gt)314 int xe_gt_record_default_lrcs(struct xe_gt *gt)
315 {
316 struct xe_device *xe = gt_to_xe(gt);
317 struct xe_hw_engine *hwe;
318 enum xe_hw_engine_id id;
319 int err = 0;
320
321 for_each_hw_engine(hwe, gt, id) {
322 struct xe_exec_queue *q, *nop_q;
323 void *default_lrc;
324
325 if (gt->default_lrc[hwe->class])
326 continue;
327
328 xe_reg_sr_init(&hwe->reg_lrc, hwe->name, xe);
329 xe_wa_process_lrc(hwe);
330 xe_hw_engine_setup_default_lrc_state(hwe);
331 xe_tuning_process_lrc(hwe);
332
333 default_lrc = drmm_kzalloc(&xe->drm,
334 xe_gt_lrc_size(gt, hwe->class),
335 GFP_KERNEL);
336 if (!default_lrc)
337 return -ENOMEM;
338
339 q = xe_exec_queue_create(xe, NULL, BIT(hwe->logical_instance), 1,
340 hwe, EXEC_QUEUE_FLAG_KERNEL, 0);
341 if (IS_ERR(q)) {
342 err = PTR_ERR(q);
343 xe_gt_err(gt, "hwe %s: xe_exec_queue_create failed (%pe)\n",
344 hwe->name, q);
345 return err;
346 }
347
348 /* Prime golden LRC with known good state */
349 err = emit_wa_job(gt, q);
350 if (err) {
351 xe_gt_err(gt, "hwe %s: emit_wa_job failed (%pe) guc_id=%u\n",
352 hwe->name, ERR_PTR(err), q->guc->id);
353 goto put_exec_queue;
354 }
355
356 nop_q = xe_exec_queue_create(xe, NULL, BIT(hwe->logical_instance),
357 1, hwe, EXEC_QUEUE_FLAG_KERNEL, 0);
358 if (IS_ERR(nop_q)) {
359 err = PTR_ERR(nop_q);
360 xe_gt_err(gt, "hwe %s: nop xe_exec_queue_create failed (%pe)\n",
361 hwe->name, nop_q);
362 goto put_exec_queue;
363 }
364
365 /* Switch to different LRC */
366 err = emit_nop_job(gt, nop_q);
367 if (err) {
368 xe_gt_err(gt, "hwe %s: nop emit_nop_job failed (%pe) guc_id=%u\n",
369 hwe->name, ERR_PTR(err), nop_q->guc->id);
370 goto put_nop_q;
371 }
372
373 xe_map_memcpy_from(xe, default_lrc,
374 &q->lrc[0]->bo->vmap,
375 xe_lrc_pphwsp_offset(q->lrc[0]),
376 xe_gt_lrc_size(gt, hwe->class));
377
378 gt->default_lrc[hwe->class] = default_lrc;
379 put_nop_q:
380 xe_exec_queue_put(nop_q);
381 put_exec_queue:
382 xe_exec_queue_put(q);
383 if (err)
384 break;
385 }
386
387 return err;
388 }
389
xe_gt_init_early(struct xe_gt * gt)390 int xe_gt_init_early(struct xe_gt *gt)
391 {
392 unsigned int fw_ref;
393 int err;
394
395 if (IS_SRIOV_PF(gt_to_xe(gt))) {
396 err = xe_gt_sriov_pf_init_early(gt);
397 if (err)
398 return err;
399 }
400
401 xe_reg_sr_init(>->reg_sr, "GT", gt_to_xe(gt));
402
403 err = xe_wa_gt_init(gt);
404 if (err)
405 return err;
406
407 err = xe_tuning_init(gt);
408 if (err)
409 return err;
410
411 xe_wa_process_gt_oob(gt);
412
413 xe_force_wake_init_gt(gt, gt_to_fw(gt));
414 spin_lock_init(>->global_invl_lock);
415
416 err = xe_gt_tlb_inval_init_early(gt);
417 if (err)
418 return err;
419
420 xe_mocs_init_early(gt);
421
422 /*
423 * Only after this point can GT-specific MMIO operations
424 * (including things like communication with the GuC)
425 * be performed.
426 */
427 xe_gt_mmio_init(gt);
428
429 err = xe_uc_init_noalloc(>->uc);
430 if (err)
431 return err;
432
433 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
434 if (!fw_ref)
435 return -ETIMEDOUT;
436
437 xe_gt_mcr_init_early(gt);
438 xe_pat_init(gt);
439 xe_force_wake_put(gt_to_fw(gt), fw_ref);
440
441 return 0;
442 }
443
dump_pat_on_error(struct xe_gt * gt)444 static void dump_pat_on_error(struct xe_gt *gt)
445 {
446 struct drm_printer p;
447 char prefix[32];
448
449 snprintf(prefix, sizeof(prefix), "[GT%u Error]", gt->info.id);
450 p = drm_dbg_printer(>_to_xe(gt)->drm, DRM_UT_DRIVER, prefix);
451
452 xe_pat_dump(gt, &p);
453 }
454
gt_init_with_gt_forcewake(struct xe_gt * gt)455 static int gt_init_with_gt_forcewake(struct xe_gt *gt)
456 {
457 unsigned int fw_ref;
458 int err;
459
460 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
461 if (!fw_ref)
462 return -ETIMEDOUT;
463
464 err = xe_uc_init(>->uc);
465 if (err)
466 goto err_force_wake;
467
468 xe_gt_topology_init(gt);
469 xe_gt_mcr_init(gt);
470 xe_gt_enable_host_l2_vram(gt);
471
472 if (xe_gt_is_main_type(gt)) {
473 err = xe_ggtt_init(gt_to_tile(gt)->mem.ggtt);
474 if (err)
475 goto err_force_wake;
476 if (IS_SRIOV_PF(gt_to_xe(gt)))
477 xe_lmtt_init(>_to_tile(gt)->sriov.pf.lmtt);
478 }
479
480 /* Enable per hw engine IRQs */
481 xe_irq_enable_hwe(gt);
482
483 /* Rerun MCR init as we now have hw engine list */
484 xe_gt_mcr_init(gt);
485
486 err = xe_hw_engines_init_early(gt);
487 if (err) {
488 dump_pat_on_error(gt);
489 goto err_force_wake;
490 }
491
492 err = xe_hw_engine_class_sysfs_init(gt);
493 if (err)
494 goto err_force_wake;
495
496 /* Initialize CCS mode sysfs after early initialization of HW engines */
497 err = xe_gt_ccs_mode_sysfs_init(gt);
498 if (err)
499 goto err_force_wake;
500
501 /*
502 * Stash hardware-reported version. Since this register does not exist
503 * on pre-MTL platforms, reading it there will (correctly) return 0.
504 */
505 gt->info.gmdid = xe_mmio_read32(>->mmio, GMD_ID);
506
507 xe_force_wake_put(gt_to_fw(gt), fw_ref);
508 return 0;
509
510 err_force_wake:
511 xe_force_wake_put(gt_to_fw(gt), fw_ref);
512
513 return err;
514 }
515
gt_init_with_all_forcewake(struct xe_gt * gt)516 static int gt_init_with_all_forcewake(struct xe_gt *gt)
517 {
518 unsigned int fw_ref;
519 int err;
520
521 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);
522 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) {
523 err = -ETIMEDOUT;
524 goto err_force_wake;
525 }
526
527 xe_gt_mcr_set_implicit_defaults(gt);
528 xe_wa_process_gt(gt);
529 xe_tuning_process_gt(gt);
530 xe_reg_sr_apply_mmio(>->reg_sr, gt);
531
532 err = xe_gt_clock_init(gt);
533 if (err)
534 goto err_force_wake;
535
536 xe_mocs_init(gt);
537 err = xe_execlist_init(gt);
538 if (err)
539 goto err_force_wake;
540
541 err = xe_hw_engines_init(gt);
542 if (err)
543 goto err_force_wake;
544
545 err = xe_uc_init_post_hwconfig(>->uc);
546 if (err)
547 goto err_force_wake;
548
549 if (xe_gt_is_main_type(gt)) {
550 /*
551 * USM has its only SA pool to non-block behind user operations
552 */
553 if (gt_to_xe(gt)->info.has_usm) {
554 struct xe_device *xe = gt_to_xe(gt);
555
556 gt->usm.bb_pool = xe_sa_bo_manager_init(gt_to_tile(gt),
557 IS_DGFX(xe) ? SZ_1M : SZ_512K, 16);
558 if (IS_ERR(gt->usm.bb_pool)) {
559 err = PTR_ERR(gt->usm.bb_pool);
560 goto err_force_wake;
561 }
562 }
563 }
564
565 if (xe_gt_is_main_type(gt)) {
566 struct xe_tile *tile = gt_to_tile(gt);
567
568 err = xe_migrate_init(tile->migrate);
569 if (err)
570 goto err_force_wake;
571 }
572
573 err = xe_uc_load_hw(>->uc);
574 if (err)
575 goto err_force_wake;
576
577 /* Configure default CCS mode of 1 engine with all resources */
578 if (xe_gt_ccs_mode_enabled(gt)) {
579 gt->ccs_mode = 1;
580 xe_gt_apply_ccs_mode(gt);
581 }
582
583 if (IS_SRIOV_PF(gt_to_xe(gt)) && xe_gt_is_main_type(gt))
584 xe_lmtt_init_hw(>_to_tile(gt)->sriov.pf.lmtt);
585
586 if (IS_SRIOV_PF(gt_to_xe(gt))) {
587 xe_gt_sriov_pf_init(gt);
588 xe_gt_sriov_pf_init_hw(gt);
589 }
590
591 xe_force_wake_put(gt_to_fw(gt), fw_ref);
592
593 return 0;
594
595 err_force_wake:
596 xe_force_wake_put(gt_to_fw(gt), fw_ref);
597
598 return err;
599 }
600
xe_gt_fini(void * arg)601 static void xe_gt_fini(void *arg)
602 {
603 struct xe_gt *gt = arg;
604 int i;
605
606 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i)
607 xe_hw_fence_irq_finish(>->fence_irq[i]);
608
609 xe_gt_disable_host_l2_vram(gt);
610 }
611
xe_gt_init(struct xe_gt * gt)612 int xe_gt_init(struct xe_gt *gt)
613 {
614 int err;
615 int i;
616
617 INIT_WORK(>->reset.worker, gt_reset_worker);
618
619 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) {
620 gt->ring_ops[i] = xe_ring_ops_get(gt, i);
621 xe_hw_fence_irq_init(>->fence_irq[i]);
622 }
623
624 err = devm_add_action_or_reset(gt_to_xe(gt)->drm.dev, xe_gt_fini, gt);
625 if (err)
626 return err;
627
628 err = xe_gt_sysfs_init(gt);
629 if (err)
630 return err;
631
632 err = gt_init_with_gt_forcewake(gt);
633 if (err)
634 return err;
635
636 err = xe_gt_pagefault_init(gt);
637 if (err)
638 return err;
639
640 err = xe_gt_idle_init(>->gtidle);
641 if (err)
642 return err;
643
644 err = xe_gt_freq_init(gt);
645 if (err)
646 return err;
647
648 xe_force_wake_init_engines(gt, gt_to_fw(gt));
649
650 err = gt_init_with_all_forcewake(gt);
651 if (err)
652 return err;
653
654 xe_gt_record_user_engines(gt);
655
656 err = xe_eu_stall_init(gt);
657 if (err)
658 return err;
659
660 return 0;
661 }
662
663 /**
664 * xe_gt_mmio_init() - Initialize GT's MMIO access
665 * @gt: the GT object
666 *
667 * Initialize GT's MMIO accessor, which will be used to access registers inside
668 * this GT.
669 */
xe_gt_mmio_init(struct xe_gt * gt)670 void xe_gt_mmio_init(struct xe_gt *gt)
671 {
672 struct xe_tile *tile = gt_to_tile(gt);
673 struct xe_device *xe = tile_to_xe(tile);
674
675 xe_mmio_init(>->mmio, tile, tile->mmio.regs, tile->mmio.regs_size);
676
677 if (gt->info.type == XE_GT_TYPE_MEDIA) {
678 gt->mmio.adj_offset = MEDIA_GT_GSI_OFFSET;
679 gt->mmio.adj_limit = MEDIA_GT_GSI_LENGTH;
680 } else {
681 gt->mmio.adj_offset = 0;
682 gt->mmio.adj_limit = 0;
683 }
684
685 if (IS_SRIOV_VF(xe))
686 gt->mmio.sriov_vf_gt = gt;
687 }
688
xe_gt_record_user_engines(struct xe_gt * gt)689 void xe_gt_record_user_engines(struct xe_gt *gt)
690 {
691 struct xe_hw_engine *hwe;
692 enum xe_hw_engine_id id;
693
694 gt->user_engines.mask = 0;
695 memset(gt->user_engines.instances_per_class, 0,
696 sizeof(gt->user_engines.instances_per_class));
697
698 for_each_hw_engine(hwe, gt, id) {
699 if (xe_hw_engine_is_reserved(hwe))
700 continue;
701
702 gt->user_engines.mask |= BIT_ULL(id);
703 gt->user_engines.instances_per_class[hwe->class]++;
704 }
705
706 xe_gt_assert(gt, (gt->user_engines.mask | gt->info.engine_mask)
707 == gt->info.engine_mask);
708 }
709
do_gt_reset(struct xe_gt * gt)710 static int do_gt_reset(struct xe_gt *gt)
711 {
712 int err;
713
714 if (IS_SRIOV_VF(gt_to_xe(gt)))
715 return xe_gt_sriov_vf_reset(gt);
716
717 xe_gsc_wa_14015076503(gt, true);
718
719 xe_mmio_write32(>->mmio, GDRST, GRDOM_FULL);
720 err = xe_mmio_wait32(>->mmio, GDRST, GRDOM_FULL, 0, 5000, NULL, false);
721 if (err)
722 xe_gt_err(gt, "failed to clear GRDOM_FULL (%pe)\n",
723 ERR_PTR(err));
724
725 xe_gsc_wa_14015076503(gt, false);
726
727 return err;
728 }
729
vf_gt_restart(struct xe_gt * gt)730 static int vf_gt_restart(struct xe_gt *gt)
731 {
732 int err;
733
734 err = xe_uc_sanitize_reset(>->uc);
735 if (err)
736 return err;
737
738 err = xe_uc_load_hw(>->uc);
739 if (err)
740 return err;
741
742 err = xe_uc_start(>->uc);
743 if (err)
744 return err;
745
746 return 0;
747 }
748
do_gt_restart(struct xe_gt * gt)749 static int do_gt_restart(struct xe_gt *gt)
750 {
751 struct xe_hw_engine *hwe;
752 enum xe_hw_engine_id id;
753 int err;
754
755 if (IS_SRIOV_VF(gt_to_xe(gt)))
756 return vf_gt_restart(gt);
757
758 xe_pat_init(gt);
759
760 xe_gt_enable_host_l2_vram(gt);
761
762 xe_gt_mcr_set_implicit_defaults(gt);
763 xe_reg_sr_apply_mmio(>->reg_sr, gt);
764
765 err = xe_wopcm_init(>->uc.wopcm);
766 if (err)
767 return err;
768
769 for_each_hw_engine(hwe, gt, id)
770 xe_hw_engine_enable_ring(hwe);
771
772 err = xe_uc_sanitize_reset(>->uc);
773 if (err)
774 return err;
775
776 err = xe_uc_load_hw(>->uc);
777 if (err)
778 return err;
779
780 if (IS_SRIOV_PF(gt_to_xe(gt)) && xe_gt_is_main_type(gt))
781 xe_lmtt_init_hw(>_to_tile(gt)->sriov.pf.lmtt);
782
783 if (IS_SRIOV_PF(gt_to_xe(gt)))
784 xe_gt_sriov_pf_init_hw(gt);
785
786 xe_mocs_init(gt);
787 err = xe_uc_start(>->uc);
788 if (err)
789 return err;
790
791 for_each_hw_engine(hwe, gt, id)
792 xe_reg_sr_apply_mmio(&hwe->reg_sr, gt);
793
794 /* Get CCS mode in sync between sw/hw */
795 xe_gt_apply_ccs_mode(gt);
796
797 /* Restore GT freq to expected values */
798 xe_gt_sanitize_freq(gt);
799
800 if (IS_SRIOV_PF(gt_to_xe(gt)))
801 xe_gt_sriov_pf_restart(gt);
802
803 return 0;
804 }
805
gt_wait_reset_unblock(struct xe_gt * gt)806 static int gt_wait_reset_unblock(struct xe_gt *gt)
807 {
808 return xe_guc_wait_reset_unblock(>->uc.guc);
809 }
810
gt_reset(struct xe_gt * gt)811 static int gt_reset(struct xe_gt *gt)
812 {
813 unsigned int fw_ref;
814 int err;
815
816 if (xe_device_wedged(gt_to_xe(gt)))
817 return -ECANCELED;
818
819 /* We only support GT resets with GuC submission */
820 if (!xe_device_uc_enabled(gt_to_xe(gt)))
821 return -ENODEV;
822
823 xe_gt_info(gt, "reset started\n");
824
825 err = gt_wait_reset_unblock(gt);
826 if (!err)
827 xe_gt_warn(gt, "reset block failed to get lifted");
828
829 xe_pm_runtime_get(gt_to_xe(gt));
830
831 if (xe_fault_inject_gt_reset()) {
832 err = -ECANCELED;
833 goto err_fail;
834 }
835
836 xe_gt_sanitize(gt);
837
838 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);
839 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) {
840 err = -ETIMEDOUT;
841 goto err_out;
842 }
843
844 if (IS_SRIOV_PF(gt_to_xe(gt)))
845 xe_gt_sriov_pf_stop_prepare(gt);
846
847 xe_uc_gucrc_disable(>->uc);
848 xe_uc_stop_prepare(>->uc);
849 xe_gt_pagefault_reset(gt);
850
851 xe_uc_stop(>->uc);
852
853 xe_tlb_inval_reset(>->tlb_inval);
854
855 err = do_gt_reset(gt);
856 if (err)
857 goto err_out;
858
859 err = do_gt_restart(gt);
860 if (err)
861 goto err_out;
862
863 xe_force_wake_put(gt_to_fw(gt), fw_ref);
864 xe_pm_runtime_put(gt_to_xe(gt));
865
866 xe_gt_info(gt, "reset done\n");
867
868 return 0;
869
870 err_out:
871 xe_force_wake_put(gt_to_fw(gt), fw_ref);
872 XE_WARN_ON(xe_uc_start(>->uc));
873 err_fail:
874 xe_gt_err(gt, "reset failed (%pe)\n", ERR_PTR(err));
875
876 xe_device_declare_wedged(gt_to_xe(gt));
877 xe_pm_runtime_put(gt_to_xe(gt));
878
879 return err;
880 }
881
gt_reset_worker(struct work_struct * w)882 static void gt_reset_worker(struct work_struct *w)
883 {
884 struct xe_gt *gt = container_of(w, typeof(*gt), reset.worker);
885
886 gt_reset(gt);
887 }
888
xe_gt_reset_async(struct xe_gt * gt)889 void xe_gt_reset_async(struct xe_gt *gt)
890 {
891 xe_gt_info(gt, "trying reset from %ps\n", __builtin_return_address(0));
892
893 /* Don't do a reset while one is already in flight */
894 if (!xe_fault_inject_gt_reset() && xe_uc_reset_prepare(>->uc))
895 return;
896
897 xe_gt_info(gt, "reset queued\n");
898 queue_work(gt->ordered_wq, >->reset.worker);
899 }
900
xe_gt_suspend_prepare(struct xe_gt * gt)901 void xe_gt_suspend_prepare(struct xe_gt *gt)
902 {
903 unsigned int fw_ref;
904
905 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);
906
907 xe_uc_suspend_prepare(>->uc);
908
909 xe_force_wake_put(gt_to_fw(gt), fw_ref);
910 }
911
xe_gt_suspend(struct xe_gt * gt)912 int xe_gt_suspend(struct xe_gt *gt)
913 {
914 unsigned int fw_ref;
915 int err;
916
917 xe_gt_dbg(gt, "suspending\n");
918 xe_gt_sanitize(gt);
919
920 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);
921 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL))
922 goto err_msg;
923
924 err = xe_uc_suspend(>->uc);
925 if (err)
926 goto err_force_wake;
927
928 xe_gt_idle_disable_pg(gt);
929
930 xe_gt_disable_host_l2_vram(gt);
931
932 xe_force_wake_put(gt_to_fw(gt), fw_ref);
933 xe_gt_dbg(gt, "suspended\n");
934
935 return 0;
936
937 err_msg:
938 err = -ETIMEDOUT;
939 err_force_wake:
940 xe_force_wake_put(gt_to_fw(gt), fw_ref);
941 xe_gt_err(gt, "suspend failed (%pe)\n", ERR_PTR(err));
942
943 return err;
944 }
945
xe_gt_shutdown(struct xe_gt * gt)946 void xe_gt_shutdown(struct xe_gt *gt)
947 {
948 unsigned int fw_ref;
949
950 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);
951 do_gt_reset(gt);
952 xe_force_wake_put(gt_to_fw(gt), fw_ref);
953 }
954
955 /**
956 * xe_gt_sanitize_freq() - Restore saved frequencies if necessary.
957 * @gt: the GT object
958 *
959 * Called after driver init/GSC load completes to restore GT frequencies if we
960 * limited them for any WAs.
961 */
xe_gt_sanitize_freq(struct xe_gt * gt)962 int xe_gt_sanitize_freq(struct xe_gt *gt)
963 {
964 int ret = 0;
965
966 if ((!xe_uc_fw_is_available(>->uc.gsc.fw) ||
967 xe_uc_fw_is_loaded(>->uc.gsc.fw) ||
968 xe_uc_fw_is_in_error_state(>->uc.gsc.fw)) &&
969 XE_GT_WA(gt, 22019338487))
970 ret = xe_guc_pc_restore_stashed_freq(>->uc.guc.pc);
971
972 return ret;
973 }
974
xe_gt_resume(struct xe_gt * gt)975 int xe_gt_resume(struct xe_gt *gt)
976 {
977 unsigned int fw_ref;
978 int err;
979
980 xe_gt_dbg(gt, "resuming\n");
981 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);
982 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL))
983 goto err_msg;
984
985 err = do_gt_restart(gt);
986 if (err)
987 goto err_force_wake;
988
989 xe_gt_idle_enable_pg(gt);
990
991 xe_force_wake_put(gt_to_fw(gt), fw_ref);
992 xe_gt_dbg(gt, "resumed\n");
993
994 return 0;
995
996 err_msg:
997 err = -ETIMEDOUT;
998 err_force_wake:
999 xe_force_wake_put(gt_to_fw(gt), fw_ref);
1000 xe_gt_err(gt, "resume failed (%pe)\n", ERR_PTR(err));
1001
1002 return err;
1003 }
1004
xe_gt_hw_engine(struct xe_gt * gt,enum xe_engine_class class,u16 instance,bool logical)1005 struct xe_hw_engine *xe_gt_hw_engine(struct xe_gt *gt,
1006 enum xe_engine_class class,
1007 u16 instance, bool logical)
1008 {
1009 struct xe_hw_engine *hwe;
1010 enum xe_hw_engine_id id;
1011
1012 for_each_hw_engine(hwe, gt, id)
1013 if (hwe->class == class &&
1014 ((!logical && hwe->instance == instance) ||
1015 (logical && hwe->logical_instance == instance)))
1016 return hwe;
1017
1018 return NULL;
1019 }
1020
xe_gt_any_hw_engine_by_reset_domain(struct xe_gt * gt,enum xe_engine_class class)1021 struct xe_hw_engine *xe_gt_any_hw_engine_by_reset_domain(struct xe_gt *gt,
1022 enum xe_engine_class class)
1023 {
1024 struct xe_hw_engine *hwe;
1025 enum xe_hw_engine_id id;
1026
1027 for_each_hw_engine(hwe, gt, id) {
1028 switch (class) {
1029 case XE_ENGINE_CLASS_RENDER:
1030 case XE_ENGINE_CLASS_COMPUTE:
1031 if (hwe->class == XE_ENGINE_CLASS_RENDER ||
1032 hwe->class == XE_ENGINE_CLASS_COMPUTE)
1033 return hwe;
1034 break;
1035 default:
1036 if (hwe->class == class)
1037 return hwe;
1038 }
1039 }
1040
1041 return NULL;
1042 }
1043
xe_gt_any_hw_engine(struct xe_gt * gt)1044 struct xe_hw_engine *xe_gt_any_hw_engine(struct xe_gt *gt)
1045 {
1046 struct xe_hw_engine *hwe;
1047 enum xe_hw_engine_id id;
1048
1049 for_each_hw_engine(hwe, gt, id)
1050 return hwe;
1051
1052 return NULL;
1053 }
1054
1055 /**
1056 * xe_gt_declare_wedged() - Declare GT wedged
1057 * @gt: the GT object
1058 *
1059 * Wedge the GT which stops all submission, saves desired debug state, and
1060 * cleans up anything which could timeout.
1061 */
xe_gt_declare_wedged(struct xe_gt * gt)1062 void xe_gt_declare_wedged(struct xe_gt *gt)
1063 {
1064 xe_gt_assert(gt, gt_to_xe(gt)->wedged.mode);
1065
1066 xe_uc_declare_wedged(>->uc);
1067 xe_tlb_inval_reset(>->tlb_inval);
1068 }
1069