1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef _XE_SCHED_JOB_TYPES_H_ 7 #define _XE_SCHED_JOB_TYPES_H_ 8 9 #include <linux/kref.h> 10 11 #include <drm/gpu_scheduler.h> 12 13 struct xe_exec_queue; 14 struct dma_fence; 15 struct dma_fence_chain; 16 17 /** 18 * struct xe_job_ptrs - Per hw engine instance data 19 */ 20 struct xe_job_ptrs { 21 /** @lrc_fence: Pre-allocated uinitialized lrc fence.*/ 22 struct dma_fence *lrc_fence; 23 /** @chain_fence: Pre-allocated ninitialized fence chain node. */ 24 struct dma_fence_chain *chain_fence; 25 /** @batch_addr: Batch buffer address. */ 26 u64 batch_addr; 27 }; 28 29 /** 30 * struct xe_sched_job - XE schedule job (batch buffer tracking) 31 */ 32 struct xe_sched_job { 33 /** @drm: base DRM scheduler job */ 34 struct drm_sched_job drm; 35 /** @q: Exec queue */ 36 struct xe_exec_queue *q; 37 /** @refcount: ref count of this job */ 38 struct kref refcount; 39 /** 40 * @fence: dma fence to indicate completion. 1 way relationship - job 41 * can safely reference fence, fence cannot safely reference job. 42 */ 43 struct dma_fence *fence; 44 /** @user_fence: write back value when BB is complete */ 45 struct { 46 /** @user_fence.used: user fence is used */ 47 bool used; 48 /** @user_fence.addr: address to write to */ 49 u64 addr; 50 /** @user_fence.value: write back value */ 51 u64 value; 52 } user_fence; 53 /** @lrc_seqno: LRC seqno */ 54 u32 lrc_seqno; 55 /** @migrate_flush_flags: Additional flush flags for migration jobs */ 56 u32 migrate_flush_flags; 57 /** @ring_ops_flush_tlb: The ring ops need to flush TLB before payload. */ 58 bool ring_ops_flush_tlb; 59 /** @ggtt: mapped in ggtt. */ 60 bool ggtt; 61 /** @ptrs: per instance pointers. */ 62 struct xe_job_ptrs ptrs[]; 63 }; 64 65 struct xe_sched_job_snapshot { 66 u16 batch_addr_len; 67 u64 batch_addr[] __counted_by(batch_addr_len); 68 }; 69 70 #endif 71