1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * AMD Platform Management Framework Driver 4 * 5 * Copyright (c) 2022, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 9 */ 10 11 #ifndef PMF_H 12 #define PMF_H 13 14 #include <linux/acpi.h> 15 #include <linux/amd-pmf-io.h> 16 #include <linux/bits.h> 17 #include <linux/circ_buf.h> 18 #include <linux/compiler_attributes.h> 19 #include <linux/compiler_types.h> 20 #include <linux/errno.h> 21 #include <linux/input.h> 22 #include <linux/mutex_types.h> 23 #include <linux/power_supply.h> 24 #include <linux/platform_device.h> 25 #include <linux/platform_profile.h> 26 #include <linux/types.h> 27 28 #define POLICY_BUF_MAX_SZ 0x4b000 29 #define POLICY_SIGN_COOKIE 0x31535024 30 #define POLICY_COOKIE_OFFSET 0x10 31 32 /* List of supported CPU ids */ 33 #define AMD_CPU_ID_RMB 0x14b5 34 #define AMD_CPU_ID_PS 0x14e8 35 #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507 36 #define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122 37 #define PCI_DEVICE_ID_AMD_1AH_M80H_ROOT 0x115b 38 39 /* Aliases required by PCI_DEVICE_DATA() macro naming convention */ 40 #define PCI_DEVICE_ID_AMD_CPU_ID_RMB AMD_CPU_ID_RMB 41 #define PCI_DEVICE_ID_AMD_CPU_ID_PS AMD_CPU_ID_PS 42 43 struct cookie_header { 44 u32 sign; 45 u32 length; 46 } __packed; 47 48 /* APMF Functions */ 49 #define APMF_FUNC_VERIFY_INTERFACE 0 50 #define APMF_FUNC_GET_SYS_PARAMS 1 51 #define APMF_FUNC_SBIOS_REQUESTS 2 52 #define APMF_FUNC_SBIOS_HEARTBEAT 4 53 #define APMF_FUNC_AUTO_MODE 5 54 #define APMF_FUNC_SET_FAN_IDX 7 55 #define APMF_FUNC_OS_POWER_SLIDER_UPDATE 8 56 #define APMF_FUNC_STATIC_SLIDER_GRANULAR 9 57 #define APMF_FUNC_DYN_SLIDER_AC 11 58 #define APMF_FUNC_DYN_SLIDER_DC 12 59 #define APMF_FUNC_NOTIFY_SMART_PC_UPDATES 14 60 #define APMF_FUNC_SBIOS_HEARTBEAT_V2 16 61 62 /* Message Definitions */ 63 #define SET_SPL 0x03 /* SPL: Sustained Power Limit */ 64 #define SET_SPPT 0x05 /* SPPT: Slow Package Power Tracking */ 65 #define SET_FPPT 0x07 /* FPPT: Fast Package Power Tracking */ 66 #define GET_SPL 0x0B 67 #define GET_SPPT 0x0D 68 #define GET_FPPT 0x0F 69 #define SET_DRAM_ADDR_HIGH 0x14 70 #define SET_DRAM_ADDR_LOW 0x15 71 #define SET_TRANSFER_TABLE 0x16 72 #define SET_STT_MIN_LIMIT 0x18 /* STT: Skin Temperature Tracking */ 73 #define SET_STT_LIMIT_APU 0x19 74 #define SET_STT_LIMIT_HS2 0x1A 75 #define SET_SPPT_APU_ONLY 0x1D 76 #define GET_SPPT_APU_ONLY 0x1E 77 #define GET_STT_MIN_LIMIT 0x1F 78 #define GET_STT_LIMIT_APU 0x20 79 #define GET_STT_LIMIT_HS2 0x21 80 #define SET_P3T 0x23 /* P3T: Peak Package Power Limit */ 81 #define SET_PMF_PPT 0x25 82 #define SET_PMF_PPT_APU_ONLY 0x26 83 84 /* Message IDs for 1AH_M80H platform */ 85 #define GET_1AH_M80H_METRICS_TABLE_LOG_SAMPLE 0x0E 86 #define GET_1AH_M80H_METRICS_TABLE_DRAM_ADDR 0x0F 87 88 /* OS slider update notification */ 89 #define DC_BEST_PERF 0 90 #define DC_BETTER_PERF 1 91 #define DC_BATTERY_SAVER 3 92 #define AC_BEST_PERF 4 93 #define AC_BETTER_PERF 5 94 #define AC_BETTER_BATTERY 6 95 96 /* Fan Index for Auto Mode */ 97 #define FAN_INDEX_AUTO 0xFFFFFFFF 98 99 #define ARG_NONE 0 100 #define AVG_SAMPLE_SIZE 3 101 102 /* Policy Actions */ 103 #define PMF_POLICY_SPL 2 104 #define PMF_POLICY_SPPT 3 105 #define PMF_POLICY_FPPT 4 106 #define PMF_POLICY_SPPT_APU_ONLY 5 107 #define PMF_POLICY_STT_MIN 6 108 #define PMF_POLICY_STT_SKINTEMP_APU 7 109 #define PMF_POLICY_STT_SKINTEMP_HS2 8 110 #define PMF_POLICY_SYSTEM_STATE 9 111 #define PMF_POLICY_BIOS_OUTPUT_1 10 112 #define PMF_POLICY_BIOS_OUTPUT_2 11 113 #define PMF_POLICY_P3T 38 114 #define PMF_POLICY_PMF_PPT 54 115 #define PMF_POLICY_PMF_PPT_APU_ONLY 55 116 #define PMF_POLICY_BIOS_OUTPUT_3 57 117 #define PMF_POLICY_BIOS_OUTPUT_4 58 118 #define PMF_POLICY_BIOS_OUTPUT_5 59 119 #define PMF_POLICY_BIOS_OUTPUT_6 60 120 #define PMF_POLICY_BIOS_OUTPUT_7 61 121 #define PMF_POLICY_BIOS_OUTPUT_8 62 122 #define PMF_POLICY_BIOS_OUTPUT_9 63 123 #define PMF_POLICY_BIOS_OUTPUT_10 64 124 125 /* TA macros */ 126 #define PMF_TA_IF_VERSION_MAJOR 1 127 #define TA_PMF_ACTION_MAX 32 128 #define TA_PMF_UNDO_MAX 8 129 #define TA_OUTPUT_RESERVED_MEM 922 130 #define MAX_OPERATION_PARAMS 4 131 132 #define TA_ERROR_CRYPTO_INVALID_PARAM 0x20002 133 #define TA_ERROR_CRYPTO_BIN_TOO_LARGE 0x2000d 134 135 #define PMF_IF_V1 1 136 #define PMF_IF_V2 2 137 138 #define APTS_MAX_STATES 16 139 #define CUSTOM_BIOS_INPUT_BITS GENMASK(16, 7) 140 #define BIOS_INPUTS_MAX 10 141 #define CUSTOM_BIOS_INPUT_RING_ENTRIES 64 /* Must be power of two for CIRC_* macros */ 142 143 /* amd_pmf_send_cmd() set/get */ 144 #define SET_CMD false 145 #define GET_CMD true 146 147 #define METRICS_TABLE_ID 7 148 #define BIOS_OUTPUT_MAX 10 149 150 extern int metrics_table_loop_ms; 151 152 #define AMD_PMF_METRIC_CORE_TYPE_MAX 4 153 #define AMD_PMF_METRIC_CCX_MAX 4 154 #define AMD_PMF_NUM_CLK_DPM_LEVELS 8 155 #define AMD_PMF_NUM_MAX_CORES 12 156 157 typedef void (*apmf_event_handler_t)(acpi_handle handle, u32 event, void *data); 158 159 static const uuid_t amd_pmf_ta_uuid[] __used = { UUID_INIT(0xd9b39bf2, 0x66bd, 0x4154, 0xaf, 0xb8, 160 0x8a, 0xcc, 0x2b, 0x2b, 0x60, 0xd6), 161 UUID_INIT(0x6fd93b77, 0x3fb8, 0x524d, 0xb1, 0x2d, 162 0xc5, 0x29, 0xb1, 0x3d, 0x85, 0x43), 163 }; 164 165 /* APTS PMF BIOS Interface */ 166 struct amd_pmf_apts_output { 167 u16 table_version; 168 u32 fan_table_idx; 169 u32 pmf_ppt; 170 u32 ppt_pmf_apu_only; 171 u32 stt_min_limit; 172 u8 stt_skin_temp_limit_apu; 173 u8 stt_skin_temp_limit_hs2; 174 } __packed; 175 176 struct amd_pmf_apts_granular_output { 177 u16 size; 178 struct amd_pmf_apts_output val; 179 } __packed; 180 181 struct amd_pmf_apts_granular { 182 u16 size; 183 struct amd_pmf_apts_output val[APTS_MAX_STATES]; 184 }; 185 186 struct sbios_hb_event_v2 { 187 u16 size; 188 u8 load; 189 u8 unload; 190 u8 suspend; 191 u8 resume; 192 } __packed; 193 194 enum sbios_hb_v2 { 195 ON_LOAD, 196 ON_UNLOAD, 197 ON_SUSPEND, 198 ON_RESUME, 199 }; 200 201 /* AMD PMF BIOS interfaces */ 202 struct apmf_verify_interface { 203 u16 size; 204 u16 version; 205 u32 notification_mask; 206 u32 supported_functions; 207 } __packed; 208 209 struct apmf_system_params { 210 u16 size; 211 u32 valid_mask; 212 u32 flags; 213 u8 command_code; 214 u32 heartbeat_int; 215 } __packed; 216 217 struct apmf_sbios_req { 218 u16 size; 219 u32 pending_req; 220 u8 rsd; 221 u8 cql_event; 222 u8 amt_event; 223 u32 fppt; 224 u32 sppt; 225 u32 fppt_apu_only; 226 u32 spl; 227 u32 stt_min_limit; 228 u8 skin_temp_apu; 229 u8 skin_temp_hs2; 230 } __packed; 231 232 /* As per APMF spec 1.3 */ 233 struct apmf_sbios_req_v1 { 234 u16 size; 235 u32 pending_req; 236 u8 rsvd; 237 u8 cql_event; 238 u8 amt_event; 239 u32 fppt; 240 u32 sppt; 241 u32 sppt_apu_only; 242 u32 spl; 243 u32 stt_min_limit; 244 u8 skin_temp_apu; 245 u8 skin_temp_hs2; 246 u8 enable_cnqf; 247 u32 custom_policy[BIOS_INPUTS_MAX]; 248 } __packed; 249 250 struct apmf_sbios_req_v2 { 251 u16 size; 252 u32 pending_req; 253 u8 rsd; 254 u32 ppt_pmf; 255 u32 ppt_pmf_apu_only; 256 u32 stt_min_limit; 257 u8 skin_temp_apu; 258 u8 skin_temp_hs2; 259 u32 custom_policy[BIOS_INPUTS_MAX]; 260 } __packed; 261 262 struct apmf_fan_idx { 263 u16 size; 264 u8 fan_ctl_mode; 265 u32 fan_ctl_idx; 266 } __packed; 267 268 struct amd_pmf_metrics_iod { 269 u32 counter_acc; 270 /* Set Voltage */ 271 u64 vddcr_set_voltage; 272 u64 vddcr_soc_set_voltage; 273 u64 vddcr_npu_set_voltage; 274 u64 vddcr_lp_set_voltage; 275 u64 vddcr_gfx_set_voltage; 276 u64 vdd_misc_set_voltage; 277 /* Telemetry Voltages */ 278 u64 vddcr_telemetry_voltage; 279 u64 vddcr_soc_telemetry_voltage; 280 u64 vddcr_npu_telemetry_voltage; 281 u64 vddcr_lp_telemetry_voltage; 282 u64 vddcr_gfx_telemetry_voltage; 283 u64 vdd_misc_telemetry_voltage; 284 /* Telemetry Powers */ 285 u64 vddcr_telemetry_power; 286 u64 vddcr_soc_telemetry_power; 287 u64 vddcr_npu_telemetry_power; 288 u64 vddcr_lp_telemetry_power; 289 u64 vddcr_gfx_telemetry_power; 290 u64 vdd_misc_telemetry_power; 291 /* Throttlers - Fast PPT */ 292 u32 fppt_fused_limit; 293 u32 fppt_max_irm_limit; 294 u32 fppt_max_pbo_limit; 295 u32 fppt_limit; 296 u64 fppt_value_acc; 297 u32 fppt_residency_acc; 298 /* Throttlers - Slow PPT */ 299 u32 sppt_fused_limit; 300 u32 sppt_max_irm_limit; 301 u32 sppt_max_pbo_limit; 302 u32 sppt_limit; 303 u64 sppt_value_acc; 304 u32 sppt_residency_acc; 305 /* Throttlers - STAPM */ 306 u32 spl_fused_limit; 307 u32 spl_max_irm_limit; 308 u32 spl_max_pbo_limit; 309 u32 spl_limit; 310 u64 spl_value_acc; 311 u32 spl_residency_acc; 312 /* Throttlers - TDC VDDCR */ 313 u32 tdc_vddcr_fused_limit; 314 u32 tdc_vddcr_max_irm_limit; 315 u32 tdc_vddcr_max_pbo_limit; 316 u32 tdc_vddcr_limit; 317 u64 tdc_vddcr_value_acc; 318 u32 tdc_vddcr_residency_acc; 319 /* Throttlers - TDC VDDCR_SOC */ 320 u32 tdc_vddcr_soc_fused_limit; 321 u32 tdc_vddcr_soc_max_irm_limit; 322 u32 tdc_vddcr_soc_max_pbo_limit; 323 u32 tdc_vddcr_soc_limit; 324 u64 tdc_vddcr_soc_value_acc; 325 u32 tdc_vddcr_soc_residency_acc; 326 /* Throttlers - TDC VDDCR_NPU */ 327 u32 tdc_vddcr_npu_fused_limit; 328 u32 tdc_vddcr_npu_max_irm_limit; 329 u32 tdc_vddcr_npu_max_pbo_limit; 330 u32 tdc_vddcr_npu_limit; 331 u64 tdc_vddcr_npu_value_acc; 332 u32 tdc_vddcr_npu_residency_acc; 333 /* Throttlers - TDC VDDCR_LP */ 334 u32 tdc_vddcr_lp_fused_limit; 335 u32 tdc_vddcr_lp_max_irm_limit; 336 u32 tdc_vddcr_lp_max_pbo_limit; 337 u32 tdc_vddcr_lp_limit; 338 u64 tdc_vddcr_lp_value_acc; 339 u32 tdc_vddcr_lp_residency_acc; 340 /* Throttlers - TDC VDDCR_GFX */ 341 u32 tdc_vddcr_gfx_fused_limit; 342 u32 tdc_vddcr_gfx_max_irm_limit; 343 u32 tdc_vddcr_gfx_max_pbo_limit; 344 u32 tdc_vddcr_gfx_limit; 345 u64 tdc_vddcr_gfx_value_acc; 346 u32 tdc_vddcr_gfx_residency_acc; 347 /* Throttlers - EDC VDDCR */ 348 u32 edc_vddcr_fused_limit; 349 u32 edc_vddcr_max_irm_limit; 350 u32 edc_vddcr_max_pbo_limit; 351 u32 edc_vddcr_limit; 352 /* Throttlers - Thermal */ 353 u32 thm_fused_limit; 354 u32 thm_limit; 355 u64 thm_value_acc; 356 u32 thm_residency_acc; 357 u32 prochot_residency_acc; 358 u64 gfx_temp_acc; 359 u64 soc_temp_acc; 360 u32 p3t_fused_limit; 361 u64 p3t_value_acc; 362 /* Power */ 363 u64 system_power_acc; 364 u64 apu_power_acc; 365 u64 dgpu_power_acc; 366 u64 npu_power_acc; 367 /* Frequencies */ 368 u64 fclk_freq_eff_acc; 369 u64 memclk_freq_eff_acc; 370 u64 lclk_freq_eff_acc; 371 u64 gfxclk_freq_eff_acc; 372 u64 socclk_freq_eff_acc; 373 u64 vclk_freq_eff_acc; 374 u64 vpeclk_freq_eff_acc; 375 u64 aieclk_freq_eff_acc; 376 u64 npuhclk_freq_eff_acc; 377 /* Bandwidth */ 378 u64 dram_read_bandwidth; 379 u64 dram_write_bandwidth; 380 /* Activity Monitors */ 381 u64 gfx_busy_acc; 382 u64 vcn_busy_acc; 383 u64 npu_busy_acc[3]; 384 /* STT Limits */ 385 u32 stt_min_limit; 386 u64 stt_apu_hotspot_temp_acc; 387 u64 stt_hs2_hotspot_temp_acc; 388 u32 stt_apu_temp_limit; 389 u64 stt_apu_skin_temp_acc; 390 /* Residencies */ 391 u64 cpuoff_residency_ccx0; 392 u64 cpuoff_residency_ccx1; 393 u64 cpuoff_residency_ccx2; 394 u64 cpuoff_residency_ccx3; 395 /* DF-pstates */ 396 u32 fclk_freq_table[AMD_PMF_NUM_CLK_DPM_LEVELS]; 397 u32 uclk_freq_table[AMD_PMF_NUM_CLK_DPM_LEVELS]; 398 u32 ddr_rate_table[AMD_PMF_NUM_CLK_DPM_LEVELS]; 399 u8 dfpstate_source[AMD_PMF_NUM_CLK_DPM_LEVELS]; 400 /* System */ 401 u8 gfx_disabled; 402 u8 spare2[3]; 403 u32 gfxclk_fmax; 404 u8 cclk_core_fuse_enable[AMD_PMF_METRIC_CORE_TYPE_MAX][AMD_PMF_NUM_MAX_CORES]; 405 u8 cclk_core_enabled[AMD_PMF_METRIC_CORE_TYPE_MAX][AMD_PMF_NUM_MAX_CORES]; 406 u32 cclk_fmax[AMD_PMF_METRIC_CORE_TYPE_MAX][AMD_PMF_NUM_MAX_CORES]; 407 /* Overclock Capable */ 408 u8 cpu_precise_and_direct_oc_capable; 409 u8 gfx_precise_and_direct_oc_capable; 410 u8 pbo_basic_oc_capable; 411 u8 pbo_advanced_oc_capable; 412 u8 pbo_nitro_oc_capable; 413 u8 memory_and_fabric_oc_capable; 414 u8 misc_oc_capable; 415 u8 extreme_cold_oc_capable; 416 u8 down_config_control_capable; 417 u8 spare0[3]; 418 /* Overclock Status */ 419 u32 fit_limit_scalar; 420 u8 ln2_enabled; 421 u8 cpu_precise_and_direct_oc_enabled; 422 u8 gfx_precise_and_direct_oc_enabled; 423 u8 spare1[2]; 424 /* Voltage Guardband in PSM count */ 425 s8 psm_guardband[5][5][3]; 426 s32 core_power_limit_offset; 427 u32 max_freq_offset[5]; 428 u64 npu_temp_acc; 429 u64 dfpstate_residency_acc[AMD_PMF_NUM_CLK_DPM_LEVELS]; 430 u32 cclk_fboost; 431 /* PMF */ 432 u32 pmf_fast_apu_ppt_limit; 433 u64 pmf_fast_apu_ppt_value_acc; 434 u32 pmf_fast_apu_ppt_residency_acc; 435 u32 pmf_slow_apu_ppt_limit; 436 u64 pmf_slow_apu_ppt_value_acc; 437 u32 pmf_slow_apu_ppt_residency_acc; 438 u32 pmf_fast_spm_limit; 439 u64 pmf_fast_spm_value_acc; 440 u32 pmf_fast_spm_residency_acc; 441 u32 pmf_slow_spm_limit; 442 u64 pmf_slow_spm_value_acc; 443 u32 pmf_slow_spm_residency_acc; 444 u32 spare3[5]; 445 } __packed __aligned(4); 446 447 struct amd_pmf_metrics_ccx { 448 u64 core_c0[AMD_PMF_NUM_MAX_CORES]; 449 u64 core_cc6[AMD_PMF_NUM_MAX_CORES]; 450 u64 core_freq[AMD_PMF_NUM_MAX_CORES]; 451 u64 core_freqeff[AMD_PMF_NUM_MAX_CORES]; 452 u64 core_temp[AMD_PMF_NUM_MAX_CORES]; 453 u64 core_power[AMD_PMF_NUM_MAX_CORES]; 454 } __packed __aligned(4); 455 456 struct amd_pmf_metrics_v3 { 457 struct amd_pmf_metrics_iod iod; 458 struct amd_pmf_metrics_ccx ccx[AMD_PMF_METRIC_CCX_MAX]; 459 } __packed __aligned(4); 460 461 struct smu_pmf_metrics_v2 { 462 u16 core_frequency[16]; /* MHz */ 463 u16 core_power[16]; /* mW */ 464 u16 core_temp[16]; /* centi-C */ 465 u16 gfx_temp; /* centi-C */ 466 u16 soc_temp; /* centi-C */ 467 u16 stapm_opn_limit; /* mW */ 468 u16 stapm_cur_limit; /* mW */ 469 u16 infra_cpu_maxfreq; /* MHz */ 470 u16 infra_gfx_maxfreq; /* MHz */ 471 u16 skin_temp; /* centi-C */ 472 u16 gfxclk_freq; /* MHz */ 473 u16 fclk_freq; /* MHz */ 474 u16 gfx_activity; /* GFX busy % [0-100] */ 475 u16 socclk_freq; /* MHz */ 476 u16 vclk_freq; /* MHz */ 477 u16 vcn_activity; /* VCN busy % [0-100] */ 478 u16 vpeclk_freq; /* MHz */ 479 u16 npuclk_freq; /* MHz */ 480 u16 npu_busy[8]; /* NPU busy % [0-100] */ 481 u16 dram_reads; /* MB/sec */ 482 u16 dram_writes; /* MB/sec */ 483 u16 core_c0residency[16]; /* C0 residency % [0-100] */ 484 u16 npu_power; /* mW */ 485 u32 apu_power; /* mW */ 486 u32 gfx_power; /* mW */ 487 u32 dgpu_power; /* mW */ 488 u32 socket_power; /* mW */ 489 u32 all_core_power; /* mW */ 490 u32 filter_alpha_value; /* time constant [us] */ 491 u32 metrics_counter; 492 u16 memclk_freq; /* MHz */ 493 u16 mpnpuclk_freq; /* MHz */ 494 u16 npu_reads; /* MB/sec */ 495 u16 npu_writes; /* MB/sec */ 496 u32 throttle_residency_prochot; 497 u32 throttle_residency_spl; 498 u32 throttle_residency_fppt; 499 u32 throttle_residency_sppt; 500 u32 throttle_residency_thm_core; 501 u32 throttle_residency_thm_gfx; 502 u32 throttle_residency_thm_soc; 503 u16 psys; 504 u16 spare1; 505 u32 spare[6]; 506 } __packed; 507 508 struct smu_pmf_metrics { 509 u16 gfxclk_freq; /* in MHz */ 510 u16 socclk_freq; /* in MHz */ 511 u16 vclk_freq; /* in MHz */ 512 u16 dclk_freq; /* in MHz */ 513 u16 memclk_freq; /* in MHz */ 514 u16 spare; 515 u16 gfx_activity; /* in Centi */ 516 u16 uvd_activity; /* in Centi */ 517 u16 voltage[2]; /* in mV */ 518 u16 currents[2]; /* in mA */ 519 u16 power[2];/* in mW */ 520 u16 core_freq[8]; /* in MHz */ 521 u16 core_power[8]; /* in mW */ 522 u16 core_temp[8]; /* in centi-Celsius */ 523 u16 l3_freq; /* in MHz */ 524 u16 l3_temp; /* in centi-Celsius */ 525 u16 gfx_temp; /* in centi-Celsius */ 526 u16 soc_temp; /* in centi-Celsius */ 527 u16 throttler_status; 528 u16 current_socketpower; /* in mW */ 529 u16 stapm_orig_limit; /* in W */ 530 u16 stapm_cur_limit; /* in W */ 531 u32 apu_power; /* in mW */ 532 u32 dgpu_power; /* in mW */ 533 u16 vdd_tdc_val; /* in mA */ 534 u16 soc_tdc_val; /* in mA */ 535 u16 vdd_edc_val; /* in mA */ 536 u16 soc_edcv_al; /* in mA */ 537 u16 infra_cpu_maxfreq; /* in MHz */ 538 u16 infra_gfx_maxfreq; /* in MHz */ 539 u16 skin_temp; /* in centi-Celsius */ 540 u16 device_state; 541 u16 curtemp; /* in centi-Celsius */ 542 u16 filter_alpha_value; 543 u16 avg_gfx_clkfrequency; 544 u16 avg_fclk_frequency; 545 u16 avg_gfx_activity; 546 u16 avg_socclk_frequency; 547 u16 avg_vclk_frequency; 548 u16 avg_vcn_activity; 549 u16 avg_dram_reads; 550 u16 avg_dram_writes; 551 u16 avg_socket_power; 552 u16 avg_core_power[2]; 553 u16 avg_core_c0residency[16]; 554 u16 spare1; 555 u32 metrics_counter; 556 } __packed; 557 558 enum amd_stt_skin_temp { 559 STT_TEMP_APU, 560 STT_TEMP_HS2, 561 STT_TEMP_COUNT, 562 }; 563 564 enum amd_slider_op { 565 SLIDER_OP_GET, 566 SLIDER_OP_SET, 567 }; 568 569 enum power_source { 570 POWER_SOURCE_AC, 571 POWER_SOURCE_DC, 572 POWER_SOURCE_MAX, 573 }; 574 575 enum power_modes { 576 POWER_MODE_PERFORMANCE, 577 POWER_MODE_BALANCED_POWER, 578 POWER_MODE_POWER_SAVER, 579 POWER_MODE_MAX, 580 }; 581 582 enum power_modes_v2 { 583 POWER_MODE_BEST_PERFORMANCE, 584 POWER_MODE_BALANCED, 585 POWER_MODE_BEST_POWER_EFFICIENCY, 586 POWER_MODE_ENERGY_SAVE, 587 POWER_MODE_V2_MAX, 588 }; 589 590 struct pmf_bios_inputs_prev { 591 u32 custom_bios_inputs[BIOS_INPUTS_MAX]; 592 }; 593 594 /** 595 * struct pmf_bios_input_entry - Snapshot of custom BIOS input event 596 * @val: Array of custom BIOS input values 597 * @preq: Pending request value associated with this event 598 */ 599 struct pmf_bios_input_entry { 600 u32 val[BIOS_INPUTS_MAX]; 601 u32 preq; 602 }; 603 604 struct pmf_cbi_ring_buffer { 605 struct pmf_bios_input_entry data[CUSTOM_BIOS_INPUT_RING_ENTRIES]; 606 int head; 607 int tail; 608 }; 609 610 /* SoC-specific SMU mailbox register offsets */ 611 struct amd_pmf_smu_regs { 612 u32 msg_reg; 613 u32 resp_reg; 614 u32 arg_reg[3]; 615 }; 616 617 struct amd_pmf_arg_data { 618 u32 lo; 619 u32 hi; 620 u32 size; 621 }; 622 623 struct amd_pmf_dev { 624 void __iomem *regbase; 625 void __iomem *smu_virt_addr; 626 void *buf; 627 u32 base_addr; 628 u32 cpu_id; 629 struct device *dev; 630 struct mutex lock; /* protects the PMF interface */ 631 u32 supported_func; 632 enum platform_profile_option current_profile; 633 struct device *ppdev; /* platform profile class device */ 634 struct dentry *dbgfs_dir; 635 int hb_interval; /* SBIOS heartbeat interval */ 636 struct delayed_work heart_beat; 637 struct smu_pmf_metrics m_table; 638 struct smu_pmf_metrics_v2 m_table_v2; 639 struct delayed_work work_buffer; 640 ktime_t start_time; 641 int socket_power_history[AVG_SAMPLE_SIZE]; 642 int socket_power_history_idx; 643 bool amt_enabled; 644 struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */ 645 bool cnqf_enabled; 646 bool cnqf_supported; 647 struct notifier_block pwr_src_notifier; 648 /* Smart PC solution builder */ 649 struct dentry *esbin; 650 unsigned char *policy_buf; 651 resource_size_t policy_sz; 652 struct tee_context *tee_ctx; 653 struct tee_shm *fw_shm_pool; 654 u32 session_id; 655 void *shbuf; 656 struct delayed_work pb_work; 657 struct pmf_action_table *prev_data; 658 resource_size_t policy_addr; 659 void __iomem *policy_base; 660 bool smart_pc_enabled; 661 u16 pmf_if_version; 662 struct input_dev *pmf_idev; 663 size_t mtable_size; 664 struct resource *res; 665 struct apmf_sbios_req_v2 req; /* To get custom bios pending request */ 666 struct mutex cb_mutex; 667 u32 notifications; 668 struct apmf_sbios_req_v1 req1; 669 struct pmf_bios_inputs_prev cb_prev; /* To preserve custom BIOS inputs */ 670 bool cb_flag; /* To handle first custom BIOS input */ 671 struct pmf_cbi_ring_buffer cbi_buf; 672 struct mutex cbi_mutex; /* Protects ring buffer access */ 673 struct mutex metrics_mutex; 674 u32 bios_output[BIOS_OUTPUT_MAX]; 675 const struct amd_pmf_smu_regs *smu_regs; 676 void __iomem *metrics_table_virt; /* Mapped DRAM virtual address for metrics table */ 677 phys_addr_t metrics_table_phys; /* DRAM physical address for metrics table */ 678 struct amd_pmf_metrics_v3 mtable_v3; /* IOD and CCX */ 679 struct amd_pmf_arg_data dram_addr; 680 struct amd_pmf_metrics_v3 prev_metrics; /* Previous metrics for delta calculation */ 681 bool npu_metrics_have_prev; 682 }; 683 684 struct apmf_sps_prop_granular_v2 { 685 u8 power_states[POWER_SOURCE_MAX][POWER_MODE_V2_MAX]; 686 } __packed; 687 688 struct apmf_sps_prop_granular { 689 u32 fppt; 690 u32 sppt; 691 u32 sppt_apu_only; 692 u32 spl; 693 u32 stt_min; 694 u8 stt_skin_temp[STT_TEMP_COUNT]; 695 u32 fan_id; 696 } __packed; 697 698 /* Static Slider */ 699 struct apmf_static_slider_granular_output { 700 u16 size; 701 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX]; 702 } __packed; 703 704 struct amd_pmf_static_slider_granular { 705 u16 size; 706 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX]; 707 }; 708 709 struct apmf_static_slider_granular_output_v2 { 710 u16 size; 711 struct apmf_sps_prop_granular_v2 sps_idx; 712 } __packed; 713 714 struct amd_pmf_static_slider_granular_v2 { 715 u16 size; 716 struct apmf_sps_prop_granular_v2 sps_idx; 717 }; 718 719 struct os_power_slider { 720 u16 size; 721 u8 slider_event; 722 } __packed; 723 724 struct amd_pmf_notify_smart_pc_update { 725 u16 size; 726 u32 pending_req; 727 u32 custom_bios[BIOS_INPUTS_MAX]; 728 } __packed; 729 730 struct fan_table_control { 731 bool manual; 732 unsigned long fan_id; 733 }; 734 735 struct power_table_control { 736 u32 spl; 737 u32 sppt; 738 u32 fppt; 739 u32 sppt_apu_only; 740 u32 stt_min; 741 u32 stt_skin_temp[STT_TEMP_COUNT]; 742 u32 reserved[16]; 743 }; 744 745 /* Auto Mode Layer */ 746 enum auto_mode_transition_priority { 747 AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */ 748 AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 749 AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 750 AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */ 751 AUTO_TRANSITION_MAX, 752 }; 753 754 enum auto_mode_mode { 755 AUTO_QUIET, 756 AUTO_BALANCE, 757 AUTO_PERFORMANCE_ON_LAP, 758 AUTO_PERFORMANCE, 759 AUTO_MODE_MAX, 760 }; 761 762 struct auto_mode_trans_params { 763 u32 time_constant; /* minimum time required to switch to next mode */ 764 u32 power_delta; /* delta power to shift mode */ 765 u32 power_threshold; 766 u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */ 767 u32 applied; 768 enum auto_mode_mode target_mode; 769 u32 shifting_up; 770 }; 771 772 struct auto_mode_mode_settings { 773 struct power_table_control power_control; 774 struct fan_table_control fan_control; 775 u32 power_floor; 776 }; 777 778 struct auto_mode_mode_config { 779 struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX]; 780 struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX]; 781 enum auto_mode_mode current_mode; 782 }; 783 784 struct apmf_auto_mode { 785 u16 size; 786 /* time constant */ 787 u32 balanced_to_perf; 788 u32 perf_to_balanced; 789 u32 quiet_to_balanced; 790 u32 balanced_to_quiet; 791 /* power floor */ 792 u32 pfloor_perf; 793 u32 pfloor_balanced; 794 u32 pfloor_quiet; 795 /* Power delta for mode change */ 796 u32 pd_balanced_to_perf; 797 u32 pd_perf_to_balanced; 798 u32 pd_quiet_to_balanced; 799 u32 pd_balanced_to_quiet; 800 /* skin temperature limits */ 801 u8 stt_apu_perf_on_lap; /* CQL ON */ 802 u8 stt_hs2_perf_on_lap; /* CQL ON */ 803 u8 stt_apu_perf; 804 u8 stt_hs2_perf; 805 u8 stt_apu_balanced; 806 u8 stt_hs2_balanced; 807 u8 stt_apu_quiet; 808 u8 stt_hs2_quiet; 809 u32 stt_min_limit_perf_on_lap; /* CQL ON */ 810 u32 stt_min_limit_perf; 811 u32 stt_min_limit_balanced; 812 u32 stt_min_limit_quiet; 813 /* SPL based */ 814 u32 fppt_perf_on_lap; /* CQL ON */ 815 u32 sppt_perf_on_lap; /* CQL ON */ 816 u32 spl_perf_on_lap; /* CQL ON */ 817 u32 sppt_apu_only_perf_on_lap; /* CQL ON */ 818 u32 fppt_perf; 819 u32 sppt_perf; 820 u32 spl_perf; 821 u32 sppt_apu_only_perf; 822 u32 fppt_balanced; 823 u32 sppt_balanced; 824 u32 spl_balanced; 825 u32 sppt_apu_only_balanced; 826 u32 fppt_quiet; 827 u32 sppt_quiet; 828 u32 spl_quiet; 829 u32 sppt_apu_only_quiet; 830 /* Fan ID */ 831 u32 fan_id_perf; 832 u32 fan_id_balanced; 833 u32 fan_id_quiet; 834 } __packed; 835 836 /* CnQF Layer */ 837 enum cnqf_trans_priority { 838 CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */ 839 CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */ 840 CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 841 CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 842 CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */ 843 CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */ 844 CNQF_TRANSITION_MAX, 845 }; 846 847 enum cnqf_mode { 848 CNQF_MODE_QUIET, 849 CNQF_MODE_BALANCE, 850 CNQF_MODE_PERFORMANCE, 851 CNQF_MODE_TURBO, 852 CNQF_MODE_MAX, 853 }; 854 855 enum apmf_cnqf_pos { 856 APMF_CNQF_TURBO, 857 APMF_CNQF_PERFORMANCE, 858 APMF_CNQF_BALANCE, 859 APMF_CNQF_QUIET, 860 APMF_CNQF_MAX, 861 }; 862 863 struct cnqf_mode_settings { 864 struct power_table_control power_control; 865 struct fan_table_control fan_control; 866 u32 power_floor; 867 }; 868 869 struct cnqf_tran_params { 870 u32 time_constant; /* minimum time required to switch to next mode */ 871 u32 power_threshold; 872 u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */ 873 u32 total_power; 874 u32 count; 875 bool priority; 876 bool shifting_up; 877 enum cnqf_mode target_mode; 878 }; 879 880 struct cnqf_config { 881 struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX]; 882 struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX]; 883 struct power_table_control defaults; 884 enum cnqf_mode current_mode; 885 u32 power_src; 886 u32 avg_power; 887 }; 888 889 struct apmf_cnqf_power_set { 890 u32 pfloor; 891 u32 fppt; 892 u32 sppt; 893 u32 sppt_apu_only; 894 u32 spl; 895 u32 stt_min_limit; 896 u8 stt_skintemp[STT_TEMP_COUNT]; 897 u32 fan_id; 898 } __packed; 899 900 struct apmf_dyn_slider_output { 901 u16 size; 902 u16 flags; 903 u32 t_perf_to_turbo; 904 u32 t_balanced_to_perf; 905 u32 t_quiet_to_balanced; 906 u32 t_balanced_to_quiet; 907 u32 t_perf_to_balanced; 908 u32 t_turbo_to_perf; 909 struct apmf_cnqf_power_set ps[APMF_CNQF_MAX]; 910 } __packed; 911 912 /* Smart PC - TA internals */ 913 enum system_state { 914 SYSTEM_STATE_S0i3, 915 SYSTEM_STATE_S4, 916 SYSTEM_STATE_SCREEN_LOCK, 917 SYSTEM_STATE_MAX, 918 }; 919 920 struct amd_pmf_pb_bitmap { 921 const char *name; 922 u32 bit_mask; 923 }; 924 925 static const struct amd_pmf_pb_bitmap custom_bios_inputs[] __used = { 926 {"NOTIFY_CUSTOM_BIOS_INPUT1", BIT(5)}, 927 {"NOTIFY_CUSTOM_BIOS_INPUT2", BIT(6)}, 928 {"NOTIFY_CUSTOM_BIOS_INPUT3", BIT(7)}, 929 {"NOTIFY_CUSTOM_BIOS_INPUT4", BIT(8)}, 930 {"NOTIFY_CUSTOM_BIOS_INPUT5", BIT(9)}, 931 {"NOTIFY_CUSTOM_BIOS_INPUT6", BIT(10)}, 932 {"NOTIFY_CUSTOM_BIOS_INPUT7", BIT(11)}, 933 {"NOTIFY_CUSTOM_BIOS_INPUT8", BIT(12)}, 934 {"NOTIFY_CUSTOM_BIOS_INPUT9", BIT(13)}, 935 {"NOTIFY_CUSTOM_BIOS_INPUT10", BIT(14)}, 936 }; 937 938 static const struct amd_pmf_pb_bitmap custom_bios_inputs_v1[] __used = { 939 {"NOTIFY_CUSTOM_BIOS_INPUT1", BIT(7)}, 940 {"NOTIFY_CUSTOM_BIOS_INPUT2", BIT(8)}, 941 {"NOTIFY_CUSTOM_BIOS_INPUT3", BIT(9)}, 942 {"NOTIFY_CUSTOM_BIOS_INPUT4", BIT(10)}, 943 {"NOTIFY_CUSTOM_BIOS_INPUT5", BIT(11)}, 944 {"NOTIFY_CUSTOM_BIOS_INPUT6", BIT(12)}, 945 {"NOTIFY_CUSTOM_BIOS_INPUT7", BIT(13)}, 946 {"NOTIFY_CUSTOM_BIOS_INPUT8", BIT(14)}, 947 {"NOTIFY_CUSTOM_BIOS_INPUT9", BIT(15)}, 948 {"NOTIFY_CUSTOM_BIOS_INPUT10", BIT(16)}, 949 }; 950 951 /* Command ids for TA communication */ 952 enum ta_pmf_command { 953 TA_PMF_COMMAND_POLICY_BUILDER_INITIALIZE, 954 TA_PMF_COMMAND_POLICY_BUILDER_ENACT_POLICIES, 955 }; 956 957 enum ta_pmf_error_type { 958 TA_PMF_TYPE_SUCCESS, 959 TA_PMF_ERROR_TYPE_GENERIC, 960 TA_PMF_ERROR_TYPE_CRYPTO, 961 TA_PMF_ERROR_TYPE_CRYPTO_VALIDATE, 962 TA_PMF_ERROR_TYPE_CRYPTO_VERIFY_OEM, 963 TA_PMF_ERROR_TYPE_POLICY_BUILDER, 964 TA_PMF_ERROR_TYPE_PB_CONVERT, 965 TA_PMF_ERROR_TYPE_PB_SETUP, 966 TA_PMF_ERROR_TYPE_PB_ENACT, 967 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_INFO, 968 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_PCIE_INFO, 969 TA_PMF_ERROR_TYPE_SYS_DRV_FW_VALIDATION, 970 TA_PMF_ERROR_TYPE_MAX, 971 }; 972 973 struct pmf_action_table { 974 enum system_state system_state; 975 u32 spl; /* in mW */ 976 u32 sppt; /* in mW */ 977 u32 sppt_apuonly; /* in mW */ 978 u32 fppt; /* in mW */ 979 u32 stt_minlimit; /* in mW */ 980 u32 stt_skintemp_apu; /* in C */ 981 u32 stt_skintemp_hs2; /* in C */ 982 u32 p3t_limit; /* in mW */ 983 u32 pmf_ppt; /* in mW */ 984 u32 pmf_ppt_apu_only; /* in mW */ 985 }; 986 987 /* Input conditions */ 988 struct ta_pmf_condition_info { 989 u32 power_source; 990 u32 bat_percentage; 991 u32 power_slider; 992 u32 lid_state; 993 bool user_present; 994 u32 bios_input_1[2]; 995 u32 monitor_count; 996 u32 rsvd2[2]; 997 u32 bat_design; 998 u32 full_charge_capacity; 999 int drain_rate; 1000 bool user_engaged; 1001 u32 device_state; 1002 u32 socket_power; 1003 u32 skin_temperature; 1004 u32 rsvd3[2]; 1005 u32 platform_type; 1006 u32 rsvd3_1[2]; 1007 u32 ambient_light; 1008 u32 length; 1009 u32 avg_c0residency; 1010 u32 max_c0residency; 1011 u32 s0i3_entry; 1012 u32 gfx_busy; 1013 u32 rsvd4[7]; 1014 bool camera_state; 1015 u32 workload_type; 1016 u32 display_type; 1017 u32 display_state; 1018 u32 rsvd5_1[17]; 1019 u32 bios_input_2[8]; 1020 u32 rsvd5[125]; 1021 }; 1022 1023 struct ta_pmf_load_policy_table { 1024 u32 table_size; 1025 u8 table[POLICY_BUF_MAX_SZ]; 1026 }; 1027 1028 /* TA initialization params */ 1029 struct ta_pmf_init_table { 1030 u32 frequency; /* SMU sampling frequency */ 1031 bool validate; 1032 bool sku_check; 1033 bool metadata_macrocheck; 1034 struct ta_pmf_load_policy_table policies_table; 1035 }; 1036 1037 /* Everything the TA needs to Enact Policies */ 1038 struct ta_pmf_enact_table { 1039 struct ta_pmf_condition_info ev_info; 1040 u32 name; 1041 }; 1042 1043 struct ta_pmf_action { 1044 u32 action_index; 1045 u32 value; 1046 u32 spl_arg; 1047 }; 1048 1049 /* Output actions from TA */ 1050 struct ta_pmf_enact_result { 1051 u32 actions_count; 1052 struct ta_pmf_action actions_list[TA_PMF_ACTION_MAX]; 1053 u32 undo_count; 1054 struct ta_pmf_action undo_list[TA_PMF_UNDO_MAX]; 1055 }; 1056 1057 union ta_pmf_input { 1058 struct ta_pmf_enact_table enact_table; 1059 struct ta_pmf_init_table init_table; 1060 }; 1061 1062 union ta_pmf_output { 1063 struct ta_pmf_enact_result policy_apply_table; 1064 u32 rsvd[TA_OUTPUT_RESERVED_MEM]; 1065 }; 1066 1067 struct ta_pmf_shared_memory { 1068 int command_id; 1069 int resp_id; 1070 u32 pmf_result; 1071 u32 if_version; 1072 union ta_pmf_output pmf_output; 1073 union ta_pmf_input pmf_input; 1074 }; 1075 1076 /* Core Layer */ 1077 int apmf_acpi_init(struct amd_pmf_dev *pmf_dev); 1078 void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev); 1079 int apmf_if_call_store_buffer(struct amd_pmf_dev *pdev, int fn, void *dest, size_t out_sz); 1080 int apts_if_call_store_buffer(struct amd_pmf_dev *pdev, u32 index, void *data, size_t out_sz); 1081 int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data); 1082 int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev); 1083 int apmf_install_handler(struct amd_pmf_dev *pmf_dev); 1084 int apmf_os_power_slider_update(struct amd_pmf_dev *dev, u8 flag); 1085 int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer); 1086 int amd_pmf_notify_sbios_heartbeat_event_v2(struct amd_pmf_dev *dev, u8 flag); 1087 void amd_pmf_set_device(struct device *p_device); 1088 1089 static inline int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index) 1090 { 1091 /* If bit-n is set, that indicates function n+1 is supported */ 1092 return !!(pdev->supported_func & BIT(index - 1)); 1093 } 1094 1095 static inline int is_apmf_bios_input_notifications_supported(struct amd_pmf_dev *pdev) 1096 { 1097 return !!(pdev->notifications & CUSTOM_BIOS_INPUT_BITS); 1098 } 1099 1100 static inline int amd_pmf_get_power_source(void) 1101 { 1102 if (power_supply_is_system_supplied() > 0) 1103 return POWER_SOURCE_AC; 1104 else 1105 return POWER_SOURCE_DC; 1106 } 1107 1108 /** 1109 * fixp_q88_fromint: Convert integer to Q8.8 1110 * @val: input value 1111 * 1112 * Converts an integer into binary fixed point format where 8 bits 1113 * are used for integer and 8 bits are used for the decimal. 1114 * 1115 * Return: unsigned integer converted to Q8.8 format 1116 */ 1117 static inline u32 fixp_q88_fromint(u32 val) 1118 { 1119 return val << 8; 1120 } 1121 1122 /* Metrics layer */ 1123 int amd_pmf_get_tbl_dram_addr(struct amd_pmf_dev *dev); 1124 1125 /* SPS Layer */ 1126 int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf); 1127 void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx, 1128 struct amd_pmf_static_slider_granular *table); 1129 int amd_pmf_init_sps(struct amd_pmf_dev *dev); 1130 int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev); 1131 const char *amd_pmf_source_as_str(unsigned int state); 1132 1133 int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx); 1134 int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf); 1135 1136 static inline int 1137 apts_get_static_slider_granular_v2(struct amd_pmf_dev *pdev, 1138 struct amd_pmf_apts_granular_output *data, u32 apts_idx) 1139 { 1140 if (!is_apmf_func_supported(pdev, APMF_FUNC_STATIC_SLIDER_GRANULAR)) 1141 return -EINVAL; 1142 1143 return apts_if_call_store_buffer(pdev, apts_idx, data, sizeof(*data)); 1144 } 1145 1146 static inline int 1147 apmf_get_static_slider_granular_v2(struct amd_pmf_dev *pdev, 1148 struct apmf_static_slider_granular_output_v2 *data) 1149 { 1150 if (!is_apmf_func_supported(pdev, APMF_FUNC_STATIC_SLIDER_GRANULAR)) 1151 return -EINVAL; 1152 1153 return apmf_if_call_store_buffer(pdev, APMF_FUNC_STATIC_SLIDER_GRANULAR, 1154 data, sizeof(*data)); 1155 } 1156 1157 static inline int 1158 apmf_get_static_slider_granular(struct amd_pmf_dev *pdev, 1159 struct apmf_static_slider_granular_output *data) 1160 { 1161 if (!is_apmf_func_supported(pdev, APMF_FUNC_STATIC_SLIDER_GRANULAR)) 1162 return -EINVAL; 1163 1164 return apmf_if_call_store_buffer(pdev, APMF_FUNC_STATIC_SLIDER_GRANULAR, 1165 data, sizeof(*data)); 1166 } 1167 1168 static inline bool is_pprof_balanced(struct amd_pmf_dev *pmf) 1169 { 1170 return pmf->current_profile == PLATFORM_PROFILE_BALANCED; 1171 } 1172 1173 /* Auto Mode Layer */ 1174 void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev); 1175 void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev); 1176 void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms); 1177 1178 void amd_pmf_update_2_cql(struct amd_pmf_dev *dev, bool is_cql_event); 1179 int amd_pmf_reset_amt(struct amd_pmf_dev *dev); 1180 void amd_pmf_handle_amt(struct amd_pmf_dev *dev); 1181 1182 static inline int apmf_get_auto_mode_def(struct amd_pmf_dev *pdev, struct apmf_auto_mode *data) 1183 { 1184 return apmf_if_call_store_buffer(pdev, APMF_FUNC_AUTO_MODE, data, sizeof(*data)); 1185 } 1186 1187 static inline int apmf_get_sbios_requests_v2(struct amd_pmf_dev *pdev, 1188 struct apmf_sbios_req_v2 *req) 1189 { 1190 return apmf_if_call_store_buffer(pdev, APMF_FUNC_SBIOS_REQUESTS, req, sizeof(*req)); 1191 } 1192 1193 static inline int apmf_get_sbios_requests_v1(struct amd_pmf_dev *pdev, 1194 struct apmf_sbios_req_v1 *req) 1195 { 1196 return apmf_if_call_store_buffer(pdev, APMF_FUNC_SBIOS_REQUESTS, req, sizeof(*req)); 1197 } 1198 1199 static inline int apmf_get_sbios_requests(struct amd_pmf_dev *pdev, 1200 struct apmf_sbios_req *req) 1201 { 1202 return apmf_if_call_store_buffer(pdev, APMF_FUNC_SBIOS_REQUESTS, 1203 req, sizeof(*req)); 1204 } 1205 1206 /* CnQF Layer */ 1207 int amd_pmf_init_cnqf(struct amd_pmf_dev *dev); 1208 void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev); 1209 int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms); 1210 extern const struct attribute_group cnqf_feature_attribute_group; 1211 1212 static inline int apmf_get_dyn_slider_def_ac(struct amd_pmf_dev *pdev, 1213 struct apmf_dyn_slider_output *data) 1214 { 1215 return apmf_if_call_store_buffer(pdev, APMF_FUNC_DYN_SLIDER_AC, data, sizeof(*data)); 1216 } 1217 1218 static inline int apmf_get_dyn_slider_def_dc(struct amd_pmf_dev *pdev, 1219 struct apmf_dyn_slider_output *data) 1220 { 1221 return apmf_if_call_store_buffer(pdev, APMF_FUNC_DYN_SLIDER_DC, data, sizeof(*data)); 1222 } 1223 1224 /* Smart PC builder Layer */ 1225 int amd_pmf_init_smart_pc(struct amd_pmf_dev *dev); 1226 void amd_pmf_deinit_smart_pc(struct amd_pmf_dev *dev); 1227 int apmf_check_smart_pc(struct amd_pmf_dev *pmf_dev); 1228 int amd_pmf_smartpc_apply_bios_output(struct amd_pmf_dev *dev, u32 val, u32 preq, u32 idx); 1229 1230 /* Smart PC - TA interfaces */ 1231 void amd_pmf_populate_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in); 1232 int amd_pmf_invoke_cmd_enact(struct amd_pmf_dev *dev); 1233 1234 static inline u32 amd_pmf_get_ta_custom_bios_inputs(struct ta_pmf_enact_table *in, int index) 1235 { 1236 switch (index) { 1237 case 0 ... 1: 1238 return in->ev_info.bios_input_1[index]; 1239 case 2 ... 9: 1240 return in->ev_info.bios_input_2[index - 2]; 1241 default: 1242 return 0; 1243 } 1244 } 1245 1246 #ifdef CONFIG_AMD_PMF_DEBUG 1247 void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in); 1248 #else 1249 static inline void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in) {} 1250 #endif 1251 1252 int amd_pmf_tee_init(struct amd_pmf_dev *dev, const uuid_t *uuid); 1253 void amd_pmf_tee_deinit(struct amd_pmf_dev *dev); 1254 int amd_pmf_start_policy_engine(struct amd_pmf_dev *dev); 1255 1256 /* Util Layer */ 1257 #if IS_ENABLED(CONFIG_AMD_PMF_UTIL_SUPPORT) 1258 int amd_pmf_cdev_register(struct amd_pmf_dev *dev); 1259 void amd_pmf_cdev_unregister(void); 1260 #else 1261 static inline int amd_pmf_cdev_register(struct amd_pmf_dev *dev) { return 0; } 1262 static inline void amd_pmf_cdev_unregister(void) {} 1263 #endif 1264 1265 #endif /* PMF_H */ 1266