1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 /* PPE HW initialization configs such as BM(buffer management), 7 * QM(queue management) and scheduler configs. 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bitmap.h> 12 #include <linux/bits.h> 13 #include <linux/device.h> 14 #include <linux/regmap.h> 15 16 #include "ppe.h" 17 #include "ppe_config.h" 18 #include "ppe_regs.h" 19 20 #define PPE_QUEUE_SCH_PRI_NUM 8 21 22 /** 23 * struct ppe_bm_port_config - PPE BM port configuration. 24 * @port_id_start: The fist BM port ID to configure. 25 * @port_id_end: The last BM port ID to configure. 26 * @pre_alloc: BM port dedicated buffer number. 27 * @in_fly_buf: Buffer number for receiving the packet after pause frame sent. 28 * @ceil: Ceil to generate the back pressure. 29 * @weight: Weight value. 30 * @resume_offset: Resume offset from the threshold value. 31 * @resume_ceil: Ceil to resume from the back pressure state. 32 * @dynamic: Dynamic threshold used or not. 33 * 34 * The is for configuring the threshold that impacts the port 35 * flow control. 36 */ 37 struct ppe_bm_port_config { 38 unsigned int port_id_start; 39 unsigned int port_id_end; 40 unsigned int pre_alloc; 41 unsigned int in_fly_buf; 42 unsigned int ceil; 43 unsigned int weight; 44 unsigned int resume_offset; 45 unsigned int resume_ceil; 46 bool dynamic; 47 }; 48 49 /** 50 * struct ppe_qm_queue_config - PPE queue config. 51 * @queue_start: PPE start of queue ID. 52 * @queue_end: PPE end of queue ID. 53 * @prealloc_buf: Queue dedicated buffer number. 54 * @ceil: Ceil to start drop packet from queue. 55 * @weight: Weight value. 56 * @resume_offset: Resume offset from the threshold. 57 * @dynamic: Threshold value is decided dynamically or statically. 58 * 59 * Queue configuration decides the threshold to drop packet from PPE 60 * hardware queue. 61 */ 62 struct ppe_qm_queue_config { 63 unsigned int queue_start; 64 unsigned int queue_end; 65 unsigned int prealloc_buf; 66 unsigned int ceil; 67 unsigned int weight; 68 unsigned int resume_offset; 69 bool dynamic; 70 }; 71 72 /** 73 * enum ppe_scheduler_direction - PPE scheduler direction for packet. 74 * @PPE_SCH_INGRESS: Scheduler for the packet on ingress, 75 * @PPE_SCH_EGRESS: Scheduler for the packet on egress, 76 */ 77 enum ppe_scheduler_direction { 78 PPE_SCH_INGRESS = 0, 79 PPE_SCH_EGRESS = 1, 80 }; 81 82 /** 83 * struct ppe_scheduler_bm_config - PPE arbitration for buffer config. 84 * @valid: Arbitration entry valid or not. 85 * @dir: Arbitration entry for egress or ingress. 86 * @port: Port ID to use arbitration entry. 87 * @backup_port_valid: Backup port valid or not. 88 * @backup_port: Backup port ID to use. 89 * 90 * Configure the scheduler settings for accessing and releasing the PPE buffers. 91 */ 92 struct ppe_scheduler_bm_config { 93 bool valid; 94 enum ppe_scheduler_direction dir; 95 unsigned int port; 96 bool backup_port_valid; 97 unsigned int backup_port; 98 }; 99 100 /** 101 * struct ppe_scheduler_qm_config - PPE arbitration for scheduler config. 102 * @ensch_port_bmp: Port bit map for enqueue scheduler. 103 * @ensch_port: Port ID to enqueue scheduler. 104 * @desch_port: Port ID to dequeue scheduler. 105 * @desch_backup_port_valid: Dequeue for the backup port valid or not. 106 * @desch_backup_port: Backup port ID to dequeue scheduler. 107 * 108 * Configure the scheduler settings for enqueuing and dequeuing packets on 109 * the PPE port. 110 */ 111 struct ppe_scheduler_qm_config { 112 unsigned int ensch_port_bmp; 113 unsigned int ensch_port; 114 unsigned int desch_port; 115 bool desch_backup_port_valid; 116 unsigned int desch_backup_port; 117 }; 118 119 /** 120 * struct ppe_scheduler_port_config - PPE port scheduler config. 121 * @port: Port ID to be scheduled. 122 * @flow_level: Scheduler flow level or not. 123 * @node_id: Node ID, for level 0, queue ID is used. 124 * @loop_num: Loop number of scheduler config. 125 * @pri_max: Max priority configured. 126 * @flow_id: Strict priority ID. 127 * @drr_node_id: Node ID for scheduler. 128 * 129 * PPE port scheduler configuration which decides the priority in the 130 * packet scheduler for the egress port. 131 */ 132 struct ppe_scheduler_port_config { 133 unsigned int port; 134 bool flow_level; 135 unsigned int node_id; 136 unsigned int loop_num; 137 unsigned int pri_max; 138 unsigned int flow_id; 139 unsigned int drr_node_id; 140 }; 141 142 /** 143 * struct ppe_port_schedule_resource - PPE port scheduler resource. 144 * @ucastq_start: Unicast queue start ID. 145 * @ucastq_end: Unicast queue end ID. 146 * @mcastq_start: Multicast queue start ID. 147 * @mcastq_end: Multicast queue end ID. 148 * @flow_id_start: Flow start ID. 149 * @flow_id_end: Flow end ID. 150 * @l0node_start: Scheduler node start ID for queue level. 151 * @l0node_end: Scheduler node end ID for queue level. 152 * @l1node_start: Scheduler node start ID for flow level. 153 * @l1node_end: Scheduler node end ID for flow level. 154 * 155 * PPE scheduler resource allocated among the PPE ports. 156 */ 157 struct ppe_port_schedule_resource { 158 unsigned int ucastq_start; 159 unsigned int ucastq_end; 160 unsigned int mcastq_start; 161 unsigned int mcastq_end; 162 unsigned int flow_id_start; 163 unsigned int flow_id_end; 164 unsigned int l0node_start; 165 unsigned int l0node_end; 166 unsigned int l1node_start; 167 unsigned int l1node_end; 168 }; 169 170 /* There are total 2048 buffers available in PPE, out of which some 171 * buffers are reserved for some specific purposes per PPE port. The 172 * rest of the pool of 1550 buffers are assigned to the general 'group0' 173 * which is shared among all ports of the PPE. 174 */ 175 static const int ipq9574_ppe_bm_group_config = 1550; 176 177 /* The buffer configurations per PPE port. There are 15 BM ports and 178 * 4 BM groups supported by PPE. BM port (0-7) is for EDMA port 0, 179 * BM port (8-13) is for PPE physical port 1-6 and BM port 14 is for 180 * EIP port. 181 */ 182 static const struct ppe_bm_port_config ipq9574_ppe_bm_port_config[] = { 183 { 184 /* Buffer configuration for the BM port ID 0 of EDMA. */ 185 .port_id_start = 0, 186 .port_id_end = 0, 187 .pre_alloc = 0, 188 .in_fly_buf = 100, 189 .ceil = 1146, 190 .weight = 7, 191 .resume_offset = 8, 192 .resume_ceil = 0, 193 .dynamic = true, 194 }, 195 { 196 /* Buffer configuration for the BM port ID 1-7 of EDMA. */ 197 .port_id_start = 1, 198 .port_id_end = 7, 199 .pre_alloc = 0, 200 .in_fly_buf = 100, 201 .ceil = 250, 202 .weight = 4, 203 .resume_offset = 36, 204 .resume_ceil = 0, 205 .dynamic = true, 206 }, 207 { 208 /* Buffer configuration for the BM port ID 8-13 of PPE ports. */ 209 .port_id_start = 8, 210 .port_id_end = 13, 211 .pre_alloc = 0, 212 .in_fly_buf = 128, 213 .ceil = 250, 214 .weight = 4, 215 .resume_offset = 36, 216 .resume_ceil = 0, 217 .dynamic = true, 218 }, 219 { 220 /* Buffer configuration for the BM port ID 14 of EIP. */ 221 .port_id_start = 14, 222 .port_id_end = 14, 223 .pre_alloc = 0, 224 .in_fly_buf = 40, 225 .ceil = 250, 226 .weight = 4, 227 .resume_offset = 36, 228 .resume_ceil = 0, 229 .dynamic = true, 230 }, 231 }; 232 233 /* IPQ5424 has fewer PPE physical ports (3) than IPQ9574 (6), so fewer 234 * buffers need to be reserved for per-port purposes. Out of the same 235 * 2048 total, the rest assigned to the general 'group0' pool is 236 * correspondingly larger here, 1650 versus IPQ9574's 1550. 237 */ 238 static const int ipq5424_ppe_bm_group_config = 1650; 239 240 /* The buffer configurations per PPE port on IPQ5424. There are 19 BM 241 * ports supported by PPE. BM port (0-15) is for EDMA port 0, and BM 242 * port (16-18) is for the 3 PPE physical ports. 243 */ 244 static const struct ppe_bm_port_config ipq5424_ppe_bm_port_config[] = { 245 { 246 /* Buffer configuration for the BM port ID 0 of EDMA. */ 247 .port_id_start = 0, 248 .port_id_end = 0, 249 .pre_alloc = 0, 250 .in_fly_buf = 100, 251 .ceil = 1146, 252 .weight = 7, 253 .resume_offset = 8, 254 .resume_ceil = 0, 255 .dynamic = true, 256 }, 257 { 258 /* Buffer configuration for the BM port ID 1-15 of EDMA. */ 259 .port_id_start = 1, 260 .port_id_end = 15, 261 .pre_alloc = 0, 262 .in_fly_buf = 100, 263 .ceil = 250, 264 .weight = 4, 265 .resume_offset = 36, 266 .resume_ceil = 0, 267 .dynamic = true, 268 }, 269 { 270 /* Buffer configuration for the BM port ID 16-18 of PPE ports. */ 271 .port_id_start = 16, 272 .port_id_end = 18, 273 .pre_alloc = 0, 274 .in_fly_buf = 128, 275 .ceil = 250, 276 .weight = 4, 277 .resume_offset = 36, 278 .resume_ceil = 0, 279 .dynamic = true, 280 }, 281 }; 282 283 /* QM fetches the packet from PPE buffer management for transmitting the 284 * packet out. The QM group configuration limits the total number of buffers 285 * enqueued by all PPE hardware queues. 286 * There are total 2048 buffers available, out of which some buffers are 287 * dedicated to hardware exception handlers. The remaining buffers are 288 * assigned to the general 'group0', which is the group assigned to all 289 * queues by default. 290 */ 291 static const int ipq9574_ppe_qm_group_config = 2000; 292 293 /* Default QM settings for unicast and multicast queues for IPQ9754. */ 294 static const struct ppe_qm_queue_config ipq9574_ppe_qm_queue_config[] = { 295 { 296 /* QM settings for unicast queues 0 to 255. */ 297 .queue_start = 0, 298 .queue_end = 255, 299 .prealloc_buf = 0, 300 .ceil = 1200, 301 .weight = 7, 302 .resume_offset = 36, 303 .dynamic = true, 304 }, 305 { 306 /* QM settings for multicast queues 256 to 299. */ 307 .queue_start = 256, 308 .queue_end = 299, 309 .prealloc_buf = 0, 310 .ceil = 250, 311 .weight = 0, 312 .resume_offset = 36, 313 .dynamic = false, 314 }, 315 }; 316 317 /* Multicast queues are dedicated per PPE port. IPQ5424 has only 3 physical 318 * PPE ports, versus IPQ9574's 6 PPE ports, so multicast queues 284 to 299 319 * are not available on IPQ5424, and the buffer pool assigned to the general 320 * 'group0' is larger here, 2010 versus IPQ9574's 2000. 321 */ 322 static const int ipq5424_ppe_qm_group_config = 2010; 323 324 /* Default QM settings for unicast and multicast queues for IPQ5424. */ 325 static const struct ppe_qm_queue_config ipq5424_ppe_qm_queue_config[] = { 326 { 327 /* QM settings for unicast queues 0 to 255. */ 328 .queue_start = 0, 329 .queue_end = 255, 330 .prealloc_buf = 0, 331 .ceil = 1200, 332 .weight = 7, 333 .resume_offset = 36, 334 .dynamic = true, 335 }, 336 { 337 /* QM settings for multicast queues 256 to 283. */ 338 .queue_start = 256, 339 .queue_end = 283, 340 .prealloc_buf = 0, 341 .ceil = 250, 342 .weight = 0, 343 .resume_offset = 36, 344 .dynamic = false, 345 }, 346 }; 347 348 /* PPE scheduler configuration for BM includes multiple entries. Each entry 349 * indicates the primary port to be assigned the buffers for the ingress or 350 * to release the buffers for the egress. Backup port ID will be used when 351 * the primary port ID is down. 352 */ 353 static const struct ppe_scheduler_bm_config ipq9574_ppe_sch_bm_config[] = { 354 {true, PPE_SCH_INGRESS, 0, false, 0}, 355 {true, PPE_SCH_EGRESS, 0, false, 0}, 356 {true, PPE_SCH_INGRESS, 5, false, 0}, 357 {true, PPE_SCH_EGRESS, 5, false, 0}, 358 {true, PPE_SCH_INGRESS, 6, false, 0}, 359 {true, PPE_SCH_EGRESS, 6, false, 0}, 360 {true, PPE_SCH_INGRESS, 1, false, 0}, 361 {true, PPE_SCH_EGRESS, 1, false, 0}, 362 {true, PPE_SCH_INGRESS, 0, false, 0}, 363 {true, PPE_SCH_EGRESS, 0, false, 0}, 364 {true, PPE_SCH_INGRESS, 5, false, 0}, 365 {true, PPE_SCH_EGRESS, 5, false, 0}, 366 {true, PPE_SCH_INGRESS, 6, false, 0}, 367 {true, PPE_SCH_EGRESS, 6, false, 0}, 368 {true, PPE_SCH_INGRESS, 7, false, 0}, 369 {true, PPE_SCH_EGRESS, 7, false, 0}, 370 {true, PPE_SCH_INGRESS, 0, false, 0}, 371 {true, PPE_SCH_EGRESS, 0, false, 0}, 372 {true, PPE_SCH_INGRESS, 1, false, 0}, 373 {true, PPE_SCH_EGRESS, 1, false, 0}, 374 {true, PPE_SCH_INGRESS, 5, false, 0}, 375 {true, PPE_SCH_EGRESS, 5, false, 0}, 376 {true, PPE_SCH_INGRESS, 6, false, 0}, 377 {true, PPE_SCH_EGRESS, 6, false, 0}, 378 {true, PPE_SCH_INGRESS, 2, false, 0}, 379 {true, PPE_SCH_EGRESS, 2, false, 0}, 380 {true, PPE_SCH_INGRESS, 0, false, 0}, 381 {true, PPE_SCH_EGRESS, 0, false, 0}, 382 {true, PPE_SCH_INGRESS, 5, false, 0}, 383 {true, PPE_SCH_EGRESS, 5, false, 0}, 384 {true, PPE_SCH_INGRESS, 6, false, 0}, 385 {true, PPE_SCH_EGRESS, 6, false, 0}, 386 {true, PPE_SCH_INGRESS, 1, false, 0}, 387 {true, PPE_SCH_EGRESS, 1, false, 0}, 388 {true, PPE_SCH_INGRESS, 3, false, 0}, 389 {true, PPE_SCH_EGRESS, 3, false, 0}, 390 {true, PPE_SCH_INGRESS, 0, false, 0}, 391 {true, PPE_SCH_EGRESS, 0, false, 0}, 392 {true, PPE_SCH_INGRESS, 5, false, 0}, 393 {true, PPE_SCH_EGRESS, 5, false, 0}, 394 {true, PPE_SCH_INGRESS, 6, false, 0}, 395 {true, PPE_SCH_EGRESS, 6, false, 0}, 396 {true, PPE_SCH_INGRESS, 7, false, 0}, 397 {true, PPE_SCH_EGRESS, 7, false, 0}, 398 {true, PPE_SCH_INGRESS, 0, false, 0}, 399 {true, PPE_SCH_EGRESS, 0, false, 0}, 400 {true, PPE_SCH_INGRESS, 1, false, 0}, 401 {true, PPE_SCH_EGRESS, 1, false, 0}, 402 {true, PPE_SCH_INGRESS, 5, false, 0}, 403 {true, PPE_SCH_EGRESS, 5, false, 0}, 404 {true, PPE_SCH_INGRESS, 6, false, 0}, 405 {true, PPE_SCH_EGRESS, 6, false, 0}, 406 {true, PPE_SCH_INGRESS, 4, false, 0}, 407 {true, PPE_SCH_EGRESS, 4, false, 0}, 408 {true, PPE_SCH_INGRESS, 0, false, 0}, 409 {true, PPE_SCH_EGRESS, 0, false, 0}, 410 {true, PPE_SCH_INGRESS, 5, false, 0}, 411 {true, PPE_SCH_EGRESS, 5, false, 0}, 412 {true, PPE_SCH_INGRESS, 6, false, 0}, 413 {true, PPE_SCH_EGRESS, 6, false, 0}, 414 {true, PPE_SCH_INGRESS, 1, false, 0}, 415 {true, PPE_SCH_EGRESS, 1, false, 0}, 416 {true, PPE_SCH_INGRESS, 0, false, 0}, 417 {true, PPE_SCH_EGRESS, 0, false, 0}, 418 {true, PPE_SCH_INGRESS, 5, false, 0}, 419 {true, PPE_SCH_EGRESS, 5, false, 0}, 420 {true, PPE_SCH_INGRESS, 6, false, 0}, 421 {true, PPE_SCH_EGRESS, 6, false, 0}, 422 {true, PPE_SCH_INGRESS, 2, false, 0}, 423 {true, PPE_SCH_EGRESS, 2, false, 0}, 424 {true, PPE_SCH_INGRESS, 0, false, 0}, 425 {true, PPE_SCH_EGRESS, 0, false, 0}, 426 {true, PPE_SCH_INGRESS, 7, false, 0}, 427 {true, PPE_SCH_EGRESS, 7, false, 0}, 428 {true, PPE_SCH_INGRESS, 5, false, 0}, 429 {true, PPE_SCH_EGRESS, 5, false, 0}, 430 {true, PPE_SCH_INGRESS, 6, false, 0}, 431 {true, PPE_SCH_EGRESS, 6, false, 0}, 432 {true, PPE_SCH_INGRESS, 1, false, 0}, 433 {true, PPE_SCH_EGRESS, 1, false, 0}, 434 {true, PPE_SCH_INGRESS, 0, false, 0}, 435 {true, PPE_SCH_EGRESS, 0, false, 0}, 436 {true, PPE_SCH_INGRESS, 5, false, 0}, 437 {true, PPE_SCH_EGRESS, 5, false, 0}, 438 {true, PPE_SCH_INGRESS, 6, false, 0}, 439 {true, PPE_SCH_EGRESS, 6, false, 0}, 440 {true, PPE_SCH_INGRESS, 3, false, 0}, 441 {true, PPE_SCH_EGRESS, 3, false, 0}, 442 {true, PPE_SCH_INGRESS, 1, false, 0}, 443 {true, PPE_SCH_EGRESS, 1, false, 0}, 444 {true, PPE_SCH_INGRESS, 0, false, 0}, 445 {true, PPE_SCH_EGRESS, 0, false, 0}, 446 {true, PPE_SCH_INGRESS, 5, false, 0}, 447 {true, PPE_SCH_EGRESS, 5, false, 0}, 448 {true, PPE_SCH_INGRESS, 6, false, 0}, 449 {true, PPE_SCH_EGRESS, 6, false, 0}, 450 {true, PPE_SCH_INGRESS, 4, false, 0}, 451 {true, PPE_SCH_EGRESS, 4, false, 0}, 452 {true, PPE_SCH_INGRESS, 7, false, 0}, 453 {true, PPE_SCH_EGRESS, 7, false, 0}, 454 }; 455 456 /* PPE scheduler configuration for QM includes multiple entries. Each entry 457 * contains ports to be dispatched for enqueueing and dequeueing. The backup 458 * port for dequeueing is supported to be used when the primary port for 459 * dequeueing is down. 460 */ 461 static const struct ppe_scheduler_qm_config ipq9574_ppe_sch_qm_config[] = { 462 {0x98, 6, 0, true, 1}, 463 {0x94, 5, 6, true, 3}, 464 {0x86, 0, 5, true, 4}, 465 {0x8C, 1, 6, true, 0}, 466 {0x1C, 7, 5, true, 1}, 467 {0x98, 2, 6, true, 0}, 468 {0x1C, 5, 7, true, 1}, 469 {0x34, 3, 6, true, 0}, 470 {0x8C, 4, 5, true, 1}, 471 {0x98, 2, 6, true, 0}, 472 {0x8C, 5, 4, true, 1}, 473 {0xA8, 0, 6, true, 2}, 474 {0x98, 5, 1, true, 0}, 475 {0x98, 6, 5, true, 2}, 476 {0x89, 1, 6, true, 4}, 477 {0xA4, 3, 0, true, 1}, 478 {0x8C, 5, 6, true, 4}, 479 {0xA8, 0, 2, true, 1}, 480 {0x98, 6, 5, true, 0}, 481 {0xC4, 4, 3, true, 1}, 482 {0x94, 6, 5, true, 0}, 483 {0x1C, 7, 6, true, 1}, 484 {0x98, 2, 5, true, 0}, 485 {0x1C, 6, 7, true, 1}, 486 {0x1C, 5, 6, true, 0}, 487 {0x94, 3, 5, true, 1}, 488 {0x8C, 4, 6, true, 0}, 489 {0x94, 1, 5, true, 3}, 490 {0x94, 6, 1, true, 0}, 491 {0xD0, 3, 5, true, 2}, 492 {0x98, 6, 0, true, 1}, 493 {0x94, 5, 6, true, 3}, 494 {0x94, 1, 5, true, 0}, 495 {0x98, 2, 6, true, 1}, 496 {0x8C, 4, 5, true, 0}, 497 {0x1C, 7, 6, true, 1}, 498 {0x8C, 0, 5, true, 4}, 499 {0x89, 1, 6, true, 2}, 500 {0x98, 5, 0, true, 1}, 501 {0x94, 6, 5, true, 3}, 502 {0x92, 0, 6, true, 2}, 503 {0x98, 1, 5, true, 0}, 504 {0x98, 6, 2, true, 1}, 505 {0xD0, 0, 5, true, 3}, 506 {0x94, 6, 0, true, 1}, 507 {0x8C, 5, 6, true, 4}, 508 {0x8C, 1, 5, true, 0}, 509 {0x1C, 6, 7, true, 1}, 510 {0x1C, 5, 6, true, 0}, 511 {0xB0, 2, 3, true, 1}, 512 {0xC4, 4, 5, true, 0}, 513 {0x8C, 6, 4, true, 1}, 514 {0xA4, 3, 6, true, 0}, 515 {0x1C, 5, 7, true, 1}, 516 {0x4C, 0, 5, true, 4}, 517 {0x8C, 6, 0, true, 1}, 518 {0x34, 7, 6, true, 3}, 519 {0x94, 5, 0, true, 1}, 520 {0x98, 6, 5, true, 2}, 521 }; 522 523 static const struct ppe_scheduler_bm_config ipq5424_ppe_sch_bm_config[] = { 524 {true, PPE_SCH_INGRESS, 3, false, 0}, 525 {true, PPE_SCH_EGRESS, 0, false, 0}, 526 {true, PPE_SCH_INGRESS, 2, false, 0}, 527 {true, PPE_SCH_EGRESS, 3, true, 1}, 528 {true, PPE_SCH_INGRESS, 0, false, 0}, 529 {true, PPE_SCH_EGRESS, 2, false, 0}, 530 {true, PPE_SCH_INGRESS, 1, false, 0}, 531 {true, PPE_SCH_EGRESS, 0, false, 0}, 532 {true, PPE_SCH_INGRESS, 3, false, 0}, 533 {true, PPE_SCH_EGRESS, 1, true, 2}, 534 {true, PPE_SCH_INGRESS, 2, false, 0}, 535 {true, PPE_SCH_EGRESS, 3, false, 0}, 536 {true, PPE_SCH_INGRESS, 0, false, 0}, 537 {true, PPE_SCH_EGRESS, 2, true, 1}, 538 {true, PPE_SCH_INGRESS, 1, false, 0}, 539 {true, PPE_SCH_EGRESS, 0, false, 0}, 540 {true, PPE_SCH_INGRESS, 3, false, 0}, 541 {true, PPE_SCH_EGRESS, 1, false, 0}, 542 {true, PPE_SCH_INGRESS, 2, false, 0}, 543 {true, PPE_SCH_EGRESS, 3, false, 0}, 544 {true, PPE_SCH_INGRESS, 0, false, 0}, 545 {true, PPE_SCH_EGRESS, 2, true, 1}, 546 {true, PPE_SCH_INGRESS, 1, false, 0}, 547 {true, PPE_SCH_EGRESS, 0, false, 0}, 548 {true, PPE_SCH_INGRESS, 3, false, 0}, 549 {true, PPE_SCH_EGRESS, 3, true, 2}, 550 {true, PPE_SCH_INGRESS, 2, false, 0}, 551 {true, PPE_SCH_EGRESS, 1, false, 0}, 552 {true, PPE_SCH_INGRESS, 0, false, 0}, 553 {true, PPE_SCH_EGRESS, 2, true, 3}, 554 {true, PPE_SCH_INGRESS, 1, false, 0}, 555 {true, PPE_SCH_EGRESS, 0, false, 0}, 556 {true, PPE_SCH_INGRESS, 3, false, 0}, 557 {true, PPE_SCH_EGRESS, 1, true, 2}, 558 {true, PPE_SCH_INGRESS, 0, false, 0}, 559 {true, PPE_SCH_EGRESS, 3, false, 0}, 560 {true, PPE_SCH_INGRESS, 2, false, 0}, 561 {true, PPE_SCH_EGRESS, 0, false, 0}, 562 {true, PPE_SCH_INGRESS, 1, false, 0}, 563 {true, PPE_SCH_EGRESS, 2, true, 3}, 564 {true, PPE_SCH_INGRESS, 0, false, 0}, 565 {true, PPE_SCH_EGRESS, 1, false, 0}, 566 {true, PPE_SCH_INGRESS, 3, false, 0}, 567 {true, PPE_SCH_EGRESS, 0, false, 0}, 568 {true, PPE_SCH_INGRESS, 2, false, 0}, 569 {true, PPE_SCH_EGRESS, 3, true, 1}, 570 {true, PPE_SCH_INGRESS, 0, false, 0}, 571 {true, PPE_SCH_EGRESS, 2, false, 0}, 572 {true, PPE_SCH_INGRESS, 1, false, 0}, 573 {true, PPE_SCH_EGRESS, 0, false, 0}, 574 {true, PPE_SCH_INGRESS, 3, false, 0}, 575 {true, PPE_SCH_EGRESS, 1, true, 2}, 576 {true, PPE_SCH_INGRESS, 2, false, 0}, 577 {true, PPE_SCH_EGRESS, 3, false, 0}, 578 {true, PPE_SCH_INGRESS, 0, false, 0}, 579 {true, PPE_SCH_EGRESS, 2, true, 1}, 580 {true, PPE_SCH_INGRESS, 1, false, 0}, 581 {true, PPE_SCH_EGRESS, 0, false, 0}, 582 {true, PPE_SCH_INGRESS, 3, false, 0}, 583 {true, PPE_SCH_EGRESS, 1, true, 2}, 584 {true, PPE_SCH_INGRESS, 2, false, 0}, 585 {true, PPE_SCH_EGRESS, 3, false, 0}, 586 {true, PPE_SCH_INGRESS, 0, false, 0}, 587 {true, PPE_SCH_EGRESS, 2, true, 1}, 588 {true, PPE_SCH_INGRESS, 1, false, 0}, 589 {true, PPE_SCH_EGRESS, 0, false, 0}, 590 {true, PPE_SCH_INGRESS, 3, false, 0}, 591 {true, PPE_SCH_EGRESS, 1, true, 3}, 592 {true, PPE_SCH_INGRESS, 2, false, 0}, 593 {true, PPE_SCH_EGRESS, 2, false, 0}, 594 {true, PPE_SCH_INGRESS, 0, false, 0}, 595 {true, PPE_SCH_EGRESS, 3, true, 1}, 596 {true, PPE_SCH_INGRESS, 1, false, 0}, 597 {true, PPE_SCH_EGRESS, 0, false, 0}, 598 {true, PPE_SCH_INGRESS, 3, false, 0}, 599 {true, PPE_SCH_EGRESS, 1, true, 2}, 600 {true, PPE_SCH_INGRESS, 0, false, 0}, 601 {true, PPE_SCH_EGRESS, 3, false, 0}, 602 {true, PPE_SCH_INGRESS, 2, false, 0}, 603 {true, PPE_SCH_EGRESS, 0, false, 0}, 604 {true, PPE_SCH_INGRESS, 1, false, 0}, 605 {true, PPE_SCH_EGRESS, 2, true, 3}, 606 {true, PPE_SCH_INGRESS, 0, false, 0}, 607 {true, PPE_SCH_EGRESS, 1, false, 0}, 608 {true, PPE_SCH_INGRESS, 3, false, 0}, 609 {true, PPE_SCH_EGRESS, 0, false, 0}, 610 {true, PPE_SCH_INGRESS, 2, false, 0}, 611 {true, PPE_SCH_EGRESS, 3, true, 1}, 612 {true, PPE_SCH_INGRESS, 0, false, 0}, 613 {true, PPE_SCH_EGRESS, 2, false, 0}, 614 {true, PPE_SCH_INGRESS, 1, false, 0}, 615 {true, PPE_SCH_EGRESS, 0, false, 0}, 616 {true, PPE_SCH_INGRESS, 3, false, 0}, 617 {true, PPE_SCH_EGRESS, 1, true, 3}, 618 {true, PPE_SCH_INGRESS, 2, false, 0}, 619 {true, PPE_SCH_EGRESS, 2, false, 0}, 620 {true, PPE_SCH_INGRESS, 0, false, 0}, 621 {true, PPE_SCH_EGRESS, 3, true, 1}, 622 {true, PPE_SCH_INGRESS, 1, false, 0}, 623 {true, PPE_SCH_EGRESS, 0, false, 0}, 624 {true, PPE_SCH_INGRESS, 3, false, 0}, 625 {true, PPE_SCH_EGRESS, 1, true, 2}, 626 {true, PPE_SCH_INGRESS, 2, false, 0}, 627 {true, PPE_SCH_EGRESS, 3, false, 0}, 628 {true, PPE_SCH_INGRESS, 0, false, 0}, 629 {true, PPE_SCH_EGRESS, 2, true, 1}, 630 {true, PPE_SCH_INGRESS, 1, false, 0}, 631 {true, PPE_SCH_EGRESS, 0, false, 0}, 632 {true, PPE_SCH_INGRESS, 3, false, 0}, 633 {true, PPE_SCH_EGRESS, 3, true, 2}, 634 {true, PPE_SCH_INGRESS, 2, false, 0}, 635 {true, PPE_SCH_EGRESS, 1, false, 0}, 636 {true, PPE_SCH_INGRESS, 0, false, 0}, 637 {true, PPE_SCH_EGRESS, 2, true, 3}, 638 {true, PPE_SCH_INGRESS, 1, false, 0}, 639 {true, PPE_SCH_EGRESS, 0, false, 0}, 640 {true, PPE_SCH_INGRESS, 3, false, 0}, 641 {true, PPE_SCH_EGRESS, 1, true, 2}, 642 {true, PPE_SCH_INGRESS, 0, false, 0}, 643 {true, PPE_SCH_EGRESS, 3, false, 0}, 644 {true, PPE_SCH_INGRESS, 2, false, 0}, 645 {true, PPE_SCH_EGRESS, 0, false, 0}, 646 {true, PPE_SCH_INGRESS, 1, false, 0}, 647 {true, PPE_SCH_EGRESS, 2, true, 3}, 648 {true, PPE_SCH_INGRESS, 0, false, 0}, 649 {true, PPE_SCH_EGRESS, 1, false, 0}, 650 }; 651 652 /* ensch_port_bmp is left as 0 for every entry here, unlike 653 * ipq9574_ppe_sch_qm_config[] above. This is expected for IPQ5424, 654 * not an omission. 655 */ 656 static const struct ppe_scheduler_qm_config ipq5424_ppe_sch_qm_config[] = { 657 {0x0, 3, 2, false, 0}, 658 {0x0, 1, 3, false, 0}, 659 {0x0, 0, 1, false, 0}, 660 {0x0, 2, 0, false, 0}, 661 {0x0, 1, 2, false, 0}, 662 {0x0, 3, 1, true, 0}, 663 {0x0, 3, 2, false, 0}, 664 {0x0, 1, 0, false, 0}, 665 {0x0, 2, 1, false, 0}, 666 {0x0, 2, 0, false, 0}, 667 {0x0, 1, 2, false, 0}, 668 {0x0, 3, 1, true, 0}, 669 {0x0, 3, 2, false, 0}, 670 {0x0, 1, 3, false, 0}, 671 {0x0, 0, 1, false, 0}, 672 {0x0, 2, 0, false, 0}, 673 {0x0, 1, 2, false, 0}, 674 {0x0, 3, 1, true, 0}, 675 {0x0, 3, 2, false, 0}, 676 {0x0, 1, 0, false, 0}, 677 {0x0, 2, 1, false, 0}, 678 {0x0, 2, 0, false, 0}, 679 {0x0, 1, 2, false, 0}, 680 {0x0, 0, 1, false, 0}, 681 {0x0, 2, 0, false, 0}, 682 {0x0, 3, 1, false, 0}, 683 {0x0, 2, 0, false, 0}, 684 {0x0, 1, 2, false, 0}, 685 {0x0, 1, 0, false, 0}, 686 {0x0, 2, 1, false, 0}, 687 {0x0, 3, 2, true, 0}, 688 {0x0, 3, 1, false, 0}, 689 {0x0, 2, 0, false, 0}, 690 {0x0, 1, 2, false, 0}, 691 {0x0, 1, 3, false, 0}, 692 {0x0, 0, 1, false, 0}, 693 {0x0, 3, 2, true, 0}, 694 {0x0, 3, 1, false, 0}, 695 {0x0, 2, 0, false, 0}, 696 {0x0, 1, 2, false, 0}, 697 {0x0, 1, 0, false, 0}, 698 {0x0, 2, 1, false, 0}, 699 {0x0, 0, 2, false, 0}, 700 {0x0, 3, 1, false, 0}, 701 {0x0, 2, 0, false, 0}, 702 {0x0, 1, 2, false, 0}, 703 {0x0, 1, 0, false, 0}, 704 {0x0, 2, 1, false, 0}, 705 {0x0, 0, 2, false, 0}, 706 {0x0, 3, 0, false, 0}, 707 {0x0, 3, 1, false, 0}, 708 {0x0, 2, 3, false, 0}, 709 {0x0, 0, 2, false, 0}, 710 {0x0, 1, 0, false, 0}, 711 {0x0, 2, 1, false, 0}, 712 {0x0, 3, 2, true, 0}, 713 {0x0, 3, 1, false, 0}, 714 {0x0, 2, 3, false, 0}, 715 {0x0, 0, 2, false, 0}, 716 {0x0, 1, 0, false, 0}, 717 {0x0, 2, 1, false, 0}, 718 {0x0, 0, 2, false, 0}, 719 {0x0, 3, 0, false, 0}, 720 }; 721 722 static const struct ppe_scheduler_port_config ppe_port_sch_config[] = { 723 { 724 .port = 0, 725 .flow_level = true, 726 .node_id = 0, 727 .loop_num = 1, 728 .pri_max = 1, 729 .flow_id = 0, 730 .drr_node_id = 0, 731 }, 732 { 733 .port = 0, 734 .flow_level = false, 735 .node_id = 0, 736 .loop_num = 8, 737 .pri_max = 8, 738 .flow_id = 0, 739 .drr_node_id = 0, 740 }, 741 { 742 .port = 0, 743 .flow_level = false, 744 .node_id = 8, 745 .loop_num = 8, 746 .pri_max = 8, 747 .flow_id = 0, 748 .drr_node_id = 0, 749 }, 750 { 751 .port = 0, 752 .flow_level = false, 753 .node_id = 16, 754 .loop_num = 8, 755 .pri_max = 8, 756 .flow_id = 0, 757 .drr_node_id = 0, 758 }, 759 { 760 .port = 0, 761 .flow_level = false, 762 .node_id = 24, 763 .loop_num = 8, 764 .pri_max = 8, 765 .flow_id = 0, 766 .drr_node_id = 0, 767 }, 768 { 769 .port = 0, 770 .flow_level = false, 771 .node_id = 32, 772 .loop_num = 8, 773 .pri_max = 8, 774 .flow_id = 0, 775 .drr_node_id = 0, 776 }, 777 { 778 .port = 0, 779 .flow_level = false, 780 .node_id = 40, 781 .loop_num = 8, 782 .pri_max = 8, 783 .flow_id = 0, 784 .drr_node_id = 0, 785 }, 786 { 787 .port = 0, 788 .flow_level = false, 789 .node_id = 48, 790 .loop_num = 8, 791 .pri_max = 8, 792 .flow_id = 0, 793 .drr_node_id = 0, 794 }, 795 { 796 .port = 0, 797 .flow_level = false, 798 .node_id = 56, 799 .loop_num = 8, 800 .pri_max = 8, 801 .flow_id = 0, 802 .drr_node_id = 0, 803 }, 804 { 805 .port = 0, 806 .flow_level = false, 807 .node_id = 256, 808 .loop_num = 8, 809 .pri_max = 8, 810 .flow_id = 0, 811 .drr_node_id = 0, 812 }, 813 { 814 .port = 0, 815 .flow_level = false, 816 .node_id = 264, 817 .loop_num = 8, 818 .pri_max = 8, 819 .flow_id = 0, 820 .drr_node_id = 0, 821 }, 822 { 823 .port = 1, 824 .flow_level = true, 825 .node_id = 36, 826 .loop_num = 2, 827 .pri_max = 0, 828 .flow_id = 1, 829 .drr_node_id = 8, 830 }, 831 { 832 .port = 1, 833 .flow_level = false, 834 .node_id = 144, 835 .loop_num = 16, 836 .pri_max = 8, 837 .flow_id = 36, 838 .drr_node_id = 48, 839 }, 840 { 841 .port = 1, 842 .flow_level = false, 843 .node_id = 272, 844 .loop_num = 4, 845 .pri_max = 4, 846 .flow_id = 36, 847 .drr_node_id = 48, 848 }, 849 { 850 .port = 2, 851 .flow_level = true, 852 .node_id = 40, 853 .loop_num = 2, 854 .pri_max = 0, 855 .flow_id = 2, 856 .drr_node_id = 12, 857 }, 858 { 859 .port = 2, 860 .flow_level = false, 861 .node_id = 160, 862 .loop_num = 16, 863 .pri_max = 8, 864 .flow_id = 40, 865 .drr_node_id = 64, 866 }, 867 { 868 .port = 2, 869 .flow_level = false, 870 .node_id = 276, 871 .loop_num = 4, 872 .pri_max = 4, 873 .flow_id = 40, 874 .drr_node_id = 64, 875 }, 876 { 877 .port = 3, 878 .flow_level = true, 879 .node_id = 44, 880 .loop_num = 2, 881 .pri_max = 0, 882 .flow_id = 3, 883 .drr_node_id = 16, 884 }, 885 { 886 .port = 3, 887 .flow_level = false, 888 .node_id = 176, 889 .loop_num = 16, 890 .pri_max = 8, 891 .flow_id = 44, 892 .drr_node_id = 80, 893 }, 894 { 895 .port = 3, 896 .flow_level = false, 897 .node_id = 280, 898 .loop_num = 4, 899 .pri_max = 4, 900 .flow_id = 44, 901 .drr_node_id = 80, 902 }, 903 { 904 .port = 4, 905 .flow_level = true, 906 .node_id = 48, 907 .loop_num = 2, 908 .pri_max = 0, 909 .flow_id = 4, 910 .drr_node_id = 20, 911 }, 912 { 913 .port = 4, 914 .flow_level = false, 915 .node_id = 192, 916 .loop_num = 16, 917 .pri_max = 8, 918 .flow_id = 48, 919 .drr_node_id = 96, 920 }, 921 { 922 .port = 4, 923 .flow_level = false, 924 .node_id = 284, 925 .loop_num = 4, 926 .pri_max = 4, 927 .flow_id = 48, 928 .drr_node_id = 96, 929 }, 930 { 931 .port = 5, 932 .flow_level = true, 933 .node_id = 52, 934 .loop_num = 2, 935 .pri_max = 0, 936 .flow_id = 5, 937 .drr_node_id = 24, 938 }, 939 { 940 .port = 5, 941 .flow_level = false, 942 .node_id = 208, 943 .loop_num = 16, 944 .pri_max = 8, 945 .flow_id = 52, 946 .drr_node_id = 112, 947 }, 948 { 949 .port = 5, 950 .flow_level = false, 951 .node_id = 288, 952 .loop_num = 4, 953 .pri_max = 4, 954 .flow_id = 52, 955 .drr_node_id = 112, 956 }, 957 { 958 .port = 6, 959 .flow_level = true, 960 .node_id = 56, 961 .loop_num = 2, 962 .pri_max = 0, 963 .flow_id = 6, 964 .drr_node_id = 28, 965 }, 966 { 967 .port = 6, 968 .flow_level = false, 969 .node_id = 224, 970 .loop_num = 16, 971 .pri_max = 8, 972 .flow_id = 56, 973 .drr_node_id = 128, 974 }, 975 { 976 .port = 6, 977 .flow_level = false, 978 .node_id = 292, 979 .loop_num = 4, 980 .pri_max = 4, 981 .flow_id = 56, 982 .drr_node_id = 128, 983 }, 984 { 985 .port = 7, 986 .flow_level = true, 987 .node_id = 60, 988 .loop_num = 2, 989 .pri_max = 0, 990 .flow_id = 7, 991 .drr_node_id = 32, 992 }, 993 { 994 .port = 7, 995 .flow_level = false, 996 .node_id = 240, 997 .loop_num = 16, 998 .pri_max = 8, 999 .flow_id = 60, 1000 .drr_node_id = 144, 1001 }, 1002 { 1003 .port = 7, 1004 .flow_level = false, 1005 .node_id = 296, 1006 .loop_num = 4, 1007 .pri_max = 4, 1008 .flow_id = 60, 1009 .drr_node_id = 144, 1010 }, 1011 }; 1012 1013 /* The scheduler resource is applied to each PPE port, The resource 1014 * includes the unicast & multicast queues, flow nodes and DRR nodes. 1015 */ 1016 static const struct ppe_port_schedule_resource ipq9574_ppe_scheduler_res[] = { 1017 { .ucastq_start = 0, 1018 .ucastq_end = 63, 1019 .mcastq_start = 256, 1020 .mcastq_end = 271, 1021 .flow_id_start = 0, 1022 .flow_id_end = 0, 1023 .l0node_start = 0, 1024 .l0node_end = 7, 1025 .l1node_start = 0, 1026 .l1node_end = 0, 1027 }, 1028 { .ucastq_start = 144, 1029 .ucastq_end = 159, 1030 .mcastq_start = 272, 1031 .mcastq_end = 275, 1032 .flow_id_start = 36, 1033 .flow_id_end = 39, 1034 .l0node_start = 48, 1035 .l0node_end = 63, 1036 .l1node_start = 8, 1037 .l1node_end = 11, 1038 }, 1039 { .ucastq_start = 160, 1040 .ucastq_end = 175, 1041 .mcastq_start = 276, 1042 .mcastq_end = 279, 1043 .flow_id_start = 40, 1044 .flow_id_end = 43, 1045 .l0node_start = 64, 1046 .l0node_end = 79, 1047 .l1node_start = 12, 1048 .l1node_end = 15, 1049 }, 1050 { .ucastq_start = 176, 1051 .ucastq_end = 191, 1052 .mcastq_start = 280, 1053 .mcastq_end = 283, 1054 .flow_id_start = 44, 1055 .flow_id_end = 47, 1056 .l0node_start = 80, 1057 .l0node_end = 95, 1058 .l1node_start = 16, 1059 .l1node_end = 19, 1060 }, 1061 { .ucastq_start = 192, 1062 .ucastq_end = 207, 1063 .mcastq_start = 284, 1064 .mcastq_end = 287, 1065 .flow_id_start = 48, 1066 .flow_id_end = 51, 1067 .l0node_start = 96, 1068 .l0node_end = 111, 1069 .l1node_start = 20, 1070 .l1node_end = 23, 1071 }, 1072 { .ucastq_start = 208, 1073 .ucastq_end = 223, 1074 .mcastq_start = 288, 1075 .mcastq_end = 291, 1076 .flow_id_start = 52, 1077 .flow_id_end = 55, 1078 .l0node_start = 112, 1079 .l0node_end = 127, 1080 .l1node_start = 24, 1081 .l1node_end = 27, 1082 }, 1083 { .ucastq_start = 224, 1084 .ucastq_end = 239, 1085 .mcastq_start = 292, 1086 .mcastq_end = 295, 1087 .flow_id_start = 56, 1088 .flow_id_end = 59, 1089 .l0node_start = 128, 1090 .l0node_end = 143, 1091 .l1node_start = 28, 1092 .l1node_end = 31, 1093 }, 1094 { .ucastq_start = 240, 1095 .ucastq_end = 255, 1096 .mcastq_start = 296, 1097 .mcastq_end = 299, 1098 .flow_id_start = 60, 1099 .flow_id_end = 63, 1100 .l0node_start = 144, 1101 .l0node_end = 159, 1102 .l1node_start = 32, 1103 .l1node_end = 35, 1104 }, 1105 { .ucastq_start = 64, 1106 .ucastq_end = 143, 1107 .mcastq_start = 0, 1108 .mcastq_end = 0, 1109 .flow_id_start = 1, 1110 .flow_id_end = 35, 1111 .l0node_start = 8, 1112 .l0node_end = 47, 1113 .l1node_start = 1, 1114 .l1node_end = 7, 1115 }, 1116 }; 1117 1118 static const struct ppe_port_schedule_resource ipq5424_ppe_scheduler_res[] = { 1119 { .ucastq_start = 0, 1120 .ucastq_end = 63, 1121 .mcastq_start = 256, 1122 .mcastq_end = 271, 1123 .flow_id_start = 0, 1124 .flow_id_end = 0, 1125 .l0node_start = 0, 1126 .l0node_end = 7, 1127 .l1node_start = 0, 1128 .l1node_end = 0, 1129 }, 1130 { .ucastq_start = 144, 1131 .ucastq_end = 159, 1132 .mcastq_start = 272, 1133 .mcastq_end = 275, 1134 .flow_id_start = 36, 1135 .flow_id_end = 39, 1136 .l0node_start = 48, 1137 .l0node_end = 63, 1138 .l1node_start = 8, 1139 .l1node_end = 11, 1140 }, 1141 { .ucastq_start = 160, 1142 .ucastq_end = 175, 1143 .mcastq_start = 276, 1144 .mcastq_end = 279, 1145 .flow_id_start = 40, 1146 .flow_id_end = 43, 1147 .l0node_start = 64, 1148 .l0node_end = 79, 1149 .l1node_start = 12, 1150 .l1node_end = 15, 1151 }, 1152 { .ucastq_start = 176, 1153 .ucastq_end = 191, 1154 .mcastq_start = 280, 1155 .mcastq_end = 283, 1156 .flow_id_start = 44, 1157 .flow_id_end = 47, 1158 .l0node_start = 80, 1159 .l0node_end = 95, 1160 .l1node_start = 16, 1161 .l1node_end = 19, 1162 }, 1163 { .ucastq_start = 64, 1164 .ucastq_end = 143, 1165 .mcastq_start = 0, 1166 .mcastq_end = 0, 1167 .flow_id_start = 1, 1168 .flow_id_end = 35, 1169 .l0node_start = 8, 1170 .l0node_end = 47, 1171 .l1node_start = 1, 1172 .l1node_end = 7, 1173 }, 1174 }; 1175 1176 /* Set the PPE queue level scheduler configuration. */ 1177 static int ppe_scheduler_l0_queue_map_set(struct ppe_device *ppe_dev, 1178 int node_id, int port, 1179 struct ppe_scheduler_cfg scheduler_cfg) 1180 { 1181 u32 val, reg; 1182 int ret; 1183 1184 reg = PPE_L0_FLOW_MAP_TBL_ADDR + node_id * PPE_L0_FLOW_MAP_TBL_INC; 1185 val = FIELD_PREP(PPE_L0_FLOW_MAP_TBL_FLOW_ID, scheduler_cfg.flow_id); 1186 val |= FIELD_PREP(PPE_L0_FLOW_MAP_TBL_C_PRI, scheduler_cfg.pri); 1187 val |= FIELD_PREP(PPE_L0_FLOW_MAP_TBL_E_PRI, scheduler_cfg.pri); 1188 val |= FIELD_PREP(PPE_L0_FLOW_MAP_TBL_C_NODE_WT, scheduler_cfg.drr_node_wt); 1189 val |= FIELD_PREP(PPE_L0_FLOW_MAP_TBL_E_NODE_WT, scheduler_cfg.drr_node_wt); 1190 1191 ret = regmap_write(ppe_dev->regmap, reg, val); 1192 if (ret) 1193 return ret; 1194 1195 reg = PPE_L0_C_FLOW_CFG_TBL_ADDR + 1196 (scheduler_cfg.flow_id * PPE_QUEUE_SCH_PRI_NUM + scheduler_cfg.pri) * 1197 PPE_L0_C_FLOW_CFG_TBL_INC; 1198 val = FIELD_PREP(PPE_L0_C_FLOW_CFG_TBL_NODE_ID, scheduler_cfg.drr_node_id); 1199 val |= FIELD_PREP(PPE_L0_C_FLOW_CFG_TBL_NODE_CREDIT_UNIT, scheduler_cfg.unit_is_packet); 1200 1201 ret = regmap_write(ppe_dev->regmap, reg, val); 1202 if (ret) 1203 return ret; 1204 1205 reg = PPE_L0_E_FLOW_CFG_TBL_ADDR + 1206 (scheduler_cfg.flow_id * PPE_QUEUE_SCH_PRI_NUM + scheduler_cfg.pri) * 1207 PPE_L0_E_FLOW_CFG_TBL_INC; 1208 val = FIELD_PREP(PPE_L0_E_FLOW_CFG_TBL_NODE_ID, scheduler_cfg.drr_node_id); 1209 val |= FIELD_PREP(PPE_L0_E_FLOW_CFG_TBL_NODE_CREDIT_UNIT, scheduler_cfg.unit_is_packet); 1210 1211 ret = regmap_write(ppe_dev->regmap, reg, val); 1212 if (ret) 1213 return ret; 1214 1215 reg = PPE_L0_FLOW_PORT_MAP_TBL_ADDR + node_id * PPE_L0_FLOW_PORT_MAP_TBL_INC; 1216 val = FIELD_PREP(PPE_L0_FLOW_PORT_MAP_TBL_PORT_NUM, port); 1217 1218 ret = regmap_write(ppe_dev->regmap, reg, val); 1219 if (ret) 1220 return ret; 1221 1222 reg = PPE_L0_COMP_CFG_TBL_ADDR + node_id * PPE_L0_COMP_CFG_TBL_INC; 1223 val = FIELD_PREP(PPE_L0_COMP_CFG_TBL_NODE_METER_LEN, scheduler_cfg.frame_mode); 1224 1225 return regmap_update_bits(ppe_dev->regmap, reg, 1226 PPE_L0_COMP_CFG_TBL_NODE_METER_LEN, 1227 val); 1228 } 1229 1230 /* Set the PPE flow level scheduler configuration. */ 1231 static int ppe_scheduler_l1_queue_map_set(struct ppe_device *ppe_dev, 1232 int node_id, int port, 1233 struct ppe_scheduler_cfg scheduler_cfg) 1234 { 1235 u32 val, reg; 1236 int ret; 1237 1238 val = FIELD_PREP(PPE_L1_FLOW_MAP_TBL_FLOW_ID, scheduler_cfg.flow_id); 1239 val |= FIELD_PREP(PPE_L1_FLOW_MAP_TBL_C_PRI, scheduler_cfg.pri); 1240 val |= FIELD_PREP(PPE_L1_FLOW_MAP_TBL_E_PRI, scheduler_cfg.pri); 1241 val |= FIELD_PREP(PPE_L1_FLOW_MAP_TBL_C_NODE_WT, scheduler_cfg.drr_node_wt); 1242 val |= FIELD_PREP(PPE_L1_FLOW_MAP_TBL_E_NODE_WT, scheduler_cfg.drr_node_wt); 1243 reg = PPE_L1_FLOW_MAP_TBL_ADDR + node_id * PPE_L1_FLOW_MAP_TBL_INC; 1244 1245 ret = regmap_write(ppe_dev->regmap, reg, val); 1246 if (ret) 1247 return ret; 1248 1249 val = FIELD_PREP(PPE_L1_C_FLOW_CFG_TBL_NODE_ID, scheduler_cfg.drr_node_id); 1250 val |= FIELD_PREP(PPE_L1_C_FLOW_CFG_TBL_NODE_CREDIT_UNIT, scheduler_cfg.unit_is_packet); 1251 reg = PPE_L1_C_FLOW_CFG_TBL_ADDR + 1252 (scheduler_cfg.flow_id * PPE_QUEUE_SCH_PRI_NUM + scheduler_cfg.pri) * 1253 PPE_L1_C_FLOW_CFG_TBL_INC; 1254 1255 ret = regmap_write(ppe_dev->regmap, reg, val); 1256 if (ret) 1257 return ret; 1258 1259 val = FIELD_PREP(PPE_L1_E_FLOW_CFG_TBL_NODE_ID, scheduler_cfg.drr_node_id); 1260 val |= FIELD_PREP(PPE_L1_E_FLOW_CFG_TBL_NODE_CREDIT_UNIT, scheduler_cfg.unit_is_packet); 1261 reg = PPE_L1_E_FLOW_CFG_TBL_ADDR + 1262 (scheduler_cfg.flow_id * PPE_QUEUE_SCH_PRI_NUM + scheduler_cfg.pri) * 1263 PPE_L1_E_FLOW_CFG_TBL_INC; 1264 1265 ret = regmap_write(ppe_dev->regmap, reg, val); 1266 if (ret) 1267 return ret; 1268 1269 val = FIELD_PREP(PPE_L1_FLOW_PORT_MAP_TBL_PORT_NUM, port); 1270 reg = PPE_L1_FLOW_PORT_MAP_TBL_ADDR + node_id * PPE_L1_FLOW_PORT_MAP_TBL_INC; 1271 1272 ret = regmap_write(ppe_dev->regmap, reg, val); 1273 if (ret) 1274 return ret; 1275 1276 reg = PPE_L1_COMP_CFG_TBL_ADDR + node_id * PPE_L1_COMP_CFG_TBL_INC; 1277 val = FIELD_PREP(PPE_L1_COMP_CFG_TBL_NODE_METER_LEN, scheduler_cfg.frame_mode); 1278 1279 return regmap_update_bits(ppe_dev->regmap, reg, PPE_L1_COMP_CFG_TBL_NODE_METER_LEN, val); 1280 } 1281 1282 /** 1283 * ppe_queue_scheduler_set - Configure scheduler for PPE hardware queue 1284 * @ppe_dev: PPE device 1285 * @node_id: PPE queue ID or flow ID 1286 * @flow_level: Flow level scheduler or queue level scheduler 1287 * @port: PPE port ID set scheduler configuration 1288 * @scheduler_cfg: PPE scheduler configuration 1289 * 1290 * PPE scheduler configuration supports queue level and flow level on 1291 * the PPE egress port. 1292 * 1293 * Return: 0 on success, negative error code on failure. 1294 */ 1295 int ppe_queue_scheduler_set(struct ppe_device *ppe_dev, 1296 int node_id, bool flow_level, int port, 1297 struct ppe_scheduler_cfg scheduler_cfg) 1298 { 1299 if (flow_level) 1300 return ppe_scheduler_l1_queue_map_set(ppe_dev, node_id, 1301 port, scheduler_cfg); 1302 1303 return ppe_scheduler_l0_queue_map_set(ppe_dev, node_id, 1304 port, scheduler_cfg); 1305 } 1306 1307 /** 1308 * ppe_queue_ucast_base_set - Set PPE unicast queue base ID and profile ID 1309 * @ppe_dev: PPE device 1310 * @queue_dst: PPE queue destination configuration 1311 * @queue_base: PPE queue base ID 1312 * @profile_id: Profile ID 1313 * 1314 * The PPE unicast queue base ID and profile ID are configured based on the 1315 * destination port information that can be service code or CPU code or the 1316 * destination port. 1317 * 1318 * Return: 0 on success, negative error code on failure. 1319 */ 1320 int ppe_queue_ucast_base_set(struct ppe_device *ppe_dev, 1321 struct ppe_queue_ucast_dest queue_dst, 1322 int queue_base, int profile_id) 1323 { 1324 int index, profile_size; 1325 u32 val, reg; 1326 1327 profile_size = queue_dst.src_profile << 8; 1328 if (queue_dst.service_code_en) 1329 index = PPE_QUEUE_BASE_SERVICE_CODE + profile_size + 1330 queue_dst.service_code; 1331 else if (queue_dst.cpu_code_en) 1332 index = PPE_QUEUE_BASE_CPU_CODE + profile_size + 1333 queue_dst.cpu_code; 1334 else 1335 index = profile_size + queue_dst.dest_port; 1336 1337 val = FIELD_PREP(PPE_UCAST_QUEUE_MAP_TBL_PROFILE_ID, profile_id); 1338 val |= FIELD_PREP(PPE_UCAST_QUEUE_MAP_TBL_QUEUE_ID, queue_base); 1339 reg = PPE_UCAST_QUEUE_MAP_TBL_ADDR + index * PPE_UCAST_QUEUE_MAP_TBL_INC; 1340 1341 return regmap_write(ppe_dev->regmap, reg, val); 1342 } 1343 1344 /** 1345 * ppe_queue_ucast_offset_pri_set - Set PPE unicast queue offset based on priority 1346 * @ppe_dev: PPE device 1347 * @profile_id: Profile ID 1348 * @priority: PPE internal priority to be used to set queue offset 1349 * @queue_offset: Queue offset used for calculating the destination queue ID 1350 * 1351 * The PPE unicast queue offset is configured based on the PPE 1352 * internal priority. 1353 * 1354 * Return: 0 on success, negative error code on failure. 1355 */ 1356 int ppe_queue_ucast_offset_pri_set(struct ppe_device *ppe_dev, 1357 int profile_id, 1358 int priority, 1359 int queue_offset) 1360 { 1361 u32 val, reg; 1362 int index; 1363 1364 index = (profile_id << 4) + priority; 1365 val = FIELD_PREP(PPE_UCAST_PRIORITY_MAP_TBL_CLASS, queue_offset); 1366 reg = PPE_UCAST_PRIORITY_MAP_TBL_ADDR + index * PPE_UCAST_PRIORITY_MAP_TBL_INC; 1367 1368 return regmap_write(ppe_dev->regmap, reg, val); 1369 } 1370 1371 /** 1372 * ppe_queue_ucast_offset_hash_set - Set PPE unicast queue offset based on hash 1373 * @ppe_dev: PPE device 1374 * @profile_id: Profile ID 1375 * @rss_hash: Packet hash value to be used to set queue offset 1376 * @queue_offset: Queue offset used for calculating the destination queue ID 1377 * 1378 * The PPE unicast queue offset is configured based on the RSS hash value. 1379 * 1380 * Return: 0 on success, negative error code on failure. 1381 */ 1382 int ppe_queue_ucast_offset_hash_set(struct ppe_device *ppe_dev, 1383 int profile_id, 1384 int rss_hash, 1385 int queue_offset) 1386 { 1387 u32 val, reg; 1388 int index; 1389 1390 index = (profile_id << 8) + rss_hash; 1391 val = FIELD_PREP(PPE_UCAST_HASH_MAP_TBL_HASH, queue_offset); 1392 reg = PPE_UCAST_HASH_MAP_TBL_ADDR + index * PPE_UCAST_HASH_MAP_TBL_INC; 1393 1394 return regmap_write(ppe_dev->regmap, reg, val); 1395 } 1396 1397 /** 1398 * ppe_port_resource_get - Get PPE resource per port 1399 * @ppe_dev: PPE device 1400 * @port: PPE port 1401 * @type: Resource type 1402 * @res_start: Resource start ID returned 1403 * @res_end: Resource end ID returned 1404 * 1405 * PPE resource is assigned per PPE port, which is acquired for QoS scheduler. 1406 * 1407 * Return: 0 on success, negative error code on failure. 1408 */ 1409 int ppe_port_resource_get(struct ppe_device *ppe_dev, int port, 1410 enum ppe_resource_type type, 1411 int *res_start, int *res_end) 1412 { 1413 const struct ppe_port_schedule_resource *scheduler_res; 1414 struct ppe_port_schedule_resource res; 1415 unsigned int scheduler_res_len; 1416 1417 switch (ppe_dev->type) { 1418 case IPQ9574_PPE: 1419 scheduler_res = ipq9574_ppe_scheduler_res; 1420 scheduler_res_len = ARRAY_SIZE(ipq9574_ppe_scheduler_res); 1421 break; 1422 case IPQ5424_PPE: 1423 scheduler_res = ipq5424_ppe_scheduler_res; 1424 scheduler_res_len = ARRAY_SIZE(ipq5424_ppe_scheduler_res); 1425 break; 1426 default: 1427 dev_err(ppe_dev->dev, "Invalid PPE type %d\n", ppe_dev->type); 1428 return -EINVAL; 1429 } 1430 1431 /* The reserved resource, stored at the last entry of the 1432 * scheduler resource table, is also allowed to be acquired. 1433 */ 1434 if (port >= scheduler_res_len) 1435 return -EINVAL; 1436 1437 res = scheduler_res[port]; 1438 switch (type) { 1439 case PPE_RES_UCAST: 1440 *res_start = res.ucastq_start; 1441 *res_end = res.ucastq_end; 1442 break; 1443 case PPE_RES_MCAST: 1444 *res_start = res.mcastq_start; 1445 *res_end = res.mcastq_end; 1446 break; 1447 case PPE_RES_FLOW_ID: 1448 *res_start = res.flow_id_start; 1449 *res_end = res.flow_id_end; 1450 break; 1451 case PPE_RES_L0_NODE: 1452 *res_start = res.l0node_start; 1453 *res_end = res.l0node_end; 1454 break; 1455 case PPE_RES_L1_NODE: 1456 *res_start = res.l1node_start; 1457 *res_end = res.l1node_end; 1458 break; 1459 default: 1460 return -EINVAL; 1461 } 1462 1463 return 0; 1464 } 1465 1466 /** 1467 * ppe_sc_config_set - Set PPE service code configuration 1468 * @ppe_dev: PPE device 1469 * @sc: Service ID, 0-255 supported by PPE 1470 * @cfg: Service code configuration 1471 * 1472 * PPE service code is used by the PPE during its packet processing stages, 1473 * to perform or bypass certain selected packet operations on the packet. 1474 * 1475 * Return: 0 on success, negative error code on failure. 1476 */ 1477 int ppe_sc_config_set(struct ppe_device *ppe_dev, int sc, struct ppe_sc_cfg cfg) 1478 { 1479 u32 val, reg, servcode_val[2] = {}, in_l2_val[2] = {}; 1480 unsigned long bitmap_value; 1481 int ret; 1482 1483 val = FIELD_PREP(PPE_IN_L2_SERVICE_TBL_DST_PORT_ID_VALID, cfg.dest_port_valid); 1484 val |= FIELD_PREP(PPE_IN_L2_SERVICE_TBL_DST_PORT_ID, cfg.dest_port); 1485 val |= FIELD_PREP(PPE_IN_L2_SERVICE_TBL_DST_DIRECTION, cfg.is_src); 1486 1487 bitmap_value = bitmap_read(cfg.bitmaps.egress, 0, PPE_SC_BYPASS_EGRESS_SIZE); 1488 val |= FIELD_PREP(PPE_IN_L2_SERVICE_TBL_DST_BYPASS_BITMAP, bitmap_value); 1489 val |= FIELD_PREP(PPE_IN_L2_SERVICE_TBL_RX_CNT_EN, 1490 test_bit(PPE_SC_BYPASS_COUNTER_RX, cfg.bitmaps.counter)); 1491 val |= FIELD_PREP(PPE_IN_L2_SERVICE_TBL_TX_CNT_EN, 1492 test_bit(PPE_SC_BYPASS_COUNTER_TX, cfg.bitmaps.counter)); 1493 reg = PPE_IN_L2_SERVICE_TBL_ADDR + PPE_IN_L2_SERVICE_TBL_INC(ppe_dev) * sc; 1494 1495 in_l2_val[0] = val; 1496 1497 bitmap_value = bitmap_read(cfg.bitmaps.egress, PPE_SC_BYPASS_EGRESS_SMAC_MC_DROP, 1498 PPE_SC_BYPASS_EGRESS_SIZE - PPE_SC_BYPASS_EGRESS_SMAC_MC_DROP); 1499 in_l2_val[1] = FIELD_PREP(PPE_IN_L2_SERVICE_TBL_W1_BYPASS_BITMAP_EXT, bitmap_value); 1500 1501 ret = regmap_bulk_write(ppe_dev->regmap, reg, in_l2_val, 1502 PPE_IN_L2_SERVICE_TBL_WORDS(ppe_dev)); 1503 if (ret) 1504 return ret; 1505 1506 bitmap_value = bitmap_read(cfg.bitmaps.ingress, 0, PPE_SC_BYPASS_INGRESS_SIZE); 1507 PPE_SERVICE_SET_BYPASS_BITMAP(servcode_val, bitmap_value); 1508 PPE_SERVICE_SET_RX_CNT_EN(servcode_val, 1509 test_bit(PPE_SC_BYPASS_COUNTER_RX_VLAN, cfg.bitmaps.counter)); 1510 reg = PPE_SERVICE_TBL_ADDR + PPE_SERVICE_TBL_INC * sc; 1511 1512 ret = regmap_bulk_write(ppe_dev->regmap, reg, 1513 servcode_val, ARRAY_SIZE(servcode_val)); 1514 if (ret) 1515 return ret; 1516 1517 reg = PPE_EG_SERVICE_TBL_ADDR + PPE_EG_SERVICE_TBL_INC * sc; 1518 ret = regmap_bulk_read(ppe_dev->regmap, reg, 1519 servcode_val, ARRAY_SIZE(servcode_val)); 1520 if (ret) 1521 return ret; 1522 1523 PPE_EG_SERVICE_SET_NEXT_SERVCODE(servcode_val, cfg.next_service_code); 1524 PPE_EG_SERVICE_SET_UPDATE_ACTION(servcode_val, cfg.eip_field_update_bitmap); 1525 PPE_EG_SERVICE_SET_HW_SERVICE(servcode_val, cfg.eip_hw_service); 1526 PPE_EG_SERVICE_SET_OFFSET_SEL(servcode_val, cfg.eip_offset_sel); 1527 PPE_EG_SERVICE_SET_TX_CNT_EN(servcode_val, 1528 test_bit(PPE_SC_BYPASS_COUNTER_TX_VLAN, cfg.bitmaps.counter)); 1529 1530 ret = regmap_bulk_write(ppe_dev->regmap, reg, 1531 servcode_val, ARRAY_SIZE(servcode_val)); 1532 if (ret) 1533 return ret; 1534 1535 bitmap_value = bitmap_read(cfg.bitmaps.tunnel, 0, PPE_SC_BYPASS_TUNNEL_SIZE); 1536 val = FIELD_PREP(PPE_TL_SERVICE_TBL_BYPASS_BITMAP, bitmap_value); 1537 reg = PPE_TL_SERVICE_TBL_ADDR + PPE_TL_SERVICE_TBL_INC * sc; 1538 1539 return regmap_write(ppe_dev->regmap, reg, val); 1540 } 1541 1542 /** 1543 * ppe_counter_enable_set - Set PPE port counter enabled 1544 * @ppe_dev: PPE device 1545 * @port: PPE port ID 1546 * 1547 * Enable PPE counters on the given port for the unicast packet, multicast 1548 * packet and VLAN packet received and transmitted by PPE. 1549 * 1550 * Return: 0 on success, negative error code on failure. 1551 */ 1552 int ppe_counter_enable_set(struct ppe_device *ppe_dev, int port) 1553 { 1554 u32 reg, mru_mtu_val[3]; 1555 int ret; 1556 1557 reg = PPE_MRU_MTU_CTRL_TBL_ADDR + PPE_MRU_MTU_CTRL_TBL_INC * port; 1558 ret = regmap_bulk_read(ppe_dev->regmap, reg, 1559 mru_mtu_val, ARRAY_SIZE(mru_mtu_val)); 1560 if (ret) 1561 return ret; 1562 1563 PPE_MRU_MTU_CTRL_SET_RX_CNT_EN(mru_mtu_val, true); 1564 PPE_MRU_MTU_CTRL_SET_TX_CNT_EN(mru_mtu_val, true); 1565 ret = regmap_bulk_write(ppe_dev->regmap, reg, 1566 mru_mtu_val, ARRAY_SIZE(mru_mtu_val)); 1567 if (ret) 1568 return ret; 1569 1570 reg = PPE_MC_MTU_CTRL_TBL_ADDR + PPE_MC_MTU_CTRL_TBL_INC * port; 1571 ret = regmap_set_bits(ppe_dev->regmap, reg, PPE_MC_MTU_CTRL_TBL_TX_CNT_EN); 1572 if (ret) 1573 return ret; 1574 1575 reg = PPE_PORT_EG_VLAN_TBL_ADDR + PPE_PORT_EG_VLAN_TBL_INC * port; 1576 1577 return regmap_set_bits(ppe_dev->regmap, reg, PPE_PORT_EG_VLAN_TBL_TX_COUNTING_EN); 1578 } 1579 1580 static int ppe_rss_hash_ipv4_config(struct ppe_device *ppe_dev, int index, 1581 struct ppe_rss_hash_cfg cfg) 1582 { 1583 u32 reg, val; 1584 1585 switch (index) { 1586 case 0: 1587 val = cfg.hash_sip_mix[0]; 1588 break; 1589 case 1: 1590 val = cfg.hash_dip_mix[0]; 1591 break; 1592 case 2: 1593 val = cfg.hash_protocol_mix; 1594 break; 1595 case 3: 1596 val = cfg.hash_dport_mix; 1597 break; 1598 case 4: 1599 val = cfg.hash_sport_mix; 1600 break; 1601 default: 1602 return -EINVAL; 1603 } 1604 1605 reg = PPE_RSS_HASH_MIX_IPV4_ADDR + index * PPE_RSS_HASH_MIX_IPV4_INC; 1606 1607 return regmap_update_bits(ppe_dev->regmap, reg, 1608 PPE_RSS_HASH_MIX_IPV4_VAL, 1609 FIELD_PREP(PPE_RSS_HASH_MIX_IPV4_VAL, val)); 1610 } 1611 1612 static int ppe_rss_hash_ipv6_config(struct ppe_device *ppe_dev, int index, 1613 struct ppe_rss_hash_cfg cfg) 1614 { 1615 u32 reg, val; 1616 1617 switch (index) { 1618 case 0 ... 3: 1619 val = cfg.hash_sip_mix[index]; 1620 break; 1621 case 4 ... 7: 1622 val = cfg.hash_dip_mix[index - 4]; 1623 break; 1624 case 8: 1625 val = cfg.hash_protocol_mix; 1626 break; 1627 case 9: 1628 val = cfg.hash_dport_mix; 1629 break; 1630 case 10: 1631 val = cfg.hash_sport_mix; 1632 break; 1633 default: 1634 return -EINVAL; 1635 } 1636 1637 reg = PPE_RSS_HASH_MIX_ADDR + index * PPE_RSS_HASH_MIX_INC; 1638 1639 return regmap_update_bits(ppe_dev->regmap, reg, 1640 PPE_RSS_HASH_MIX_VAL, 1641 FIELD_PREP(PPE_RSS_HASH_MIX_VAL, val)); 1642 } 1643 1644 /** 1645 * ppe_rss_hash_config_set - Configure the PPE hash settings for the packet received. 1646 * @ppe_dev: PPE device. 1647 * @mode: Configure RSS hash for the packet type IPv4 and IPv6. 1648 * @cfg: RSS hash configuration. 1649 * 1650 * PPE RSS hash settings are configured for the packet type IPv4 and IPv6. 1651 * 1652 * Return: 0 on success, negative error code on failure. 1653 */ 1654 int ppe_rss_hash_config_set(struct ppe_device *ppe_dev, int mode, 1655 struct ppe_rss_hash_cfg cfg) 1656 { 1657 u32 val, reg; 1658 int i, ret; 1659 1660 if (mode & PPE_RSS_HASH_MODE_IPV4) { 1661 val = FIELD_PREP(PPE_RSS_HASH_MASK_IPV4_HASH_MASK, cfg.hash_mask); 1662 val |= FIELD_PREP(PPE_RSS_HASH_MASK_IPV4_FRAGMENT, cfg.hash_fragment_mode); 1663 ret = regmap_write(ppe_dev->regmap, PPE_RSS_HASH_MASK_IPV4_ADDR, val); 1664 if (ret) 1665 return ret; 1666 1667 val = FIELD_PREP(PPE_RSS_HASH_SEED_IPV4_VAL, cfg.hash_seed); 1668 ret = regmap_write(ppe_dev->regmap, PPE_RSS_HASH_SEED_IPV4_ADDR, val); 1669 if (ret) 1670 return ret; 1671 1672 for (i = 0; i < PPE_RSS_HASH_MIX_IPV4_ENTRIES; i++) { 1673 ret = ppe_rss_hash_ipv4_config(ppe_dev, i, cfg); 1674 if (ret) 1675 return ret; 1676 } 1677 1678 for (i = 0; i < PPE_RSS_HASH_FIN_IPV4_ENTRIES; i++) { 1679 val = FIELD_PREP(PPE_RSS_HASH_FIN_IPV4_INNER, cfg.hash_fin_inner[i]); 1680 val |= FIELD_PREP(PPE_RSS_HASH_FIN_IPV4_OUTER, cfg.hash_fin_outer[i]); 1681 reg = PPE_RSS_HASH_FIN_IPV4_ADDR + i * PPE_RSS_HASH_FIN_IPV4_INC; 1682 1683 ret = regmap_write(ppe_dev->regmap, reg, val); 1684 if (ret) 1685 return ret; 1686 } 1687 } 1688 1689 if (mode & PPE_RSS_HASH_MODE_IPV6) { 1690 val = FIELD_PREP(PPE_RSS_HASH_MASK_HASH_MASK, cfg.hash_mask); 1691 val |= FIELD_PREP(PPE_RSS_HASH_MASK_FRAGMENT, cfg.hash_fragment_mode); 1692 ret = regmap_write(ppe_dev->regmap, PPE_RSS_HASH_MASK_ADDR, val); 1693 if (ret) 1694 return ret; 1695 1696 val = FIELD_PREP(PPE_RSS_HASH_SEED_VAL, cfg.hash_seed); 1697 ret = regmap_write(ppe_dev->regmap, PPE_RSS_HASH_SEED_ADDR, val); 1698 if (ret) 1699 return ret; 1700 1701 for (i = 0; i < PPE_RSS_HASH_MIX_ENTRIES; i++) { 1702 ret = ppe_rss_hash_ipv6_config(ppe_dev, i, cfg); 1703 if (ret) 1704 return ret; 1705 } 1706 1707 for (i = 0; i < PPE_RSS_HASH_FIN_ENTRIES; i++) { 1708 val = FIELD_PREP(PPE_RSS_HASH_FIN_INNER, cfg.hash_fin_inner[i]); 1709 val |= FIELD_PREP(PPE_RSS_HASH_FIN_OUTER, cfg.hash_fin_outer[i]); 1710 reg = PPE_RSS_HASH_FIN_ADDR + i * PPE_RSS_HASH_FIN_INC; 1711 1712 ret = regmap_write(ppe_dev->regmap, reg, val); 1713 if (ret) 1714 return ret; 1715 } 1716 } 1717 1718 return 0; 1719 } 1720 1721 /** 1722 * ppe_ring_queue_map_set - Set the PPE queue to Ethernet DMA ring mapping 1723 * @ppe_dev: PPE device 1724 * @ring_id: Ethernet DMA ring ID 1725 * @queue_map: Bit map of queue IDs to given Ethernet DMA ring 1726 * 1727 * Configure the mapping from a set of PPE queues to a given Ethernet DMA ring. 1728 * 1729 * Return: 0 on success, negative error code on failure. 1730 */ 1731 int ppe_ring_queue_map_set(struct ppe_device *ppe_dev, int ring_id, 1732 const u32 *queue_map) 1733 { 1734 u32 reg, queue_bitmap_val[PPE_RING_TO_QUEUE_BITMAP_WORD_CNT]; 1735 1736 memcpy(queue_bitmap_val, queue_map, sizeof(queue_bitmap_val)); 1737 reg = PPE_RING_Q_MAP_TBL_ADDR + PPE_RING_Q_MAP_TBL_INC * ring_id; 1738 1739 return regmap_bulk_write(ppe_dev->regmap, reg, 1740 queue_bitmap_val, 1741 ARRAY_SIZE(queue_bitmap_val)); 1742 } 1743 1744 static int ppe_config_bm_threshold(struct ppe_device *ppe_dev, int bm_port_id, 1745 struct ppe_bm_port_config port_cfg) 1746 { 1747 u32 reg, val, bm_fc_val[2]; 1748 int ret; 1749 1750 reg = PPE_BM_PORT_FC_CFG_TBL_ADDR + PPE_BM_PORT_FC_CFG_TBL_INC * bm_port_id; 1751 ret = regmap_bulk_read(ppe_dev->regmap, reg, 1752 bm_fc_val, ARRAY_SIZE(bm_fc_val)); 1753 if (ret) 1754 return ret; 1755 1756 /* Configure BM flow control related threshold. */ 1757 PPE_BM_PORT_FC_SET_WEIGHT(bm_fc_val, port_cfg.weight); 1758 PPE_BM_PORT_FC_SET_RESUME_OFFSET(bm_fc_val, port_cfg.resume_offset); 1759 PPE_BM_PORT_FC_SET_RESUME_THRESHOLD(bm_fc_val, port_cfg.resume_ceil); 1760 PPE_BM_PORT_FC_SET_DYNAMIC(bm_fc_val, port_cfg.dynamic); 1761 PPE_BM_PORT_FC_SET_REACT_LIMIT(bm_fc_val, port_cfg.in_fly_buf); 1762 PPE_BM_PORT_FC_SET_PRE_ALLOC(bm_fc_val, port_cfg.pre_alloc); 1763 1764 /* Configure low/high bits of the ceiling for the BM port. */ 1765 val = FIELD_GET(GENMASK(2, 0), port_cfg.ceil); 1766 PPE_BM_PORT_FC_SET_CEILING_LOW(bm_fc_val, val); 1767 val = FIELD_GET(GENMASK(10, 3), port_cfg.ceil); 1768 PPE_BM_PORT_FC_SET_CEILING_HIGH(bm_fc_val, val); 1769 1770 ret = regmap_bulk_write(ppe_dev->regmap, reg, 1771 bm_fc_val, ARRAY_SIZE(bm_fc_val)); 1772 if (ret) 1773 return ret; 1774 1775 /* Assign the default group ID 0 to the BM port. */ 1776 val = FIELD_PREP(PPE_BM_PORT_GROUP_ID_SHARED_GROUP_ID, 0); 1777 reg = PPE_BM_PORT_GROUP_ID_ADDR(ppe_dev) + PPE_BM_PORT_GROUP_ID_INC * bm_port_id; 1778 ret = regmap_update_bits(ppe_dev->regmap, reg, 1779 PPE_BM_PORT_GROUP_ID_SHARED_GROUP_ID, 1780 val); 1781 if (ret) 1782 return ret; 1783 1784 /* Enable BM port flow control. */ 1785 reg = PPE_BM_PORT_FC_MODE_ADDR + PPE_BM_PORT_FC_MODE_INC * bm_port_id; 1786 1787 return regmap_set_bits(ppe_dev->regmap, reg, PPE_BM_PORT_FC_MODE_EN); 1788 } 1789 1790 /* Configure the buffer threshold for the port flow control function. */ 1791 static int ppe_config_bm(struct ppe_device *ppe_dev) 1792 { 1793 const struct ppe_bm_port_config *port_cfg; 1794 unsigned int i, bm_port_id, port_cfg_cnt; 1795 u32 reg, val, group_cfg; 1796 int ret; 1797 1798 switch (ppe_dev->type) { 1799 case IPQ9574_PPE: 1800 port_cfg = ipq9574_ppe_bm_port_config; 1801 port_cfg_cnt = ARRAY_SIZE(ipq9574_ppe_bm_port_config); 1802 group_cfg = ipq9574_ppe_bm_group_config; 1803 break; 1804 case IPQ5424_PPE: 1805 port_cfg = ipq5424_ppe_bm_port_config; 1806 port_cfg_cnt = ARRAY_SIZE(ipq5424_ppe_bm_port_config); 1807 group_cfg = ipq5424_ppe_bm_group_config; 1808 break; 1809 default: 1810 dev_err(ppe_dev->dev, "Invalid PPE type %d\n", ppe_dev->type); 1811 return -EINVAL; 1812 } 1813 1814 reg = PPE_BM_SHARED_GROUP_CFG_ADDR(ppe_dev); 1815 1816 /* Configure the allocated buffer number only for group 0. 1817 * The buffer number of group 1-3 is already cleared to 0 1818 * after PPE reset during the probe of PPE driver. 1819 */ 1820 val = FIELD_PREP(PPE_BM_SHARED_GROUP_CFG_SHARED_LIMIT, group_cfg); 1821 ret = regmap_update_bits(ppe_dev->regmap, reg, 1822 PPE_BM_SHARED_GROUP_CFG_SHARED_LIMIT, 1823 val); 1824 if (ret) 1825 goto bm_config_fail; 1826 1827 for (i = 0; i < port_cfg_cnt; i++) { 1828 for (bm_port_id = port_cfg[i].port_id_start; 1829 bm_port_id <= port_cfg[i].port_id_end; bm_port_id++) { 1830 ret = ppe_config_bm_threshold(ppe_dev, bm_port_id, 1831 port_cfg[i]); 1832 if (ret) 1833 goto bm_config_fail; 1834 } 1835 } 1836 1837 return 0; 1838 1839 bm_config_fail: 1840 dev_err(ppe_dev->dev, "PPE BM config error %d\n", ret); 1841 return ret; 1842 } 1843 1844 /* Configure PPE hardware queue depth, which is decided by the threshold 1845 * of queue. 1846 */ 1847 static int ppe_config_qm(struct ppe_device *ppe_dev) 1848 { 1849 int ret, i, group_buffer_cfg, queue_id, queue_cfg_count; 1850 const struct ppe_qm_queue_config *queue_cfg; 1851 u32 reg, multicast_queue_cfg[3]; 1852 u32 unicast_queue_cfg[4]; 1853 u32 group_cfg[3]; 1854 1855 switch (ppe_dev->type) { 1856 case IPQ9574_PPE: 1857 group_buffer_cfg = ipq9574_ppe_qm_group_config; 1858 queue_cfg = ipq9574_ppe_qm_queue_config; 1859 queue_cfg_count = ARRAY_SIZE(ipq9574_ppe_qm_queue_config); 1860 break; 1861 case IPQ5424_PPE: 1862 group_buffer_cfg = ipq5424_ppe_qm_group_config; 1863 queue_cfg = ipq5424_ppe_qm_queue_config; 1864 queue_cfg_count = ARRAY_SIZE(ipq5424_ppe_qm_queue_config); 1865 break; 1866 default: 1867 dev_err(ppe_dev->dev, "Invalid PPE type %d\n", ppe_dev->type); 1868 return -EINVAL; 1869 } 1870 1871 /* Assign the buffer number to the group 0 by default. */ 1872 reg = PPE_AC_GRP_CFG_TBL_ADDR; 1873 ret = regmap_bulk_read(ppe_dev->regmap, reg, 1874 group_cfg, ARRAY_SIZE(group_cfg)); 1875 if (ret) 1876 goto qm_config_fail; 1877 1878 PPE_AC_GRP_SET_BUF_LIMIT(group_cfg, group_buffer_cfg); 1879 1880 ret = regmap_bulk_write(ppe_dev->regmap, reg, 1881 group_cfg, ARRAY_SIZE(group_cfg)); 1882 if (ret) 1883 goto qm_config_fail; 1884 1885 for (i = 0; i < queue_cfg_count; i++) { 1886 queue_id = queue_cfg[i].queue_start; 1887 1888 /* Configure threshold for dropping packets separately for 1889 * unicast and multicast PPE queues. 1890 */ 1891 while (queue_id <= queue_cfg[i].queue_end) { 1892 if (queue_id < PPE_AC_UNICAST_QUEUE_CFG_TBL_ENTRIES) { 1893 reg = PPE_AC_UNICAST_QUEUE_CFG_TBL_ADDR + 1894 PPE_AC_UNICAST_QUEUE_CFG_TBL_INC * queue_id; 1895 1896 ret = regmap_bulk_read(ppe_dev->regmap, reg, 1897 unicast_queue_cfg, 1898 ARRAY_SIZE(unicast_queue_cfg)); 1899 if (ret) 1900 goto qm_config_fail; 1901 1902 PPE_AC_UNICAST_QUEUE_SET_EN(unicast_queue_cfg, true); 1903 PPE_AC_UNICAST_QUEUE_SET_GRP_ID(unicast_queue_cfg, 0); 1904 PPE_AC_UNICAST_QUEUE_SET_PRE_LIMIT(unicast_queue_cfg, 1905 queue_cfg[i].prealloc_buf); 1906 PPE_AC_UNICAST_QUEUE_SET_DYNAMIC(unicast_queue_cfg, 1907 queue_cfg[i].dynamic); 1908 PPE_AC_UNICAST_QUEUE_SET_WEIGHT(unicast_queue_cfg, 1909 queue_cfg[i].weight); 1910 PPE_AC_UNICAST_QUEUE_SET_THRESHOLD(unicast_queue_cfg, 1911 queue_cfg[i].ceil); 1912 PPE_AC_UNICAST_QUEUE_SET_GRN_RESUME(unicast_queue_cfg, 1913 queue_cfg[i].resume_offset); 1914 1915 ret = regmap_bulk_write(ppe_dev->regmap, reg, 1916 unicast_queue_cfg, 1917 ARRAY_SIZE(unicast_queue_cfg)); 1918 if (ret) 1919 goto qm_config_fail; 1920 } else { 1921 /* The multicast queue table is indexed from 0 for 1922 * the first multicast queue, which follows the 1923 * unicast queues. 1924 */ 1925 reg = PPE_AC_MULTICAST_QUEUE_CFG_TBL_ADDR + 1926 PPE_AC_MULTICAST_QUEUE_CFG_TBL_INC * 1927 (queue_id - PPE_AC_UNICAST_QUEUE_CFG_TBL_ENTRIES); 1928 1929 ret = regmap_bulk_read(ppe_dev->regmap, reg, 1930 multicast_queue_cfg, 1931 ARRAY_SIZE(multicast_queue_cfg)); 1932 if (ret) 1933 goto qm_config_fail; 1934 1935 PPE_AC_MULTICAST_QUEUE_SET_EN(multicast_queue_cfg, true); 1936 PPE_AC_MULTICAST_QUEUE_SET_GRN_GRP_ID(multicast_queue_cfg, 0); 1937 PPE_AC_MULTICAST_QUEUE_SET_GRN_PRE_LIMIT(multicast_queue_cfg, 1938 queue_cfg[i].prealloc_buf); 1939 PPE_AC_MULTICAST_QUEUE_SET_GRN_THRESHOLD(multicast_queue_cfg, 1940 queue_cfg[i].ceil); 1941 PPE_AC_MULTICAST_QUEUE_SET_GRN_RESUME(multicast_queue_cfg, 1942 queue_cfg[i].resume_offset); 1943 1944 ret = regmap_bulk_write(ppe_dev->regmap, reg, 1945 multicast_queue_cfg, 1946 ARRAY_SIZE(multicast_queue_cfg)); 1947 if (ret) 1948 goto qm_config_fail; 1949 } 1950 1951 /* Enable enqueue. */ 1952 reg = PPE_ENQ_OPR_TBL_ADDR + PPE_ENQ_OPR_TBL_INC * queue_id; 1953 ret = regmap_clear_bits(ppe_dev->regmap, reg, 1954 PPE_ENQ_OPR_TBL_ENQ_DISABLE); 1955 if (ret) 1956 goto qm_config_fail; 1957 1958 /* Enable dequeue. */ 1959 reg = PPE_DEQ_OPR_TBL_ADDR + PPE_DEQ_OPR_TBL_INC * queue_id; 1960 ret = regmap_clear_bits(ppe_dev->regmap, reg, 1961 PPE_DEQ_OPR_TBL_DEQ_DISABLE); 1962 if (ret) 1963 goto qm_config_fail; 1964 1965 queue_id++; 1966 } 1967 } 1968 1969 /* Enable queue counter for all PPE hardware queues. */ 1970 ret = regmap_set_bits(ppe_dev->regmap, PPE_EG_BRIDGE_CONFIG_ADDR, 1971 PPE_EG_BRIDGE_CONFIG_QUEUE_CNT_EN); 1972 if (ret) 1973 goto qm_config_fail; 1974 1975 return 0; 1976 1977 qm_config_fail: 1978 dev_err(ppe_dev->dev, "PPE QM config error %d\n", ret); 1979 return ret; 1980 } 1981 1982 static int ppe_node_scheduler_config(struct ppe_device *ppe_dev, 1983 struct ppe_scheduler_port_config config) 1984 { 1985 struct ppe_scheduler_cfg sch_cfg; 1986 int ret, i; 1987 1988 for (i = 0; i < config.loop_num; i++) { 1989 if (!config.pri_max) { 1990 /* Round robin scheduler without priority. */ 1991 sch_cfg.flow_id = config.flow_id; 1992 sch_cfg.pri = 0; 1993 sch_cfg.drr_node_id = config.drr_node_id; 1994 } else { 1995 sch_cfg.flow_id = config.flow_id + (i / config.pri_max); 1996 sch_cfg.pri = i % config.pri_max; 1997 sch_cfg.drr_node_id = config.drr_node_id + i; 1998 } 1999 2000 /* Scheduler weight, must be more than 0. */ 2001 sch_cfg.drr_node_wt = 1; 2002 /* Byte based to be scheduled. */ 2003 sch_cfg.unit_is_packet = false; 2004 /* Frame + CRC calculated. */ 2005 sch_cfg.frame_mode = PPE_SCH_WITH_FRAME_CRC; 2006 2007 ret = ppe_queue_scheduler_set(ppe_dev, config.node_id + i, 2008 config.flow_level, 2009 config.port, 2010 sch_cfg); 2011 if (ret) 2012 return ret; 2013 } 2014 2015 return 0; 2016 } 2017 2018 /* Initialize scheduler settings for PPE buffer utilization and dispatching 2019 * packet on PPE queue. 2020 */ 2021 static int ppe_config_scheduler(struct ppe_device *ppe_dev) 2022 { 2023 const struct ppe_scheduler_port_config *port_cfg; 2024 const struct ppe_scheduler_qm_config *qm_cfg; 2025 const struct ppe_scheduler_bm_config *bm_cfg; 2026 int ret, i, bm_count, qm_count, count; 2027 u32 val, reg; 2028 2029 switch (ppe_dev->type) { 2030 case IPQ9574_PPE: 2031 bm_cfg = ipq9574_ppe_sch_bm_config; 2032 bm_count = ARRAY_SIZE(ipq9574_ppe_sch_bm_config); 2033 qm_cfg = ipq9574_ppe_sch_qm_config; 2034 qm_count = ARRAY_SIZE(ipq9574_ppe_sch_qm_config); 2035 break; 2036 case IPQ5424_PPE: 2037 bm_cfg = ipq5424_ppe_sch_bm_config; 2038 bm_count = ARRAY_SIZE(ipq5424_ppe_sch_bm_config); 2039 qm_cfg = ipq5424_ppe_sch_qm_config; 2040 qm_count = ARRAY_SIZE(ipq5424_ppe_sch_qm_config); 2041 break; 2042 default: 2043 dev_err(ppe_dev->dev, "Invalid PPE type %d\n", ppe_dev->type); 2044 return -EINVAL; 2045 } 2046 2047 /* Configure the depth of BM scheduler entries. */ 2048 val = FIELD_PREP(PPE_BM_SCH_CTRL_SCH_DEPTH, bm_count); 2049 val |= FIELD_PREP(PPE_BM_SCH_CTRL_SCH_OFFSET, 0); 2050 val |= FIELD_PREP(PPE_BM_SCH_CTRL_SCH_EN, 1); 2051 2052 ret = regmap_write(ppe_dev->regmap, PPE_BM_SCH_CTRL_ADDR, val); 2053 if (ret) 2054 goto sch_config_fail; 2055 2056 /* Configure each BM scheduler entry with the valid ingress port and 2057 * egress port, the second port takes effect when the specified port 2058 * is in the inactive state. 2059 */ 2060 for (i = 0; i < bm_count; i++) { 2061 val = FIELD_PREP(PPE_BM_SCH_CFG_TBL_VALID, bm_cfg[i].valid); 2062 val |= FIELD_PREP(PPE_BM_SCH_CFG_TBL_DIR, bm_cfg[i].dir); 2063 val |= FIELD_PREP(PPE_BM_SCH_CFG_TBL_PORT_NUM, bm_cfg[i].port); 2064 val |= FIELD_PREP(PPE_BM_SCH_CFG_TBL_SECOND_PORT_VALID, 2065 bm_cfg[i].backup_port_valid); 2066 val |= FIELD_PREP(PPE_BM_SCH_CFG_TBL_SECOND_PORT, 2067 bm_cfg[i].backup_port); 2068 2069 reg = PPE_BM_SCH_CFG_TBL_ADDR + i * PPE_BM_SCH_CFG_TBL_INC; 2070 ret = regmap_write(ppe_dev->regmap, reg, val); 2071 if (ret) 2072 goto sch_config_fail; 2073 } 2074 2075 /* Configure the depth of QM scheduler entries. */ 2076 val = FIELD_PREP(PPE_PSCH_SCH_DEPTH_CFG_SCH_DEPTH, qm_count); 2077 ret = regmap_write(ppe_dev->regmap, PPE_PSCH_SCH_DEPTH_CFG_ADDR, val); 2078 if (ret) 2079 goto sch_config_fail; 2080 2081 /* Configure each QM scheduler entry with enqueue port and dequeue 2082 * port, the second port takes effect when the specified dequeue 2083 * port is in the inactive port. 2084 */ 2085 for (i = 0; i < qm_count; i++) { 2086 val = FIELD_PREP(PPE_PSCH_SCH_CFG_TBL_ENS_PORT_BITMAP, 2087 qm_cfg[i].ensch_port_bmp); 2088 val |= FIELD_PREP(PPE_PSCH_SCH_CFG_TBL_ENS_PORT, 2089 qm_cfg[i].ensch_port); 2090 val |= FIELD_PREP(PPE_PSCH_SCH_CFG_TBL_DES_PORT, 2091 qm_cfg[i].desch_port); 2092 val |= FIELD_PREP(PPE_PSCH_SCH_CFG_TBL_DES_SECOND_PORT_EN, 2093 qm_cfg[i].desch_backup_port_valid); 2094 val |= FIELD_PREP(PPE_PSCH_SCH_CFG_TBL_DES_SECOND_PORT, 2095 qm_cfg[i].desch_backup_port); 2096 2097 reg = PPE_PSCH_SCH_CFG_TBL_ADDR + i * PPE_PSCH_SCH_CFG_TBL_INC; 2098 ret = regmap_write(ppe_dev->regmap, reg, val); 2099 if (ret) 2100 goto sch_config_fail; 2101 } 2102 2103 count = ARRAY_SIZE(ppe_port_sch_config); 2104 port_cfg = ppe_port_sch_config; 2105 2106 /* Configure scheduler per PPE queue or flow. */ 2107 for (i = 0; i < count; i++) { 2108 if (port_cfg[i].port >= ppe_dev->num_ports) 2109 break; 2110 2111 ret = ppe_node_scheduler_config(ppe_dev, port_cfg[i]); 2112 if (ret) 2113 goto sch_config_fail; 2114 } 2115 2116 return 0; 2117 2118 sch_config_fail: 2119 dev_err(ppe_dev->dev, "PPE scheduler arbitration config error %d\n", ret); 2120 return ret; 2121 }; 2122 2123 /* Configure PPE queue destination of each PPE port. */ 2124 static int ppe_queue_dest_init(struct ppe_device *ppe_dev) 2125 { 2126 int ret, port_id, index, q_base, q_offset, res_start, res_end, pri_max; 2127 struct ppe_queue_ucast_dest queue_dst; 2128 2129 for (port_id = 0; port_id < ppe_dev->num_ports; port_id++) { 2130 memset(&queue_dst, 0, sizeof(queue_dst)); 2131 2132 ret = ppe_port_resource_get(ppe_dev, port_id, PPE_RES_UCAST, 2133 &res_start, &res_end); 2134 if (ret) 2135 return ret; 2136 2137 q_base = res_start; 2138 queue_dst.dest_port = port_id; 2139 2140 /* Configure queue base ID and profile ID that is same as 2141 * physical port ID. 2142 */ 2143 ret = ppe_queue_ucast_base_set(ppe_dev, queue_dst, 2144 q_base, port_id); 2145 if (ret) 2146 return ret; 2147 2148 /* Queue priority range supported by each PPE port */ 2149 ret = ppe_port_resource_get(ppe_dev, port_id, PPE_RES_L0_NODE, 2150 &res_start, &res_end); 2151 if (ret) 2152 return ret; 2153 2154 pri_max = res_end - res_start; 2155 2156 /* Redirect ARP reply packet with the max priority on CPU port, 2157 * which keeps the ARP reply directed to CPU (CPU code is 101) 2158 * with highest priority queue of EDMA. 2159 */ 2160 if (port_id == 0) { 2161 memset(&queue_dst, 0, sizeof(queue_dst)); 2162 2163 queue_dst.cpu_code_en = true; 2164 queue_dst.cpu_code = 101; 2165 ret = ppe_queue_ucast_base_set(ppe_dev, queue_dst, 2166 q_base + pri_max, 2167 0); 2168 if (ret) 2169 return ret; 2170 } 2171 2172 /* Initialize the queue offset of internal priority. */ 2173 for (index = 0; index < PPE_QUEUE_INTER_PRI_NUM; index++) { 2174 q_offset = index > pri_max ? pri_max : index; 2175 2176 ret = ppe_queue_ucast_offset_pri_set(ppe_dev, port_id, 2177 index, q_offset); 2178 if (ret) 2179 return ret; 2180 } 2181 2182 /* Initialize the queue offset of RSS hash as 0 to avoid the 2183 * random hardware value that will lead to the unexpected 2184 * destination queue generated. 2185 */ 2186 for (index = 0; index < PPE_QUEUE_HASH_NUM; index++) { 2187 ret = ppe_queue_ucast_offset_hash_set(ppe_dev, port_id, 2188 index, 0); 2189 if (ret) 2190 return ret; 2191 } 2192 } 2193 2194 return 0; 2195 } 2196 2197 /* Initialize the service code 1 used by CPU port. */ 2198 static int ppe_servcode_init(struct ppe_device *ppe_dev) 2199 { 2200 struct ppe_sc_cfg sc_cfg = {}; 2201 2202 bitmap_zero(sc_cfg.bitmaps.counter, PPE_SC_BYPASS_COUNTER_SIZE); 2203 bitmap_zero(sc_cfg.bitmaps.tunnel, PPE_SC_BYPASS_TUNNEL_SIZE); 2204 2205 bitmap_fill(sc_cfg.bitmaps.ingress, PPE_SC_BYPASS_INGRESS_SIZE); 2206 clear_bit(PPE_SC_BYPASS_INGRESS_FAKE_MAC_HEADER, sc_cfg.bitmaps.ingress); 2207 clear_bit(PPE_SC_BYPASS_INGRESS_SERVICE_CODE, sc_cfg.bitmaps.ingress); 2208 clear_bit(PPE_SC_BYPASS_INGRESS_FAKE_L2_PROTO, sc_cfg.bitmaps.ingress); 2209 2210 bitmap_fill(sc_cfg.bitmaps.egress, PPE_SC_BYPASS_EGRESS_SIZE); 2211 clear_bit(PPE_SC_BYPASS_EGRESS_ACL_POST_ROUTING_CHECK, sc_cfg.bitmaps.egress); 2212 2213 return ppe_sc_config_set(ppe_dev, PPE_EDMA_SC_BYPASS_ID, sc_cfg); 2214 } 2215 2216 /* Initialize PPE port configurations. */ 2217 static int ppe_port_config_init(struct ppe_device *ppe_dev) 2218 { 2219 u32 reg, val, mru_mtu_val[3]; 2220 int i, ret; 2221 2222 /* MTU and MRU settings are not required for CPU port 0. */ 2223 for (i = 1; i < ppe_dev->num_ports; i++) { 2224 /* Enable Ethernet port counter */ 2225 ret = ppe_counter_enable_set(ppe_dev, i); 2226 if (ret) 2227 return ret; 2228 2229 reg = PPE_MRU_MTU_CTRL_TBL_ADDR + PPE_MRU_MTU_CTRL_TBL_INC * i; 2230 ret = regmap_bulk_read(ppe_dev->regmap, reg, 2231 mru_mtu_val, ARRAY_SIZE(mru_mtu_val)); 2232 if (ret) 2233 return ret; 2234 2235 /* Drop the packet when the packet size is more than the MTU 2236 * and redirect the packet to the CPU port when the received 2237 * packet size is more than the MRU of the physical interface. 2238 */ 2239 PPE_MRU_MTU_CTRL_SET_MRU_CMD(mru_mtu_val, PPE_ACTION_REDIRECT_TO_CPU); 2240 PPE_MRU_MTU_CTRL_SET_MTU_CMD(mru_mtu_val, PPE_ACTION_DROP); 2241 ret = regmap_bulk_write(ppe_dev->regmap, reg, 2242 mru_mtu_val, ARRAY_SIZE(mru_mtu_val)); 2243 if (ret) 2244 return ret; 2245 2246 reg = PPE_MC_MTU_CTRL_TBL_ADDR + PPE_MC_MTU_CTRL_TBL_INC * i; 2247 val = FIELD_PREP(PPE_MC_MTU_CTRL_TBL_MTU_CMD, PPE_ACTION_DROP); 2248 ret = regmap_update_bits(ppe_dev->regmap, reg, 2249 PPE_MC_MTU_CTRL_TBL_MTU_CMD, 2250 val); 2251 if (ret) 2252 return ret; 2253 } 2254 2255 /* Enable CPU port counters. */ 2256 return ppe_counter_enable_set(ppe_dev, 0); 2257 } 2258 2259 /* Initialize the PPE RSS configuration for IPv4 and IPv6 packet receive. 2260 * RSS settings are to calculate the random RSS hash value generated during 2261 * packet receive. This hash is then used to generate the queue offset used 2262 * to determine the queue used to transmit the packet. 2263 */ 2264 static int ppe_rss_hash_init(struct ppe_device *ppe_dev) 2265 { 2266 u16 fins[PPE_RSS_HASH_TUPLES] = { 0x205, 0x264, 0x227, 0x245, 0x201 }; 2267 u8 ips[PPE_RSS_HASH_IP_LENGTH] = { 0x13, 0xb, 0x13, 0xb }; 2268 struct ppe_rss_hash_cfg hash_cfg; 2269 int i, ret; 2270 2271 hash_cfg.hash_seed = get_random_u32(); 2272 hash_cfg.hash_mask = 0xfff; 2273 2274 /* Use 5 tuple as RSS hash key for the first fragment of TCP, UDP 2275 * and UDP-Lite packets. 2276 */ 2277 hash_cfg.hash_fragment_mode = false; 2278 2279 /* The final common seed configs used to calculate the RSS has value, 2280 * which is available for both IPv4 and IPv6 packet. 2281 */ 2282 for (i = 0; i < ARRAY_SIZE(fins); i++) { 2283 hash_cfg.hash_fin_inner[i] = fins[i] & 0x1f; 2284 hash_cfg.hash_fin_outer[i] = fins[i] >> 5; 2285 } 2286 2287 /* RSS seeds for IP protocol, L4 destination & source port and 2288 * destination & source IP used to calculate the RSS hash value. 2289 */ 2290 hash_cfg.hash_protocol_mix = 0x13; 2291 hash_cfg.hash_dport_mix = 0xb; 2292 hash_cfg.hash_sport_mix = 0x13; 2293 hash_cfg.hash_dip_mix[0] = 0xb; 2294 hash_cfg.hash_sip_mix[0] = 0x13; 2295 2296 /* Configure RSS seed configs for IPv4 packet. */ 2297 ret = ppe_rss_hash_config_set(ppe_dev, PPE_RSS_HASH_MODE_IPV4, hash_cfg); 2298 if (ret) 2299 return ret; 2300 2301 for (i = 0; i < ARRAY_SIZE(ips); i++) { 2302 hash_cfg.hash_sip_mix[i] = ips[i]; 2303 hash_cfg.hash_dip_mix[i] = ips[i]; 2304 } 2305 2306 /* Configure RSS seed configs for IPv6 packet. */ 2307 return ppe_rss_hash_config_set(ppe_dev, PPE_RSS_HASH_MODE_IPV6, hash_cfg); 2308 } 2309 2310 /* Initialize mapping between PPE queues assigned to CPU port 0 2311 * to Ethernet DMA ring 0. 2312 */ 2313 static int ppe_queues_to_ring_init(struct ppe_device *ppe_dev) 2314 { 2315 u32 queue_bmap[PPE_RING_TO_QUEUE_BITMAP_WORD_CNT] = {}; 2316 int ret, queue_id, queue_max; 2317 2318 ret = ppe_port_resource_get(ppe_dev, 0, PPE_RES_UCAST, 2319 &queue_id, &queue_max); 2320 if (ret) 2321 return ret; 2322 2323 for (; queue_id <= queue_max; queue_id++) 2324 queue_bmap[queue_id / 32] |= BIT_MASK(queue_id % 32); 2325 2326 return ppe_ring_queue_map_set(ppe_dev, 0, queue_bmap); 2327 } 2328 2329 /* Initialize PPE bridge settings to only enable L2 frame receive and 2330 * transmit between CPU port and PPE Ethernet ports. 2331 */ 2332 static int ppe_bridge_init(struct ppe_device *ppe_dev) 2333 { 2334 u32 reg, mask, port_cfg[4], vsi_cfg[2]; 2335 int ret, i; 2336 2337 /* Configure the following settings for CPU port0: 2338 * a.) Enable Bridge TX 2339 * b.) Disable FDB new address learning 2340 * c.) Disable station move address learning 2341 */ 2342 mask = PPE_PORT_BRIDGE_TXMAC_EN; 2343 mask |= PPE_PORT_BRIDGE_NEW_LRN_EN; 2344 mask |= PPE_PORT_BRIDGE_STA_MOVE_LRN_EN; 2345 ret = regmap_update_bits(ppe_dev->regmap, 2346 PPE_PORT_BRIDGE_CTRL_ADDR, 2347 mask, 2348 PPE_PORT_BRIDGE_TXMAC_EN); 2349 if (ret) 2350 return ret; 2351 2352 for (i = 1; i < ppe_dev->num_ports; i++) { 2353 /* Enable invalid VSI forwarding for all the physical ports 2354 * to CPU port0, in case no VSI is assigned to the physical 2355 * port. 2356 */ 2357 reg = PPE_L2_VP_PORT_TBL_ADDR + PPE_L2_VP_PORT_TBL_INC * i; 2358 ret = regmap_bulk_read(ppe_dev->regmap, reg, 2359 port_cfg, ARRAY_SIZE(port_cfg)); 2360 2361 if (ret) 2362 return ret; 2363 2364 PPE_L2_PORT_SET_INVALID_VSI_FWD_EN(port_cfg, true); 2365 PPE_L2_PORT_SET_DST_INFO(port_cfg, 0); 2366 2367 ret = regmap_bulk_write(ppe_dev->regmap, reg, 2368 port_cfg, ARRAY_SIZE(port_cfg)); 2369 if (ret) 2370 return ret; 2371 } 2372 2373 for (i = 0; i < PPE_VSI_TBL_ENTRIES; i++) { 2374 /* Set the VSI forward membership to include only CPU port0. 2375 * FDB learning and forwarding take place only after switchdev 2376 * is supported later to create the VSI and join the physical 2377 * ports to the VSI port member. 2378 */ 2379 reg = PPE_VSI_TBL_ADDR + PPE_VSI_TBL_INC * i; 2380 ret = regmap_bulk_read(ppe_dev->regmap, reg, 2381 vsi_cfg, ARRAY_SIZE(vsi_cfg)); 2382 if (ret) 2383 return ret; 2384 2385 PPE_VSI_SET_MEMBER_PORT_BITMAP(vsi_cfg, BIT(0)); 2386 PPE_VSI_SET_UUC_BITMAP(vsi_cfg, BIT(0)); 2387 PPE_VSI_SET_UMC_BITMAP(vsi_cfg, BIT(0)); 2388 PPE_VSI_SET_BC_BITMAP(vsi_cfg, BIT(0)); 2389 PPE_VSI_SET_NEW_ADDR_LRN_EN(vsi_cfg, true); 2390 PPE_VSI_SET_NEW_ADDR_FWD_CMD(vsi_cfg, PPE_ACTION_FORWARD); 2391 PPE_VSI_SET_STATION_MOVE_LRN_EN(vsi_cfg, true); 2392 PPE_VSI_SET_STATION_MOVE_FWD_CMD(vsi_cfg, PPE_ACTION_FORWARD); 2393 2394 ret = regmap_bulk_write(ppe_dev->regmap, reg, 2395 vsi_cfg, ARRAY_SIZE(vsi_cfg)); 2396 if (ret) 2397 return ret; 2398 } 2399 2400 return 0; 2401 } 2402 2403 int ppe_hw_config(struct ppe_device *ppe_dev) 2404 { 2405 int ret; 2406 2407 ret = ppe_config_bm(ppe_dev); 2408 if (ret) 2409 return ret; 2410 2411 ret = ppe_config_qm(ppe_dev); 2412 if (ret) 2413 return ret; 2414 2415 ret = ppe_config_scheduler(ppe_dev); 2416 if (ret) 2417 return ret; 2418 2419 ret = ppe_queue_dest_init(ppe_dev); 2420 if (ret) 2421 return ret; 2422 2423 ret = ppe_servcode_init(ppe_dev); 2424 if (ret) 2425 return ret; 2426 2427 ret = ppe_port_config_init(ppe_dev); 2428 if (ret) 2429 return ret; 2430 2431 ret = ppe_rss_hash_init(ppe_dev); 2432 if (ret) 2433 return ret; 2434 2435 ret = ppe_queues_to_ring_init(ppe_dev); 2436 if (ret) 2437 return ret; 2438 2439 return ppe_bridge_init(ppe_dev); 2440 } 2441