1 // SPDX-License-Identifier: GPL-2.0 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 8 #include "Mp_Precomp.h" 9 10 /* defines */ 11 #define HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(val) \ 12 do { \ 13 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, val); \ 14 pCoexDm->psTdmaDuAdjType = val; \ 15 } while (0) 16 17 /* Global variables, these are static variables */ 18 static struct coex_dm_8723b_2ant GLCoexDm8723b2Ant; 19 static struct coex_dm_8723b_2ant *pCoexDm = &GLCoexDm8723b2Ant; 20 static struct coex_sta_8723b_2ant GLCoexSta8723b2Ant; 21 static struct coex_sta_8723b_2ant *pCoexSta = &GLCoexSta8723b2Ant; 22 23 /* local function start with halbtc8723b2ant_ */ 24 static u8 halbtc8723b2ant_BtRssiState( 25 u8 levelNum, u8 rssiThresh, u8 rssiThresh1 26 ) 27 { 28 s32 btRssi = 0; 29 u8 btRssiState = pCoexSta->preBtRssiState; 30 31 btRssi = pCoexSta->btRssi; 32 33 if (levelNum == 2) { 34 if ( 35 (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || 36 (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW) 37 ) { 38 if (btRssi >= (rssiThresh + BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) { 39 btRssiState = BTC_RSSI_STATE_HIGH; 40 } else { 41 btRssiState = BTC_RSSI_STATE_STAY_LOW; 42 } 43 } else { 44 if (btRssi < rssiThresh) { 45 btRssiState = BTC_RSSI_STATE_LOW; 46 } else { 47 btRssiState = BTC_RSSI_STATE_STAY_HIGH; 48 } 49 } 50 } else if (levelNum == 3) { 51 if (rssiThresh > rssiThresh1) { 52 return pCoexSta->preBtRssiState; 53 } 54 55 if ( 56 (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || 57 (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW) 58 ) { 59 if (btRssi >= (rssiThresh + BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) { 60 btRssiState = BTC_RSSI_STATE_MEDIUM; 61 } else { 62 btRssiState = BTC_RSSI_STATE_STAY_LOW; 63 } 64 } else if ( 65 (pCoexSta->preBtRssiState == BTC_RSSI_STATE_MEDIUM) || 66 (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_MEDIUM) 67 ) { 68 if (btRssi >= (rssiThresh1 + BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) { 69 btRssiState = BTC_RSSI_STATE_HIGH; 70 } else if (btRssi < rssiThresh) { 71 btRssiState = BTC_RSSI_STATE_LOW; 72 } else { 73 btRssiState = BTC_RSSI_STATE_STAY_MEDIUM; 74 } 75 } else { 76 if (btRssi < rssiThresh1) { 77 btRssiState = BTC_RSSI_STATE_MEDIUM; 78 } else { 79 btRssiState = BTC_RSSI_STATE_STAY_HIGH; 80 } 81 } 82 } 83 84 pCoexSta->preBtRssiState = btRssiState; 85 86 return btRssiState; 87 } 88 89 static u8 halbtc8723b2ant_WifiRssiState( 90 struct btc_coexist *pBtCoexist, 91 u8 index, 92 u8 levelNum, 93 u8 rssiThresh, 94 u8 rssiThresh1 95 ) 96 { 97 s32 wifiRssi = 0; 98 u8 wifiRssiState = pCoexSta->preWifiRssiState[index]; 99 100 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); 101 102 if (levelNum == 2) { 103 if ( 104 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || 105 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW) 106 ) { 107 if (wifiRssi >= (rssiThresh + BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) { 108 wifiRssiState = BTC_RSSI_STATE_HIGH; 109 } else { 110 wifiRssiState = BTC_RSSI_STATE_STAY_LOW; 111 } 112 } else { 113 if (wifiRssi < rssiThresh) { 114 wifiRssiState = BTC_RSSI_STATE_LOW; 115 } else { 116 wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; 117 } 118 } 119 } else if (levelNum == 3) { 120 if (rssiThresh > rssiThresh1) { 121 return pCoexSta->preWifiRssiState[index]; 122 } 123 124 if ( 125 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || 126 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW) 127 ) { 128 if (wifiRssi >= (rssiThresh + BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) { 129 wifiRssiState = BTC_RSSI_STATE_MEDIUM; 130 } else { 131 wifiRssiState = BTC_RSSI_STATE_STAY_LOW; 132 } 133 } else if ( 134 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) || 135 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM) 136 ) { 137 if (wifiRssi >= (rssiThresh1 + BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) { 138 wifiRssiState = BTC_RSSI_STATE_HIGH; 139 } else if (wifiRssi < rssiThresh) { 140 wifiRssiState = BTC_RSSI_STATE_LOW; 141 } else { 142 wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM; 143 } 144 } else { 145 if (wifiRssi < rssiThresh1) { 146 wifiRssiState = BTC_RSSI_STATE_MEDIUM; 147 } else { 148 wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; 149 } 150 } 151 } 152 153 pCoexSta->preWifiRssiState[index] = wifiRssiState; 154 155 return wifiRssiState; 156 } 157 158 static void halbtc8723b2ant_LimitedRx( 159 struct btc_coexist *pBtCoexist, 160 bool bForceExec, 161 bool bRejApAggPkt, 162 bool bBtCtrlAggBufSize, 163 u8 aggBufSize 164 ) 165 { 166 bool bRejectRxAgg = bRejApAggPkt; 167 bool bBtCtrlRxAggSize = bBtCtrlAggBufSize; 168 u8 rxAggSize = aggBufSize; 169 170 /* */ 171 /* Rx Aggregation related setting */ 172 /* */ 173 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejectRxAgg); 174 /* decide BT control aggregation buf size or not */ 175 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, &bBtCtrlRxAggSize); 176 /* aggregation buf size, only work when BT control Rx aggregation size. */ 177 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_AGG_BUF_SIZE, &rxAggSize); 178 /* real update aggregation setting */ 179 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); 180 } 181 182 static void halbtc8723b2ant_QueryBtInfo(struct btc_coexist *pBtCoexist) 183 { 184 u8 H2C_Parameter[1] = {0}; 185 186 pCoexSta->bC2hBtInfoReqSent = true; 187 188 H2C_Parameter[0] |= BIT(0); /* trigger */ 189 190 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x61, 1, H2C_Parameter); 191 } 192 193 static bool halbtc8723b2ant_IsWifiStatusChanged(struct btc_coexist *pBtCoexist) 194 { 195 static bool bPreWifiBusy, bPreUnder4way, bPreBtHsOn; 196 bool bWifiBusy = false, bUnder4way = false, bBtHsOn = false; 197 bool bWifiConnected = false; 198 199 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); 200 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); 201 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); 202 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way); 203 204 if (bWifiConnected) { 205 if (bWifiBusy != bPreWifiBusy) { 206 bPreWifiBusy = bWifiBusy; 207 return true; 208 } 209 210 if (bUnder4way != bPreUnder4way) { 211 bPreUnder4way = bUnder4way; 212 return true; 213 } 214 215 if (bBtHsOn != bPreBtHsOn) { 216 bPreBtHsOn = bBtHsOn; 217 return true; 218 } 219 } 220 221 return false; 222 } 223 224 static void halbtc8723b2ant_UpdateBtLinkInfo(struct btc_coexist *pBtCoexist) 225 { 226 struct btc_bt_link_info *pBtLinkInfo = &pBtCoexist->btLinkInfo; 227 bool bBtHsOn = false; 228 229 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); 230 231 pBtLinkInfo->bBtLinkExist = pCoexSta->bBtLinkExist; 232 pBtLinkInfo->bScoExist = pCoexSta->bScoExist; 233 pBtLinkInfo->bA2dpExist = pCoexSta->bA2dpExist; 234 pBtLinkInfo->bPanExist = pCoexSta->bPanExist; 235 pBtLinkInfo->bHidExist = pCoexSta->bHidExist; 236 237 /* work around for HS mode. */ 238 if (bBtHsOn) { 239 pBtLinkInfo->bPanExist = true; 240 pBtLinkInfo->bBtLinkExist = true; 241 } 242 243 /* check if Sco only */ 244 if ( 245 pBtLinkInfo->bScoExist && 246 !pBtLinkInfo->bA2dpExist && 247 !pBtLinkInfo->bPanExist && 248 !pBtLinkInfo->bHidExist 249 ) 250 pBtLinkInfo->bScoOnly = true; 251 else 252 pBtLinkInfo->bScoOnly = false; 253 254 /* check if A2dp only */ 255 if ( 256 !pBtLinkInfo->bScoExist && 257 pBtLinkInfo->bA2dpExist && 258 !pBtLinkInfo->bPanExist && 259 !pBtLinkInfo->bHidExist 260 ) 261 pBtLinkInfo->bA2dpOnly = true; 262 else 263 pBtLinkInfo->bA2dpOnly = false; 264 265 /* check if Pan only */ 266 if ( 267 !pBtLinkInfo->bScoExist && 268 !pBtLinkInfo->bA2dpExist && 269 pBtLinkInfo->bPanExist && 270 !pBtLinkInfo->bHidExist 271 ) 272 pBtLinkInfo->bPanOnly = true; 273 else 274 pBtLinkInfo->bPanOnly = false; 275 276 /* check if Hid only */ 277 if ( 278 !pBtLinkInfo->bScoExist && 279 !pBtLinkInfo->bA2dpExist && 280 !pBtLinkInfo->bPanExist && 281 pBtLinkInfo->bHidExist 282 ) 283 pBtLinkInfo->bHidOnly = true; 284 else 285 pBtLinkInfo->bHidOnly = false; 286 } 287 288 static u8 halbtc8723b2ant_ActionAlgorithm(struct btc_coexist *pBtCoexist) 289 { 290 struct btc_bt_link_info *pBtLinkInfo = &pBtCoexist->btLinkInfo; 291 bool bBtHsOn = false; 292 u8 algorithm = BT_8723B_2ANT_COEX_ALGO_UNDEFINED; 293 u8 numOfDiffProfile = 0; 294 295 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); 296 297 if (!pBtLinkInfo->bBtLinkExist) 298 return algorithm; 299 300 if (pBtLinkInfo->bScoExist) 301 numOfDiffProfile++; 302 303 if (pBtLinkInfo->bHidExist) 304 numOfDiffProfile++; 305 306 if (pBtLinkInfo->bPanExist) 307 numOfDiffProfile++; 308 309 if (pBtLinkInfo->bA2dpExist) 310 numOfDiffProfile++; 311 312 if (numOfDiffProfile == 1) { 313 if (pBtLinkInfo->bScoExist) { 314 algorithm = BT_8723B_2ANT_COEX_ALGO_SCO; 315 } else { 316 if (pBtLinkInfo->bHidExist) { 317 algorithm = BT_8723B_2ANT_COEX_ALGO_HID; 318 } else if (pBtLinkInfo->bA2dpExist) { 319 algorithm = BT_8723B_2ANT_COEX_ALGO_A2DP; 320 } else if (pBtLinkInfo->bPanExist) { 321 if (bBtHsOn) { 322 algorithm = BT_8723B_2ANT_COEX_ALGO_PANHS; 323 } else { 324 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR; 325 } 326 } 327 } 328 } else if (numOfDiffProfile == 2) { 329 if (pBtLinkInfo->bScoExist) { 330 if (pBtLinkInfo->bHidExist) { 331 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; 332 } else if (pBtLinkInfo->bA2dpExist) { 333 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; 334 } else if (pBtLinkInfo->bPanExist) { 335 if (bBtHsOn) { 336 algorithm = BT_8723B_2ANT_COEX_ALGO_SCO; 337 } else { 338 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; 339 } 340 } 341 } else { 342 if ( 343 pBtLinkInfo->bHidExist && 344 pBtLinkInfo->bA2dpExist 345 ) { 346 algorithm = BT_8723B_2ANT_COEX_ALGO_HID_A2DP; 347 } else if ( 348 pBtLinkInfo->bHidExist && 349 pBtLinkInfo->bPanExist 350 ) { 351 if (bBtHsOn) { 352 algorithm = BT_8723B_2ANT_COEX_ALGO_HID; 353 } else { 354 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; 355 } 356 } else if ( 357 pBtLinkInfo->bPanExist && 358 pBtLinkInfo->bA2dpExist 359 ) { 360 if (bBtHsOn) { 361 algorithm = BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS; 362 } else { 363 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP; 364 } 365 } 366 } 367 } else if (numOfDiffProfile == 3) { 368 if (pBtLinkInfo->bScoExist) { 369 if ( 370 pBtLinkInfo->bHidExist && 371 pBtLinkInfo->bA2dpExist 372 ) { 373 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; 374 } else if ( 375 pBtLinkInfo->bHidExist && 376 pBtLinkInfo->bPanExist 377 ) { 378 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; 379 } else if ( 380 pBtLinkInfo->bPanExist && 381 pBtLinkInfo->bA2dpExist 382 ) { 383 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; 384 } 385 } else { 386 if ( 387 pBtLinkInfo->bHidExist && 388 pBtLinkInfo->bPanExist && 389 pBtLinkInfo->bA2dpExist 390 ) { 391 if (bBtHsOn) { 392 algorithm = BT_8723B_2ANT_COEX_ALGO_HID_A2DP; 393 } else { 394 algorithm = BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR; 395 } 396 } 397 } 398 } else if (numOfDiffProfile >= 3) { 399 if (pBtLinkInfo->bScoExist) { 400 if ( 401 pBtLinkInfo->bHidExist && 402 pBtLinkInfo->bPanExist && 403 pBtLinkInfo->bA2dpExist 404 ) { 405 if (bBtHsOn) { 406 } else { 407 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; 408 } 409 } 410 } 411 } 412 413 return algorithm; 414 } 415 416 static void halbtc8723b2ant_SetFwDacSwingLevel( 417 struct btc_coexist *pBtCoexist, u8 dacSwingLvl 418 ) 419 { 420 u8 H2C_Parameter[1] = {0}; 421 422 /* There are several type of dacswing */ 423 /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ 424 H2C_Parameter[0] = dacSwingLvl; 425 426 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x64, 1, H2C_Parameter); 427 } 428 429 static void halbtc8723b2ant_SetFwDecBtPwr( 430 struct btc_coexist *pBtCoexist, u8 decBtPwrLvl 431 ) 432 { 433 u8 H2C_Parameter[1] = {0}; 434 435 H2C_Parameter[0] = decBtPwrLvl; 436 437 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x62, 1, H2C_Parameter); 438 } 439 440 static void halbtc8723b2ant_DecBtPwr( 441 struct btc_coexist *pBtCoexist, bool bForceExec, u8 decBtPwrLvl 442 ) 443 { 444 pCoexDm->curBtDecPwrLvl = decBtPwrLvl; 445 446 if (!bForceExec) { 447 if (pCoexDm->preBtDecPwrLvl == pCoexDm->curBtDecPwrLvl) 448 return; 449 } 450 halbtc8723b2ant_SetFwDecBtPwr(pBtCoexist, pCoexDm->curBtDecPwrLvl); 451 452 pCoexDm->preBtDecPwrLvl = pCoexDm->curBtDecPwrLvl; 453 } 454 455 static void halbtc8723b2ant_FwDacSwingLvl( 456 struct btc_coexist *pBtCoexist, bool bForceExec, u8 fwDacSwingLvl 457 ) 458 { 459 pCoexDm->curFwDacSwingLvl = fwDacSwingLvl; 460 461 if (!bForceExec) { 462 if (pCoexDm->preFwDacSwingLvl == pCoexDm->curFwDacSwingLvl) 463 return; 464 } 465 466 halbtc8723b2ant_SetFwDacSwingLevel(pBtCoexist, pCoexDm->curFwDacSwingLvl); 467 468 pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl; 469 } 470 471 static void halbtc8723b2ant_SetSwRfRxLpfCorner( 472 struct btc_coexist *pBtCoexist, 473 bool bRxRfShrinkOn 474 ) 475 { 476 if (bRxRfShrinkOn) { 477 /* Shrink RF Rx LPF corner */ 478 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xffffc); 479 } else { 480 /* Resume RF Rx LPF corner */ 481 /* After initialized, we can use pCoexDm->btRf0x1eBackup */ 482 if (pBtCoexist->bInitilized) { 483 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup); 484 } 485 } 486 } 487 488 static void halbtc8723b2ant_RfShrink( 489 struct btc_coexist *pBtCoexist, bool bForceExec, bool bRxRfShrinkOn 490 ) 491 { 492 pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn; 493 494 if (!bForceExec) { 495 if (pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink) 496 return; 497 } 498 halbtc8723b2ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink); 499 500 pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink; 501 } 502 503 static void halbtc8723b2ant_SetSwPenaltyTxRateAdaptive( 504 struct btc_coexist *pBtCoexist, bool bLowPenaltyRa 505 ) 506 { 507 u8 H2C_Parameter[6] = {0}; 508 509 H2C_Parameter[0] = 0x6; /* opCode, 0x6 = Retry_Penalty */ 510 511 if (bLowPenaltyRa) { 512 H2C_Parameter[1] |= BIT(0); 513 H2C_Parameter[2] = 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ 514 H2C_Parameter[3] = 0xf7; /* MCS7 or OFDM54 */ 515 H2C_Parameter[4] = 0xf8; /* MCS6 or OFDM48 */ 516 H2C_Parameter[5] = 0xf9; /* MCS5 or OFDM36 */ 517 } 518 519 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x69, 6, H2C_Parameter); 520 } 521 522 static void halbtc8723b2ant_LowPenaltyRa( 523 struct btc_coexist *pBtCoexist, bool bForceExec, bool bLowPenaltyRa 524 ) 525 { 526 /* return; */ 527 pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; 528 529 if (!bForceExec) { 530 if (pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) 531 return; 532 } 533 halbtc8723b2ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); 534 535 pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; 536 } 537 538 static void halbtc8723b2ant_SetDacSwingReg(struct btc_coexist *pBtCoexist, u32 level) 539 { 540 u8 val = (u8)level; 541 542 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x883, 0x3e, val); 543 } 544 545 static void halbtc8723b2ant_SetSwFullTimeDacSwing( 546 struct btc_coexist *pBtCoexist, bool bSwDacSwingOn, u32 swDacSwingLvl 547 ) 548 { 549 if (bSwDacSwingOn) 550 halbtc8723b2ant_SetDacSwingReg(pBtCoexist, swDacSwingLvl); 551 else 552 halbtc8723b2ant_SetDacSwingReg(pBtCoexist, 0x18); 553 } 554 555 static void halbtc8723b2ant_DacSwing( 556 struct btc_coexist *pBtCoexist, 557 bool bForceExec, 558 bool bDacSwingOn, 559 u32 dacSwingLvl 560 ) 561 { 562 pCoexDm->bCurDacSwingOn = bDacSwingOn; 563 pCoexDm->curDacSwingLvl = dacSwingLvl; 564 565 if (!bForceExec) { 566 if ((pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) && 567 (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl)) 568 return; 569 } 570 mdelay(30); 571 halbtc8723b2ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl); 572 573 pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn; 574 pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl; 575 } 576 577 static void halbtc8723b2ant_SetAgcTable( 578 struct btc_coexist *pBtCoexist, bool bAgcTableEn 579 ) 580 { 581 u8 rssiAdjustVal = 0; 582 583 /* BB AGC Gain Table */ 584 if (bAgcTableEn) { 585 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6e1A0001); 586 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6d1B0001); 587 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6c1C0001); 588 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6b1D0001); 589 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6a1E0001); 590 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x691F0001); 591 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x68200001); 592 } else { 593 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xaa1A0001); 594 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa91B0001); 595 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa81C0001); 596 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa71D0001); 597 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa61E0001); 598 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa51F0001); 599 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa4200001); 600 } 601 602 /* RF Gain */ 603 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000); 604 if (bAgcTableEn) { 605 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x38fff); 606 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x38ffe); 607 } else { 608 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x380c3); 609 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x28ce6); 610 } 611 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xef, 0xfffff, 0x0); 612 613 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xed, 0xfffff, 0x1); 614 if (bAgcTableEn) { 615 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x38fff); 616 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x38ffe); 617 } else { 618 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x380c3); 619 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x28ce6); 620 } 621 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xed, 0xfffff, 0x0); 622 623 /* set rssiAdjustVal for wifi module. */ 624 if (bAgcTableEn) 625 rssiAdjustVal = 8; 626 627 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal); 628 } 629 630 static void halbtc8723b2ant_AgcTable( 631 struct btc_coexist *pBtCoexist, bool bForceExec, bool bAgcTableEn 632 ) 633 { 634 pCoexDm->bCurAgcTableEn = bAgcTableEn; 635 636 if (!bForceExec) { 637 if (pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn) 638 return; 639 } 640 halbtc8723b2ant_SetAgcTable(pBtCoexist, bAgcTableEn); 641 642 pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn; 643 } 644 645 static void halbtc8723b2ant_SetCoexTable( 646 struct btc_coexist *pBtCoexist, 647 u32 val0x6c0, 648 u32 val0x6c4, 649 u32 val0x6c8, 650 u8 val0x6cc 651 ) 652 { 653 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, val0x6c0); 654 655 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4); 656 657 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); 658 659 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, val0x6cc); 660 } 661 662 static void halbtc8723b2ant_CoexTable( 663 struct btc_coexist *pBtCoexist, 664 bool bForceExec, 665 u32 val0x6c0, 666 u32 val0x6c4, 667 u32 val0x6c8, 668 u8 val0x6cc 669 ) 670 { 671 pCoexDm->curVal0x6c0 = val0x6c0; 672 pCoexDm->curVal0x6c4 = val0x6c4; 673 pCoexDm->curVal0x6c8 = val0x6c8; 674 pCoexDm->curVal0x6cc = val0x6cc; 675 676 if (!bForceExec) { 677 if ( 678 (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) && 679 (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) && 680 (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && 681 (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) 682 ) 683 return; 684 } 685 halbtc8723b2ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c4, val0x6c8, val0x6cc); 686 687 pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0; 688 pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4; 689 pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; 690 pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; 691 } 692 693 static void halbtc8723b2ant_CoexTableWithType( 694 struct btc_coexist *pBtCoexist, bool bForceExec, u8 type 695 ) 696 { 697 switch (type) { 698 case 0: 699 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x55555555, 0xffff, 0x3); 700 break; 701 case 1: 702 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x5afa5afa, 0xffff, 0x3); 703 break; 704 case 2: 705 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x5a5a5a5a, 0x5a5a5a5a, 0xffff, 0x3); 706 break; 707 case 3: 708 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0xaaaaaaaa, 0xaaaaaaaa, 0xffff, 0x3); 709 break; 710 case 4: 711 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0xffffffff, 0xffffffff, 0xffff, 0x3); 712 break; 713 case 5: 714 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x5fff5fff, 0x5fff5fff, 0xffff, 0x3); 715 break; 716 case 6: 717 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55ff55ff, 0x5a5a5a5a, 0xffff, 0x3); 718 break; 719 case 7: 720 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55ff55ff, 0xfafafafa, 0xffff, 0x3); 721 break; 722 case 8: 723 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x5aea5aea, 0x5aea5aea, 0xffff, 0x3); 724 break; 725 case 9: 726 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55ff55ff, 0x5aea5aea, 0xffff, 0x3); 727 break; 728 case 10: 729 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55ff55ff, 0x5aff5aff, 0xffff, 0x3); 730 break; 731 case 11: 732 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55ff55ff, 0x5a5f5a5f, 0xffff, 0x3); 733 break; 734 case 12: 735 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55ff55ff, 0x5f5f5f5f, 0xffff, 0x3); 736 break; 737 default: 738 break; 739 } 740 } 741 742 static void halbtc8723b2ant_SetFwIgnoreWlanAct( 743 struct btc_coexist *pBtCoexist, bool bEnable 744 ) 745 { 746 u8 H2C_Parameter[1] = {0}; 747 748 if (bEnable) 749 H2C_Parameter[0] |= BIT(0); /* function enable */ 750 751 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x63, 1, H2C_Parameter); 752 } 753 754 static void halbtc8723b2ant_IgnoreWlanAct( 755 struct btc_coexist *pBtCoexist, bool bForceExec, bool bEnable 756 ) 757 { 758 pCoexDm->bCurIgnoreWlanAct = bEnable; 759 760 if (!bForceExec) { 761 if (pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct) 762 return; 763 } 764 halbtc8723b2ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable); 765 766 pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct; 767 } 768 769 static void halbtc8723b2ant_SetFwPstdma( 770 struct btc_coexist *pBtCoexist, 771 u8 byte1, 772 u8 byte2, 773 u8 byte3, 774 u8 byte4, 775 u8 byte5 776 ) 777 { 778 u8 H2C_Parameter[5] = {0}; 779 780 H2C_Parameter[0] = byte1; 781 H2C_Parameter[1] = byte2; 782 H2C_Parameter[2] = byte3; 783 H2C_Parameter[3] = byte4; 784 H2C_Parameter[4] = byte5; 785 786 pCoexDm->psTdmaPara[0] = byte1; 787 pCoexDm->psTdmaPara[1] = byte2; 788 pCoexDm->psTdmaPara[2] = byte3; 789 pCoexDm->psTdmaPara[3] = byte4; 790 pCoexDm->psTdmaPara[4] = byte5; 791 792 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x60, 5, H2C_Parameter); 793 } 794 795 static void halbtc8723b2ant_SwMechanism1( 796 struct btc_coexist *pBtCoexist, 797 bool bShrinkRxLPF, 798 bool bLowPenaltyRA, 799 bool bLimitedDIG, 800 bool bBTLNAConstrain 801 ) 802 { 803 halbtc8723b2ant_RfShrink(pBtCoexist, NORMAL_EXEC, bShrinkRxLPF); 804 halbtc8723b2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, bLowPenaltyRA); 805 } 806 807 static void halbtc8723b2ant_SwMechanism2( 808 struct btc_coexist *pBtCoexist, 809 bool bAGCTableShift, 810 bool bADCBackOff, 811 bool bSWDACSwing, 812 u32 dacSwingLvl 813 ) 814 { 815 halbtc8723b2ant_AgcTable(pBtCoexist, NORMAL_EXEC, bAGCTableShift); 816 halbtc8723b2ant_DacSwing(pBtCoexist, NORMAL_EXEC, bSWDACSwing, dacSwingLvl); 817 } 818 819 static void halbtc8723b2ant_SetAntPath( 820 struct btc_coexist *pBtCoexist, u8 antPosType, bool bInitHwCfg, bool bWifiOff 821 ) 822 { 823 struct btc_board_info *pBoardInfo = &pBtCoexist->boardInfo; 824 u32 fwVer = 0, u4Tmp = 0; 825 bool bPgExtSwitch = false; 826 bool bUseExtSwitch = false; 827 u8 H2C_Parameter[2] = {0}; 828 829 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_EXT_SWITCH, &bPgExtSwitch); 830 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); /* [31:16]=fw ver, [15:0]=fw sub ver */ 831 832 if ((fwVer > 0 && fwVer < 0xc0000) || bPgExtSwitch) 833 bUseExtSwitch = true; 834 835 if (bInitHwCfg) { 836 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x39, 0x8, 0x1); 837 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x974, 0xff); 838 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x944, 0x3, 0x3); 839 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x930, 0x77); 840 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x67, 0x20, 0x1); 841 842 if (fwVer >= 0x180000) { 843 /* Use H2C to set GNT_BT to LOW */ 844 H2C_Parameter[0] = 0; 845 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x6E, 1, H2C_Parameter); 846 } else { 847 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x765, 0x0); 848 } 849 850 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); 851 852 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); /* WiFi TRx Mask off */ 853 pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x01); /* BT TRx Mask off */ 854 855 if (pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) { 856 /* tell firmware "no antenna inverse" */ 857 H2C_Parameter[0] = 0; 858 } else { 859 /* tell firmware "antenna inverse" */ 860 H2C_Parameter[0] = 1; 861 } 862 863 if (bUseExtSwitch) { 864 /* ext switch type */ 865 H2C_Parameter[1] = 1; 866 } else { 867 /* int switch type */ 868 H2C_Parameter[1] = 0; 869 } 870 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x65, 2, H2C_Parameter); 871 } 872 873 /* ext switch setting */ 874 if (bUseExtSwitch) { 875 if (bInitHwCfg) { 876 /* 0x4c[23]= 0, 0x4c[24]= 1 Antenna control by WL/BT */ 877 u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); 878 u4Tmp &= ~BIT(23); 879 u4Tmp |= BIT(24); 880 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x4c, u4Tmp); 881 } 882 883 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); /* fixed internal switch S1->WiFi, S0->BT */ 884 switch (antPosType) { 885 case BTC_ANT_WIFI_AT_MAIN: 886 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x92c, 0x3, 0x1); /* ext switch main at wifi */ 887 break; 888 case BTC_ANT_WIFI_AT_AUX: 889 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x92c, 0x3, 0x2); /* ext switch aux at wifi */ 890 break; 891 } 892 } else { /* internal switch */ 893 if (bInitHwCfg) { 894 /* 0x4c[23]= 0, 0x4c[24]= 1 Antenna control by WL/BT */ 895 u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); 896 u4Tmp |= BIT(23); 897 u4Tmp &= ~BIT(24); 898 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x4c, u4Tmp); 899 } 900 901 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x64, 0x1, 0x0); /* fixed external switch S1->Main, S0->Aux */ 902 switch (antPosType) { 903 case BTC_ANT_WIFI_AT_MAIN: 904 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); /* fixed internal switch S1->WiFi, S0->BT */ 905 break; 906 case BTC_ANT_WIFI_AT_AUX: 907 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x280); /* fixed internal switch S0->WiFi, S1->BT */ 908 break; 909 } 910 } 911 } 912 913 static void halbtc8723b2ant_PsTdma( 914 struct btc_coexist *pBtCoexist, bool bForceExec, bool bTurnOn, u8 type 915 ) 916 { 917 pCoexDm->bCurPsTdmaOn = bTurnOn; 918 pCoexDm->curPsTdma = type; 919 920 if (!bForceExec) { 921 if ( 922 (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) && 923 (pCoexDm->prePsTdma == pCoexDm->curPsTdma) 924 ) 925 return; 926 } 927 928 if (bTurnOn) { 929 switch (type) { 930 case 1: 931 default: 932 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); 933 break; 934 case 2: 935 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); 936 break; 937 case 3: 938 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1c, 0x3, 0xf1, 0x90); 939 break; 940 case 4: 941 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x10, 0x03, 0xf1, 0x90); 942 break; 943 case 5: 944 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); 945 break; 946 case 6: 947 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); 948 break; 949 case 7: 950 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1c, 0x3, 0x70, 0x90); 951 break; 952 case 8: 953 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x10, 0x3, 0x70, 0x90); 954 break; 955 case 9: 956 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); 957 break; 958 case 10: 959 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); 960 break; 961 case 11: 962 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0xe1, 0x90); 963 break; 964 case 12: 965 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x90); 966 break; 967 case 13: 968 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); 969 break; 970 case 14: 971 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); 972 break; 973 case 15: 974 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0x60, 0x90); 975 break; 976 case 16: 977 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0x60, 0x90); 978 break; 979 case 17: 980 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x2f, 0x2f, 0x60, 0x90); 981 break; 982 case 18: 983 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x90); 984 break; 985 case 19: 986 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0xe1, 0x90); 987 break; 988 case 20: 989 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0x60, 0x90); 990 break; 991 case 21: 992 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x15, 0x03, 0x70, 0x90); 993 break; 994 case 71: 995 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); 996 break; 997 } 998 } else { 999 /* disable PS tdma */ 1000 switch (type) { 1001 case 0: 1002 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x40, 0x0); 1003 break; 1004 case 1: 1005 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x48, 0x0); 1006 break; 1007 default: 1008 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x40, 0x0); 1009 break; 1010 } 1011 } 1012 1013 /* update pre state */ 1014 pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn; 1015 pCoexDm->prePsTdma = pCoexDm->curPsTdma; 1016 } 1017 1018 static void halbtc8723b2ant_CoexAllOff(struct btc_coexist *pBtCoexist) 1019 { 1020 /* fw all off */ 1021 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, false, 1); 1022 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 1023 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1024 1025 /* sw all off */ 1026 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1027 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1028 1029 /* hw all off */ 1030 /* pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ 1031 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); 1032 } 1033 1034 static void halbtc8723b2ant_InitCoexDm(struct btc_coexist *pBtCoexist) 1035 { 1036 /* force to reset coex mechanism */ 1037 1038 halbtc8723b2ant_PsTdma(pBtCoexist, FORCE_EXEC, false, 1); 1039 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, FORCE_EXEC, 6); 1040 halbtc8723b2ant_DecBtPwr(pBtCoexist, FORCE_EXEC, 0); 1041 1042 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1043 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1044 } 1045 1046 static void halbtc8723b2ant_ActionBtInquiry(struct btc_coexist *pBtCoexist) 1047 { 1048 bool bWifiConnected = false; 1049 bool bLowPwrDisable = true; 1050 1051 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); 1052 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); 1053 1054 if (bWifiConnected) { 1055 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 1056 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 3); 1057 } else { 1058 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); 1059 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, false, 1); 1060 } 1061 1062 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, FORCE_EXEC, 6); 1063 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1064 1065 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1066 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1067 1068 pCoexDm->bNeedRecover0x948 = true; 1069 pCoexDm->backup0x948 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948); 1070 1071 halbtc8723b2ant_SetAntPath(pBtCoexist, BTC_ANT_WIFI_AT_AUX, false, false); 1072 } 1073 1074 static bool halbtc8723b2ant_IsCommonAction(struct btc_coexist *pBtCoexist) 1075 { 1076 u8 btRssiState = BTC_RSSI_STATE_HIGH; 1077 bool bCommon = false, bWifiConnected = false, bWifiBusy = false; 1078 bool bBtHsOn = false, bLowPwrDisable = false; 1079 1080 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); 1081 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); 1082 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); 1083 1084 if (!bWifiConnected) { 1085 bLowPwrDisable = false; 1086 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); 1087 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1088 1089 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1090 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); 1091 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, false, 1); 1092 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 1093 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1094 1095 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1096 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1097 1098 bCommon = true; 1099 } else { 1100 if (pCoexDm->btStatus == BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE) { 1101 bLowPwrDisable = false; 1102 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); 1103 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1104 1105 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1106 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); 1107 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, false, 1); 1108 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0xb); 1109 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1110 1111 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1112 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1113 1114 bCommon = true; 1115 } else if (pCoexDm->btStatus == BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE) { 1116 bLowPwrDisable = true; 1117 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); 1118 1119 if (bBtHsOn) 1120 return false; 1121 1122 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1123 1124 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1125 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); 1126 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, false, 1); 1127 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0xb); 1128 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1129 1130 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1131 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1132 1133 bCommon = true; 1134 } else { 1135 bLowPwrDisable = true; 1136 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); 1137 1138 if (bWifiBusy) { 1139 bCommon = false; 1140 } else { 1141 if (bBtHsOn) 1142 return false; 1143 1144 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 1145 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1146 1147 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1148 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 1149 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 21); 1150 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0xb); 1151 1152 if (BTC_RSSI_HIGH(btRssiState)) 1153 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 1154 else 1155 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1156 1157 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1158 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1159 bCommon = true; 1160 } 1161 } 1162 } 1163 1164 return bCommon; 1165 } 1166 1167 static void halbtc8723b2ant_TdmaDurationAdjust( 1168 struct btc_coexist *pBtCoexist, bool bScoHid, bool bTxPause, u8 maxInterval 1169 ) 1170 { 1171 static s32 up, dn, m, n, WaitCount; 1172 s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ 1173 u8 retryCount = 0; 1174 1175 if (!pCoexDm->bAutoTdmaAdjust) { 1176 pCoexDm->bAutoTdmaAdjust = true; 1177 { 1178 if (bScoHid) { 1179 if (bTxPause) { 1180 if (maxInterval == 1) 1181 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(13); 1182 else if (maxInterval == 2) 1183 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(14); 1184 else 1185 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1186 } else { 1187 if (maxInterval == 1) 1188 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(9); 1189 else if (maxInterval == 2) 1190 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(10); 1191 else 1192 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1193 } 1194 } else { 1195 if (bTxPause) { 1196 if (maxInterval == 1) 1197 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(5); 1198 else if (maxInterval == 2) 1199 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(6); 1200 else 1201 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1202 } else { 1203 if (maxInterval == 1) 1204 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(1); 1205 else if (maxInterval == 2) 1206 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(2); 1207 else 1208 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1209 } 1210 } 1211 } 1212 /* */ 1213 up = 0; 1214 dn = 0; 1215 m = 1; 1216 n = 3; 1217 result = 0; 1218 WaitCount = 0; 1219 } else { 1220 /* acquire the BT TRx retry count from BT_Info byte2 */ 1221 retryCount = pCoexSta->btRetryCnt; 1222 result = 0; 1223 WaitCount++; 1224 1225 if (retryCount == 0) { /* no retry in the last 2-second duration */ 1226 up++; 1227 dn--; 1228 1229 if (dn <= 0) 1230 dn = 0; 1231 1232 if (up >= n) { /* if 連續 n 個2秒 retry count為0, 則調寬WiFi duration */ 1233 WaitCount = 0; 1234 n = 3; 1235 up = 0; 1236 dn = 0; 1237 result = 1; 1238 } 1239 } else if (retryCount <= 3) { /* <=3 retry in the last 2-second duration */ 1240 up--; 1241 dn++; 1242 1243 if (up <= 0) 1244 up = 0; 1245 1246 if (dn == 2) { /* if 連續 2 個2秒 retry count< 3, 則調窄WiFi duration */ 1247 if (WaitCount <= 2) 1248 m++; /* 避免一直在兩個level中來回 */ 1249 else 1250 m = 1; 1251 1252 if (m >= 20) /* m 最大值 = 20 ' 最大120秒 recheck是否調整 WiFi duration. */ 1253 m = 20; 1254 1255 n = 3 * m; 1256 up = 0; 1257 dn = 0; 1258 WaitCount = 0; 1259 result = -1; 1260 } 1261 } else { /* retry count > 3, 只要1次 retry count > 3, 則調窄WiFi duration */ 1262 if (WaitCount == 1) 1263 m++; /* 避免一直在兩個level中來回 */ 1264 else 1265 m = 1; 1266 1267 if (m >= 20) /* m 最大值 = 20 ' 最大120秒 recheck是否調整 WiFi duration. */ 1268 m = 20; 1269 1270 n = 3 * m; 1271 up = 0; 1272 dn = 0; 1273 WaitCount = 0; 1274 result = -1; 1275 } 1276 1277 if (maxInterval == 1) { 1278 if (bTxPause) { 1279 if (pCoexDm->curPsTdma == 71) 1280 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(5); 1281 else if (pCoexDm->curPsTdma == 1) 1282 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(5); 1283 else if (pCoexDm->curPsTdma == 2) 1284 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(6); 1285 else if (pCoexDm->curPsTdma == 3) 1286 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1287 else if (pCoexDm->curPsTdma == 4) 1288 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(8); 1289 1290 if (pCoexDm->curPsTdma == 9) 1291 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(13); 1292 else if (pCoexDm->curPsTdma == 10) 1293 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(14); 1294 else if (pCoexDm->curPsTdma == 11) 1295 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1296 else if (pCoexDm->curPsTdma == 12) 1297 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(16); 1298 1299 if (result == -1) { 1300 if (pCoexDm->curPsTdma == 5) 1301 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(6); 1302 else if (pCoexDm->curPsTdma == 6) 1303 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1304 else if (pCoexDm->curPsTdma == 7) 1305 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(8); 1306 else if (pCoexDm->curPsTdma == 13) 1307 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(14); 1308 else if (pCoexDm->curPsTdma == 14) 1309 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1310 else if (pCoexDm->curPsTdma == 15) 1311 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(16); 1312 } else if (result == 1) { 1313 if (pCoexDm->curPsTdma == 8) 1314 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1315 else if (pCoexDm->curPsTdma == 7) 1316 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(6); 1317 else if (pCoexDm->curPsTdma == 6) 1318 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(5); 1319 else if (pCoexDm->curPsTdma == 16) 1320 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1321 else if (pCoexDm->curPsTdma == 15) 1322 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(14); 1323 else if (pCoexDm->curPsTdma == 14) 1324 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(13); 1325 } 1326 } else { 1327 if (pCoexDm->curPsTdma == 5) 1328 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(71); 1329 else if (pCoexDm->curPsTdma == 6) 1330 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(2); 1331 else if (pCoexDm->curPsTdma == 7) 1332 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1333 else if (pCoexDm->curPsTdma == 8) 1334 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(4); 1335 1336 if (pCoexDm->curPsTdma == 13) 1337 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(9); 1338 else if (pCoexDm->curPsTdma == 14) 1339 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(10); 1340 else if (pCoexDm->curPsTdma == 15) 1341 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1342 else if (pCoexDm->curPsTdma == 16) 1343 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(12); 1344 1345 if (result == -1) { 1346 if (pCoexDm->curPsTdma == 71) 1347 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(1); 1348 else if (pCoexDm->curPsTdma == 1) 1349 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(2); 1350 else if (pCoexDm->curPsTdma == 2) 1351 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1352 else if (pCoexDm->curPsTdma == 3) 1353 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(4); 1354 else if (pCoexDm->curPsTdma == 9) 1355 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(10); 1356 else if (pCoexDm->curPsTdma == 10) 1357 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1358 else if (pCoexDm->curPsTdma == 11) 1359 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(12); 1360 } else if (result == 1) { 1361 if (pCoexDm->curPsTdma == 4) 1362 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1363 else if (pCoexDm->curPsTdma == 3) 1364 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(2); 1365 else if (pCoexDm->curPsTdma == 2) 1366 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(1); 1367 else if (pCoexDm->curPsTdma == 1) 1368 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(71); 1369 else if (pCoexDm->curPsTdma == 12) 1370 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1371 else if (pCoexDm->curPsTdma == 11) 1372 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(10); 1373 else if (pCoexDm->curPsTdma == 10) 1374 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(9); 1375 } 1376 } 1377 } else if (maxInterval == 2) { 1378 if (bTxPause) { 1379 if (pCoexDm->curPsTdma == 1) 1380 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(6); 1381 else if (pCoexDm->curPsTdma == 2) 1382 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(6); 1383 else if (pCoexDm->curPsTdma == 3) 1384 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1385 else if (pCoexDm->curPsTdma == 4) 1386 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(8); 1387 1388 if (pCoexDm->curPsTdma == 9) 1389 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(14); 1390 else if (pCoexDm->curPsTdma == 10) 1391 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(14); 1392 else if (pCoexDm->curPsTdma == 11) 1393 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1394 else if (pCoexDm->curPsTdma == 12) 1395 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(16); 1396 1397 if (result == -1) { 1398 if (pCoexDm->curPsTdma == 5) 1399 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(6); 1400 else if (pCoexDm->curPsTdma == 6) 1401 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1402 else if (pCoexDm->curPsTdma == 7) 1403 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(8); 1404 else if (pCoexDm->curPsTdma == 13) 1405 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(14); 1406 else if (pCoexDm->curPsTdma == 14) 1407 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1408 else if (pCoexDm->curPsTdma == 15) 1409 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(16); 1410 } else if (result == 1) { 1411 if (pCoexDm->curPsTdma == 8) 1412 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1413 else if (pCoexDm->curPsTdma == 7) 1414 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(6); 1415 else if (pCoexDm->curPsTdma == 6) 1416 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(6); 1417 else if (pCoexDm->curPsTdma == 16) 1418 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1419 else if (pCoexDm->curPsTdma == 15) 1420 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(14); 1421 else if (pCoexDm->curPsTdma == 14) 1422 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(14); 1423 } 1424 } else { 1425 if (pCoexDm->curPsTdma == 5) 1426 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(2); 1427 else if (pCoexDm->curPsTdma == 6) 1428 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(2); 1429 else if (pCoexDm->curPsTdma == 7) 1430 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1431 else if (pCoexDm->curPsTdma == 8) 1432 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(4); 1433 1434 if (pCoexDm->curPsTdma == 13) 1435 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(10); 1436 else if (pCoexDm->curPsTdma == 14) 1437 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(10); 1438 else if (pCoexDm->curPsTdma == 15) 1439 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1440 else if (pCoexDm->curPsTdma == 16) 1441 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(12); 1442 1443 if (result == -1) { 1444 if (pCoexDm->curPsTdma == 1) 1445 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(2); 1446 else if (pCoexDm->curPsTdma == 2) 1447 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1448 else if (pCoexDm->curPsTdma == 3) 1449 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(4); 1450 else if (pCoexDm->curPsTdma == 9) 1451 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(10); 1452 else if (pCoexDm->curPsTdma == 10) 1453 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1454 else if (pCoexDm->curPsTdma == 11) 1455 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(12); 1456 } else if (result == 1) { 1457 if (pCoexDm->curPsTdma == 4) 1458 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1459 else if (pCoexDm->curPsTdma == 3) 1460 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(2); 1461 else if (pCoexDm->curPsTdma == 2) 1462 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(2); 1463 else if (pCoexDm->curPsTdma == 12) 1464 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1465 else if (pCoexDm->curPsTdma == 11) 1466 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(10); 1467 else if (pCoexDm->curPsTdma == 10) 1468 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(10); 1469 } 1470 } 1471 } else if (maxInterval == 3) { 1472 if (bTxPause) { 1473 if (pCoexDm->curPsTdma == 1) 1474 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1475 else if (pCoexDm->curPsTdma == 2) 1476 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1477 else if (pCoexDm->curPsTdma == 3) 1478 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1479 else if (pCoexDm->curPsTdma == 4) 1480 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(8); 1481 1482 if (pCoexDm->curPsTdma == 9) 1483 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1484 else if (pCoexDm->curPsTdma == 10) 1485 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1486 else if (pCoexDm->curPsTdma == 11) 1487 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1488 else if (pCoexDm->curPsTdma == 12) 1489 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(16); 1490 1491 if (result == -1) { 1492 if (pCoexDm->curPsTdma == 5) 1493 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1494 else if (pCoexDm->curPsTdma == 6) 1495 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1496 else if (pCoexDm->curPsTdma == 7) 1497 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(8); 1498 else if (pCoexDm->curPsTdma == 13) 1499 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1500 else if (pCoexDm->curPsTdma == 14) 1501 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1502 else if (pCoexDm->curPsTdma == 15) 1503 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(16); 1504 } else if (result == 1) { 1505 if (pCoexDm->curPsTdma == 8) 1506 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1507 else if (pCoexDm->curPsTdma == 7) 1508 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1509 else if (pCoexDm->curPsTdma == 6) 1510 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1511 else if (pCoexDm->curPsTdma == 16) 1512 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1513 else if (pCoexDm->curPsTdma == 15) 1514 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1515 else if (pCoexDm->curPsTdma == 14) 1516 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1517 } 1518 } else { 1519 if (pCoexDm->curPsTdma == 5) 1520 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1521 else if (pCoexDm->curPsTdma == 6) 1522 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1523 else if (pCoexDm->curPsTdma == 7) 1524 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1525 else if (pCoexDm->curPsTdma == 8) 1526 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(4); 1527 1528 if (pCoexDm->curPsTdma == 13) 1529 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1530 else if (pCoexDm->curPsTdma == 14) 1531 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1532 else if (pCoexDm->curPsTdma == 15) 1533 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1534 else if (pCoexDm->curPsTdma == 16) 1535 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(12); 1536 1537 if (result == -1) { 1538 if (pCoexDm->curPsTdma == 1) 1539 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1540 else if (pCoexDm->curPsTdma == 2) 1541 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1542 else if (pCoexDm->curPsTdma == 3) 1543 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(4); 1544 else if (pCoexDm->curPsTdma == 9) 1545 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1546 else if (pCoexDm->curPsTdma == 10) 1547 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1548 else if (pCoexDm->curPsTdma == 11) 1549 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(12); 1550 } else if (result == 1) { 1551 if (pCoexDm->curPsTdma == 4) 1552 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1553 else if (pCoexDm->curPsTdma == 3) 1554 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1555 else if (pCoexDm->curPsTdma == 2) 1556 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1557 else if (pCoexDm->curPsTdma == 12) 1558 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1559 else if (pCoexDm->curPsTdma == 11) 1560 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1561 else if (pCoexDm->curPsTdma == 10) 1562 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1563 } 1564 } 1565 } 1566 } 1567 1568 /* if current PsTdma not match with the recorded one (when scan, dhcp...), */ 1569 /* then we have to adjust it back to the previous record one. */ 1570 if (pCoexDm->curPsTdma != pCoexDm->psTdmaDuAdjType) { 1571 bool bScan = false, bLink = false, bRoam = false; 1572 1573 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); 1574 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); 1575 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); 1576 1577 if (!bScan && !bLink && !bRoam) 1578 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, pCoexDm->psTdmaDuAdjType); 1579 1580 } 1581 } 1582 1583 /* SCO only or SCO+PAN(HS) */ 1584 static void halbtc8723b2ant_ActionSco(struct btc_coexist *pBtCoexist) 1585 { 1586 u8 wifiRssiState, btRssiState; 1587 u32 wifiBw; 1588 1589 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 1590 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 1591 1592 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1593 1594 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1595 1596 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 4); 1597 1598 if (BTC_RSSI_HIGH(btRssiState)) 1599 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 1600 else 1601 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1602 1603 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 1604 1605 if (wifiBw == BTC_WIFI_BW_LEGACY) /* for SCO quality at 11b/g mode */ 1606 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); 1607 else /* for SCO quality & wifi performance balance at 11n mode */ 1608 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 8); 1609 1610 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, false, 0); /* for voice quality */ 1611 1612 /* sw mechanism */ 1613 if (wifiBw == BTC_WIFI_BW_HT40) { 1614 if ( 1615 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1616 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1617 ) { 1618 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 1619 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, true, 0x4); 1620 } else { 1621 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 1622 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, true, 0x4); 1623 } 1624 } else { 1625 if ( 1626 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1627 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1628 ) { 1629 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 1630 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, true, 0x4); 1631 } else { 1632 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 1633 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, true, 0x4); 1634 } 1635 } 1636 } 1637 1638 static void halbtc8723b2ant_ActionHid(struct btc_coexist *pBtCoexist) 1639 { 1640 u8 wifiRssiState, btRssiState; 1641 u32 wifiBw; 1642 1643 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 1644 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 1645 1646 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1647 1648 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1649 1650 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 1651 1652 if (BTC_RSSI_HIGH(btRssiState)) 1653 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 1654 else 1655 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1656 1657 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 1658 1659 if (wifiBw == BTC_WIFI_BW_LEGACY) /* for HID at 11b/g mode */ 1660 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 1661 else /* for HID quality & wifi performance balance at 11n mode */ 1662 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 9); 1663 1664 if ( 1665 (btRssiState == BTC_RSSI_STATE_HIGH) || 1666 (btRssiState == BTC_RSSI_STATE_STAY_HIGH) 1667 ) 1668 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 9); 1669 else 1670 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 13); 1671 1672 /* sw mechanism */ 1673 if (wifiBw == BTC_WIFI_BW_HT40) { 1674 if ( 1675 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1676 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1677 ) { 1678 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 1679 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1680 } else { 1681 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 1682 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1683 } 1684 } else { 1685 if ( 1686 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1687 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1688 ) { 1689 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 1690 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1691 } else { 1692 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 1693 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1694 } 1695 } 1696 } 1697 1698 /* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ 1699 static void halbtc8723b2ant_ActionA2dp(struct btc_coexist *pBtCoexist) 1700 { 1701 u8 wifiRssiState, wifiRssiState1, btRssiState; 1702 u32 wifiBw; 1703 u8 apNum = 0; 1704 1705 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 1706 wifiRssiState1 = halbtc8723b2ant_WifiRssiState(pBtCoexist, 1, 2, 40, 0); 1707 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 1708 1709 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &apNum); 1710 1711 /* define the office environment */ 1712 if (apNum >= 10 && BTC_RSSI_HIGH(wifiRssiState1)) { 1713 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1714 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1715 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 1716 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1717 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); 1718 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, false, 1); 1719 1720 /* sw mechanism */ 1721 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 1722 if (wifiBw == BTC_WIFI_BW_HT40) { 1723 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1724 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, true, 0x18); 1725 } else { 1726 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1727 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, true, 0x18); 1728 } 1729 return; 1730 } 1731 1732 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1733 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1734 1735 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 1736 1737 if (BTC_RSSI_HIGH(btRssiState)) 1738 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 1739 else 1740 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1741 1742 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 1743 1744 if ( 1745 (btRssiState == BTC_RSSI_STATE_HIGH) || 1746 (btRssiState == BTC_RSSI_STATE_STAY_HIGH) 1747 ) 1748 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, false, false, 1); 1749 else 1750 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, false, true, 1); 1751 1752 /* sw mechanism */ 1753 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 1754 if (wifiBw == BTC_WIFI_BW_HT40) { 1755 if ( 1756 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1757 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1758 ) { 1759 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1760 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1761 } else { 1762 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1763 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1764 } 1765 } else { 1766 if ( 1767 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1768 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1769 ) { 1770 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1771 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1772 } else { 1773 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1774 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1775 } 1776 } 1777 } 1778 1779 static void halbtc8723b2ant_ActionA2dpPanHs(struct btc_coexist *pBtCoexist) 1780 { 1781 u8 wifiRssiState, btRssiState; 1782 u32 wifiBw; 1783 1784 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 1785 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 1786 1787 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1788 1789 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1790 1791 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 1792 1793 if (BTC_RSSI_HIGH(btRssiState)) 1794 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 1795 else 1796 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1797 1798 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 1799 1800 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, false, true, 2); 1801 1802 /* sw mechanism */ 1803 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 1804 if (wifiBw == BTC_WIFI_BW_HT40) { 1805 if ( 1806 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1807 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1808 ) { 1809 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1810 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1811 } else { 1812 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1813 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1814 } 1815 } else { 1816 if ( 1817 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1818 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1819 ) { 1820 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1821 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1822 } else { 1823 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1824 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1825 } 1826 } 1827 } 1828 1829 static void halbtc8723b2ant_ActionPanEdr(struct btc_coexist *pBtCoexist) 1830 { 1831 u8 wifiRssiState, btRssiState; 1832 u32 wifiBw; 1833 1834 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 1835 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 1836 1837 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1838 1839 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1840 1841 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 1842 1843 if (BTC_RSSI_HIGH(btRssiState)) 1844 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 1845 else 1846 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1847 1848 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 10); 1849 1850 if ( 1851 (btRssiState == BTC_RSSI_STATE_HIGH) || 1852 (btRssiState == BTC_RSSI_STATE_STAY_HIGH) 1853 ) 1854 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 1); 1855 else 1856 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 5); 1857 1858 /* sw mechanism */ 1859 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 1860 if (wifiBw == BTC_WIFI_BW_HT40) { 1861 if ( 1862 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1863 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1864 ) { 1865 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1866 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1867 } else { 1868 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1869 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1870 } 1871 } else { 1872 if ( 1873 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1874 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1875 ) { 1876 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1877 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1878 } else { 1879 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1880 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1881 } 1882 } 1883 } 1884 1885 /* PAN(HS) only */ 1886 static void halbtc8723b2ant_ActionPanHs(struct btc_coexist *pBtCoexist) 1887 { 1888 u8 wifiRssiState, btRssiState; 1889 u32 wifiBw; 1890 1891 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 1892 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 1893 1894 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1895 1896 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1897 1898 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 1899 1900 if (BTC_RSSI_HIGH(btRssiState)) 1901 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 1902 else 1903 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1904 1905 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 1906 1907 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, false, 1); 1908 1909 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 1910 if (wifiBw == BTC_WIFI_BW_HT40) { 1911 if ( 1912 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1913 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1914 ) { 1915 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1916 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1917 } else { 1918 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1919 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1920 } 1921 } else { 1922 if ( 1923 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1924 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1925 ) { 1926 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1927 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1928 } else { 1929 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1930 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1931 } 1932 } 1933 } 1934 1935 /* PAN(EDR)+A2DP */ 1936 static void halbtc8723b2ant_ActionPanEdrA2dp(struct btc_coexist *pBtCoexist) 1937 { 1938 u8 wifiRssiState, btRssiState; 1939 u32 wifiBw; 1940 1941 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 1942 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 1943 1944 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1945 1946 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1947 1948 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 1949 1950 if (BTC_RSSI_HIGH(btRssiState)) 1951 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 1952 else 1953 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1954 1955 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 1956 1957 if ( 1958 (btRssiState == BTC_RSSI_STATE_HIGH) || 1959 (btRssiState == BTC_RSSI_STATE_STAY_HIGH) 1960 ) { 1961 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 12); 1962 if (wifiBw == BTC_WIFI_BW_HT40) 1963 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, false, true, 3); 1964 else 1965 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, false, false, 3); 1966 } else { 1967 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 1968 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, false, true, 3); 1969 } 1970 1971 /* sw mechanism */ 1972 if (wifiBw == BTC_WIFI_BW_HT40) { 1973 if ( 1974 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1975 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1976 ) { 1977 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1978 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1979 } else { 1980 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1981 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1982 } 1983 } else { 1984 if ( 1985 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1986 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1987 ) { 1988 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1989 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1990 } else { 1991 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1992 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1993 } 1994 } 1995 } 1996 1997 static void halbtc8723b2ant_ActionPanEdrHid(struct btc_coexist *pBtCoexist) 1998 { 1999 u8 wifiRssiState, btRssiState; 2000 u32 wifiBw; 2001 2002 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 2003 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 2004 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 2005 2006 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 2007 2008 if (BTC_RSSI_HIGH(btRssiState)) 2009 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 2010 else 2011 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 2012 2013 if ( 2014 (btRssiState == BTC_RSSI_STATE_HIGH) || 2015 (btRssiState == BTC_RSSI_STATE_STAY_HIGH) 2016 ) { 2017 if (wifiBw == BTC_WIFI_BW_HT40) { 2018 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 3); 2019 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 11); 2020 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x780); 2021 } else { 2022 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 2023 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 2024 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 2025 } 2026 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, true, false, 2); 2027 } else { 2028 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 2029 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 11); 2030 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 2031 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, true, true, 2); 2032 } 2033 2034 /* sw mechanism */ 2035 if (wifiBw == BTC_WIFI_BW_HT40) { 2036 if ( 2037 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 2038 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 2039 ) { 2040 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 2041 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 2042 } else { 2043 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 2044 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 2045 } 2046 } else { 2047 if ( 2048 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 2049 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 2050 ) { 2051 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 2052 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 2053 } else { 2054 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 2055 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 2056 } 2057 } 2058 } 2059 2060 /* HID+A2DP+PAN(EDR) */ 2061 static void halbtc8723b2ant_ActionHidA2dpPanEdr(struct btc_coexist *pBtCoexist) 2062 { 2063 u8 wifiRssiState, btRssiState; 2064 u32 wifiBw; 2065 2066 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 2067 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 2068 2069 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 2070 2071 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 2072 2073 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 2074 2075 if (BTC_RSSI_HIGH(btRssiState)) 2076 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 2077 else 2078 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 2079 2080 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 2081 2082 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 2083 2084 if ( 2085 (btRssiState == BTC_RSSI_STATE_HIGH) || 2086 (btRssiState == BTC_RSSI_STATE_STAY_HIGH) 2087 ) { 2088 if (wifiBw == BTC_WIFI_BW_HT40) 2089 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, true, true, 2); 2090 else 2091 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, true, false, 3); 2092 } else 2093 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, true, true, 3); 2094 2095 /* sw mechanism */ 2096 if (wifiBw == BTC_WIFI_BW_HT40) { 2097 if ( 2098 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 2099 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 2100 ) { 2101 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 2102 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 2103 } else { 2104 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 2105 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 2106 } 2107 } else { 2108 if ( 2109 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 2110 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 2111 ) { 2112 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 2113 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 2114 } else { 2115 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 2116 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 2117 } 2118 } 2119 } 2120 2121 static void halbtc8723b2ant_ActionHidA2dp(struct btc_coexist *pBtCoexist) 2122 { 2123 u8 wifiRssiState, btRssiState; 2124 u32 wifiBw; 2125 u8 apNum = 0; 2126 2127 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 2128 /* btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); */ 2129 btRssiState = halbtc8723b2ant_BtRssiState(3, 29, 37); 2130 2131 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 2132 2133 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, true, 0x5); 2134 2135 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 2136 2137 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 2138 if (wifiBw == BTC_WIFI_BW_LEGACY) { 2139 if (BTC_RSSI_HIGH(btRssiState)) 2140 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 2141 else if (BTC_RSSI_MEDIUM(btRssiState)) 2142 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 2143 else 2144 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 2145 } else { 2146 /* only 802.11N mode we have to dec bt power to 4 degree */ 2147 if (BTC_RSSI_HIGH(btRssiState)) { 2148 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &apNum); 2149 /* need to check ap Number of Not */ 2150 if (apNum < 10) 2151 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); 2152 else 2153 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 2154 } else if (BTC_RSSI_MEDIUM(btRssiState)) 2155 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 2156 else 2157 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 2158 } 2159 2160 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 2161 2162 if ( 2163 (btRssiState == BTC_RSSI_STATE_HIGH) || 2164 (btRssiState == BTC_RSSI_STATE_STAY_HIGH) 2165 ) 2166 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, true, false, 2); 2167 else 2168 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, true, true, 2); 2169 2170 /* sw mechanism */ 2171 if (wifiBw == BTC_WIFI_BW_HT40) { 2172 if ( 2173 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 2174 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 2175 ) { 2176 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 2177 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 2178 } else { 2179 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 2180 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 2181 } 2182 } else { 2183 if ( 2184 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 2185 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 2186 ) { 2187 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 2188 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 2189 } else { 2190 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 2191 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 2192 } 2193 } 2194 } 2195 2196 static void halbtc8723b2ant_RunCoexistMechanism(struct btc_coexist *pBtCoexist) 2197 { 2198 u8 algorithm = 0; 2199 2200 if (pBtCoexist->bManualControl) { 2201 return; 2202 } 2203 2204 if (pCoexSta->bUnderIps) { 2205 return; 2206 } 2207 2208 algorithm = halbtc8723b2ant_ActionAlgorithm(pBtCoexist); 2209 if (pCoexSta->bC2hBtInquiryPage && (algorithm != BT_8723B_2ANT_COEX_ALGO_PANHS)) { 2210 halbtc8723b2ant_ActionBtInquiry(pBtCoexist); 2211 return; 2212 } else { 2213 if (pCoexDm->bNeedRecover0x948) { 2214 pCoexDm->bNeedRecover0x948 = false; 2215 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, pCoexDm->backup0x948); 2216 } 2217 } 2218 2219 pCoexDm->curAlgorithm = algorithm; 2220 2221 if (halbtc8723b2ant_IsCommonAction(pBtCoexist)) { 2222 pCoexDm->bAutoTdmaAdjust = false; 2223 } else { 2224 if (pCoexDm->curAlgorithm != pCoexDm->preAlgorithm) { 2225 pCoexDm->bAutoTdmaAdjust = false; 2226 } 2227 2228 switch (pCoexDm->curAlgorithm) { 2229 case BT_8723B_2ANT_COEX_ALGO_SCO: 2230 halbtc8723b2ant_ActionSco(pBtCoexist); 2231 break; 2232 case BT_8723B_2ANT_COEX_ALGO_HID: 2233 halbtc8723b2ant_ActionHid(pBtCoexist); 2234 break; 2235 case BT_8723B_2ANT_COEX_ALGO_A2DP: 2236 halbtc8723b2ant_ActionA2dp(pBtCoexist); 2237 break; 2238 case BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS: 2239 halbtc8723b2ant_ActionA2dpPanHs(pBtCoexist); 2240 break; 2241 case BT_8723B_2ANT_COEX_ALGO_PANEDR: 2242 halbtc8723b2ant_ActionPanEdr(pBtCoexist); 2243 break; 2244 case BT_8723B_2ANT_COEX_ALGO_PANHS: 2245 halbtc8723b2ant_ActionPanHs(pBtCoexist); 2246 break; 2247 case BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP: 2248 halbtc8723b2ant_ActionPanEdrA2dp(pBtCoexist); 2249 break; 2250 case BT_8723B_2ANT_COEX_ALGO_PANEDR_HID: 2251 halbtc8723b2ant_ActionPanEdrHid(pBtCoexist); 2252 break; 2253 case BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR: 2254 halbtc8723b2ant_ActionHidA2dpPanEdr(pBtCoexist); 2255 break; 2256 case BT_8723B_2ANT_COEX_ALGO_HID_A2DP: 2257 halbtc8723b2ant_ActionHidA2dp(pBtCoexist); 2258 break; 2259 default: 2260 halbtc8723b2ant_CoexAllOff(pBtCoexist); 2261 break; 2262 } 2263 pCoexDm->preAlgorithm = pCoexDm->curAlgorithm; 2264 } 2265 } 2266 2267 static void halbtc8723b2ant_WifiOffHwCfg(struct btc_coexist *pBtCoexist) 2268 { 2269 bool bIsInMpMode = false; 2270 u8 H2C_Parameter[2] = {0}; 2271 u32 fwVer = 0; 2272 2273 /* set wlan_act to low */ 2274 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); 2275 2276 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x780); /* WiFi goto standby while GNT_BT 0-->1 */ 2277 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); 2278 if (fwVer >= 0x180000) { 2279 /* Use H2C to set GNT_BT to HIGH */ 2280 H2C_Parameter[0] = 1; 2281 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x6E, 1, H2C_Parameter); 2282 } else 2283 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x765, 0x18); 2284 2285 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_IS_IN_MP_MODE, &bIsInMpMode); 2286 if (!bIsInMpMode) 2287 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x67, 0x20, 0x0); /* BT select s0/s1 is controlled by BT */ 2288 else 2289 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x67, 0x20, 0x1); /* BT select s0/s1 is controlled by WiFi */ 2290 } 2291 2292 static void halbtc8723b2ant_InitHwConfig(struct btc_coexist *pBtCoexist, bool bBackUp) 2293 { 2294 u8 u1Tmp = 0; 2295 2296 /* backup rf 0x1e value */ 2297 pCoexDm->btRf0x1eBackup = 2298 pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff); 2299 2300 /* 0x790[5:0]= 0x5 */ 2301 u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x790); 2302 u1Tmp &= 0xc0; 2303 u1Tmp |= 0x5; 2304 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x790, u1Tmp); 2305 2306 /* Antenna config */ 2307 halbtc8723b2ant_SetAntPath(pBtCoexist, BTC_ANT_WIFI_AT_MAIN, true, false); 2308 2309 /* PTA parameter */ 2310 halbtc8723b2ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); 2311 2312 /* Enable counter statistics */ 2313 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); /* 0x76e[3] = 1, WLAN_Act control by PTA */ 2314 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x3); 2315 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x40, 0x20, 0x1); 2316 } 2317 2318 /* */ 2319 /* work around function start with wa_halbtc8723b2ant_ */ 2320 /* */ 2321 /* */ 2322 /* extern function start with EXhalbtc8723b2ant_ */ 2323 /* */ 2324 void EXhalbtc8723b2ant_PowerOnSetting(struct btc_coexist *pBtCoexist) 2325 { 2326 struct btc_board_info *pBoardInfo = &pBtCoexist->boardInfo; 2327 u8 u1Tmp = 0x4; /* Set BIT2 by default since it's 2ant case */ 2328 u16 u2Tmp = 0x0; 2329 2330 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x67, 0x20); 2331 2332 /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */ 2333 u2Tmp = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x2); 2334 pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x2, u2Tmp | BIT(0) | BIT(1)); 2335 2336 /* set GRAN_BT = 1 */ 2337 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x765, 0x18); 2338 /* set WLAN_ACT = 0 */ 2339 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); 2340 2341 /* */ 2342 /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ 2343 /* Local setting bit define */ 2344 /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ 2345 /* BIT1: "0" for internal switch; "1" for external switch */ 2346 /* BIT2: "0" for one antenna; "1" for two antenna */ 2347 /* NOTE: here default all internal switch and 1-antenna ==> BIT1 = 0 and BIT2 = 0 */ 2348 if (pBtCoexist->chipInterface == BTC_INTF_USB) { 2349 /* fixed at S0 for USB interface */ 2350 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); 2351 2352 u1Tmp |= 0x1; /* antenna inverse */ 2353 pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0xfe08, u1Tmp); 2354 2355 pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_AUX_PORT; 2356 } else { 2357 /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ 2358 if (pBoardInfo->singleAntPath == 0) { 2359 /* set to S1 */ 2360 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x280); 2361 pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT; 2362 } else if (pBoardInfo->singleAntPath == 1) { 2363 /* set to S0 */ 2364 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); 2365 u1Tmp |= 0x1; /* antenna inverse */ 2366 pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_AUX_PORT; 2367 } 2368 2369 if (pBtCoexist->chipInterface == BTC_INTF_PCI) 2370 pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0x384, u1Tmp); 2371 else if (pBtCoexist->chipInterface == BTC_INTF_SDIO) 2372 pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0x60, u1Tmp); 2373 } 2374 } 2375 2376 void EXhalbtc8723b2ant_InitHwConfig(struct btc_coexist *pBtCoexist, bool bWifiOnly) 2377 { 2378 halbtc8723b2ant_InitHwConfig(pBtCoexist, true); 2379 } 2380 2381 void EXhalbtc8723b2ant_InitCoexDm(struct btc_coexist *pBtCoexist) 2382 { 2383 halbtc8723b2ant_InitCoexDm(pBtCoexist); 2384 } 2385 2386 void EXhalbtc8723b2ant_IpsNotify(struct btc_coexist *pBtCoexist, u8 type) 2387 { 2388 if (type == BTC_IPS_ENTER) { 2389 pCoexSta->bUnderIps = true; 2390 halbtc8723b2ant_WifiOffHwCfg(pBtCoexist); 2391 halbtc8723b2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, true); 2392 halbtc8723b2ant_CoexAllOff(pBtCoexist); 2393 } else if (type == BTC_IPS_LEAVE) { 2394 pCoexSta->bUnderIps = false; 2395 halbtc8723b2ant_InitHwConfig(pBtCoexist, false); 2396 halbtc8723b2ant_InitCoexDm(pBtCoexist); 2397 halbtc8723b2ant_QueryBtInfo(pBtCoexist); 2398 } 2399 } 2400 2401 void EXhalbtc8723b2ant_LpsNotify(struct btc_coexist *pBtCoexist, u8 type) 2402 { 2403 if (type == BTC_LPS_ENABLE) { 2404 pCoexSta->bUnderLps = true; 2405 } else if (type == BTC_LPS_DISABLE) { 2406 pCoexSta->bUnderLps = false; 2407 } 2408 } 2409 2410 void EXhalbtc8723b2ant_ScanNotify(struct btc_coexist *pBtCoexist, u8 type) 2411 { 2412 if (type == BTC_SCAN_START) { 2413 } else if (type == BTC_SCAN_FINISH) { 2414 } 2415 } 2416 2417 void EXhalbtc8723b2ant_ConnectNotify(struct btc_coexist *pBtCoexist, u8 type) 2418 { 2419 if (type == BTC_ASSOCIATE_START) { 2420 } else if (type == BTC_ASSOCIATE_FINISH) { 2421 } 2422 } 2423 2424 void EXhalbtc8723b2ant_MediaStatusNotify(struct btc_coexist *pBtCoexist, u8 type) 2425 { 2426 u8 H2C_Parameter[3] = {0}; 2427 u32 wifiBw; 2428 u8 wifiCentralChnl; 2429 u8 apNum = 0; 2430 2431 /* only 2.4G we need to inform bt the chnl mask */ 2432 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifiCentralChnl); 2433 if ((type == BTC_MEDIA_CONNECT) && (wifiCentralChnl <= 14)) { 2434 H2C_Parameter[0] = 0x1; 2435 H2C_Parameter[1] = wifiCentralChnl; 2436 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 2437 if (wifiBw == BTC_WIFI_BW_HT40) 2438 H2C_Parameter[2] = 0x30; 2439 else { 2440 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &apNum); 2441 if (apNum < 10) 2442 H2C_Parameter[2] = 0x30; 2443 else 2444 H2C_Parameter[2] = 0x20; 2445 } 2446 } 2447 2448 pCoexDm->wifiChnlInfo[0] = H2C_Parameter[0]; 2449 pCoexDm->wifiChnlInfo[1] = H2C_Parameter[1]; 2450 pCoexDm->wifiChnlInfo[2] = H2C_Parameter[2]; 2451 2452 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x66, 3, H2C_Parameter); 2453 } 2454 2455 void EXhalbtc8723b2ant_SpecialPacketNotify(struct btc_coexist *pBtCoexist, u8 type) 2456 { 2457 } 2458 2459 void EXhalbtc8723b2ant_BtInfoNotify( 2460 struct btc_coexist *pBtCoexist, u8 *tmpBuf, u8 length 2461 ) 2462 { 2463 u8 btInfo = 0; 2464 u8 i, rspSource = 0; 2465 bool bBtBusy = false, bLimitedDig = false; 2466 bool bWifiConnected = false; 2467 2468 pCoexSta->bC2hBtInfoReqSent = false; 2469 2470 rspSource = tmpBuf[0] & 0xf; 2471 if (rspSource >= BT_INFO_SRC_8723B_2ANT_MAX) 2472 rspSource = BT_INFO_SRC_8723B_2ANT_WIFI_FW; 2473 2474 pCoexSta->btInfoC2hCnt[rspSource]++; 2475 2476 for (i = 0; i < length; i++) { 2477 pCoexSta->btInfoC2h[rspSource][i] = tmpBuf[i]; 2478 if (i == 1) 2479 btInfo = tmpBuf[i]; 2480 2481 } 2482 2483 if (pBtCoexist->bManualControl) { 2484 return; 2485 } 2486 2487 if (rspSource != BT_INFO_SRC_8723B_2ANT_WIFI_FW) { 2488 pCoexSta->btRetryCnt = pCoexSta->btInfoC2h[rspSource][2] & 0xf; /* [3:0] */ 2489 2490 pCoexSta->btRssi = pCoexSta->btInfoC2h[rspSource][3] * 2 + 10; 2491 2492 pCoexSta->btInfoExt = pCoexSta->btInfoC2h[rspSource][4]; 2493 2494 pCoexSta->bBtTxRxMask = (pCoexSta->btInfoC2h[rspSource][2] & 0x40); 2495 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TX_RX_MASK, &pCoexSta->bBtTxRxMask); 2496 if (pCoexSta->bBtTxRxMask) { 2497 /* BT into is responded by BT FW and BT RF REG 0x3C != 0x01 => Need to switch BT TRx Mask */ 2498 pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x01); 2499 } 2500 2501 /* Here we need to resend some wifi info to BT */ 2502 /* because bt is reset and loss of the info. */ 2503 if ((pCoexSta->btInfoExt & BIT(1))) { 2504 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); 2505 2506 if (bWifiConnected) 2507 EXhalbtc8723b2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_CONNECT); 2508 else 2509 EXhalbtc8723b2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); 2510 } 2511 2512 if ((pCoexSta->btInfoExt & BIT(3))) { 2513 halbtc8723b2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, false); 2514 } else { 2515 /* BT already NOT ignore Wlan active, do nothing here. */ 2516 } 2517 } 2518 2519 /* check BIT2 first ==> check if bt is under inquiry or page scan */ 2520 if (btInfo & BT_INFO_8723B_2ANT_B_INQ_PAGE) 2521 pCoexSta->bC2hBtInquiryPage = true; 2522 else 2523 pCoexSta->bC2hBtInquiryPage = false; 2524 2525 /* set link exist status */ 2526 if (!(btInfo & BT_INFO_8723B_2ANT_B_CONNECTION)) { 2527 pCoexSta->bBtLinkExist = false; 2528 pCoexSta->bPanExist = false; 2529 pCoexSta->bA2dpExist = false; 2530 pCoexSta->bHidExist = false; 2531 pCoexSta->bScoExist = false; 2532 } else { /* connection exists */ 2533 pCoexSta->bBtLinkExist = true; 2534 if (btInfo & BT_INFO_8723B_2ANT_B_FTP) 2535 pCoexSta->bPanExist = true; 2536 else 2537 pCoexSta->bPanExist = false; 2538 if (btInfo & BT_INFO_8723B_2ANT_B_A2DP) 2539 pCoexSta->bA2dpExist = true; 2540 else 2541 pCoexSta->bA2dpExist = false; 2542 if (btInfo & BT_INFO_8723B_2ANT_B_HID) 2543 pCoexSta->bHidExist = true; 2544 else 2545 pCoexSta->bHidExist = false; 2546 if (btInfo & BT_INFO_8723B_2ANT_B_SCO_ESCO) 2547 pCoexSta->bScoExist = true; 2548 else 2549 pCoexSta->bScoExist = false; 2550 } 2551 2552 halbtc8723b2ant_UpdateBtLinkInfo(pBtCoexist); 2553 2554 if (!(btInfo & BT_INFO_8723B_2ANT_B_CONNECTION)) { 2555 pCoexDm->btStatus = BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE; 2556 } else if (btInfo == BT_INFO_8723B_2ANT_B_CONNECTION) { /* connection exists but no busy */ 2557 pCoexDm->btStatus = BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE; 2558 } else if ( 2559 (btInfo & BT_INFO_8723B_2ANT_B_SCO_ESCO) || 2560 (btInfo & BT_INFO_8723B_2ANT_B_SCO_BUSY) 2561 ) { 2562 pCoexDm->btStatus = BT_8723B_2ANT_BT_STATUS_SCO_BUSY; 2563 } else if (btInfo & BT_INFO_8723B_2ANT_B_ACL_BUSY) { 2564 pCoexDm->btStatus = BT_8723B_2ANT_BT_STATUS_ACL_BUSY; 2565 } else { 2566 pCoexDm->btStatus = BT_8723B_2ANT_BT_STATUS_MAX; 2567 } 2568 2569 if ( 2570 (pCoexDm->btStatus == BT_8723B_2ANT_BT_STATUS_ACL_BUSY) || 2571 (pCoexDm->btStatus == BT_8723B_2ANT_BT_STATUS_SCO_BUSY) || 2572 (pCoexDm->btStatus == BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY) 2573 ) { 2574 bBtBusy = true; 2575 bLimitedDig = true; 2576 } else { 2577 bBtBusy = false; 2578 bLimitedDig = false; 2579 } 2580 2581 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); 2582 2583 pCoexDm->bLimitedDig = bLimitedDig; 2584 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &bLimitedDig); 2585 2586 halbtc8723b2ant_RunCoexistMechanism(pBtCoexist); 2587 } 2588 2589 void EXhalbtc8723b2ant_HaltNotify(struct btc_coexist *pBtCoexist) 2590 { 2591 halbtc8723b2ant_WifiOffHwCfg(pBtCoexist); 2592 pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x15); /* BT goto standby while GNT_BT 1-->0 */ 2593 halbtc8723b2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, true); 2594 2595 EXhalbtc8723b2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); 2596 } 2597 2598 void EXhalbtc8723b2ant_PnpNotify(struct btc_coexist *pBtCoexist, u8 pnpState) 2599 { 2600 if (pnpState == BTC_WIFI_PNP_SLEEP) { 2601 } else if (pnpState == BTC_WIFI_PNP_WAKE_UP) { 2602 halbtc8723b2ant_InitHwConfig(pBtCoexist, false); 2603 halbtc8723b2ant_InitCoexDm(pBtCoexist); 2604 halbtc8723b2ant_QueryBtInfo(pBtCoexist); 2605 } 2606 } 2607 2608 void EXhalbtc8723b2ant_Periodical(struct btc_coexist *pBtCoexist) 2609 { 2610 static u8 disVerInfoCnt; 2611 u32 fwVer = 0, btPatchVer = 0; 2612 2613 if (disVerInfoCnt <= 5) { 2614 disVerInfoCnt += 1; 2615 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); 2616 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); 2617 } 2618 2619 if ( 2620 halbtc8723b2ant_IsWifiStatusChanged(pBtCoexist) || 2621 pCoexDm->bAutoTdmaAdjust 2622 ) 2623 halbtc8723b2ant_RunCoexistMechanism(pBtCoexist); 2624 } 2625