1 /*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/export.h>
22 #include <linux/gpio.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/platform_data/b53.h>
26 #include <linux/phy.h>
27 #include <linux/phylink.h>
28 #include <linux/etherdevice.h>
29 #include <linux/if_bridge.h>
30 #include <linux/if_vlan.h>
31 #include <net/dsa.h>
32
33 #include "b53_regs.h"
34 #include "b53_priv.h"
35
36 struct b53_mib_desc {
37 u8 size;
38 u8 offset;
39 const char *name;
40 };
41
42 /* BCM5365 MIB counters */
43 static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
76 };
77
78 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
79
80 /* BCM63xx MIB counters */
81 static const struct b53_mib_desc b53_mibs_63xx[] = {
82 { 8, 0x00, "TxOctets" },
83 { 4, 0x08, "TxDropPkts" },
84 { 4, 0x0c, "TxQoSPkts" },
85 { 4, 0x10, "TxBroadcastPkts" },
86 { 4, 0x14, "TxMulticastPkts" },
87 { 4, 0x18, "TxUnicastPkts" },
88 { 4, 0x1c, "TxCollisions" },
89 { 4, 0x20, "TxSingleCollision" },
90 { 4, 0x24, "TxMultipleCollision" },
91 { 4, 0x28, "TxDeferredTransmit" },
92 { 4, 0x2c, "TxLateCollision" },
93 { 4, 0x30, "TxExcessiveCollision" },
94 { 4, 0x38, "TxPausePkts" },
95 { 8, 0x3c, "TxQoSOctets" },
96 { 8, 0x44, "RxOctets" },
97 { 4, 0x4c, "RxUndersizePkts" },
98 { 4, 0x50, "RxPausePkts" },
99 { 4, 0x54, "Pkts64Octets" },
100 { 4, 0x58, "Pkts65to127Octets" },
101 { 4, 0x5c, "Pkts128to255Octets" },
102 { 4, 0x60, "Pkts256to511Octets" },
103 { 4, 0x64, "Pkts512to1023Octets" },
104 { 4, 0x68, "Pkts1024to1522Octets" },
105 { 4, 0x6c, "RxOversizePkts" },
106 { 4, 0x70, "RxJabbers" },
107 { 4, 0x74, "RxAlignmentErrors" },
108 { 4, 0x78, "RxFCSErrors" },
109 { 8, 0x7c, "RxGoodOctets" },
110 { 4, 0x84, "RxDropPkts" },
111 { 4, 0x88, "RxUnicastPkts" },
112 { 4, 0x8c, "RxMulticastPkts" },
113 { 4, 0x90, "RxBroadcastPkts" },
114 { 4, 0x94, "RxSAChanges" },
115 { 4, 0x98, "RxFragments" },
116 { 4, 0xa0, "RxSymbolErrors" },
117 { 4, 0xa4, "RxQoSPkts" },
118 { 8, 0xa8, "RxQoSOctets" },
119 { 4, 0xb0, "Pkts1523to2047Octets" },
120 { 4, 0xb4, "Pkts2048to4095Octets" },
121 { 4, 0xb8, "Pkts4096to8191Octets" },
122 { 4, 0xbc, "Pkts8192to9728Octets" },
123 { 4, 0xc0, "RxDiscarded" },
124 };
125
126 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
127
128 /* MIB counters */
129 static const struct b53_mib_desc b53_mibs[] = {
130 { 8, 0x00, "TxOctets" },
131 { 4, 0x08, "TxDropPkts" },
132 { 4, 0x10, "TxBroadcastPkts" },
133 { 4, 0x14, "TxMulticastPkts" },
134 { 4, 0x18, "TxUnicastPkts" },
135 { 4, 0x1c, "TxCollisions" },
136 { 4, 0x20, "TxSingleCollision" },
137 { 4, 0x24, "TxMultipleCollision" },
138 { 4, 0x28, "TxDeferredTransmit" },
139 { 4, 0x2c, "TxLateCollision" },
140 { 4, 0x30, "TxExcessiveCollision" },
141 { 4, 0x38, "TxPausePkts" },
142 { 8, 0x50, "RxOctets" },
143 { 4, 0x58, "RxUndersizePkts" },
144 { 4, 0x5c, "RxPausePkts" },
145 { 4, 0x60, "Pkts64Octets" },
146 { 4, 0x64, "Pkts65to127Octets" },
147 { 4, 0x68, "Pkts128to255Octets" },
148 { 4, 0x6c, "Pkts256to511Octets" },
149 { 4, 0x70, "Pkts512to1023Octets" },
150 { 4, 0x74, "Pkts1024to1522Octets" },
151 { 4, 0x78, "RxOversizePkts" },
152 { 4, 0x7c, "RxJabbers" },
153 { 4, 0x80, "RxAlignmentErrors" },
154 { 4, 0x84, "RxFCSErrors" },
155 { 8, 0x88, "RxGoodOctets" },
156 { 4, 0x90, "RxDropPkts" },
157 { 4, 0x94, "RxUnicastPkts" },
158 { 4, 0x98, "RxMulticastPkts" },
159 { 4, 0x9c, "RxBroadcastPkts" },
160 { 4, 0xa0, "RxSAChanges" },
161 { 4, 0xa4, "RxFragments" },
162 { 4, 0xa8, "RxJumboPkts" },
163 { 4, 0xac, "RxSymbolErrors" },
164 { 4, 0xc0, "RxDiscarded" },
165 };
166
167 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
168
169 static const struct b53_mib_desc b53_mibs_58xx[] = {
170 { 8, 0x00, "TxOctets" },
171 { 4, 0x08, "TxDropPkts" },
172 { 4, 0x0c, "TxQPKTQ0" },
173 { 4, 0x10, "TxBroadcastPkts" },
174 { 4, 0x14, "TxMulticastPkts" },
175 { 4, 0x18, "TxUnicastPKts" },
176 { 4, 0x1c, "TxCollisions" },
177 { 4, 0x20, "TxSingleCollision" },
178 { 4, 0x24, "TxMultipleCollision" },
179 { 4, 0x28, "TxDeferredCollision" },
180 { 4, 0x2c, "TxLateCollision" },
181 { 4, 0x30, "TxExcessiveCollision" },
182 { 4, 0x34, "TxFrameInDisc" },
183 { 4, 0x38, "TxPausePkts" },
184 { 4, 0x3c, "TxQPKTQ1" },
185 { 4, 0x40, "TxQPKTQ2" },
186 { 4, 0x44, "TxQPKTQ3" },
187 { 4, 0x48, "TxQPKTQ4" },
188 { 4, 0x4c, "TxQPKTQ5" },
189 { 8, 0x50, "RxOctets" },
190 { 4, 0x58, "RxUndersizePkts" },
191 { 4, 0x5c, "RxPausePkts" },
192 { 4, 0x60, "RxPkts64Octets" },
193 { 4, 0x64, "RxPkts65to127Octets" },
194 { 4, 0x68, "RxPkts128to255Octets" },
195 { 4, 0x6c, "RxPkts256to511Octets" },
196 { 4, 0x70, "RxPkts512to1023Octets" },
197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
198 { 4, 0x78, "RxOversizePkts" },
199 { 4, 0x7c, "RxJabbers" },
200 { 4, 0x80, "RxAlignmentErrors" },
201 { 4, 0x84, "RxFCSErrors" },
202 { 8, 0x88, "RxGoodOctets" },
203 { 4, 0x90, "RxDropPkts" },
204 { 4, 0x94, "RxUnicastPkts" },
205 { 4, 0x98, "RxMulticastPkts" },
206 { 4, 0x9c, "RxBroadcastPkts" },
207 { 4, 0xa0, "RxSAChanges" },
208 { 4, 0xa4, "RxFragments" },
209 { 4, 0xa8, "RxJumboPkt" },
210 { 4, 0xac, "RxSymblErr" },
211 { 4, 0xb0, "InRangeErrCount" },
212 { 4, 0xb4, "OutRangeErrCount" },
213 { 4, 0xb8, "EEELpiEvent" },
214 { 4, 0xbc, "EEELpiDuration" },
215 { 4, 0xc0, "RxDiscard" },
216 { 4, 0xc8, "TxQPKTQ6" },
217 { 4, 0xcc, "TxQPKTQ7" },
218 { 4, 0xd0, "TxPkts64Octets" },
219 { 4, 0xd4, "TxPkts65to127Octets" },
220 { 4, 0xd8, "TxPkts128to255Octets" },
221 { 4, 0xdc, "TxPkts256to511Ocets" },
222 { 4, 0xe0, "TxPkts512to1023Ocets" },
223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
224 };
225
226 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
227
228 #define B53_MAX_MTU_25 (1536 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN)
229 #define B53_MAX_MTU (9720 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN)
230
b53_do_vlan_op(struct b53_device * dev,u8 op)231 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
232 {
233 unsigned int i;
234
235 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
236
237 for (i = 0; i < 10; i++) {
238 u8 vta;
239
240 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
241 if (!(vta & VTA_START_CMD))
242 return 0;
243
244 usleep_range(100, 200);
245 }
246
247 return -EIO;
248 }
249
b53_set_vlan_entry(struct b53_device * dev,u16 vid,struct b53_vlan * vlan)250 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
251 struct b53_vlan *vlan)
252 {
253 if (is5325(dev)) {
254 u32 entry = 0;
255
256 if (vlan->members) {
257 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
258 VA_UNTAG_S_25) | vlan->members;
259 if (dev->core_rev >= 3)
260 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
261 else
262 entry |= VA_VALID_25;
263 }
264
265 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
266 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
267 VTA_RW_STATE_WR | VTA_RW_OP_EN);
268 } else if (is5365(dev)) {
269 u16 entry = 0;
270
271 if (vlan->members)
272 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
273 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
274
275 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
276 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
277 VTA_RW_STATE_WR | VTA_RW_OP_EN);
278 } else {
279 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
280 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
281 (vlan->untag << VTE_UNTAG_S) | vlan->members);
282
283 b53_do_vlan_op(dev, VTA_CMD_WRITE);
284 }
285
286 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
287 vid, vlan->members, vlan->untag);
288 }
289
b53_get_vlan_entry(struct b53_device * dev,u16 vid,struct b53_vlan * vlan)290 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
291 struct b53_vlan *vlan)
292 {
293 if (is5325(dev)) {
294 u32 entry = 0;
295
296 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
297 VTA_RW_STATE_RD | VTA_RW_OP_EN);
298 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
299
300 if (dev->core_rev >= 3)
301 vlan->valid = !!(entry & VA_VALID_25_R4);
302 else
303 vlan->valid = !!(entry & VA_VALID_25);
304 vlan->members = entry & VA_MEMBER_MASK;
305 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
306
307 } else if (is5365(dev)) {
308 u16 entry = 0;
309
310 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
311 VTA_RW_STATE_WR | VTA_RW_OP_EN);
312 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
313
314 vlan->valid = !!(entry & VA_VALID_65);
315 vlan->members = entry & VA_MEMBER_MASK;
316 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
317 } else {
318 u32 entry = 0;
319
320 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
321 b53_do_vlan_op(dev, VTA_CMD_READ);
322 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
323 vlan->members = entry & VTE_MEMBERS;
324 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
325 vlan->valid = true;
326 }
327 }
328
b53_set_forwarding(struct b53_device * dev,int enable)329 static void b53_set_forwarding(struct b53_device *dev, int enable)
330 {
331 u8 mgmt;
332
333 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
334
335 if (enable)
336 mgmt |= SM_SW_FWD_EN;
337 else
338 mgmt &= ~SM_SW_FWD_EN;
339
340 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
341
342 /* Include IMP port in dumb forwarding mode
343 */
344 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
345 mgmt |= B53_MII_DUMB_FWDG_EN;
346 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
347
348 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether
349 * frames should be flooded or not.
350 */
351 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt);
352 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN;
353 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt);
354 }
355
b53_enable_vlan(struct b53_device * dev,int port,bool enable,bool enable_filtering)356 static void b53_enable_vlan(struct b53_device *dev, int port, bool enable,
357 bool enable_filtering)
358 {
359 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
360
361 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
364
365 if (is5325(dev) || is5365(dev)) {
366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
367 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
368 } else if (is63xx(dev)) {
369 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
370 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
371 } else {
372 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
373 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
374 }
375
376 if (enable) {
377 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
378 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
379 vc4 &= ~VC4_ING_VID_CHECK_MASK;
380 if (enable_filtering) {
381 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
382 vc5 |= VC5_DROP_VTABLE_MISS;
383 } else {
384 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
385 vc5 &= ~VC5_DROP_VTABLE_MISS;
386 }
387
388 if (is5325(dev))
389 vc0 &= ~VC0_RESERVED_1;
390
391 if (is5325(dev) || is5365(dev))
392 vc1 |= VC1_RX_MCST_TAG_EN;
393
394 } else {
395 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
396 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
397 vc4 &= ~VC4_ING_VID_CHECK_MASK;
398 vc5 &= ~VC5_DROP_VTABLE_MISS;
399
400 if (is5325(dev) || is5365(dev))
401 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
402 else
403 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
404
405 if (is5325(dev) || is5365(dev))
406 vc1 &= ~VC1_RX_MCST_TAG_EN;
407 }
408
409 if (!is5325(dev) && !is5365(dev))
410 vc5 &= ~VC5_VID_FFF_EN;
411
412 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
414
415 if (is5325(dev) || is5365(dev)) {
416 /* enable the high 8 bit vid check on 5325 */
417 if (is5325(dev) && enable)
418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
419 VC3_HIGH_8BIT_EN);
420 else
421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
422
423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
425 } else if (is63xx(dev)) {
426 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
427 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
428 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
429 } else {
430 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
431 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
432 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
433 }
434
435 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
436
437 dev->vlan_enabled = enable;
438
439 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n",
440 port, enable, enable_filtering);
441 }
442
b53_set_jumbo(struct b53_device * dev,bool enable,bool allow_10_100)443 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
444 {
445 u32 port_mask = 0;
446 u16 max_size = JMS_MIN_SIZE;
447
448 if (is5325(dev) || is5365(dev))
449 return -EINVAL;
450
451 if (enable) {
452 port_mask = dev->enabled_ports;
453 max_size = JMS_MAX_SIZE;
454 if (allow_10_100)
455 port_mask |= JPM_10_100_JUMBO_EN;
456 }
457
458 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
459 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
460 }
461
b53_flush_arl(struct b53_device * dev,u8 mask)462 static int b53_flush_arl(struct b53_device *dev, u8 mask)
463 {
464 unsigned int i;
465
466 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
467 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
468
469 for (i = 0; i < 10; i++) {
470 u8 fast_age_ctrl;
471
472 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
473 &fast_age_ctrl);
474
475 if (!(fast_age_ctrl & FAST_AGE_DONE))
476 goto out;
477
478 msleep(1);
479 }
480
481 return -ETIMEDOUT;
482 out:
483 /* Only age dynamic entries (default behavior) */
484 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
485 return 0;
486 }
487
b53_fast_age_port(struct b53_device * dev,int port)488 static int b53_fast_age_port(struct b53_device *dev, int port)
489 {
490 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
491
492 return b53_flush_arl(dev, FAST_AGE_PORT);
493 }
494
b53_fast_age_vlan(struct b53_device * dev,u16 vid)495 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
496 {
497 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
498
499 return b53_flush_arl(dev, FAST_AGE_VLAN);
500 }
501
b53_imp_vlan_setup(struct dsa_switch * ds,int cpu_port)502 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
503 {
504 struct b53_device *dev = ds->priv;
505 unsigned int i;
506 u16 pvlan;
507
508 /* Enable the IMP port to be in the same VLAN as the other ports
509 * on a per-port basis such that we only have Port i and IMP in
510 * the same VLAN.
511 */
512 b53_for_each_port(dev, i) {
513 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
514 pvlan |= BIT(cpu_port);
515 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
516 }
517 }
518 EXPORT_SYMBOL(b53_imp_vlan_setup);
519
b53_port_set_ucast_flood(struct b53_device * dev,int port,bool unicast)520 static void b53_port_set_ucast_flood(struct b53_device *dev, int port,
521 bool unicast)
522 {
523 u16 uc;
524
525 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc);
526 if (unicast)
527 uc |= BIT(port);
528 else
529 uc &= ~BIT(port);
530 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc);
531 }
532
b53_port_set_mcast_flood(struct b53_device * dev,int port,bool multicast)533 static void b53_port_set_mcast_flood(struct b53_device *dev, int port,
534 bool multicast)
535 {
536 u16 mc;
537
538 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc);
539 if (multicast)
540 mc |= BIT(port);
541 else
542 mc &= ~BIT(port);
543 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc);
544
545 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc);
546 if (multicast)
547 mc |= BIT(port);
548 else
549 mc &= ~BIT(port);
550 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc);
551 }
552
b53_port_set_learning(struct b53_device * dev,int port,bool learning)553 static void b53_port_set_learning(struct b53_device *dev, int port,
554 bool learning)
555 {
556 u16 reg;
557
558 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®);
559 if (learning)
560 reg &= ~BIT(port);
561 else
562 reg |= BIT(port);
563 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg);
564 }
565
b53_eee_enable_set(struct dsa_switch * ds,int port,bool enable)566 static void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
567 {
568 struct b53_device *dev = ds->priv;
569 u16 reg;
570
571 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®);
572 if (enable)
573 reg |= BIT(port);
574 else
575 reg &= ~BIT(port);
576 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
577 }
578
b53_enable_port(struct dsa_switch * ds,int port,struct phy_device * phy)579 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
580 {
581 struct b53_device *dev = ds->priv;
582 unsigned int cpu_port;
583 int ret = 0;
584 u16 pvlan;
585
586 if (!dsa_is_user_port(ds, port))
587 return 0;
588
589 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
590
591 b53_port_set_ucast_flood(dev, port, true);
592 b53_port_set_mcast_flood(dev, port, true);
593 b53_port_set_learning(dev, port, false);
594
595 if (dev->ops->irq_enable)
596 ret = dev->ops->irq_enable(dev, port);
597 if (ret)
598 return ret;
599
600 /* Clear the Rx and Tx disable bits and set to no spanning tree */
601 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
602
603 /* Set this port, and only this one to be in the default VLAN,
604 * if member of a bridge, restore its membership prior to
605 * bringing down this port.
606 */
607 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
608 pvlan &= ~0x1ff;
609 pvlan |= BIT(port);
610 pvlan |= dev->ports[port].vlan_ctl_mask;
611 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
612
613 b53_imp_vlan_setup(ds, cpu_port);
614
615 /* If EEE was enabled, restore it */
616 if (dev->ports[port].eee.eee_enabled)
617 b53_eee_enable_set(ds, port, true);
618
619 return 0;
620 }
621 EXPORT_SYMBOL(b53_enable_port);
622
b53_disable_port(struct dsa_switch * ds,int port)623 void b53_disable_port(struct dsa_switch *ds, int port)
624 {
625 struct b53_device *dev = ds->priv;
626 u8 reg;
627
628 /* Disable Tx/Rx for the port */
629 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
630 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
631 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
632
633 if (dev->ops->irq_disable)
634 dev->ops->irq_disable(dev, port);
635 }
636 EXPORT_SYMBOL(b53_disable_port);
637
b53_brcm_hdr_setup(struct dsa_switch * ds,int port)638 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
639 {
640 struct b53_device *dev = ds->priv;
641 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE);
642 u8 hdr_ctl, val;
643 u16 reg;
644
645 /* Resolve which bit controls the Broadcom tag */
646 switch (port) {
647 case 8:
648 val = BRCM_HDR_P8_EN;
649 break;
650 case 7:
651 val = BRCM_HDR_P7_EN;
652 break;
653 case 5:
654 val = BRCM_HDR_P5_EN;
655 break;
656 default:
657 val = 0;
658 break;
659 }
660
661 /* Enable management mode if tagging is requested */
662 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl);
663 if (tag_en)
664 hdr_ctl |= SM_SW_FWD_MODE;
665 else
666 hdr_ctl &= ~SM_SW_FWD_MODE;
667 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl);
668
669 /* Configure the appropriate IMP port */
670 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl);
671 if (port == 8)
672 hdr_ctl |= GC_FRM_MGMT_PORT_MII;
673 else if (port == 5)
674 hdr_ctl |= GC_FRM_MGMT_PORT_M;
675 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl);
676
677 /* Enable Broadcom tags for IMP port */
678 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
679 if (tag_en)
680 hdr_ctl |= val;
681 else
682 hdr_ctl &= ~val;
683 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
684
685 /* Registers below are only accessible on newer devices */
686 if (!is58xx(dev))
687 return;
688
689 /* Enable reception Broadcom tag for CPU TX (switch RX) to
690 * allow us to tag outgoing frames
691 */
692 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®);
693 if (tag_en)
694 reg &= ~BIT(port);
695 else
696 reg |= BIT(port);
697 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
698
699 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
700 * allow delivering frames to the per-port net_devices
701 */
702 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®);
703 if (tag_en)
704 reg &= ~BIT(port);
705 else
706 reg |= BIT(port);
707 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
708 }
709 EXPORT_SYMBOL(b53_brcm_hdr_setup);
710
b53_enable_cpu_port(struct b53_device * dev,int port)711 static void b53_enable_cpu_port(struct b53_device *dev, int port)
712 {
713 u8 port_ctrl;
714
715 /* BCM5325 CPU port is at 8 */
716 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
717 port = B53_CPU_PORT;
718
719 port_ctrl = PORT_CTRL_RX_BCST_EN |
720 PORT_CTRL_RX_MCST_EN |
721 PORT_CTRL_RX_UCST_EN;
722 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
723
724 b53_brcm_hdr_setup(dev->ds, port);
725
726 b53_port_set_ucast_flood(dev, port, true);
727 b53_port_set_mcast_flood(dev, port, true);
728 b53_port_set_learning(dev, port, false);
729 }
730
b53_enable_mib(struct b53_device * dev)731 static void b53_enable_mib(struct b53_device *dev)
732 {
733 u8 gc;
734
735 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
736 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
737 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
738 }
739
b53_default_pvid(struct b53_device * dev)740 static u16 b53_default_pvid(struct b53_device *dev)
741 {
742 if (is5325(dev) || is5365(dev))
743 return 1;
744 else
745 return 0;
746 }
747
b53_vlan_port_needs_forced_tagged(struct dsa_switch * ds,int port)748 static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port)
749 {
750 struct b53_device *dev = ds->priv;
751
752 return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port);
753 }
754
b53_configure_vlan(struct dsa_switch * ds)755 int b53_configure_vlan(struct dsa_switch *ds)
756 {
757 struct b53_device *dev = ds->priv;
758 struct b53_vlan vl = { 0 };
759 struct b53_vlan *v;
760 int i, def_vid;
761 u16 vid;
762
763 def_vid = b53_default_pvid(dev);
764
765 /* clear all vlan entries */
766 if (is5325(dev) || is5365(dev)) {
767 for (i = def_vid; i < dev->num_vlans; i++)
768 b53_set_vlan_entry(dev, i, &vl);
769 } else {
770 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
771 }
772
773 b53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering);
774
775 /* Create an untagged VLAN entry for the default PVID in case
776 * CONFIG_VLAN_8021Q is disabled and there are no calls to
777 * dsa_user_vlan_rx_add_vid() to create the default VLAN
778 * entry. Do this only when the tagging protocol is not
779 * DSA_TAG_PROTO_NONE
780 */
781 b53_for_each_port(dev, i) {
782 v = &dev->vlans[def_vid];
783 v->members |= BIT(i);
784 if (!b53_vlan_port_needs_forced_tagged(ds, i))
785 v->untag = v->members;
786 b53_write16(dev, B53_VLAN_PAGE,
787 B53_VLAN_PORT_DEF_TAG(i), def_vid);
788 }
789
790 /* Upon initial call we have not set-up any VLANs, but upon
791 * system resume, we need to restore all VLAN entries.
792 */
793 for (vid = def_vid; vid < dev->num_vlans; vid++) {
794 v = &dev->vlans[vid];
795
796 if (!v->members)
797 continue;
798
799 b53_set_vlan_entry(dev, vid, v);
800 b53_fast_age_vlan(dev, vid);
801 }
802
803 return 0;
804 }
805 EXPORT_SYMBOL(b53_configure_vlan);
806
b53_switch_reset_gpio(struct b53_device * dev)807 static void b53_switch_reset_gpio(struct b53_device *dev)
808 {
809 int gpio = dev->reset_gpio;
810
811 if (gpio < 0)
812 return;
813
814 /* Reset sequence: RESET low(50ms)->high(20ms)
815 */
816 gpio_set_value(gpio, 0);
817 mdelay(50);
818
819 gpio_set_value(gpio, 1);
820 mdelay(20);
821
822 dev->current_page = 0xff;
823 }
824
b53_switch_reset(struct b53_device * dev)825 static int b53_switch_reset(struct b53_device *dev)
826 {
827 unsigned int timeout = 1000;
828 u8 mgmt, reg;
829
830 b53_switch_reset_gpio(dev);
831
832 if (is539x(dev)) {
833 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
834 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
835 }
836
837 /* This is specific to 58xx devices here, do not use is58xx() which
838 * covers the larger Starfigther 2 family, including 7445/7278 which
839 * still use this driver as a library and need to perform the reset
840 * earlier.
841 */
842 if (dev->chip_id == BCM58XX_DEVICE_ID ||
843 dev->chip_id == BCM583XX_DEVICE_ID) {
844 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
845 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
846 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
847
848 do {
849 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
850 if (!(reg & SW_RST))
851 break;
852
853 usleep_range(1000, 2000);
854 } while (timeout-- > 0);
855
856 if (timeout == 0) {
857 dev_err(dev->dev,
858 "Timeout waiting for SW_RST to clear!\n");
859 return -ETIMEDOUT;
860 }
861 }
862
863 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
864
865 if (!(mgmt & SM_SW_FWD_EN)) {
866 mgmt &= ~SM_SW_FWD_MODE;
867 mgmt |= SM_SW_FWD_EN;
868
869 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
870 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
871
872 if (!(mgmt & SM_SW_FWD_EN)) {
873 dev_err(dev->dev, "Failed to enable switch!\n");
874 return -EINVAL;
875 }
876 }
877
878 b53_enable_mib(dev);
879
880 return b53_flush_arl(dev, FAST_AGE_STATIC);
881 }
882
b53_phy_read16(struct dsa_switch * ds,int addr,int reg)883 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
884 {
885 struct b53_device *priv = ds->priv;
886 u16 value = 0;
887 int ret;
888
889 if (priv->ops->phy_read16)
890 ret = priv->ops->phy_read16(priv, addr, reg, &value);
891 else
892 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
893 reg * 2, &value);
894
895 return ret ? ret : value;
896 }
897
b53_phy_write16(struct dsa_switch * ds,int addr,int reg,u16 val)898 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
899 {
900 struct b53_device *priv = ds->priv;
901
902 if (priv->ops->phy_write16)
903 return priv->ops->phy_write16(priv, addr, reg, val);
904
905 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
906 }
907
b53_reset_switch(struct b53_device * priv)908 static int b53_reset_switch(struct b53_device *priv)
909 {
910 /* reset vlans */
911 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
912 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
913
914 priv->serdes_lane = B53_INVALID_LANE;
915
916 return b53_switch_reset(priv);
917 }
918
b53_apply_config(struct b53_device * priv)919 static int b53_apply_config(struct b53_device *priv)
920 {
921 /* disable switching */
922 b53_set_forwarding(priv, 0);
923
924 b53_configure_vlan(priv->ds);
925
926 /* enable switching */
927 b53_set_forwarding(priv, 1);
928
929 return 0;
930 }
931
b53_reset_mib(struct b53_device * priv)932 static void b53_reset_mib(struct b53_device *priv)
933 {
934 u8 gc;
935
936 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
937
938 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
939 msleep(1);
940 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
941 msleep(1);
942 }
943
b53_get_mib(struct b53_device * dev)944 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
945 {
946 if (is5365(dev))
947 return b53_mibs_65;
948 else if (is63xx(dev))
949 return b53_mibs_63xx;
950 else if (is58xx(dev))
951 return b53_mibs_58xx;
952 else
953 return b53_mibs;
954 }
955
b53_get_mib_size(struct b53_device * dev)956 static unsigned int b53_get_mib_size(struct b53_device *dev)
957 {
958 if (is5365(dev))
959 return B53_MIBS_65_SIZE;
960 else if (is63xx(dev))
961 return B53_MIBS_63XX_SIZE;
962 else if (is58xx(dev))
963 return B53_MIBS_58XX_SIZE;
964 else
965 return B53_MIBS_SIZE;
966 }
967
b53_get_phy_device(struct dsa_switch * ds,int port)968 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
969 {
970 /* These ports typically do not have built-in PHYs */
971 switch (port) {
972 case B53_CPU_PORT_25:
973 case 7:
974 case B53_CPU_PORT:
975 return NULL;
976 }
977
978 return mdiobus_get_phy(ds->user_mii_bus, port);
979 }
980
b53_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)981 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
982 uint8_t *data)
983 {
984 struct b53_device *dev = ds->priv;
985 const struct b53_mib_desc *mibs = b53_get_mib(dev);
986 unsigned int mib_size = b53_get_mib_size(dev);
987 struct phy_device *phydev;
988 unsigned int i;
989
990 if (stringset == ETH_SS_STATS) {
991 for (i = 0; i < mib_size; i++)
992 strscpy(data + i * ETH_GSTRING_LEN,
993 mibs[i].name, ETH_GSTRING_LEN);
994 } else if (stringset == ETH_SS_PHY_STATS) {
995 phydev = b53_get_phy_device(ds, port);
996 if (!phydev)
997 return;
998
999 phy_ethtool_get_strings(phydev, data);
1000 }
1001 }
1002 EXPORT_SYMBOL(b53_get_strings);
1003
b53_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1004 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
1005 {
1006 struct b53_device *dev = ds->priv;
1007 const struct b53_mib_desc *mibs = b53_get_mib(dev);
1008 unsigned int mib_size = b53_get_mib_size(dev);
1009 const struct b53_mib_desc *s;
1010 unsigned int i;
1011 u64 val = 0;
1012
1013 if (is5365(dev) && port == 5)
1014 port = 8;
1015
1016 mutex_lock(&dev->stats_mutex);
1017
1018 for (i = 0; i < mib_size; i++) {
1019 s = &mibs[i];
1020
1021 if (s->size == 8) {
1022 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
1023 } else {
1024 u32 val32;
1025
1026 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
1027 &val32);
1028 val = val32;
1029 }
1030 data[i] = (u64)val;
1031 }
1032
1033 mutex_unlock(&dev->stats_mutex);
1034 }
1035 EXPORT_SYMBOL(b53_get_ethtool_stats);
1036
b53_get_ethtool_phy_stats(struct dsa_switch * ds,int port,uint64_t * data)1037 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
1038 {
1039 struct phy_device *phydev;
1040
1041 phydev = b53_get_phy_device(ds, port);
1042 if (!phydev)
1043 return;
1044
1045 phy_ethtool_get_stats(phydev, NULL, data);
1046 }
1047 EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
1048
b53_get_sset_count(struct dsa_switch * ds,int port,int sset)1049 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
1050 {
1051 struct b53_device *dev = ds->priv;
1052 struct phy_device *phydev;
1053
1054 if (sset == ETH_SS_STATS) {
1055 return b53_get_mib_size(dev);
1056 } else if (sset == ETH_SS_PHY_STATS) {
1057 phydev = b53_get_phy_device(ds, port);
1058 if (!phydev)
1059 return 0;
1060
1061 return phy_ethtool_get_sset_count(phydev);
1062 }
1063
1064 return 0;
1065 }
1066 EXPORT_SYMBOL(b53_get_sset_count);
1067
1068 enum b53_devlink_resource_id {
1069 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1070 };
1071
b53_devlink_vlan_table_get(void * priv)1072 static u64 b53_devlink_vlan_table_get(void *priv)
1073 {
1074 struct b53_device *dev = priv;
1075 struct b53_vlan *vl;
1076 unsigned int i;
1077 u64 count = 0;
1078
1079 for (i = 0; i < dev->num_vlans; i++) {
1080 vl = &dev->vlans[i];
1081 if (vl->members)
1082 count++;
1083 }
1084
1085 return count;
1086 }
1087
b53_setup_devlink_resources(struct dsa_switch * ds)1088 int b53_setup_devlink_resources(struct dsa_switch *ds)
1089 {
1090 struct devlink_resource_size_params size_params;
1091 struct b53_device *dev = ds->priv;
1092 int err;
1093
1094 devlink_resource_size_params_init(&size_params, dev->num_vlans,
1095 dev->num_vlans,
1096 1, DEVLINK_RESOURCE_UNIT_ENTRY);
1097
1098 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans,
1099 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1100 DEVLINK_RESOURCE_ID_PARENT_TOP,
1101 &size_params);
1102 if (err)
1103 goto out;
1104
1105 dsa_devlink_resource_occ_get_register(ds,
1106 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1107 b53_devlink_vlan_table_get, dev);
1108
1109 return 0;
1110 out:
1111 dsa_devlink_resources_unregister(ds);
1112 return err;
1113 }
1114 EXPORT_SYMBOL(b53_setup_devlink_resources);
1115
b53_setup(struct dsa_switch * ds)1116 static int b53_setup(struct dsa_switch *ds)
1117 {
1118 struct b53_device *dev = ds->priv;
1119 unsigned int port;
1120 int ret;
1121
1122 /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set
1123 * which forces the CPU port to be tagged in all VLANs.
1124 */
1125 ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE;
1126
1127 ret = b53_reset_switch(dev);
1128 if (ret) {
1129 dev_err(ds->dev, "failed to reset switch\n");
1130 return ret;
1131 }
1132
1133 b53_reset_mib(dev);
1134
1135 ret = b53_apply_config(dev);
1136 if (ret) {
1137 dev_err(ds->dev, "failed to apply configuration\n");
1138 return ret;
1139 }
1140
1141 /* Configure IMP/CPU port, disable all other ports. Enabled
1142 * ports will be configured with .port_enable
1143 */
1144 for (port = 0; port < dev->num_ports; port++) {
1145 if (dsa_is_cpu_port(ds, port))
1146 b53_enable_cpu_port(dev, port);
1147 else
1148 b53_disable_port(ds, port);
1149 }
1150
1151 return b53_setup_devlink_resources(ds);
1152 }
1153
b53_teardown(struct dsa_switch * ds)1154 static void b53_teardown(struct dsa_switch *ds)
1155 {
1156 dsa_devlink_resources_unregister(ds);
1157 }
1158
b53_force_link(struct b53_device * dev,int port,int link)1159 static void b53_force_link(struct b53_device *dev, int port, int link)
1160 {
1161 u8 reg, val, off;
1162
1163 /* Override the port settings */
1164 if (port == dev->imp_port) {
1165 off = B53_PORT_OVERRIDE_CTRL;
1166 val = PORT_OVERRIDE_EN;
1167 } else {
1168 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1169 val = GMII_PO_EN;
1170 }
1171
1172 b53_read8(dev, B53_CTRL_PAGE, off, ®);
1173 reg |= val;
1174 if (link)
1175 reg |= PORT_OVERRIDE_LINK;
1176 else
1177 reg &= ~PORT_OVERRIDE_LINK;
1178 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1179 }
1180
b53_force_port_config(struct b53_device * dev,int port,int speed,int duplex,bool tx_pause,bool rx_pause)1181 static void b53_force_port_config(struct b53_device *dev, int port,
1182 int speed, int duplex,
1183 bool tx_pause, bool rx_pause)
1184 {
1185 u8 reg, val, off;
1186
1187 /* Override the port settings */
1188 if (port == dev->imp_port) {
1189 off = B53_PORT_OVERRIDE_CTRL;
1190 val = PORT_OVERRIDE_EN;
1191 } else {
1192 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1193 val = GMII_PO_EN;
1194 }
1195
1196 b53_read8(dev, B53_CTRL_PAGE, off, ®);
1197 reg |= val;
1198 if (duplex == DUPLEX_FULL)
1199 reg |= PORT_OVERRIDE_FULL_DUPLEX;
1200 else
1201 reg &= ~PORT_OVERRIDE_FULL_DUPLEX;
1202
1203 switch (speed) {
1204 case 2000:
1205 reg |= PORT_OVERRIDE_SPEED_2000M;
1206 fallthrough;
1207 case SPEED_1000:
1208 reg |= PORT_OVERRIDE_SPEED_1000M;
1209 break;
1210 case SPEED_100:
1211 reg |= PORT_OVERRIDE_SPEED_100M;
1212 break;
1213 case SPEED_10:
1214 reg |= PORT_OVERRIDE_SPEED_10M;
1215 break;
1216 default:
1217 dev_err(dev->dev, "unknown speed: %d\n", speed);
1218 return;
1219 }
1220
1221 if (rx_pause)
1222 reg |= PORT_OVERRIDE_RX_FLOW;
1223 if (tx_pause)
1224 reg |= PORT_OVERRIDE_TX_FLOW;
1225
1226 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1227 }
1228
b53_adjust_63xx_rgmii(struct dsa_switch * ds,int port,phy_interface_t interface)1229 static void b53_adjust_63xx_rgmii(struct dsa_switch *ds, int port,
1230 phy_interface_t interface)
1231 {
1232 struct b53_device *dev = ds->priv;
1233 u8 rgmii_ctrl = 0, off;
1234
1235 if (port == dev->imp_port)
1236 off = B53_RGMII_CTRL_IMP;
1237 else
1238 off = B53_RGMII_CTRL_P(port);
1239
1240 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1241
1242 switch (interface) {
1243 case PHY_INTERFACE_MODE_RGMII_ID:
1244 rgmii_ctrl |= (RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC);
1245 break;
1246 case PHY_INTERFACE_MODE_RGMII_RXID:
1247 rgmii_ctrl &= ~(RGMII_CTRL_DLL_TXC);
1248 rgmii_ctrl |= RGMII_CTRL_DLL_RXC;
1249 break;
1250 case PHY_INTERFACE_MODE_RGMII_TXID:
1251 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC);
1252 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1253 break;
1254 case PHY_INTERFACE_MODE_RGMII:
1255 default:
1256 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC);
1257 break;
1258 }
1259
1260 if (port != dev->imp_port) {
1261 if (is63268(dev))
1262 rgmii_ctrl |= RGMII_CTRL_MII_OVERRIDE;
1263
1264 rgmii_ctrl |= RGMII_CTRL_ENABLE_GMII;
1265 }
1266
1267 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1268
1269 dev_dbg(ds->dev, "Configured port %d for %s\n", port,
1270 phy_modes(interface));
1271 }
1272
b53_adjust_531x5_rgmii(struct dsa_switch * ds,int port,phy_interface_t interface)1273 static void b53_adjust_531x5_rgmii(struct dsa_switch *ds, int port,
1274 phy_interface_t interface)
1275 {
1276 struct b53_device *dev = ds->priv;
1277 u8 rgmii_ctrl = 0, off;
1278
1279 if (port == dev->imp_port)
1280 off = B53_RGMII_CTRL_IMP;
1281 else
1282 off = B53_RGMII_CTRL_P(port);
1283
1284 /* Configure the port RGMII clock delay by DLL disabled and
1285 * tx_clk aligned timing (restoring to reset defaults)
1286 */
1287 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1288 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1289 RGMII_CTRL_TIMING_SEL);
1290
1291 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1292 * sure that we enable the port TX clock internal delay to
1293 * account for this internal delay that is inserted, otherwise
1294 * the switch won't be able to receive correctly.
1295 *
1296 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1297 * any delay neither on transmission nor reception, so the
1298 * BCM53125 must also be configured accordingly to account for
1299 * the lack of delay and introduce
1300 *
1301 * The BCM53125 switch has its RX clock and TX clock control
1302 * swapped, hence the reason why we modify the TX clock path in
1303 * the "RGMII" case
1304 */
1305 if (interface == PHY_INTERFACE_MODE_RGMII_TXID)
1306 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1307 if (interface == PHY_INTERFACE_MODE_RGMII)
1308 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1309 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1310 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1311
1312 dev_info(ds->dev, "Configured port %d for %s\n", port,
1313 phy_modes(interface));
1314 }
1315
b53_adjust_5325_mii(struct dsa_switch * ds,int port)1316 static void b53_adjust_5325_mii(struct dsa_switch *ds, int port)
1317 {
1318 struct b53_device *dev = ds->priv;
1319 u8 reg = 0;
1320
1321 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1322 ®);
1323
1324 /* reverse mii needs to be enabled */
1325 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1326 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1327 reg | PORT_OVERRIDE_RV_MII_25);
1328 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1329 ®);
1330
1331 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1332 dev_err(ds->dev,
1333 "Failed to enable reverse MII mode\n");
1334 return;
1335 }
1336 }
1337 }
1338
b53_port_event(struct dsa_switch * ds,int port)1339 void b53_port_event(struct dsa_switch *ds, int port)
1340 {
1341 struct b53_device *dev = ds->priv;
1342 bool link;
1343 u16 sts;
1344
1345 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts);
1346 link = !!(sts & BIT(port));
1347 dsa_port_phylink_mac_change(ds, port, link);
1348 }
1349 EXPORT_SYMBOL(b53_port_event);
1350
b53_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1351 static void b53_phylink_get_caps(struct dsa_switch *ds, int port,
1352 struct phylink_config *config)
1353 {
1354 struct b53_device *dev = ds->priv;
1355
1356 /* Internal ports need GMII for PHYLIB */
1357 __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces);
1358
1359 /* These switches appear to support MII and RevMII too, but beyond
1360 * this, the code gives very few clues. FIXME: We probably need more
1361 * interface modes here.
1362 *
1363 * According to b53_srab_mux_init(), ports 3..5 can support:
1364 * SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting.
1365 * However, the interface mode read from the MUX configuration is
1366 * not passed back to DSA, so phylink uses NA.
1367 * DT can specify RGMII for ports 0, 1.
1368 * For MDIO, port 8 can be RGMII_TXID.
1369 */
1370 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1371 __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces);
1372
1373 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1374 MAC_10 | MAC_100;
1375
1376 /* 5325/5365 are not capable of gigabit speeds, everything else is.
1377 * Note: the original code also exclulded Gigagbit for MII, RevMII
1378 * and 802.3z modes. MII and RevMII are not able to work above 100M,
1379 * so will be excluded by the generic validator implementation.
1380 * However, the exclusion of Gigabit for 802.3z just seems wrong.
1381 */
1382 if (!(is5325(dev) || is5365(dev)))
1383 config->mac_capabilities |= MAC_1000;
1384
1385 /* Get the implementation specific capabilities */
1386 if (dev->ops->phylink_get_caps)
1387 dev->ops->phylink_get_caps(dev, port, config);
1388 }
1389
b53_phylink_mac_select_pcs(struct phylink_config * config,phy_interface_t interface)1390 static struct phylink_pcs *b53_phylink_mac_select_pcs(struct phylink_config *config,
1391 phy_interface_t interface)
1392 {
1393 struct dsa_port *dp = dsa_phylink_to_port(config);
1394 struct b53_device *dev = dp->ds->priv;
1395
1396 if (!dev->ops->phylink_mac_select_pcs)
1397 return NULL;
1398
1399 return dev->ops->phylink_mac_select_pcs(dev, dp->index, interface);
1400 }
1401
b53_phylink_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)1402 static void b53_phylink_mac_config(struct phylink_config *config,
1403 unsigned int mode,
1404 const struct phylink_link_state *state)
1405 {
1406 struct dsa_port *dp = dsa_phylink_to_port(config);
1407 phy_interface_t interface = state->interface;
1408 struct dsa_switch *ds = dp->ds;
1409 struct b53_device *dev = ds->priv;
1410 int port = dp->index;
1411
1412 if (is63xx(dev) && port >= B53_63XX_RGMII0)
1413 b53_adjust_63xx_rgmii(ds, port, interface);
1414
1415 if (mode == MLO_AN_FIXED) {
1416 if (is531x5(dev) && phy_interface_mode_is_rgmii(interface))
1417 b53_adjust_531x5_rgmii(ds, port, interface);
1418
1419 /* configure MII port if necessary */
1420 if (is5325(dev))
1421 b53_adjust_5325_mii(ds, port);
1422 }
1423 }
1424
b53_phylink_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)1425 static void b53_phylink_mac_link_down(struct phylink_config *config,
1426 unsigned int mode,
1427 phy_interface_t interface)
1428 {
1429 struct dsa_port *dp = dsa_phylink_to_port(config);
1430 struct b53_device *dev = dp->ds->priv;
1431 int port = dp->index;
1432
1433 if (mode == MLO_AN_PHY)
1434 return;
1435
1436 if (mode == MLO_AN_FIXED) {
1437 b53_force_link(dev, port, false);
1438 return;
1439 }
1440
1441 if (phy_interface_mode_is_8023z(interface) &&
1442 dev->ops->serdes_link_set)
1443 dev->ops->serdes_link_set(dev, port, mode, interface, false);
1444 }
1445
b53_phylink_mac_link_up(struct phylink_config * config,struct phy_device * phydev,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)1446 static void b53_phylink_mac_link_up(struct phylink_config *config,
1447 struct phy_device *phydev,
1448 unsigned int mode,
1449 phy_interface_t interface,
1450 int speed, int duplex,
1451 bool tx_pause, bool rx_pause)
1452 {
1453 struct dsa_port *dp = dsa_phylink_to_port(config);
1454 struct dsa_switch *ds = dp->ds;
1455 struct b53_device *dev = ds->priv;
1456 struct ethtool_keee *p = &dev->ports[dp->index].eee;
1457 int port = dp->index;
1458
1459 if (mode == MLO_AN_PHY) {
1460 /* Re-negotiate EEE if it was enabled already */
1461 p->eee_enabled = b53_eee_init(ds, port, phydev);
1462 return;
1463 }
1464
1465 if (mode == MLO_AN_FIXED) {
1466 /* Force flow control on BCM5301x's CPU port */
1467 if (is5301x(dev) && dsa_is_cpu_port(ds, port))
1468 tx_pause = rx_pause = true;
1469
1470 b53_force_port_config(dev, port, speed, duplex,
1471 tx_pause, rx_pause);
1472 b53_force_link(dev, port, true);
1473 return;
1474 }
1475
1476 if (phy_interface_mode_is_8023z(interface) &&
1477 dev->ops->serdes_link_set)
1478 dev->ops->serdes_link_set(dev, port, mode, interface, true);
1479 }
1480
b53_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)1481 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1482 struct netlink_ext_ack *extack)
1483 {
1484 struct b53_device *dev = ds->priv;
1485
1486 b53_enable_vlan(dev, port, dev->vlan_enabled, vlan_filtering);
1487
1488 return 0;
1489 }
1490 EXPORT_SYMBOL(b53_vlan_filtering);
1491
b53_vlan_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1492 static int b53_vlan_prepare(struct dsa_switch *ds, int port,
1493 const struct switchdev_obj_port_vlan *vlan)
1494 {
1495 struct b53_device *dev = ds->priv;
1496
1497 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0)
1498 return -EOPNOTSUPP;
1499
1500 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of
1501 * receiving VLAN tagged frames at all, we can still allow the port to
1502 * be configured for egress untagged.
1503 */
1504 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 &&
1505 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED))
1506 return -EINVAL;
1507
1508 if (vlan->vid >= dev->num_vlans)
1509 return -ERANGE;
1510
1511 b53_enable_vlan(dev, port, true, ds->vlan_filtering);
1512
1513 return 0;
1514 }
1515
b53_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)1516 int b53_vlan_add(struct dsa_switch *ds, int port,
1517 const struct switchdev_obj_port_vlan *vlan,
1518 struct netlink_ext_ack *extack)
1519 {
1520 struct b53_device *dev = ds->priv;
1521 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1522 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1523 struct b53_vlan *vl;
1524 int err;
1525
1526 err = b53_vlan_prepare(ds, port, vlan);
1527 if (err)
1528 return err;
1529
1530 vl = &dev->vlans[vlan->vid];
1531
1532 b53_get_vlan_entry(dev, vlan->vid, vl);
1533
1534 if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev))
1535 untagged = true;
1536
1537 vl->members |= BIT(port);
1538 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))
1539 vl->untag |= BIT(port);
1540 else
1541 vl->untag &= ~BIT(port);
1542
1543 b53_set_vlan_entry(dev, vlan->vid, vl);
1544 b53_fast_age_vlan(dev, vlan->vid);
1545
1546 if (pvid && !dsa_is_cpu_port(ds, port)) {
1547 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1548 vlan->vid);
1549 b53_fast_age_vlan(dev, vlan->vid);
1550 }
1551
1552 return 0;
1553 }
1554 EXPORT_SYMBOL(b53_vlan_add);
1555
b53_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1556 int b53_vlan_del(struct dsa_switch *ds, int port,
1557 const struct switchdev_obj_port_vlan *vlan)
1558 {
1559 struct b53_device *dev = ds->priv;
1560 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1561 struct b53_vlan *vl;
1562 u16 pvid;
1563
1564 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1565
1566 vl = &dev->vlans[vlan->vid];
1567
1568 b53_get_vlan_entry(dev, vlan->vid, vl);
1569
1570 vl->members &= ~BIT(port);
1571
1572 if (pvid == vlan->vid)
1573 pvid = b53_default_pvid(dev);
1574
1575 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))
1576 vl->untag &= ~(BIT(port));
1577
1578 b53_set_vlan_entry(dev, vlan->vid, vl);
1579 b53_fast_age_vlan(dev, vlan->vid);
1580
1581 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1582 b53_fast_age_vlan(dev, pvid);
1583
1584 return 0;
1585 }
1586 EXPORT_SYMBOL(b53_vlan_del);
1587
1588 /* Address Resolution Logic routines. Caller must hold &dev->arl_mutex. */
b53_arl_op_wait(struct b53_device * dev)1589 static int b53_arl_op_wait(struct b53_device *dev)
1590 {
1591 unsigned int timeout = 10;
1592 u8 reg;
1593
1594 do {
1595 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1596 if (!(reg & ARLTBL_START_DONE))
1597 return 0;
1598
1599 usleep_range(1000, 2000);
1600 } while (timeout--);
1601
1602 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1603
1604 return -ETIMEDOUT;
1605 }
1606
b53_arl_rw_op(struct b53_device * dev,unsigned int op)1607 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1608 {
1609 u8 reg;
1610
1611 if (op > ARLTBL_RW)
1612 return -EINVAL;
1613
1614 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1615 reg |= ARLTBL_START_DONE;
1616 if (op)
1617 reg |= ARLTBL_RW;
1618 else
1619 reg &= ~ARLTBL_RW;
1620 if (dev->vlan_enabled)
1621 reg &= ~ARLTBL_IVL_SVL_SELECT;
1622 else
1623 reg |= ARLTBL_IVL_SVL_SELECT;
1624 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1625
1626 return b53_arl_op_wait(dev);
1627 }
1628
b53_arl_read(struct b53_device * dev,u64 mac,u16 vid,struct b53_arl_entry * ent,u8 * idx)1629 static int b53_arl_read(struct b53_device *dev, u64 mac,
1630 u16 vid, struct b53_arl_entry *ent, u8 *idx)
1631 {
1632 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES);
1633 unsigned int i;
1634 int ret;
1635
1636 ret = b53_arl_op_wait(dev);
1637 if (ret)
1638 return ret;
1639
1640 bitmap_zero(free_bins, dev->num_arl_bins);
1641
1642 /* Read the bins */
1643 for (i = 0; i < dev->num_arl_bins; i++) {
1644 u64 mac_vid;
1645 u32 fwd_entry;
1646
1647 b53_read64(dev, B53_ARLIO_PAGE,
1648 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1649 b53_read32(dev, B53_ARLIO_PAGE,
1650 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1651 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1652
1653 if (!(fwd_entry & ARLTBL_VALID)) {
1654 set_bit(i, free_bins);
1655 continue;
1656 }
1657 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1658 continue;
1659 if (dev->vlan_enabled &&
1660 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid)
1661 continue;
1662 *idx = i;
1663 return 0;
1664 }
1665
1666 *idx = find_first_bit(free_bins, dev->num_arl_bins);
1667 return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT;
1668 }
1669
b53_arl_op(struct b53_device * dev,int op,int port,const unsigned char * addr,u16 vid,bool is_valid)1670 static int b53_arl_op(struct b53_device *dev, int op, int port,
1671 const unsigned char *addr, u16 vid, bool is_valid)
1672 {
1673 struct b53_arl_entry ent;
1674 u32 fwd_entry;
1675 u64 mac, mac_vid = 0;
1676 u8 idx = 0;
1677 int ret;
1678
1679 /* Convert the array into a 64-bit MAC */
1680 mac = ether_addr_to_u64(addr);
1681
1682 /* Perform a read for the given MAC and VID */
1683 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1684 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1685
1686 /* Issue a read operation for this MAC */
1687 ret = b53_arl_rw_op(dev, 1);
1688 if (ret)
1689 return ret;
1690
1691 ret = b53_arl_read(dev, mac, vid, &ent, &idx);
1692
1693 /* If this is a read, just finish now */
1694 if (op)
1695 return ret;
1696
1697 switch (ret) {
1698 case -ETIMEDOUT:
1699 return ret;
1700 case -ENOSPC:
1701 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n",
1702 addr, vid);
1703 return is_valid ? ret : 0;
1704 case -ENOENT:
1705 /* We could not find a matching MAC, so reset to a new entry */
1706 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n",
1707 addr, vid, idx);
1708 fwd_entry = 0;
1709 break;
1710 default:
1711 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n",
1712 addr, vid, idx);
1713 break;
1714 }
1715
1716 /* For multicast address, the port is a bitmask and the validity
1717 * is determined by having at least one port being still active
1718 */
1719 if (!is_multicast_ether_addr(addr)) {
1720 ent.port = port;
1721 ent.is_valid = is_valid;
1722 } else {
1723 if (is_valid)
1724 ent.port |= BIT(port);
1725 else
1726 ent.port &= ~BIT(port);
1727
1728 ent.is_valid = !!(ent.port);
1729 }
1730
1731 ent.vid = vid;
1732 ent.is_static = true;
1733 ent.is_age = false;
1734 memcpy(ent.mac, addr, ETH_ALEN);
1735 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1736
1737 b53_write64(dev, B53_ARLIO_PAGE,
1738 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1739 b53_write32(dev, B53_ARLIO_PAGE,
1740 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1741
1742 return b53_arl_rw_op(dev, 0);
1743 }
1744
b53_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1745 int b53_fdb_add(struct dsa_switch *ds, int port,
1746 const unsigned char *addr, u16 vid,
1747 struct dsa_db db)
1748 {
1749 struct b53_device *priv = ds->priv;
1750 int ret;
1751
1752 /* 5325 and 5365 require some more massaging, but could
1753 * be supported eventually
1754 */
1755 if (is5325(priv) || is5365(priv))
1756 return -EOPNOTSUPP;
1757
1758 mutex_lock(&priv->arl_mutex);
1759 ret = b53_arl_op(priv, 0, port, addr, vid, true);
1760 mutex_unlock(&priv->arl_mutex);
1761
1762 return ret;
1763 }
1764 EXPORT_SYMBOL(b53_fdb_add);
1765
b53_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1766 int b53_fdb_del(struct dsa_switch *ds, int port,
1767 const unsigned char *addr, u16 vid,
1768 struct dsa_db db)
1769 {
1770 struct b53_device *priv = ds->priv;
1771 int ret;
1772
1773 mutex_lock(&priv->arl_mutex);
1774 ret = b53_arl_op(priv, 0, port, addr, vid, false);
1775 mutex_unlock(&priv->arl_mutex);
1776
1777 return ret;
1778 }
1779 EXPORT_SYMBOL(b53_fdb_del);
1780
b53_arl_search_wait(struct b53_device * dev)1781 static int b53_arl_search_wait(struct b53_device *dev)
1782 {
1783 unsigned int timeout = 1000;
1784 u8 reg;
1785
1786 do {
1787 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®);
1788 if (!(reg & ARL_SRCH_STDN))
1789 return 0;
1790
1791 if (reg & ARL_SRCH_VLID)
1792 return 0;
1793
1794 usleep_range(1000, 2000);
1795 } while (timeout--);
1796
1797 return -ETIMEDOUT;
1798 }
1799
b53_arl_search_rd(struct b53_device * dev,u8 idx,struct b53_arl_entry * ent)1800 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1801 struct b53_arl_entry *ent)
1802 {
1803 u64 mac_vid;
1804 u32 fwd_entry;
1805
1806 b53_read64(dev, B53_ARLIO_PAGE,
1807 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1808 b53_read32(dev, B53_ARLIO_PAGE,
1809 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1810 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1811 }
1812
b53_fdb_copy(int port,const struct b53_arl_entry * ent,dsa_fdb_dump_cb_t * cb,void * data)1813 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1814 dsa_fdb_dump_cb_t *cb, void *data)
1815 {
1816 if (!ent->is_valid)
1817 return 0;
1818
1819 if (port != ent->port)
1820 return 0;
1821
1822 return cb(ent->mac, ent->vid, ent->is_static, data);
1823 }
1824
b53_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)1825 int b53_fdb_dump(struct dsa_switch *ds, int port,
1826 dsa_fdb_dump_cb_t *cb, void *data)
1827 {
1828 struct b53_device *priv = ds->priv;
1829 struct b53_arl_entry results[2];
1830 unsigned int count = 0;
1831 int ret;
1832 u8 reg;
1833
1834 mutex_lock(&priv->arl_mutex);
1835
1836 /* Start search operation */
1837 reg = ARL_SRCH_STDN;
1838 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1839
1840 do {
1841 ret = b53_arl_search_wait(priv);
1842 if (ret)
1843 break;
1844
1845 b53_arl_search_rd(priv, 0, &results[0]);
1846 ret = b53_fdb_copy(port, &results[0], cb, data);
1847 if (ret)
1848 break;
1849
1850 if (priv->num_arl_bins > 2) {
1851 b53_arl_search_rd(priv, 1, &results[1]);
1852 ret = b53_fdb_copy(port, &results[1], cb, data);
1853 if (ret)
1854 break;
1855
1856 if (!results[0].is_valid && !results[1].is_valid)
1857 break;
1858 }
1859
1860 } while (count++ < b53_max_arl_entries(priv) / 2);
1861
1862 mutex_unlock(&priv->arl_mutex);
1863
1864 return 0;
1865 }
1866 EXPORT_SYMBOL(b53_fdb_dump);
1867
b53_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1868 int b53_mdb_add(struct dsa_switch *ds, int port,
1869 const struct switchdev_obj_port_mdb *mdb,
1870 struct dsa_db db)
1871 {
1872 struct b53_device *priv = ds->priv;
1873 int ret;
1874
1875 /* 5325 and 5365 require some more massaging, but could
1876 * be supported eventually
1877 */
1878 if (is5325(priv) || is5365(priv))
1879 return -EOPNOTSUPP;
1880
1881 mutex_lock(&priv->arl_mutex);
1882 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true);
1883 mutex_unlock(&priv->arl_mutex);
1884
1885 return ret;
1886 }
1887 EXPORT_SYMBOL(b53_mdb_add);
1888
b53_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1889 int b53_mdb_del(struct dsa_switch *ds, int port,
1890 const struct switchdev_obj_port_mdb *mdb,
1891 struct dsa_db db)
1892 {
1893 struct b53_device *priv = ds->priv;
1894 int ret;
1895
1896 mutex_lock(&priv->arl_mutex);
1897 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false);
1898 mutex_unlock(&priv->arl_mutex);
1899 if (ret)
1900 dev_err(ds->dev, "failed to delete MDB entry\n");
1901
1902 return ret;
1903 }
1904 EXPORT_SYMBOL(b53_mdb_del);
1905
b53_br_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)1906 int b53_br_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge,
1907 bool *tx_fwd_offload, struct netlink_ext_ack *extack)
1908 {
1909 struct b53_device *dev = ds->priv;
1910 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1911 u16 pvlan, reg;
1912 unsigned int i;
1913
1914 /* On 7278, port 7 which connects to the ASP should only receive
1915 * traffic from matching CFP rules.
1916 */
1917 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7)
1918 return -EINVAL;
1919
1920 /* Make this port leave the all VLANs join since we will have proper
1921 * VLAN entries from now on
1922 */
1923 if (is58xx(dev)) {
1924 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1925 reg &= ~BIT(port);
1926 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1927 reg &= ~BIT(cpu_port);
1928 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1929 }
1930
1931 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1932
1933 b53_for_each_port(dev, i) {
1934 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1935 continue;
1936
1937 /* Add this local port to the remote port VLAN control
1938 * membership and update the remote port bitmask
1939 */
1940 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1941 reg |= BIT(port);
1942 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1943 dev->ports[i].vlan_ctl_mask = reg;
1944
1945 pvlan |= BIT(i);
1946 }
1947
1948 /* Configure the local port VLAN control membership to include
1949 * remote ports and update the local port bitmask
1950 */
1951 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1952 dev->ports[port].vlan_ctl_mask = pvlan;
1953
1954 return 0;
1955 }
1956 EXPORT_SYMBOL(b53_br_join);
1957
b53_br_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)1958 void b53_br_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge)
1959 {
1960 struct b53_device *dev = ds->priv;
1961 struct b53_vlan *vl = &dev->vlans[0];
1962 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1963 unsigned int i;
1964 u16 pvlan, reg, pvid;
1965
1966 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1967
1968 b53_for_each_port(dev, i) {
1969 /* Don't touch the remaining ports */
1970 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1971 continue;
1972
1973 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1974 reg &= ~BIT(port);
1975 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1976 dev->ports[port].vlan_ctl_mask = reg;
1977
1978 /* Prevent self removal to preserve isolation */
1979 if (port != i)
1980 pvlan &= ~BIT(i);
1981 }
1982
1983 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1984 dev->ports[port].vlan_ctl_mask = pvlan;
1985
1986 pvid = b53_default_pvid(dev);
1987
1988 /* Make this port join all VLANs without VLAN entries */
1989 if (is58xx(dev)) {
1990 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1991 reg |= BIT(port);
1992 if (!(reg & BIT(cpu_port)))
1993 reg |= BIT(cpu_port);
1994 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1995 } else {
1996 b53_get_vlan_entry(dev, pvid, vl);
1997 vl->members |= BIT(port) | BIT(cpu_port);
1998 vl->untag |= BIT(port) | BIT(cpu_port);
1999 b53_set_vlan_entry(dev, pvid, vl);
2000 }
2001 }
2002 EXPORT_SYMBOL(b53_br_leave);
2003
b53_br_set_stp_state(struct dsa_switch * ds,int port,u8 state)2004 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
2005 {
2006 struct b53_device *dev = ds->priv;
2007 u8 hw_state;
2008 u8 reg;
2009
2010 switch (state) {
2011 case BR_STATE_DISABLED:
2012 hw_state = PORT_CTRL_DIS_STATE;
2013 break;
2014 case BR_STATE_LISTENING:
2015 hw_state = PORT_CTRL_LISTEN_STATE;
2016 break;
2017 case BR_STATE_LEARNING:
2018 hw_state = PORT_CTRL_LEARN_STATE;
2019 break;
2020 case BR_STATE_FORWARDING:
2021 hw_state = PORT_CTRL_FWD_STATE;
2022 break;
2023 case BR_STATE_BLOCKING:
2024 hw_state = PORT_CTRL_BLOCK_STATE;
2025 break;
2026 default:
2027 dev_err(ds->dev, "invalid STP state: %d\n", state);
2028 return;
2029 }
2030
2031 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
2032 reg &= ~PORT_CTRL_STP_STATE_MASK;
2033 reg |= hw_state;
2034 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
2035 }
2036 EXPORT_SYMBOL(b53_br_set_stp_state);
2037
b53_br_fast_age(struct dsa_switch * ds,int port)2038 void b53_br_fast_age(struct dsa_switch *ds, int port)
2039 {
2040 struct b53_device *dev = ds->priv;
2041
2042 if (b53_fast_age_port(dev, port))
2043 dev_err(ds->dev, "fast ageing failed\n");
2044 }
2045 EXPORT_SYMBOL(b53_br_fast_age);
2046
b53_br_flags_pre(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2047 int b53_br_flags_pre(struct dsa_switch *ds, int port,
2048 struct switchdev_brport_flags flags,
2049 struct netlink_ext_ack *extack)
2050 {
2051 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING))
2052 return -EINVAL;
2053
2054 return 0;
2055 }
2056 EXPORT_SYMBOL(b53_br_flags_pre);
2057
b53_br_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2058 int b53_br_flags(struct dsa_switch *ds, int port,
2059 struct switchdev_brport_flags flags,
2060 struct netlink_ext_ack *extack)
2061 {
2062 if (flags.mask & BR_FLOOD)
2063 b53_port_set_ucast_flood(ds->priv, port,
2064 !!(flags.val & BR_FLOOD));
2065 if (flags.mask & BR_MCAST_FLOOD)
2066 b53_port_set_mcast_flood(ds->priv, port,
2067 !!(flags.val & BR_MCAST_FLOOD));
2068 if (flags.mask & BR_LEARNING)
2069 b53_port_set_learning(ds->priv, port,
2070 !!(flags.val & BR_LEARNING));
2071
2072 return 0;
2073 }
2074 EXPORT_SYMBOL(b53_br_flags);
2075
b53_possible_cpu_port(struct dsa_switch * ds,int port)2076 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
2077 {
2078 /* Broadcom switches will accept enabling Broadcom tags on the
2079 * following ports: 5, 7 and 8, any other port is not supported
2080 */
2081 switch (port) {
2082 case B53_CPU_PORT_25:
2083 case 7:
2084 case B53_CPU_PORT:
2085 return true;
2086 }
2087
2088 return false;
2089 }
2090
b53_can_enable_brcm_tags(struct dsa_switch * ds,int port,enum dsa_tag_protocol tag_protocol)2091 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port,
2092 enum dsa_tag_protocol tag_protocol)
2093 {
2094 bool ret = b53_possible_cpu_port(ds, port);
2095
2096 if (!ret) {
2097 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
2098 port);
2099 return ret;
2100 }
2101
2102 switch (tag_protocol) {
2103 case DSA_TAG_PROTO_BRCM:
2104 case DSA_TAG_PROTO_BRCM_PREPEND:
2105 dev_warn(ds->dev,
2106 "Port %d is stacked to Broadcom tag switch\n", port);
2107 ret = false;
2108 break;
2109 default:
2110 ret = true;
2111 break;
2112 }
2113
2114 return ret;
2115 }
2116
b53_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mprot)2117 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port,
2118 enum dsa_tag_protocol mprot)
2119 {
2120 struct b53_device *dev = ds->priv;
2121
2122 if (!b53_can_enable_brcm_tags(ds, port, mprot)) {
2123 dev->tag_protocol = DSA_TAG_PROTO_NONE;
2124 goto out;
2125 }
2126
2127 /* Older models require a different 6 byte tag */
2128 if (is5325(dev) || is5365(dev) || is63xx(dev)) {
2129 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY;
2130 goto out;
2131 }
2132
2133 /* Broadcom BCM58xx chips have a flow accelerator on Port 8
2134 * which requires us to use the prepended Broadcom tag type
2135 */
2136 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) {
2137 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND;
2138 goto out;
2139 }
2140
2141 dev->tag_protocol = DSA_TAG_PROTO_BRCM;
2142 out:
2143 return dev->tag_protocol;
2144 }
2145 EXPORT_SYMBOL(b53_get_tag_protocol);
2146
b53_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)2147 int b53_mirror_add(struct dsa_switch *ds, int port,
2148 struct dsa_mall_mirror_tc_entry *mirror, bool ingress,
2149 struct netlink_ext_ack *extack)
2150 {
2151 struct b53_device *dev = ds->priv;
2152 u16 reg, loc;
2153
2154 if (ingress)
2155 loc = B53_IG_MIR_CTL;
2156 else
2157 loc = B53_EG_MIR_CTL;
2158
2159 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
2160 reg |= BIT(port);
2161 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2162
2163 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
2164 reg &= ~CAP_PORT_MASK;
2165 reg |= mirror->to_local_port;
2166 reg |= MIRROR_EN;
2167 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2168
2169 return 0;
2170 }
2171 EXPORT_SYMBOL(b53_mirror_add);
2172
b53_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)2173 void b53_mirror_del(struct dsa_switch *ds, int port,
2174 struct dsa_mall_mirror_tc_entry *mirror)
2175 {
2176 struct b53_device *dev = ds->priv;
2177 bool loc_disable = false, other_loc_disable = false;
2178 u16 reg, loc;
2179
2180 if (mirror->ingress)
2181 loc = B53_IG_MIR_CTL;
2182 else
2183 loc = B53_EG_MIR_CTL;
2184
2185 /* Update the desired ingress/egress register */
2186 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
2187 reg &= ~BIT(port);
2188 if (!(reg & MIRROR_MASK))
2189 loc_disable = true;
2190 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2191
2192 /* Now look at the other one to know if we can disable mirroring
2193 * entirely
2194 */
2195 if (mirror->ingress)
2196 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®);
2197 else
2198 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®);
2199 if (!(reg & MIRROR_MASK))
2200 other_loc_disable = true;
2201
2202 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
2203 /* Both no longer have ports, let's disable mirroring */
2204 if (loc_disable && other_loc_disable) {
2205 reg &= ~MIRROR_EN;
2206 reg &= ~mirror->to_local_port;
2207 }
2208 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2209 }
2210 EXPORT_SYMBOL(b53_mirror_del);
2211
2212 /* Returns 0 if EEE was not enabled, or 1 otherwise
2213 */
b53_eee_init(struct dsa_switch * ds,int port,struct phy_device * phy)2214 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
2215 {
2216 int ret;
2217
2218 ret = phy_init_eee(phy, false);
2219 if (ret)
2220 return 0;
2221
2222 b53_eee_enable_set(ds, port, true);
2223
2224 return 1;
2225 }
2226 EXPORT_SYMBOL(b53_eee_init);
2227
b53_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_keee * e)2228 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e)
2229 {
2230 struct b53_device *dev = ds->priv;
2231
2232 if (is5325(dev) || is5365(dev))
2233 return -EOPNOTSUPP;
2234
2235 return 0;
2236 }
2237 EXPORT_SYMBOL(b53_get_mac_eee);
2238
b53_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_keee * e)2239 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e)
2240 {
2241 struct b53_device *dev = ds->priv;
2242 struct ethtool_keee *p = &dev->ports[port].eee;
2243
2244 if (is5325(dev) || is5365(dev))
2245 return -EOPNOTSUPP;
2246
2247 p->eee_enabled = e->eee_enabled;
2248 b53_eee_enable_set(ds, port, e->eee_enabled);
2249
2250 return 0;
2251 }
2252 EXPORT_SYMBOL(b53_set_mac_eee);
2253
b53_change_mtu(struct dsa_switch * ds,int port,int mtu)2254 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu)
2255 {
2256 struct b53_device *dev = ds->priv;
2257 bool enable_jumbo;
2258 bool allow_10_100;
2259
2260 if (is5325(dev) || is5365(dev))
2261 return 0;
2262
2263 if (!dsa_is_cpu_port(ds, port))
2264 return 0;
2265
2266 enable_jumbo = (mtu > ETH_DATA_LEN);
2267 allow_10_100 = !is63xx(dev);
2268
2269 return b53_set_jumbo(dev, enable_jumbo, allow_10_100);
2270 }
2271
b53_get_max_mtu(struct dsa_switch * ds,int port)2272 static int b53_get_max_mtu(struct dsa_switch *ds, int port)
2273 {
2274 struct b53_device *dev = ds->priv;
2275
2276 if (is5325(dev) || is5365(dev))
2277 return B53_MAX_MTU_25;
2278
2279 return B53_MAX_MTU;
2280 }
2281
2282 static const struct phylink_mac_ops b53_phylink_mac_ops = {
2283 .mac_select_pcs = b53_phylink_mac_select_pcs,
2284 .mac_config = b53_phylink_mac_config,
2285 .mac_link_down = b53_phylink_mac_link_down,
2286 .mac_link_up = b53_phylink_mac_link_up,
2287 };
2288
2289 static const struct dsa_switch_ops b53_switch_ops = {
2290 .get_tag_protocol = b53_get_tag_protocol,
2291 .setup = b53_setup,
2292 .teardown = b53_teardown,
2293 .get_strings = b53_get_strings,
2294 .get_ethtool_stats = b53_get_ethtool_stats,
2295 .get_sset_count = b53_get_sset_count,
2296 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
2297 .phy_read = b53_phy_read16,
2298 .phy_write = b53_phy_write16,
2299 .phylink_get_caps = b53_phylink_get_caps,
2300 .port_enable = b53_enable_port,
2301 .port_disable = b53_disable_port,
2302 .get_mac_eee = b53_get_mac_eee,
2303 .set_mac_eee = b53_set_mac_eee,
2304 .port_bridge_join = b53_br_join,
2305 .port_bridge_leave = b53_br_leave,
2306 .port_pre_bridge_flags = b53_br_flags_pre,
2307 .port_bridge_flags = b53_br_flags,
2308 .port_stp_state_set = b53_br_set_stp_state,
2309 .port_fast_age = b53_br_fast_age,
2310 .port_vlan_filtering = b53_vlan_filtering,
2311 .port_vlan_add = b53_vlan_add,
2312 .port_vlan_del = b53_vlan_del,
2313 .port_fdb_dump = b53_fdb_dump,
2314 .port_fdb_add = b53_fdb_add,
2315 .port_fdb_del = b53_fdb_del,
2316 .port_mirror_add = b53_mirror_add,
2317 .port_mirror_del = b53_mirror_del,
2318 .port_mdb_add = b53_mdb_add,
2319 .port_mdb_del = b53_mdb_del,
2320 .port_max_mtu = b53_get_max_mtu,
2321 .port_change_mtu = b53_change_mtu,
2322 };
2323
2324 struct b53_chip_data {
2325 u32 chip_id;
2326 const char *dev_name;
2327 u16 vlans;
2328 u16 enabled_ports;
2329 u8 imp_port;
2330 u8 cpu_port;
2331 u8 vta_regs[3];
2332 u8 arl_bins;
2333 u16 arl_buckets;
2334 u8 duplex_reg;
2335 u8 jumbo_pm_reg;
2336 u8 jumbo_size_reg;
2337 };
2338
2339 #define B53_VTA_REGS \
2340 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
2341 #define B53_VTA_REGS_9798 \
2342 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
2343 #define B53_VTA_REGS_63XX \
2344 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
2345
2346 static const struct b53_chip_data b53_switch_chips[] = {
2347 {
2348 .chip_id = BCM5325_DEVICE_ID,
2349 .dev_name = "BCM5325",
2350 .vlans = 16,
2351 .enabled_ports = 0x3f,
2352 .arl_bins = 2,
2353 .arl_buckets = 1024,
2354 .imp_port = 5,
2355 .duplex_reg = B53_DUPLEX_STAT_FE,
2356 },
2357 {
2358 .chip_id = BCM5365_DEVICE_ID,
2359 .dev_name = "BCM5365",
2360 .vlans = 256,
2361 .enabled_ports = 0x3f,
2362 .arl_bins = 2,
2363 .arl_buckets = 1024,
2364 .imp_port = 5,
2365 .duplex_reg = B53_DUPLEX_STAT_FE,
2366 },
2367 {
2368 .chip_id = BCM5389_DEVICE_ID,
2369 .dev_name = "BCM5389",
2370 .vlans = 4096,
2371 .enabled_ports = 0x11f,
2372 .arl_bins = 4,
2373 .arl_buckets = 1024,
2374 .imp_port = 8,
2375 .vta_regs = B53_VTA_REGS,
2376 .duplex_reg = B53_DUPLEX_STAT_GE,
2377 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2378 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2379 },
2380 {
2381 .chip_id = BCM5395_DEVICE_ID,
2382 .dev_name = "BCM5395",
2383 .vlans = 4096,
2384 .enabled_ports = 0x11f,
2385 .arl_bins = 4,
2386 .arl_buckets = 1024,
2387 .imp_port = 8,
2388 .vta_regs = B53_VTA_REGS,
2389 .duplex_reg = B53_DUPLEX_STAT_GE,
2390 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2391 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2392 },
2393 {
2394 .chip_id = BCM5397_DEVICE_ID,
2395 .dev_name = "BCM5397",
2396 .vlans = 4096,
2397 .enabled_ports = 0x11f,
2398 .arl_bins = 4,
2399 .arl_buckets = 1024,
2400 .imp_port = 8,
2401 .vta_regs = B53_VTA_REGS_9798,
2402 .duplex_reg = B53_DUPLEX_STAT_GE,
2403 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2404 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2405 },
2406 {
2407 .chip_id = BCM5398_DEVICE_ID,
2408 .dev_name = "BCM5398",
2409 .vlans = 4096,
2410 .enabled_ports = 0x17f,
2411 .arl_bins = 4,
2412 .arl_buckets = 1024,
2413 .imp_port = 8,
2414 .vta_regs = B53_VTA_REGS_9798,
2415 .duplex_reg = B53_DUPLEX_STAT_GE,
2416 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2417 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2418 },
2419 {
2420 .chip_id = BCM53115_DEVICE_ID,
2421 .dev_name = "BCM53115",
2422 .vlans = 4096,
2423 .enabled_ports = 0x11f,
2424 .arl_bins = 4,
2425 .arl_buckets = 1024,
2426 .vta_regs = B53_VTA_REGS,
2427 .imp_port = 8,
2428 .duplex_reg = B53_DUPLEX_STAT_GE,
2429 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2430 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2431 },
2432 {
2433 .chip_id = BCM53125_DEVICE_ID,
2434 .dev_name = "BCM53125",
2435 .vlans = 4096,
2436 .enabled_ports = 0x1ff,
2437 .arl_bins = 4,
2438 .arl_buckets = 1024,
2439 .imp_port = 8,
2440 .vta_regs = B53_VTA_REGS,
2441 .duplex_reg = B53_DUPLEX_STAT_GE,
2442 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2443 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2444 },
2445 {
2446 .chip_id = BCM53128_DEVICE_ID,
2447 .dev_name = "BCM53128",
2448 .vlans = 4096,
2449 .enabled_ports = 0x1ff,
2450 .arl_bins = 4,
2451 .arl_buckets = 1024,
2452 .imp_port = 8,
2453 .vta_regs = B53_VTA_REGS,
2454 .duplex_reg = B53_DUPLEX_STAT_GE,
2455 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2456 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2457 },
2458 {
2459 .chip_id = BCM63XX_DEVICE_ID,
2460 .dev_name = "BCM63xx",
2461 .vlans = 4096,
2462 .enabled_ports = 0, /* pdata must provide them */
2463 .arl_bins = 4,
2464 .arl_buckets = 1024,
2465 .imp_port = 8,
2466 .vta_regs = B53_VTA_REGS_63XX,
2467 .duplex_reg = B53_DUPLEX_STAT_63XX,
2468 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2469 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2470 },
2471 {
2472 .chip_id = BCM63268_DEVICE_ID,
2473 .dev_name = "BCM63268",
2474 .vlans = 4096,
2475 .enabled_ports = 0, /* pdata must provide them */
2476 .arl_bins = 4,
2477 .arl_buckets = 1024,
2478 .imp_port = 8,
2479 .vta_regs = B53_VTA_REGS_63XX,
2480 .duplex_reg = B53_DUPLEX_STAT_63XX,
2481 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2482 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2483 },
2484 {
2485 .chip_id = BCM53010_DEVICE_ID,
2486 .dev_name = "BCM53010",
2487 .vlans = 4096,
2488 .enabled_ports = 0x1bf,
2489 .arl_bins = 4,
2490 .arl_buckets = 1024,
2491 .imp_port = 8,
2492 .vta_regs = B53_VTA_REGS,
2493 .duplex_reg = B53_DUPLEX_STAT_GE,
2494 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2495 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2496 },
2497 {
2498 .chip_id = BCM53011_DEVICE_ID,
2499 .dev_name = "BCM53011",
2500 .vlans = 4096,
2501 .enabled_ports = 0x1bf,
2502 .arl_bins = 4,
2503 .arl_buckets = 1024,
2504 .imp_port = 8,
2505 .vta_regs = B53_VTA_REGS,
2506 .duplex_reg = B53_DUPLEX_STAT_GE,
2507 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2508 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2509 },
2510 {
2511 .chip_id = BCM53012_DEVICE_ID,
2512 .dev_name = "BCM53012",
2513 .vlans = 4096,
2514 .enabled_ports = 0x1bf,
2515 .arl_bins = 4,
2516 .arl_buckets = 1024,
2517 .imp_port = 8,
2518 .vta_regs = B53_VTA_REGS,
2519 .duplex_reg = B53_DUPLEX_STAT_GE,
2520 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2521 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2522 },
2523 {
2524 .chip_id = BCM53018_DEVICE_ID,
2525 .dev_name = "BCM53018",
2526 .vlans = 4096,
2527 .enabled_ports = 0x1bf,
2528 .arl_bins = 4,
2529 .arl_buckets = 1024,
2530 .imp_port = 8,
2531 .vta_regs = B53_VTA_REGS,
2532 .duplex_reg = B53_DUPLEX_STAT_GE,
2533 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2534 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2535 },
2536 {
2537 .chip_id = BCM53019_DEVICE_ID,
2538 .dev_name = "BCM53019",
2539 .vlans = 4096,
2540 .enabled_ports = 0x1bf,
2541 .arl_bins = 4,
2542 .arl_buckets = 1024,
2543 .imp_port = 8,
2544 .vta_regs = B53_VTA_REGS,
2545 .duplex_reg = B53_DUPLEX_STAT_GE,
2546 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2547 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2548 },
2549 {
2550 .chip_id = BCM58XX_DEVICE_ID,
2551 .dev_name = "BCM585xx/586xx/88312",
2552 .vlans = 4096,
2553 .enabled_ports = 0x1ff,
2554 .arl_bins = 4,
2555 .arl_buckets = 1024,
2556 .imp_port = 8,
2557 .vta_regs = B53_VTA_REGS,
2558 .duplex_reg = B53_DUPLEX_STAT_GE,
2559 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2560 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2561 },
2562 {
2563 .chip_id = BCM583XX_DEVICE_ID,
2564 .dev_name = "BCM583xx/11360",
2565 .vlans = 4096,
2566 .enabled_ports = 0x103,
2567 .arl_bins = 4,
2568 .arl_buckets = 1024,
2569 .imp_port = 8,
2570 .vta_regs = B53_VTA_REGS,
2571 .duplex_reg = B53_DUPLEX_STAT_GE,
2572 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2573 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2574 },
2575 /* Starfighter 2 */
2576 {
2577 .chip_id = BCM4908_DEVICE_ID,
2578 .dev_name = "BCM4908",
2579 .vlans = 4096,
2580 .enabled_ports = 0x1bf,
2581 .arl_bins = 4,
2582 .arl_buckets = 256,
2583 .imp_port = 8,
2584 .vta_regs = B53_VTA_REGS,
2585 .duplex_reg = B53_DUPLEX_STAT_GE,
2586 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2587 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2588 },
2589 {
2590 .chip_id = BCM7445_DEVICE_ID,
2591 .dev_name = "BCM7445",
2592 .vlans = 4096,
2593 .enabled_ports = 0x1ff,
2594 .arl_bins = 4,
2595 .arl_buckets = 1024,
2596 .imp_port = 8,
2597 .vta_regs = B53_VTA_REGS,
2598 .duplex_reg = B53_DUPLEX_STAT_GE,
2599 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2600 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2601 },
2602 {
2603 .chip_id = BCM7278_DEVICE_ID,
2604 .dev_name = "BCM7278",
2605 .vlans = 4096,
2606 .enabled_ports = 0x1ff,
2607 .arl_bins = 4,
2608 .arl_buckets = 256,
2609 .imp_port = 8,
2610 .vta_regs = B53_VTA_REGS,
2611 .duplex_reg = B53_DUPLEX_STAT_GE,
2612 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2613 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2614 },
2615 {
2616 .chip_id = BCM53134_DEVICE_ID,
2617 .dev_name = "BCM53134",
2618 .vlans = 4096,
2619 .enabled_ports = 0x12f,
2620 .imp_port = 8,
2621 .cpu_port = B53_CPU_PORT,
2622 .vta_regs = B53_VTA_REGS,
2623 .arl_bins = 4,
2624 .arl_buckets = 1024,
2625 .duplex_reg = B53_DUPLEX_STAT_GE,
2626 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2627 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2628 },
2629 };
2630
b53_switch_init(struct b53_device * dev)2631 static int b53_switch_init(struct b53_device *dev)
2632 {
2633 unsigned int i;
2634 int ret;
2635
2636 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
2637 const struct b53_chip_data *chip = &b53_switch_chips[i];
2638
2639 if (chip->chip_id == dev->chip_id) {
2640 if (!dev->enabled_ports)
2641 dev->enabled_ports = chip->enabled_ports;
2642 dev->name = chip->dev_name;
2643 dev->duplex_reg = chip->duplex_reg;
2644 dev->vta_regs[0] = chip->vta_regs[0];
2645 dev->vta_regs[1] = chip->vta_regs[1];
2646 dev->vta_regs[2] = chip->vta_regs[2];
2647 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
2648 dev->imp_port = chip->imp_port;
2649 dev->num_vlans = chip->vlans;
2650 dev->num_arl_bins = chip->arl_bins;
2651 dev->num_arl_buckets = chip->arl_buckets;
2652 break;
2653 }
2654 }
2655
2656 /* check which BCM5325x version we have */
2657 if (is5325(dev)) {
2658 u8 vc4;
2659
2660 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2661
2662 /* check reserved bits */
2663 switch (vc4 & 3) {
2664 case 1:
2665 /* BCM5325E */
2666 break;
2667 case 3:
2668 /* BCM5325F - do not use port 4 */
2669 dev->enabled_ports &= ~BIT(4);
2670 break;
2671 default:
2672 /* On the BCM47XX SoCs this is the supported internal switch.*/
2673 #ifndef CONFIG_BCM47XX
2674 /* BCM5325M */
2675 return -EINVAL;
2676 #else
2677 break;
2678 #endif
2679 }
2680 }
2681
2682 dev->num_ports = fls(dev->enabled_ports);
2683
2684 dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS);
2685
2686 /* Include non standard CPU port built-in PHYs to be probed */
2687 if (is539x(dev) || is531x5(dev)) {
2688 for (i = 0; i < dev->num_ports; i++) {
2689 if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2690 !b53_possible_cpu_port(dev->ds, i))
2691 dev->ds->phys_mii_mask |= BIT(i);
2692 }
2693 }
2694
2695 dev->ports = devm_kcalloc(dev->dev,
2696 dev->num_ports, sizeof(struct b53_port),
2697 GFP_KERNEL);
2698 if (!dev->ports)
2699 return -ENOMEM;
2700
2701 dev->vlans = devm_kcalloc(dev->dev,
2702 dev->num_vlans, sizeof(struct b53_vlan),
2703 GFP_KERNEL);
2704 if (!dev->vlans)
2705 return -ENOMEM;
2706
2707 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2708 if (dev->reset_gpio >= 0) {
2709 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2710 GPIOF_OUT_INIT_HIGH, "robo_reset");
2711 if (ret)
2712 return ret;
2713 }
2714
2715 return 0;
2716 }
2717
b53_switch_alloc(struct device * base,const struct b53_io_ops * ops,void * priv)2718 struct b53_device *b53_switch_alloc(struct device *base,
2719 const struct b53_io_ops *ops,
2720 void *priv)
2721 {
2722 struct dsa_switch *ds;
2723 struct b53_device *dev;
2724
2725 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
2726 if (!ds)
2727 return NULL;
2728
2729 ds->dev = base;
2730
2731 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2732 if (!dev)
2733 return NULL;
2734
2735 ds->priv = dev;
2736 dev->dev = base;
2737
2738 dev->ds = ds;
2739 dev->priv = priv;
2740 dev->ops = ops;
2741 ds->ops = &b53_switch_ops;
2742 ds->phylink_mac_ops = &b53_phylink_mac_ops;
2743 dev->vlan_enabled = true;
2744 /* Let DSA handle the case were multiple bridges span the same switch
2745 * device and different VLAN awareness settings are requested, which
2746 * would be breaking filtering semantics for any of the other bridge
2747 * devices. (not hardware supported)
2748 */
2749 ds->vlan_filtering_is_global = true;
2750
2751 mutex_init(&dev->reg_mutex);
2752 mutex_init(&dev->stats_mutex);
2753 mutex_init(&dev->arl_mutex);
2754
2755 return dev;
2756 }
2757 EXPORT_SYMBOL(b53_switch_alloc);
2758
b53_switch_detect(struct b53_device * dev)2759 int b53_switch_detect(struct b53_device *dev)
2760 {
2761 u32 id32;
2762 u16 tmp;
2763 u8 id8;
2764 int ret;
2765
2766 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2767 if (ret)
2768 return ret;
2769
2770 switch (id8) {
2771 case 0:
2772 /* BCM5325 and BCM5365 do not have this register so reads
2773 * return 0. But the read operation did succeed, so assume this
2774 * is one of them.
2775 *
2776 * Next check if we can write to the 5325's VTA register; for
2777 * 5365 it is read only.
2778 */
2779 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2780 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2781
2782 if (tmp == 0xf)
2783 dev->chip_id = BCM5325_DEVICE_ID;
2784 else
2785 dev->chip_id = BCM5365_DEVICE_ID;
2786 break;
2787 case BCM5389_DEVICE_ID:
2788 case BCM5395_DEVICE_ID:
2789 case BCM5397_DEVICE_ID:
2790 case BCM5398_DEVICE_ID:
2791 dev->chip_id = id8;
2792 break;
2793 default:
2794 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2795 if (ret)
2796 return ret;
2797
2798 switch (id32) {
2799 case BCM53115_DEVICE_ID:
2800 case BCM53125_DEVICE_ID:
2801 case BCM53128_DEVICE_ID:
2802 case BCM53010_DEVICE_ID:
2803 case BCM53011_DEVICE_ID:
2804 case BCM53012_DEVICE_ID:
2805 case BCM53018_DEVICE_ID:
2806 case BCM53019_DEVICE_ID:
2807 case BCM53134_DEVICE_ID:
2808 dev->chip_id = id32;
2809 break;
2810 default:
2811 dev_err(dev->dev,
2812 "unsupported switch detected (BCM53%02x/BCM%x)\n",
2813 id8, id32);
2814 return -ENODEV;
2815 }
2816 }
2817
2818 if (dev->chip_id == BCM5325_DEVICE_ID)
2819 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2820 &dev->core_rev);
2821 else
2822 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2823 &dev->core_rev);
2824 }
2825 EXPORT_SYMBOL(b53_switch_detect);
2826
b53_switch_register(struct b53_device * dev)2827 int b53_switch_register(struct b53_device *dev)
2828 {
2829 int ret;
2830
2831 if (dev->pdata) {
2832 dev->chip_id = dev->pdata->chip_id;
2833 dev->enabled_ports = dev->pdata->enabled_ports;
2834 }
2835
2836 if (!dev->chip_id && b53_switch_detect(dev))
2837 return -EINVAL;
2838
2839 ret = b53_switch_init(dev);
2840 if (ret)
2841 return ret;
2842
2843 dev_info(dev->dev, "found switch: %s, rev %i\n",
2844 dev->name, dev->core_rev);
2845
2846 return dsa_register_switch(dev->ds);
2847 }
2848 EXPORT_SYMBOL(b53_switch_register);
2849
2850 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2851 MODULE_DESCRIPTION("B53 switch library");
2852 MODULE_LICENSE("Dual BSD/GPL");
2853