1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2026 Marvell. 5 * 6 */ 7 8 #ifndef NPC_CN20K_H 9 #define NPC_CN20K_H 10 11 #define MKEX_CN20K_SIGN 0x19bbfdbd160 12 13 #define MAX_NUM_BANKS 2 14 #define MAX_NUM_SUB_BANKS 32 15 #define MAX_SUBBANK_DEPTH 256 16 17 /* strtoull of "mkexprof" with base:36 */ 18 #define MKEX_END_SIGN 0xdeadbeef 19 20 #define NPC_CN20K_BYTESM GENMASK_ULL(18, 16) 21 #define NPC_CN20K_PARSE_NIBBLE GENMASK_ULL(22, 0) 22 #define NPC_CN20K_TOTAL_NIBBLE 23 23 24 #define CN20K_SET_EXTR_LT(intf, extr, ltype, cfg) \ 25 rvu_write64(rvu, BLKADDR_NPC, \ 26 NPC_AF_INTFX_EXTRACTORX_LTX_CFG(intf, extr, ltype), cfg) 27 28 #define CN20K_GET_KEX_CFG(intf) \ 29 rvu_read64(rvu, BLKADDR_NPC, NPC_AF_INTFX_KEX_CFG(intf)) 30 31 #define CN20K_GET_EXTR_LID(intf, extr) \ 32 rvu_read64(rvu, BLKADDR_NPC, \ 33 NPC_AF_INTFX_EXTRACTORX_CFG(intf, extr)) 34 35 #define CN20K_SET_EXTR_LT(intf, extr, ltype, cfg) \ 36 rvu_write64(rvu, BLKADDR_NPC, \ 37 NPC_AF_INTFX_EXTRACTORX_LTX_CFG(intf, extr, ltype), cfg) 38 39 #define CN20K_GET_EXTR_LT(intf, extr, ltype) \ 40 rvu_read64(rvu, BLKADDR_NPC, \ 41 NPC_AF_INTFX_EXTRACTORX_LTX_CFG(intf, extr, ltype)) 42 43 /* NPC_PARSE_KEX_S nibble definitions for each field */ 44 #define NPC_CN20K_PARSE_NIBBLE_CHAN GENMASK_ULL(2, 0) 45 #define NPC_CN20K_PARSE_NIBBLE_ERRLEV BIT_ULL(3) 46 #define NPC_CN20K_PARSE_NIBBLE_ERRCODE GENMASK_ULL(5, 4) 47 #define NPC_CN20K_PARSE_NIBBLE_L2L3_BCAST BIT_ULL(6) 48 #define NPC_CN20K_PARSE_NIBBLE_LA_FLAGS BIT_ULL(7) 49 #define NPC_CN20K_PARSE_NIBBLE_LA_LTYPE BIT_ULL(8) 50 #define NPC_CN20K_PARSE_NIBBLE_LB_FLAGS BIT_ULL(9) 51 #define NPC_CN20K_PARSE_NIBBLE_LB_LTYPE BIT_ULL(10) 52 #define NPC_CN20K_PARSE_NIBBLE_LC_FLAGS BIT_ULL(11) 53 #define NPC_CN20K_PARSE_NIBBLE_LC_LTYPE BIT_ULL(12) 54 #define NPC_CN20K_PARSE_NIBBLE_LD_FLAGS BIT_ULL(13) 55 #define NPC_CN20K_PARSE_NIBBLE_LD_LTYPE BIT_ULL(14) 56 #define NPC_CN20K_PARSE_NIBBLE_LE_FLAGS BIT_ULL(15) 57 #define NPC_CN20K_PARSE_NIBBLE_LE_LTYPE BIT_ULL(16) 58 #define NPC_CN20K_PARSE_NIBBLE_LF_FLAGS BIT_ULL(17) 59 #define NPC_CN20K_PARSE_NIBBLE_LF_LTYPE BIT_ULL(18) 60 #define NPC_CN20K_PARSE_NIBBLE_LG_FLAGS BIT_ULL(19) 61 #define NPC_CN20K_PARSE_NIBBLE_LG_LTYPE BIT_ULL(20) 62 #define NPC_CN20K_PARSE_NIBBLE_LH_FLAGS BIT_ULL(21) 63 #define NPC_CN20K_PARSE_NIBBLE_LH_LTYPE BIT_ULL(22) 64 65 /* Rx parse key extract nibble enable */ 66 #define NPC_CN20K_PARSE_NIBBLE_INTF_RX (NPC_CN20K_PARSE_NIBBLE_CHAN | \ 67 NPC_CN20K_PARSE_NIBBLE_L2L3_BCAST | \ 68 NPC_CN20K_PARSE_NIBBLE_LA_LTYPE | \ 69 NPC_CN20K_PARSE_NIBBLE_LB_LTYPE | \ 70 NPC_CN20K_PARSE_NIBBLE_LC_FLAGS | \ 71 NPC_CN20K_PARSE_NIBBLE_LC_LTYPE | \ 72 NPC_CN20K_PARSE_NIBBLE_LD_LTYPE | \ 73 NPC_CN20K_PARSE_NIBBLE_LE_LTYPE) 74 75 /* Tx parse key extract nibble enable */ 76 #define NPC_CN20K_PARSE_NIBBLE_INTF_TX (NPC_CN20K_PARSE_NIBBLE_LA_LTYPE | \ 77 NPC_CN20K_PARSE_NIBBLE_LB_LTYPE | \ 78 NPC_CN20K_PARSE_NIBBLE_LC_LTYPE | \ 79 NPC_CN20K_PARSE_NIBBLE_LD_LTYPE | \ 80 NPC_CN20K_PARSE_NIBBLE_LE_LTYPE) 81 82 /** 83 * enum npc_subbank_flag - NPC subbank status 84 * 85 * subbank flag indicates whether the subbank is free 86 * or used. 87 * 88 * @NPC_SUBBANK_FLAG_UNINIT: Subbank is not initialized. 89 * @NPC_SUBBANK_FLAG_FREE: Subbank is free. 90 * @NPC_SUBBANK_FLAG_USED: Subbank is used. 91 */ 92 enum npc_subbank_flag { 93 NPC_SUBBANK_FLAG_UNINIT, 94 NPC_SUBBANK_FLAG_FREE = BIT(0), 95 NPC_SUBBANK_FLAG_USED = BIT(1), 96 }; 97 98 /** 99 * enum npc_dft_rule_id - Default rule type 100 * 101 * Mcam default rule type. 102 * 103 * @NPC_DFT_RULE_START_ID: Not used 104 * @NPC_DFT_RULE_PROMISC_ID: promiscuous rule 105 * @NPC_DFT_RULE_MCAST_ID: multicast rule 106 * @NPC_DFT_RULE_BCAST_ID: broadcast rule 107 * @NPC_DFT_RULE_UCAST_ID: unicast rule 108 * @NPC_DFT_RULE_MAX_ID: Maximum index. 109 */ 110 enum npc_dft_rule_id { 111 NPC_DFT_RULE_START_ID = 1, 112 NPC_DFT_RULE_PROMISC_ID = NPC_DFT_RULE_START_ID, 113 NPC_DFT_RULE_MCAST_ID, 114 NPC_DFT_RULE_BCAST_ID, 115 NPC_DFT_RULE_UCAST_ID, 116 NPC_DFT_RULE_MAX_ID, 117 }; 118 119 /** 120 * struct npc_subbank - Subbank fields. 121 * @b0b: Subbanks bottom index for bank0 122 * @b1b: Subbanks bottom index for bank1 123 * @b0t: Subbanks top index for bank0 124 * @b1t: Subbanks top index for bank1 125 * @flags: Subbank flags 126 * @lock: Mutex lock for flags and rsrc mofiication 127 * @b0map: Bitmap map for bank0 indexes 128 * @b1map: Bitmap map for bank1 indexes 129 * @idx: Subbank index 130 * @arr_idx: Index to the free array or used array 131 * @free_cnt: Number of free slots in the subbank. 132 * @key_type: X4 or X2 subbank. 133 * 134 * MCAM resource is divided horizontally into multiple subbanks and 135 * Resource allocation from each subbank is managed by this data 136 * structure. 137 */ 138 struct npc_subbank { 139 u16 b0t, b0b, b1t, b1b; 140 enum npc_subbank_flag flags; 141 struct mutex lock; /* Protect subbank resources */ 142 DECLARE_BITMAP(b0map, MAX_SUBBANK_DEPTH); 143 DECLARE_BITMAP(b1map, MAX_SUBBANK_DEPTH); 144 u16 idx; 145 u16 arr_idx; 146 u16 free_cnt; 147 u8 key_type; 148 }; 149 150 /** 151 * struct npc_defrag_show_node - Defragmentation show node 152 * @old_midx: Old mcam index. 153 * @new_midx: New mcam index. 154 * @vidx: Virtual index 155 * @list: Linked list of these nodes 156 * 157 * This structure holds information on last defragmentation 158 * executed on mcam resource. 159 */ 160 struct npc_defrag_show_node { 161 u16 old_midx; 162 u16 new_midx; 163 u16 vidx; 164 struct list_head list; 165 }; 166 167 /** 168 * struct npc_priv_t - NPC private structure. 169 * @bank_depth: Total entries in each bank. 170 * @num_banks: Number of banks. 171 * @num_subbanks: Number of subbanks. 172 * @subbank_depth: Depth of subbank. 173 * @kw: Kex configured key type. 174 * @sb: Subbank array. 175 * @xa_sb_used: Array of used subbanks. 176 * @xa_sb_free: Array of free subbanks. 177 * @xa_pf2idx_map: PF to mcam index map. 178 * @xa_idx2pf_map: Mcam index to PF map. 179 * @xa_pf_map: Pcifunc to index map. 180 * @pf_cnt: Number of PFs. 181 * @init_done: Indicates MCAM initialization is done. 182 * @xa_pf2dfl_rmap: PF to default rule index map. 183 * @xa_idx2vidx_map: Mcam index to virtual index map. 184 * @xa_vidx2idx_map: virtual index to mcam index map. 185 * @defrag_lh: Defrag list head. 186 * @lock: Lock for defrag list 187 * 188 * This structure is populated during probing time by reading 189 * HW csr registers. 190 */ 191 struct npc_priv_t { 192 int bank_depth; 193 const int num_banks; 194 int num_subbanks; 195 int subbank_depth; 196 u8 kw; 197 struct npc_subbank *sb; 198 struct xarray xa_sb_used; 199 struct xarray xa_sb_free; 200 struct xarray *xa_pf2idx_map; 201 struct xarray xa_idx2pf_map; 202 struct xarray xa_pf_map; 203 struct xarray xa_pf2dfl_rmap; 204 struct xarray xa_idx2vidx_map; 205 struct xarray xa_vidx2idx_map; 206 struct list_head defrag_lh; 207 struct mutex lock; /* protect defrag nodes */ 208 int pf_cnt; 209 bool init_done; 210 }; 211 212 struct npc_kpm_action0 { 213 #if defined(__BIG_ENDIAN_BITFIELD) 214 u64 rsvd_63_57 : 7; 215 u64 byp_count : 3; 216 u64 capture_ena : 1; 217 u64 parse_done : 1; 218 u64 next_state : 8; 219 u64 rsvd_43 : 1; 220 u64 capture_lid : 3; 221 u64 capture_ltype : 4; 222 u64 rsvd_32_35 : 4; 223 u64 capture_flags : 4; 224 u64 ptr_advance : 8; 225 u64 var_len_offset : 8; 226 u64 var_len_mask : 8; 227 u64 var_len_right : 1; 228 u64 var_len_shift : 3; 229 #else 230 u64 var_len_shift : 3; 231 u64 var_len_right : 1; 232 u64 var_len_mask : 8; 233 u64 var_len_offset : 8; 234 u64 ptr_advance : 8; 235 u64 capture_flags : 4; 236 u64 rsvd_32_35 : 4; 237 u64 capture_ltype : 4; 238 u64 capture_lid : 3; 239 u64 rsvd_43 : 1; 240 u64 next_state : 8; 241 u64 parse_done : 1; 242 u64 capture_ena : 1; 243 u64 byp_count : 3; 244 u64 rsvd_63_57 : 7; 245 #endif 246 }; 247 248 struct npc_mcam_kex_extr { 249 /* MKEX Profle Header */ 250 u64 mkex_sign; /* "mcam-kex-profile" (8 bytes/ASCII characters) */ 251 u8 name[MKEX_NAME_LEN]; /* MKEX Profile name */ 252 u64 cpu_model; /* Format as profiled by CPU hardware */ 253 u64 kpu_version; /* KPU firmware/profile version */ 254 u64 reserved; /* Reserved for extension */ 255 256 /* MKEX Profle Data */ 257 u64 keyx_cfg[NPC_MAX_INTF]; /* NPC_AF_INTF(0..1)_KEX_CFG */ 258 #define NPC_MAX_EXTRACTOR 24 259 /* MKEX Extractor data */ 260 u64 intf_extr_lid[NPC_MAX_INTF][NPC_MAX_EXTRACTOR]; 261 /* KEX configuration per extractor */ 262 u64 intf_extr_lt[NPC_MAX_INTF][NPC_MAX_EXTRACTOR][NPC_MAX_LT]; 263 } __packed; 264 265 struct npc_cn20k_kpu_profile_fwdata { 266 #define KPU_SIGN 0x00666f727075706b 267 #define KPU_NAME_LEN 32 268 /* Maximum number of custom KPU entries supported by 269 * the built-in profile. 270 */ 271 #define KPU_CN20K_MAX_CST_ENT 6 272 /* KPU Profle Header */ 273 __le64 signature; /* "kpuprof\0" (8 bytes/ASCII characters) */ 274 u8 name[KPU_NAME_LEN]; /* KPU Profile name */ 275 __le64 version; /* KPU profile version */ 276 u8 kpus; 277 u8 reserved[7]; 278 279 /* Default MKEX profile to be used with this KPU profile. May be 280 * overridden with mkex_profile module parameter. 281 * Format is same as for the MKEX profile to streamline processing. 282 */ 283 struct npc_mcam_kex_extr mkex; 284 /* LTYPE values for specific HW offloaded protocols. */ 285 struct npc_lt_def_cfg lt_def; 286 /* Dynamically sized data: 287 * Custom KPU CAM and ACTION configuration entries. 288 * struct npc_kpu_fwdata kpu[kpus]; 289 */ 290 u8 data[]; 291 } __packed; 292 293 struct rvu; 294 295 struct npc_priv_t *npc_priv_get(void); 296 int npc_cn20k_init(struct rvu *rvu); 297 void npc_cn20k_deinit(struct rvu *rvu); 298 299 void npc_cn20k_subbank_calc_free(struct rvu *rvu, int *x2_free, 300 int *x4_free, int *sb_free); 301 302 int npc_cn20k_ref_idx_alloc(struct rvu *rvu, int pcifunc, int key_type, 303 int prio, u16 *mcam_idx, int ref, int limit, 304 bool contig, int count, bool virt); 305 int npc_cn20k_idx_free(struct rvu *rvu, u16 *mcam_idx, int count); 306 void npc_cn20k_parser_profile_init(struct rvu *rvu, int blkaddr); 307 struct npc_mcam_kex_extr *npc_mkex_extr_default_get(void); 308 void npc_cn20k_load_mkex_profile(struct rvu *rvu, int blkaddr, 309 const char *mkex_profile); 310 int npc_cn20k_apply_custom_kpu(struct rvu *rvu, 311 struct npc_kpu_profile_adapter *profile); 312 313 void 314 npc_cn20k_update_action_entries_n_flags(struct rvu *rvu, 315 struct npc_kpu_profile_adapter *pfl); 316 317 int npc_cn20k_dft_rules_alloc(struct rvu *rvu, u16 pcifunc); 318 void npc_cn20k_dft_rules_free(struct rvu *rvu, u16 pcifunc); 319 320 int npc_cn20k_dft_rules_idx_get(struct rvu *rvu, u16 pcifunc, u16 *bcast, 321 u16 *mcast, u16 *promisc, u16 *ucast); 322 323 int npc_cn20k_config_mcam_entry(struct rvu *rvu, int blkaddr, int index, 324 u8 intf, struct cn20k_mcam_entry *entry, 325 bool enable, u8 hw_prio, u8 req_kw_type); 326 int npc_cn20k_enable_mcam_entry(struct rvu *rvu, int blkaddr, 327 int index, bool enable); 328 int npc_cn20k_copy_mcam_entry(struct rvu *rvu, int blkaddr, 329 u16 src, u16 dest); 330 int npc_cn20k_read_mcam_entry(struct rvu *rvu, int blkaddr, u16 index, 331 struct cn20k_mcam_entry *entry, u8 *intf, 332 u8 *ena, u8 *hw_prio); 333 int npc_cn20k_clear_mcam_entry(struct rvu *rvu, int blkaddr, int index); 334 int npc_mcam_idx_2_key_type(struct rvu *rvu, u16 mcam_idx, u8 *key_type); 335 u16 npc_cn20k_vidx2idx(u16 index); 336 u16 npc_cn20k_idx2vidx(u16 idx); 337 int npc_cn20k_defrag(struct rvu *rvu); 338 bool npc_is_cgx_or_lbk(struct rvu *rvu, u16 pcifunc); 339 340 #endif /* NPC_CN20K_H */ 341