1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AmLogic Meson-AXG Clock Controller Driver 4 * 5 * Copyright (c) 2016 Baylibre SAS. 6 * Author: Michael Turquette <mturquette@baylibre.com> 7 * 8 * Copyright (c) 2017 Amlogic, inc. 9 * Author: Qiufang Dai <qiufang.dai@amlogic.com> 10 */ 11 12 #include <linux/clk-provider.h> 13 #include <linux/init.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/platform_device.h> 16 #include <linux/module.h> 17 18 #include "clk-regmap.h" 19 #include "clk-pll.h" 20 #include "clk-mpll.h" 21 #include "axg.h" 22 #include "meson-eeclk.h" 23 24 #include <dt-bindings/clock/axg-clkc.h> 25 26 static struct clk_regmap axg_fixed_pll_dco = { 27 .data = &(struct meson_clk_pll_data){ 28 .en = { 29 .reg_off = HHI_MPLL_CNTL, 30 .shift = 30, 31 .width = 1, 32 }, 33 .m = { 34 .reg_off = HHI_MPLL_CNTL, 35 .shift = 0, 36 .width = 9, 37 }, 38 .n = { 39 .reg_off = HHI_MPLL_CNTL, 40 .shift = 9, 41 .width = 5, 42 }, 43 .frac = { 44 .reg_off = HHI_MPLL_CNTL2, 45 .shift = 0, 46 .width = 12, 47 }, 48 .l = { 49 .reg_off = HHI_MPLL_CNTL, 50 .shift = 31, 51 .width = 1, 52 }, 53 .rst = { 54 .reg_off = HHI_MPLL_CNTL, 55 .shift = 29, 56 .width = 1, 57 }, 58 }, 59 .hw.init = &(struct clk_init_data){ 60 .name = "fixed_pll_dco", 61 .ops = &meson_clk_pll_ro_ops, 62 .parent_data = &(const struct clk_parent_data) { 63 .fw_name = "xtal", 64 }, 65 .num_parents = 1, 66 }, 67 }; 68 69 static struct clk_regmap axg_fixed_pll = { 70 .data = &(struct clk_regmap_div_data){ 71 .offset = HHI_MPLL_CNTL, 72 .shift = 16, 73 .width = 2, 74 .flags = CLK_DIVIDER_POWER_OF_TWO, 75 }, 76 .hw.init = &(struct clk_init_data){ 77 .name = "fixed_pll", 78 .ops = &clk_regmap_divider_ro_ops, 79 .parent_hws = (const struct clk_hw *[]) { 80 &axg_fixed_pll_dco.hw 81 }, 82 .num_parents = 1, 83 /* 84 * This clock won't ever change at runtime so 85 * CLK_SET_RATE_PARENT is not required 86 */ 87 }, 88 }; 89 90 static struct clk_regmap axg_sys_pll_dco = { 91 .data = &(struct meson_clk_pll_data){ 92 .en = { 93 .reg_off = HHI_SYS_PLL_CNTL, 94 .shift = 30, 95 .width = 1, 96 }, 97 .m = { 98 .reg_off = HHI_SYS_PLL_CNTL, 99 .shift = 0, 100 .width = 9, 101 }, 102 .n = { 103 .reg_off = HHI_SYS_PLL_CNTL, 104 .shift = 9, 105 .width = 5, 106 }, 107 .l = { 108 .reg_off = HHI_SYS_PLL_CNTL, 109 .shift = 31, 110 .width = 1, 111 }, 112 .rst = { 113 .reg_off = HHI_SYS_PLL_CNTL, 114 .shift = 29, 115 .width = 1, 116 }, 117 }, 118 .hw.init = &(struct clk_init_data){ 119 .name = "sys_pll_dco", 120 .ops = &meson_clk_pll_ro_ops, 121 .parent_data = &(const struct clk_parent_data) { 122 .fw_name = "xtal", 123 }, 124 .num_parents = 1, 125 }, 126 }; 127 128 static struct clk_regmap axg_sys_pll = { 129 .data = &(struct clk_regmap_div_data){ 130 .offset = HHI_SYS_PLL_CNTL, 131 .shift = 16, 132 .width = 2, 133 .flags = CLK_DIVIDER_POWER_OF_TWO, 134 }, 135 .hw.init = &(struct clk_init_data){ 136 .name = "sys_pll", 137 .ops = &clk_regmap_divider_ro_ops, 138 .parent_hws = (const struct clk_hw *[]) { 139 &axg_sys_pll_dco.hw 140 }, 141 .num_parents = 1, 142 .flags = CLK_SET_RATE_PARENT, 143 }, 144 }; 145 146 static const struct pll_params_table axg_gp0_pll_params_table[] = { 147 PLL_PARAMS(40, 1), 148 PLL_PARAMS(41, 1), 149 PLL_PARAMS(42, 1), 150 PLL_PARAMS(43, 1), 151 PLL_PARAMS(44, 1), 152 PLL_PARAMS(45, 1), 153 PLL_PARAMS(46, 1), 154 PLL_PARAMS(47, 1), 155 PLL_PARAMS(48, 1), 156 PLL_PARAMS(49, 1), 157 PLL_PARAMS(50, 1), 158 PLL_PARAMS(51, 1), 159 PLL_PARAMS(52, 1), 160 PLL_PARAMS(53, 1), 161 PLL_PARAMS(54, 1), 162 PLL_PARAMS(55, 1), 163 PLL_PARAMS(56, 1), 164 PLL_PARAMS(57, 1), 165 PLL_PARAMS(58, 1), 166 PLL_PARAMS(59, 1), 167 PLL_PARAMS(60, 1), 168 PLL_PARAMS(61, 1), 169 PLL_PARAMS(62, 1), 170 PLL_PARAMS(63, 1), 171 PLL_PARAMS(64, 1), 172 PLL_PARAMS(65, 1), 173 PLL_PARAMS(66, 1), 174 PLL_PARAMS(67, 1), 175 PLL_PARAMS(68, 1), 176 { /* sentinel */ }, 177 }; 178 179 static const struct reg_sequence axg_gp0_init_regs[] = { 180 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, 181 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, 182 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, 183 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, 184 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, 185 }; 186 187 static struct clk_regmap axg_gp0_pll_dco = { 188 .data = &(struct meson_clk_pll_data){ 189 .en = { 190 .reg_off = HHI_GP0_PLL_CNTL, 191 .shift = 30, 192 .width = 1, 193 }, 194 .m = { 195 .reg_off = HHI_GP0_PLL_CNTL, 196 .shift = 0, 197 .width = 9, 198 }, 199 .n = { 200 .reg_off = HHI_GP0_PLL_CNTL, 201 .shift = 9, 202 .width = 5, 203 }, 204 .frac = { 205 .reg_off = HHI_GP0_PLL_CNTL1, 206 .shift = 0, 207 .width = 10, 208 }, 209 .l = { 210 .reg_off = HHI_GP0_PLL_CNTL, 211 .shift = 31, 212 .width = 1, 213 }, 214 .rst = { 215 .reg_off = HHI_GP0_PLL_CNTL, 216 .shift = 29, 217 .width = 1, 218 }, 219 .table = axg_gp0_pll_params_table, 220 .init_regs = axg_gp0_init_regs, 221 .init_count = ARRAY_SIZE(axg_gp0_init_regs), 222 }, 223 .hw.init = &(struct clk_init_data){ 224 .name = "gp0_pll_dco", 225 .ops = &meson_clk_pll_ops, 226 .parent_data = &(const struct clk_parent_data) { 227 .fw_name = "xtal", 228 }, 229 .num_parents = 1, 230 }, 231 }; 232 233 static struct clk_regmap axg_gp0_pll = { 234 .data = &(struct clk_regmap_div_data){ 235 .offset = HHI_GP0_PLL_CNTL, 236 .shift = 16, 237 .width = 2, 238 .flags = CLK_DIVIDER_POWER_OF_TWO, 239 }, 240 .hw.init = &(struct clk_init_data){ 241 .name = "gp0_pll", 242 .ops = &clk_regmap_divider_ops, 243 .parent_hws = (const struct clk_hw *[]) { 244 &axg_gp0_pll_dco.hw 245 }, 246 .num_parents = 1, 247 .flags = CLK_SET_RATE_PARENT, 248 }, 249 }; 250 251 static const struct reg_sequence axg_hifi_init_regs[] = { 252 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 }, 253 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be }, 254 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 }, 255 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d }, 256 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 }, 257 }; 258 259 static struct clk_regmap axg_hifi_pll_dco = { 260 .data = &(struct meson_clk_pll_data){ 261 .en = { 262 .reg_off = HHI_HIFI_PLL_CNTL, 263 .shift = 30, 264 .width = 1, 265 }, 266 .m = { 267 .reg_off = HHI_HIFI_PLL_CNTL, 268 .shift = 0, 269 .width = 9, 270 }, 271 .n = { 272 .reg_off = HHI_HIFI_PLL_CNTL, 273 .shift = 9, 274 .width = 5, 275 }, 276 .frac = { 277 .reg_off = HHI_HIFI_PLL_CNTL5, 278 .shift = 0, 279 .width = 13, 280 }, 281 .l = { 282 .reg_off = HHI_HIFI_PLL_CNTL, 283 .shift = 31, 284 .width = 1, 285 }, 286 .rst = { 287 .reg_off = HHI_HIFI_PLL_CNTL, 288 .shift = 29, 289 .width = 1, 290 }, 291 .table = axg_gp0_pll_params_table, 292 .init_regs = axg_hifi_init_regs, 293 .init_count = ARRAY_SIZE(axg_hifi_init_regs), 294 .flags = CLK_MESON_PLL_ROUND_CLOSEST, 295 }, 296 .hw.init = &(struct clk_init_data){ 297 .name = "hifi_pll_dco", 298 .ops = &meson_clk_pll_ops, 299 .parent_data = &(const struct clk_parent_data) { 300 .fw_name = "xtal", 301 }, 302 .num_parents = 1, 303 }, 304 }; 305 306 static struct clk_regmap axg_hifi_pll = { 307 .data = &(struct clk_regmap_div_data){ 308 .offset = HHI_HIFI_PLL_CNTL, 309 .shift = 16, 310 .width = 2, 311 .flags = CLK_DIVIDER_POWER_OF_TWO, 312 }, 313 .hw.init = &(struct clk_init_data){ 314 .name = "hifi_pll", 315 .ops = &clk_regmap_divider_ops, 316 .parent_hws = (const struct clk_hw *[]) { 317 &axg_hifi_pll_dco.hw 318 }, 319 .num_parents = 1, 320 .flags = CLK_SET_RATE_PARENT, 321 }, 322 }; 323 324 static struct clk_fixed_factor axg_fclk_div2_div = { 325 .mult = 1, 326 .div = 2, 327 .hw.init = &(struct clk_init_data){ 328 .name = "fclk_div2_div", 329 .ops = &clk_fixed_factor_ops, 330 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 331 .num_parents = 1, 332 }, 333 }; 334 335 static struct clk_regmap axg_fclk_div2 = { 336 .data = &(struct clk_regmap_gate_data){ 337 .offset = HHI_MPLL_CNTL6, 338 .bit_idx = 27, 339 }, 340 .hw.init = &(struct clk_init_data){ 341 .name = "fclk_div2", 342 .ops = &clk_regmap_gate_ops, 343 .parent_hws = (const struct clk_hw *[]) { 344 &axg_fclk_div2_div.hw 345 }, 346 .num_parents = 1, 347 .flags = CLK_IS_CRITICAL, 348 }, 349 }; 350 351 static struct clk_fixed_factor axg_fclk_div3_div = { 352 .mult = 1, 353 .div = 3, 354 .hw.init = &(struct clk_init_data){ 355 .name = "fclk_div3_div", 356 .ops = &clk_fixed_factor_ops, 357 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 358 .num_parents = 1, 359 }, 360 }; 361 362 static struct clk_regmap axg_fclk_div3 = { 363 .data = &(struct clk_regmap_gate_data){ 364 .offset = HHI_MPLL_CNTL6, 365 .bit_idx = 28, 366 }, 367 .hw.init = &(struct clk_init_data){ 368 .name = "fclk_div3", 369 .ops = &clk_regmap_gate_ops, 370 .parent_hws = (const struct clk_hw *[]) { 371 &axg_fclk_div3_div.hw 372 }, 373 .num_parents = 1, 374 /* 375 * FIXME: 376 * This clock, as fdiv2, is used by the SCPI FW and is required 377 * by the platform to operate correctly. 378 * Until the following condition are met, we need this clock to 379 * be marked as critical: 380 * a) The SCPI generic driver claims and enable all the clocks 381 * it needs 382 * b) CCF has a clock hand-off mechanism to make the sure the 383 * clock stays on until the proper driver comes along 384 */ 385 .flags = CLK_IS_CRITICAL, 386 }, 387 }; 388 389 static struct clk_fixed_factor axg_fclk_div4_div = { 390 .mult = 1, 391 .div = 4, 392 .hw.init = &(struct clk_init_data){ 393 .name = "fclk_div4_div", 394 .ops = &clk_fixed_factor_ops, 395 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 396 .num_parents = 1, 397 }, 398 }; 399 400 static struct clk_regmap axg_fclk_div4 = { 401 .data = &(struct clk_regmap_gate_data){ 402 .offset = HHI_MPLL_CNTL6, 403 .bit_idx = 29, 404 }, 405 .hw.init = &(struct clk_init_data){ 406 .name = "fclk_div4", 407 .ops = &clk_regmap_gate_ops, 408 .parent_hws = (const struct clk_hw *[]) { 409 &axg_fclk_div4_div.hw 410 }, 411 .num_parents = 1, 412 }, 413 }; 414 415 static struct clk_fixed_factor axg_fclk_div5_div = { 416 .mult = 1, 417 .div = 5, 418 .hw.init = &(struct clk_init_data){ 419 .name = "fclk_div5_div", 420 .ops = &clk_fixed_factor_ops, 421 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 422 .num_parents = 1, 423 }, 424 }; 425 426 static struct clk_regmap axg_fclk_div5 = { 427 .data = &(struct clk_regmap_gate_data){ 428 .offset = HHI_MPLL_CNTL6, 429 .bit_idx = 30, 430 }, 431 .hw.init = &(struct clk_init_data){ 432 .name = "fclk_div5", 433 .ops = &clk_regmap_gate_ops, 434 .parent_hws = (const struct clk_hw *[]) { 435 &axg_fclk_div5_div.hw 436 }, 437 .num_parents = 1, 438 }, 439 }; 440 441 static struct clk_fixed_factor axg_fclk_div7_div = { 442 .mult = 1, 443 .div = 7, 444 .hw.init = &(struct clk_init_data){ 445 .name = "fclk_div7_div", 446 .ops = &clk_fixed_factor_ops, 447 .parent_hws = (const struct clk_hw *[]) { 448 &axg_fixed_pll.hw 449 }, 450 .num_parents = 1, 451 }, 452 }; 453 454 static struct clk_regmap axg_fclk_div7 = { 455 .data = &(struct clk_regmap_gate_data){ 456 .offset = HHI_MPLL_CNTL6, 457 .bit_idx = 31, 458 }, 459 .hw.init = &(struct clk_init_data){ 460 .name = "fclk_div7", 461 .ops = &clk_regmap_gate_ops, 462 .parent_hws = (const struct clk_hw *[]) { 463 &axg_fclk_div7_div.hw 464 }, 465 .num_parents = 1, 466 }, 467 }; 468 469 static struct clk_regmap axg_mpll_prediv = { 470 .data = &(struct clk_regmap_div_data){ 471 .offset = HHI_MPLL_CNTL5, 472 .shift = 12, 473 .width = 1, 474 }, 475 .hw.init = &(struct clk_init_data){ 476 .name = "mpll_prediv", 477 .ops = &clk_regmap_divider_ro_ops, 478 .parent_hws = (const struct clk_hw *[]) { 479 &axg_fixed_pll.hw 480 }, 481 .num_parents = 1, 482 }, 483 }; 484 485 static struct clk_regmap axg_mpll0_div = { 486 .data = &(struct meson_clk_mpll_data){ 487 .sdm = { 488 .reg_off = HHI_MPLL_CNTL7, 489 .shift = 0, 490 .width = 14, 491 }, 492 .sdm_en = { 493 .reg_off = HHI_MPLL_CNTL7, 494 .shift = 15, 495 .width = 1, 496 }, 497 .n2 = { 498 .reg_off = HHI_MPLL_CNTL7, 499 .shift = 16, 500 .width = 9, 501 }, 502 .misc = { 503 .reg_off = HHI_PLL_TOP_MISC, 504 .shift = 0, 505 .width = 1, 506 }, 507 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 508 }, 509 .hw.init = &(struct clk_init_data){ 510 .name = "mpll0_div", 511 .ops = &meson_clk_mpll_ops, 512 .parent_hws = (const struct clk_hw *[]) { 513 &axg_mpll_prediv.hw 514 }, 515 .num_parents = 1, 516 }, 517 }; 518 519 static struct clk_regmap axg_mpll0 = { 520 .data = &(struct clk_regmap_gate_data){ 521 .offset = HHI_MPLL_CNTL7, 522 .bit_idx = 14, 523 }, 524 .hw.init = &(struct clk_init_data){ 525 .name = "mpll0", 526 .ops = &clk_regmap_gate_ops, 527 .parent_hws = (const struct clk_hw *[]) { 528 &axg_mpll0_div.hw 529 }, 530 .num_parents = 1, 531 .flags = CLK_SET_RATE_PARENT, 532 }, 533 }; 534 535 static struct clk_regmap axg_mpll1_div = { 536 .data = &(struct meson_clk_mpll_data){ 537 .sdm = { 538 .reg_off = HHI_MPLL_CNTL8, 539 .shift = 0, 540 .width = 14, 541 }, 542 .sdm_en = { 543 .reg_off = HHI_MPLL_CNTL8, 544 .shift = 15, 545 .width = 1, 546 }, 547 .n2 = { 548 .reg_off = HHI_MPLL_CNTL8, 549 .shift = 16, 550 .width = 9, 551 }, 552 .misc = { 553 .reg_off = HHI_PLL_TOP_MISC, 554 .shift = 1, 555 .width = 1, 556 }, 557 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 558 }, 559 .hw.init = &(struct clk_init_data){ 560 .name = "mpll1_div", 561 .ops = &meson_clk_mpll_ops, 562 .parent_hws = (const struct clk_hw *[]) { 563 &axg_mpll_prediv.hw 564 }, 565 .num_parents = 1, 566 }, 567 }; 568 569 static struct clk_regmap axg_mpll1 = { 570 .data = &(struct clk_regmap_gate_data){ 571 .offset = HHI_MPLL_CNTL8, 572 .bit_idx = 14, 573 }, 574 .hw.init = &(struct clk_init_data){ 575 .name = "mpll1", 576 .ops = &clk_regmap_gate_ops, 577 .parent_hws = (const struct clk_hw *[]) { 578 &axg_mpll1_div.hw 579 }, 580 .num_parents = 1, 581 .flags = CLK_SET_RATE_PARENT, 582 }, 583 }; 584 585 static struct clk_regmap axg_mpll2_div = { 586 .data = &(struct meson_clk_mpll_data){ 587 .sdm = { 588 .reg_off = HHI_MPLL_CNTL9, 589 .shift = 0, 590 .width = 14, 591 }, 592 .sdm_en = { 593 .reg_off = HHI_MPLL_CNTL9, 594 .shift = 15, 595 .width = 1, 596 }, 597 .n2 = { 598 .reg_off = HHI_MPLL_CNTL9, 599 .shift = 16, 600 .width = 9, 601 }, 602 .ssen = { 603 .reg_off = HHI_MPLL_CNTL, 604 .shift = 25, 605 .width = 1, 606 }, 607 .misc = { 608 .reg_off = HHI_PLL_TOP_MISC, 609 .shift = 2, 610 .width = 1, 611 }, 612 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 613 }, 614 .hw.init = &(struct clk_init_data){ 615 .name = "mpll2_div", 616 .ops = &meson_clk_mpll_ops, 617 .parent_hws = (const struct clk_hw *[]) { 618 &axg_mpll_prediv.hw 619 }, 620 .num_parents = 1, 621 }, 622 }; 623 624 static struct clk_regmap axg_mpll2 = { 625 .data = &(struct clk_regmap_gate_data){ 626 .offset = HHI_MPLL_CNTL9, 627 .bit_idx = 14, 628 }, 629 .hw.init = &(struct clk_init_data){ 630 .name = "mpll2", 631 .ops = &clk_regmap_gate_ops, 632 .parent_hws = (const struct clk_hw *[]) { 633 &axg_mpll2_div.hw 634 }, 635 .num_parents = 1, 636 .flags = CLK_SET_RATE_PARENT, 637 }, 638 }; 639 640 static struct clk_regmap axg_mpll3_div = { 641 .data = &(struct meson_clk_mpll_data){ 642 .sdm = { 643 .reg_off = HHI_MPLL3_CNTL0, 644 .shift = 12, 645 .width = 14, 646 }, 647 .sdm_en = { 648 .reg_off = HHI_MPLL3_CNTL0, 649 .shift = 11, 650 .width = 1, 651 }, 652 .n2 = { 653 .reg_off = HHI_MPLL3_CNTL0, 654 .shift = 2, 655 .width = 9, 656 }, 657 .misc = { 658 .reg_off = HHI_PLL_TOP_MISC, 659 .shift = 3, 660 .width = 1, 661 }, 662 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 663 }, 664 .hw.init = &(struct clk_init_data){ 665 .name = "mpll3_div", 666 .ops = &meson_clk_mpll_ops, 667 .parent_hws = (const struct clk_hw *[]) { 668 &axg_mpll_prediv.hw 669 }, 670 .num_parents = 1, 671 }, 672 }; 673 674 static struct clk_regmap axg_mpll3 = { 675 .data = &(struct clk_regmap_gate_data){ 676 .offset = HHI_MPLL3_CNTL0, 677 .bit_idx = 0, 678 }, 679 .hw.init = &(struct clk_init_data){ 680 .name = "mpll3", 681 .ops = &clk_regmap_gate_ops, 682 .parent_hws = (const struct clk_hw *[]) { 683 &axg_mpll3_div.hw 684 }, 685 .num_parents = 1, 686 .flags = CLK_SET_RATE_PARENT, 687 }, 688 }; 689 690 static const struct pll_params_table axg_pcie_pll_params_table[] = { 691 { 692 .m = 200, 693 .n = 3, 694 }, 695 { /* sentinel */ }, 696 }; 697 698 static const struct reg_sequence axg_pcie_init_regs[] = { 699 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa }, 700 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be }, 701 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e }, 702 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d }, 703 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 }, 704 { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 }, 705 { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 }, 706 }; 707 708 static struct clk_regmap axg_pcie_pll_dco = { 709 .data = &(struct meson_clk_pll_data){ 710 .en = { 711 .reg_off = HHI_PCIE_PLL_CNTL, 712 .shift = 30, 713 .width = 1, 714 }, 715 .m = { 716 .reg_off = HHI_PCIE_PLL_CNTL, 717 .shift = 0, 718 .width = 9, 719 }, 720 .n = { 721 .reg_off = HHI_PCIE_PLL_CNTL, 722 .shift = 9, 723 .width = 5, 724 }, 725 .frac = { 726 .reg_off = HHI_PCIE_PLL_CNTL1, 727 .shift = 0, 728 .width = 12, 729 }, 730 .l = { 731 .reg_off = HHI_PCIE_PLL_CNTL, 732 .shift = 31, 733 .width = 1, 734 }, 735 .rst = { 736 .reg_off = HHI_PCIE_PLL_CNTL, 737 .shift = 29, 738 .width = 1, 739 }, 740 .table = axg_pcie_pll_params_table, 741 .init_regs = axg_pcie_init_regs, 742 .init_count = ARRAY_SIZE(axg_pcie_init_regs), 743 }, 744 .hw.init = &(struct clk_init_data){ 745 .name = "pcie_pll_dco", 746 .ops = &meson_clk_pll_ops, 747 .parent_data = &(const struct clk_parent_data) { 748 .fw_name = "xtal", 749 }, 750 .num_parents = 1, 751 }, 752 }; 753 754 static struct clk_regmap axg_pcie_pll_od = { 755 .data = &(struct clk_regmap_div_data){ 756 .offset = HHI_PCIE_PLL_CNTL, 757 .shift = 16, 758 .width = 2, 759 .flags = CLK_DIVIDER_POWER_OF_TWO, 760 }, 761 .hw.init = &(struct clk_init_data){ 762 .name = "pcie_pll_od", 763 .ops = &clk_regmap_divider_ops, 764 .parent_hws = (const struct clk_hw *[]) { 765 &axg_pcie_pll_dco.hw 766 }, 767 .num_parents = 1, 768 .flags = CLK_SET_RATE_PARENT, 769 }, 770 }; 771 772 static struct clk_regmap axg_pcie_pll = { 773 .data = &(struct clk_regmap_div_data){ 774 .offset = HHI_PCIE_PLL_CNTL6, 775 .shift = 6, 776 .width = 2, 777 .flags = CLK_DIVIDER_POWER_OF_TWO, 778 }, 779 .hw.init = &(struct clk_init_data){ 780 .name = "pcie_pll", 781 .ops = &clk_regmap_divider_ops, 782 .parent_hws = (const struct clk_hw *[]) { 783 &axg_pcie_pll_od.hw 784 }, 785 .num_parents = 1, 786 .flags = CLK_SET_RATE_PARENT, 787 }, 788 }; 789 790 static struct clk_regmap axg_pcie_mux = { 791 .data = &(struct clk_regmap_mux_data){ 792 .offset = HHI_PCIE_PLL_CNTL6, 793 .mask = 0x1, 794 .shift = 2, 795 /* skip the parent mpll3, reserved for debug */ 796 .table = (u32[]){ 1 }, 797 }, 798 .hw.init = &(struct clk_init_data){ 799 .name = "pcie_mux", 800 .ops = &clk_regmap_mux_ops, 801 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_pll.hw }, 802 .num_parents = 1, 803 .flags = CLK_SET_RATE_PARENT, 804 }, 805 }; 806 807 static struct clk_regmap axg_pcie_ref = { 808 .data = &(struct clk_regmap_mux_data){ 809 .offset = HHI_PCIE_PLL_CNTL6, 810 .mask = 0x1, 811 .shift = 1, 812 /* skip the parent 0, reserved for debug */ 813 .table = (u32[]){ 1 }, 814 }, 815 .hw.init = &(struct clk_init_data){ 816 .name = "pcie_ref", 817 .ops = &clk_regmap_mux_ops, 818 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_mux.hw }, 819 .num_parents = 1, 820 .flags = CLK_SET_RATE_PARENT, 821 }, 822 }; 823 824 static struct clk_regmap axg_pcie_cml_en0 = { 825 .data = &(struct clk_regmap_gate_data){ 826 .offset = HHI_PCIE_PLL_CNTL6, 827 .bit_idx = 4, 828 }, 829 .hw.init = &(struct clk_init_data) { 830 .name = "pcie_cml_en0", 831 .ops = &clk_regmap_gate_ops, 832 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw }, 833 .num_parents = 1, 834 .flags = CLK_SET_RATE_PARENT, 835 836 }, 837 }; 838 839 static struct clk_regmap axg_pcie_cml_en1 = { 840 .data = &(struct clk_regmap_gate_data){ 841 .offset = HHI_PCIE_PLL_CNTL6, 842 .bit_idx = 3, 843 }, 844 .hw.init = &(struct clk_init_data) { 845 .name = "pcie_cml_en1", 846 .ops = &clk_regmap_gate_ops, 847 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw }, 848 .num_parents = 1, 849 .flags = CLK_SET_RATE_PARENT, 850 }, 851 }; 852 853 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 854 static const struct clk_parent_data clk81_parent_data[] = { 855 { .fw_name = "xtal", }, 856 { .hw = &axg_fclk_div7.hw }, 857 { .hw = &axg_mpll1.hw }, 858 { .hw = &axg_mpll2.hw }, 859 { .hw = &axg_fclk_div4.hw }, 860 { .hw = &axg_fclk_div3.hw }, 861 { .hw = &axg_fclk_div5.hw }, 862 }; 863 864 static struct clk_regmap axg_mpeg_clk_sel = { 865 .data = &(struct clk_regmap_mux_data){ 866 .offset = HHI_MPEG_CLK_CNTL, 867 .mask = 0x7, 868 .shift = 12, 869 .table = mux_table_clk81, 870 }, 871 .hw.init = &(struct clk_init_data){ 872 .name = "mpeg_clk_sel", 873 .ops = &clk_regmap_mux_ro_ops, 874 .parent_data = clk81_parent_data, 875 .num_parents = ARRAY_SIZE(clk81_parent_data), 876 }, 877 }; 878 879 static struct clk_regmap axg_mpeg_clk_div = { 880 .data = &(struct clk_regmap_div_data){ 881 .offset = HHI_MPEG_CLK_CNTL, 882 .shift = 0, 883 .width = 7, 884 }, 885 .hw.init = &(struct clk_init_data){ 886 .name = "mpeg_clk_div", 887 .ops = &clk_regmap_divider_ops, 888 .parent_hws = (const struct clk_hw *[]) { 889 &axg_mpeg_clk_sel.hw 890 }, 891 .num_parents = 1, 892 .flags = CLK_SET_RATE_PARENT, 893 }, 894 }; 895 896 static struct clk_regmap axg_clk81 = { 897 .data = &(struct clk_regmap_gate_data){ 898 .offset = HHI_MPEG_CLK_CNTL, 899 .bit_idx = 7, 900 }, 901 .hw.init = &(struct clk_init_data){ 902 .name = "clk81", 903 .ops = &clk_regmap_gate_ops, 904 .parent_hws = (const struct clk_hw *[]) { 905 &axg_mpeg_clk_div.hw 906 }, 907 .num_parents = 1, 908 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), 909 }, 910 }; 911 912 static const struct clk_parent_data axg_sd_emmc_clk0_parent_data[] = { 913 { .fw_name = "xtal", }, 914 { .hw = &axg_fclk_div2.hw }, 915 { .hw = &axg_fclk_div3.hw }, 916 { .hw = &axg_fclk_div5.hw }, 917 { .hw = &axg_fclk_div7.hw }, 918 /* 919 * Following these parent clocks, we should also have had mpll2, mpll3 920 * and gp0_pll but these clocks are too precious to be used here. All 921 * the necessary rates for MMC and NAND operation can be acheived using 922 * xtal or fclk_div clocks 923 */ 924 }; 925 926 /* SDcard clock */ 927 static struct clk_regmap axg_sd_emmc_b_clk0_sel = { 928 .data = &(struct clk_regmap_mux_data){ 929 .offset = HHI_SD_EMMC_CLK_CNTL, 930 .mask = 0x7, 931 .shift = 25, 932 }, 933 .hw.init = &(struct clk_init_data) { 934 .name = "sd_emmc_b_clk0_sel", 935 .ops = &clk_regmap_mux_ops, 936 .parent_data = axg_sd_emmc_clk0_parent_data, 937 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data), 938 .flags = CLK_SET_RATE_PARENT, 939 }, 940 }; 941 942 static struct clk_regmap axg_sd_emmc_b_clk0_div = { 943 .data = &(struct clk_regmap_div_data){ 944 .offset = HHI_SD_EMMC_CLK_CNTL, 945 .shift = 16, 946 .width = 7, 947 .flags = CLK_DIVIDER_ROUND_CLOSEST, 948 }, 949 .hw.init = &(struct clk_init_data) { 950 .name = "sd_emmc_b_clk0_div", 951 .ops = &clk_regmap_divider_ops, 952 .parent_hws = (const struct clk_hw *[]) { 953 &axg_sd_emmc_b_clk0_sel.hw 954 }, 955 .num_parents = 1, 956 .flags = CLK_SET_RATE_PARENT, 957 }, 958 }; 959 960 static struct clk_regmap axg_sd_emmc_b_clk0 = { 961 .data = &(struct clk_regmap_gate_data){ 962 .offset = HHI_SD_EMMC_CLK_CNTL, 963 .bit_idx = 23, 964 }, 965 .hw.init = &(struct clk_init_data){ 966 .name = "sd_emmc_b_clk0", 967 .ops = &clk_regmap_gate_ops, 968 .parent_hws = (const struct clk_hw *[]) { 969 &axg_sd_emmc_b_clk0_div.hw 970 }, 971 .num_parents = 1, 972 .flags = CLK_SET_RATE_PARENT, 973 }, 974 }; 975 976 /* EMMC/NAND clock */ 977 static struct clk_regmap axg_sd_emmc_c_clk0_sel = { 978 .data = &(struct clk_regmap_mux_data){ 979 .offset = HHI_NAND_CLK_CNTL, 980 .mask = 0x7, 981 .shift = 9, 982 }, 983 .hw.init = &(struct clk_init_data) { 984 .name = "sd_emmc_c_clk0_sel", 985 .ops = &clk_regmap_mux_ops, 986 .parent_data = axg_sd_emmc_clk0_parent_data, 987 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data), 988 .flags = CLK_SET_RATE_PARENT, 989 }, 990 }; 991 992 static struct clk_regmap axg_sd_emmc_c_clk0_div = { 993 .data = &(struct clk_regmap_div_data){ 994 .offset = HHI_NAND_CLK_CNTL, 995 .shift = 0, 996 .width = 7, 997 .flags = CLK_DIVIDER_ROUND_CLOSEST, 998 }, 999 .hw.init = &(struct clk_init_data) { 1000 .name = "sd_emmc_c_clk0_div", 1001 .ops = &clk_regmap_divider_ops, 1002 .parent_hws = (const struct clk_hw *[]) { 1003 &axg_sd_emmc_c_clk0_sel.hw 1004 }, 1005 .num_parents = 1, 1006 .flags = CLK_SET_RATE_PARENT, 1007 }, 1008 }; 1009 1010 static struct clk_regmap axg_sd_emmc_c_clk0 = { 1011 .data = &(struct clk_regmap_gate_data){ 1012 .offset = HHI_NAND_CLK_CNTL, 1013 .bit_idx = 7, 1014 }, 1015 .hw.init = &(struct clk_init_data){ 1016 .name = "sd_emmc_c_clk0", 1017 .ops = &clk_regmap_gate_ops, 1018 .parent_hws = (const struct clk_hw *[]) { 1019 &axg_sd_emmc_c_clk0_div.hw 1020 }, 1021 .num_parents = 1, 1022 .flags = CLK_SET_RATE_PARENT, 1023 }, 1024 }; 1025 1026 /* VPU Clock */ 1027 1028 static const struct clk_hw *axg_vpu_parent_hws[] = { 1029 &axg_fclk_div4.hw, 1030 &axg_fclk_div3.hw, 1031 &axg_fclk_div5.hw, 1032 &axg_fclk_div7.hw, 1033 }; 1034 1035 static struct clk_regmap axg_vpu_0_sel = { 1036 .data = &(struct clk_regmap_mux_data){ 1037 .offset = HHI_VPU_CLK_CNTL, 1038 .mask = 0x3, 1039 .shift = 9, 1040 }, 1041 .hw.init = &(struct clk_init_data){ 1042 .name = "vpu_0_sel", 1043 .ops = &clk_regmap_mux_ops, 1044 .parent_hws = axg_vpu_parent_hws, 1045 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws), 1046 /* We need a specific parent for VPU clock source, let it be set in DT */ 1047 .flags = CLK_SET_RATE_NO_REPARENT, 1048 }, 1049 }; 1050 1051 static struct clk_regmap axg_vpu_0_div = { 1052 .data = &(struct clk_regmap_div_data){ 1053 .offset = HHI_VPU_CLK_CNTL, 1054 .shift = 0, 1055 .width = 7, 1056 }, 1057 .hw.init = &(struct clk_init_data){ 1058 .name = "vpu_0_div", 1059 .ops = &clk_regmap_divider_ops, 1060 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_0_sel.hw }, 1061 .num_parents = 1, 1062 .flags = CLK_SET_RATE_PARENT, 1063 }, 1064 }; 1065 1066 static struct clk_regmap axg_vpu_0 = { 1067 .data = &(struct clk_regmap_gate_data){ 1068 .offset = HHI_VPU_CLK_CNTL, 1069 .bit_idx = 8, 1070 }, 1071 .hw.init = &(struct clk_init_data) { 1072 .name = "vpu_0", 1073 .ops = &clk_regmap_gate_ops, 1074 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_0_div.hw }, 1075 .num_parents = 1, 1076 /* 1077 * We want to avoid CCF to disable the VPU clock if 1078 * display has been set by Bootloader 1079 */ 1080 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1081 }, 1082 }; 1083 1084 static struct clk_regmap axg_vpu_1_sel = { 1085 .data = &(struct clk_regmap_mux_data){ 1086 .offset = HHI_VPU_CLK_CNTL, 1087 .mask = 0x3, 1088 .shift = 25, 1089 }, 1090 .hw.init = &(struct clk_init_data){ 1091 .name = "vpu_1_sel", 1092 .ops = &clk_regmap_mux_ops, 1093 .parent_hws = axg_vpu_parent_hws, 1094 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws), 1095 /* We need a specific parent for VPU clock source, let it be set in DT */ 1096 .flags = CLK_SET_RATE_NO_REPARENT, 1097 }, 1098 }; 1099 1100 static struct clk_regmap axg_vpu_1_div = { 1101 .data = &(struct clk_regmap_div_data){ 1102 .offset = HHI_VPU_CLK_CNTL, 1103 .shift = 16, 1104 .width = 7, 1105 }, 1106 .hw.init = &(struct clk_init_data){ 1107 .name = "vpu_1_div", 1108 .ops = &clk_regmap_divider_ops, 1109 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_1_sel.hw }, 1110 .num_parents = 1, 1111 .flags = CLK_SET_RATE_PARENT, 1112 }, 1113 }; 1114 1115 static struct clk_regmap axg_vpu_1 = { 1116 .data = &(struct clk_regmap_gate_data){ 1117 .offset = HHI_VPU_CLK_CNTL, 1118 .bit_idx = 24, 1119 }, 1120 .hw.init = &(struct clk_init_data) { 1121 .name = "vpu_1", 1122 .ops = &clk_regmap_gate_ops, 1123 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_1_div.hw }, 1124 .num_parents = 1, 1125 /* 1126 * We want to avoid CCF to disable the VPU clock if 1127 * display has been set by Bootloader 1128 */ 1129 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1130 }, 1131 }; 1132 1133 static struct clk_regmap axg_vpu = { 1134 .data = &(struct clk_regmap_mux_data){ 1135 .offset = HHI_VPU_CLK_CNTL, 1136 .mask = 1, 1137 .shift = 31, 1138 }, 1139 .hw.init = &(struct clk_init_data){ 1140 .name = "vpu", 1141 .ops = &clk_regmap_mux_ops, 1142 .parent_hws = (const struct clk_hw *[]) { 1143 &axg_vpu_0.hw, 1144 &axg_vpu_1.hw 1145 }, 1146 .num_parents = 2, 1147 .flags = CLK_SET_RATE_NO_REPARENT, 1148 }, 1149 }; 1150 1151 /* VAPB Clock */ 1152 1153 static struct clk_regmap axg_vapb_0_sel = { 1154 .data = &(struct clk_regmap_mux_data){ 1155 .offset = HHI_VAPBCLK_CNTL, 1156 .mask = 0x3, 1157 .shift = 9, 1158 }, 1159 .hw.init = &(struct clk_init_data){ 1160 .name = "vapb_0_sel", 1161 .ops = &clk_regmap_mux_ops, 1162 .parent_hws = axg_vpu_parent_hws, 1163 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws), 1164 .flags = CLK_SET_RATE_NO_REPARENT, 1165 }, 1166 }; 1167 1168 static struct clk_regmap axg_vapb_0_div = { 1169 .data = &(struct clk_regmap_div_data){ 1170 .offset = HHI_VAPBCLK_CNTL, 1171 .shift = 0, 1172 .width = 7, 1173 }, 1174 .hw.init = &(struct clk_init_data){ 1175 .name = "vapb_0_div", 1176 .ops = &clk_regmap_divider_ops, 1177 .parent_hws = (const struct clk_hw *[]) { 1178 &axg_vapb_0_sel.hw 1179 }, 1180 .num_parents = 1, 1181 .flags = CLK_SET_RATE_PARENT, 1182 }, 1183 }; 1184 1185 static struct clk_regmap axg_vapb_0 = { 1186 .data = &(struct clk_regmap_gate_data){ 1187 .offset = HHI_VAPBCLK_CNTL, 1188 .bit_idx = 8, 1189 }, 1190 .hw.init = &(struct clk_init_data) { 1191 .name = "vapb_0", 1192 .ops = &clk_regmap_gate_ops, 1193 .parent_hws = (const struct clk_hw *[]) { 1194 &axg_vapb_0_div.hw 1195 }, 1196 .num_parents = 1, 1197 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1198 }, 1199 }; 1200 1201 static struct clk_regmap axg_vapb_1_sel = { 1202 .data = &(struct clk_regmap_mux_data){ 1203 .offset = HHI_VAPBCLK_CNTL, 1204 .mask = 0x3, 1205 .shift = 25, 1206 }, 1207 .hw.init = &(struct clk_init_data){ 1208 .name = "vapb_1_sel", 1209 .ops = &clk_regmap_mux_ops, 1210 .parent_hws = axg_vpu_parent_hws, 1211 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws), 1212 .flags = CLK_SET_RATE_NO_REPARENT, 1213 }, 1214 }; 1215 1216 static struct clk_regmap axg_vapb_1_div = { 1217 .data = &(struct clk_regmap_div_data){ 1218 .offset = HHI_VAPBCLK_CNTL, 1219 .shift = 16, 1220 .width = 7, 1221 }, 1222 .hw.init = &(struct clk_init_data){ 1223 .name = "vapb_1_div", 1224 .ops = &clk_regmap_divider_ops, 1225 .parent_hws = (const struct clk_hw *[]) { 1226 &axg_vapb_1_sel.hw 1227 }, 1228 .num_parents = 1, 1229 .flags = CLK_SET_RATE_PARENT, 1230 }, 1231 }; 1232 1233 static struct clk_regmap axg_vapb_1 = { 1234 .data = &(struct clk_regmap_gate_data){ 1235 .offset = HHI_VAPBCLK_CNTL, 1236 .bit_idx = 24, 1237 }, 1238 .hw.init = &(struct clk_init_data) { 1239 .name = "vapb_1", 1240 .ops = &clk_regmap_gate_ops, 1241 .parent_hws = (const struct clk_hw *[]) { 1242 &axg_vapb_1_div.hw 1243 }, 1244 .num_parents = 1, 1245 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1246 }, 1247 }; 1248 1249 static struct clk_regmap axg_vapb_sel = { 1250 .data = &(struct clk_regmap_mux_data){ 1251 .offset = HHI_VAPBCLK_CNTL, 1252 .mask = 1, 1253 .shift = 31, 1254 }, 1255 .hw.init = &(struct clk_init_data){ 1256 .name = "vapb_sel", 1257 .ops = &clk_regmap_mux_ops, 1258 .parent_hws = (const struct clk_hw *[]) { 1259 &axg_vapb_0.hw, 1260 &axg_vapb_1.hw 1261 }, 1262 .num_parents = 2, 1263 .flags = CLK_SET_RATE_NO_REPARENT, 1264 }, 1265 }; 1266 1267 static struct clk_regmap axg_vapb = { 1268 .data = &(struct clk_regmap_gate_data){ 1269 .offset = HHI_VAPBCLK_CNTL, 1270 .bit_idx = 30, 1271 }, 1272 .hw.init = &(struct clk_init_data) { 1273 .name = "vapb", 1274 .ops = &clk_regmap_gate_ops, 1275 .parent_hws = (const struct clk_hw *[]) { &axg_vapb_sel.hw }, 1276 .num_parents = 1, 1277 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1278 }, 1279 }; 1280 1281 /* Video Clocks */ 1282 1283 static const struct clk_hw *axg_vclk_parent_hws[] = { 1284 &axg_gp0_pll.hw, 1285 &axg_fclk_div4.hw, 1286 &axg_fclk_div3.hw, 1287 &axg_fclk_div5.hw, 1288 &axg_fclk_div2.hw, 1289 &axg_fclk_div7.hw, 1290 &axg_mpll1.hw, 1291 }; 1292 1293 static struct clk_regmap axg_vclk_sel = { 1294 .data = &(struct clk_regmap_mux_data){ 1295 .offset = HHI_VID_CLK_CNTL, 1296 .mask = 0x7, 1297 .shift = 16, 1298 }, 1299 .hw.init = &(struct clk_init_data){ 1300 .name = "vclk_sel", 1301 .ops = &clk_regmap_mux_ops, 1302 .parent_hws = axg_vclk_parent_hws, 1303 .num_parents = ARRAY_SIZE(axg_vclk_parent_hws), 1304 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1305 }, 1306 }; 1307 1308 static struct clk_regmap axg_vclk2_sel = { 1309 .data = &(struct clk_regmap_mux_data){ 1310 .offset = HHI_VIID_CLK_CNTL, 1311 .mask = 0x7, 1312 .shift = 16, 1313 }, 1314 .hw.init = &(struct clk_init_data){ 1315 .name = "vclk2_sel", 1316 .ops = &clk_regmap_mux_ops, 1317 .parent_hws = axg_vclk_parent_hws, 1318 .num_parents = ARRAY_SIZE(axg_vclk_parent_hws), 1319 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1320 }, 1321 }; 1322 1323 static struct clk_regmap axg_vclk_input = { 1324 .data = &(struct clk_regmap_gate_data){ 1325 .offset = HHI_VID_CLK_DIV, 1326 .bit_idx = 16, 1327 }, 1328 .hw.init = &(struct clk_init_data) { 1329 .name = "vclk_input", 1330 .ops = &clk_regmap_gate_ops, 1331 .parent_hws = (const struct clk_hw *[]) { &axg_vclk_sel.hw }, 1332 .num_parents = 1, 1333 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1334 }, 1335 }; 1336 1337 static struct clk_regmap axg_vclk2_input = { 1338 .data = &(struct clk_regmap_gate_data){ 1339 .offset = HHI_VIID_CLK_DIV, 1340 .bit_idx = 16, 1341 }, 1342 .hw.init = &(struct clk_init_data) { 1343 .name = "vclk2_input", 1344 .ops = &clk_regmap_gate_ops, 1345 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2_sel.hw }, 1346 .num_parents = 1, 1347 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1348 }, 1349 }; 1350 1351 static struct clk_regmap axg_vclk_div = { 1352 .data = &(struct clk_regmap_div_data){ 1353 .offset = HHI_VID_CLK_DIV, 1354 .shift = 0, 1355 .width = 8, 1356 }, 1357 .hw.init = &(struct clk_init_data){ 1358 .name = "vclk_div", 1359 .ops = &clk_regmap_divider_ops, 1360 .parent_hws = (const struct clk_hw *[]) { 1361 &axg_vclk_input.hw 1362 }, 1363 .num_parents = 1, 1364 .flags = CLK_GET_RATE_NOCACHE, 1365 }, 1366 }; 1367 1368 static struct clk_regmap axg_vclk2_div = { 1369 .data = &(struct clk_regmap_div_data){ 1370 .offset = HHI_VIID_CLK_DIV, 1371 .shift = 0, 1372 .width = 8, 1373 }, 1374 .hw.init = &(struct clk_init_data){ 1375 .name = "vclk2_div", 1376 .ops = &clk_regmap_divider_ops, 1377 .parent_hws = (const struct clk_hw *[]) { 1378 &axg_vclk2_input.hw 1379 }, 1380 .num_parents = 1, 1381 .flags = CLK_GET_RATE_NOCACHE, 1382 }, 1383 }; 1384 1385 static struct clk_regmap axg_vclk = { 1386 .data = &(struct clk_regmap_gate_data){ 1387 .offset = HHI_VID_CLK_CNTL, 1388 .bit_idx = 19, 1389 }, 1390 .hw.init = &(struct clk_init_data) { 1391 .name = "vclk", 1392 .ops = &clk_regmap_gate_ops, 1393 .parent_hws = (const struct clk_hw *[]) { &axg_vclk_div.hw }, 1394 .num_parents = 1, 1395 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1396 }, 1397 }; 1398 1399 static struct clk_regmap axg_vclk2 = { 1400 .data = &(struct clk_regmap_gate_data){ 1401 .offset = HHI_VIID_CLK_CNTL, 1402 .bit_idx = 19, 1403 }, 1404 .hw.init = &(struct clk_init_data) { 1405 .name = "vclk2", 1406 .ops = &clk_regmap_gate_ops, 1407 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2_div.hw }, 1408 .num_parents = 1, 1409 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1410 }, 1411 }; 1412 1413 static struct clk_regmap axg_vclk_div1 = { 1414 .data = &(struct clk_regmap_gate_data){ 1415 .offset = HHI_VID_CLK_CNTL, 1416 .bit_idx = 0, 1417 }, 1418 .hw.init = &(struct clk_init_data) { 1419 .name = "vclk_div1", 1420 .ops = &clk_regmap_gate_ops, 1421 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1422 .num_parents = 1, 1423 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1424 }, 1425 }; 1426 1427 static struct clk_regmap axg_vclk_div2_en = { 1428 .data = &(struct clk_regmap_gate_data){ 1429 .offset = HHI_VID_CLK_CNTL, 1430 .bit_idx = 1, 1431 }, 1432 .hw.init = &(struct clk_init_data) { 1433 .name = "vclk_div2_en", 1434 .ops = &clk_regmap_gate_ops, 1435 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1436 .num_parents = 1, 1437 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1438 }, 1439 }; 1440 1441 static struct clk_regmap axg_vclk_div4_en = { 1442 .data = &(struct clk_regmap_gate_data){ 1443 .offset = HHI_VID_CLK_CNTL, 1444 .bit_idx = 2, 1445 }, 1446 .hw.init = &(struct clk_init_data) { 1447 .name = "vclk_div4_en", 1448 .ops = &clk_regmap_gate_ops, 1449 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1450 .num_parents = 1, 1451 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1452 }, 1453 }; 1454 1455 static struct clk_regmap axg_vclk_div6_en = { 1456 .data = &(struct clk_regmap_gate_data){ 1457 .offset = HHI_VID_CLK_CNTL, 1458 .bit_idx = 3, 1459 }, 1460 .hw.init = &(struct clk_init_data) { 1461 .name = "vclk_div6_en", 1462 .ops = &clk_regmap_gate_ops, 1463 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1464 .num_parents = 1, 1465 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1466 }, 1467 }; 1468 1469 static struct clk_regmap axg_vclk_div12_en = { 1470 .data = &(struct clk_regmap_gate_data){ 1471 .offset = HHI_VID_CLK_CNTL, 1472 .bit_idx = 4, 1473 }, 1474 .hw.init = &(struct clk_init_data) { 1475 .name = "vclk_div12_en", 1476 .ops = &clk_regmap_gate_ops, 1477 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1478 .num_parents = 1, 1479 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1480 }, 1481 }; 1482 1483 static struct clk_regmap axg_vclk2_div1 = { 1484 .data = &(struct clk_regmap_gate_data){ 1485 .offset = HHI_VIID_CLK_CNTL, 1486 .bit_idx = 0, 1487 }, 1488 .hw.init = &(struct clk_init_data) { 1489 .name = "vclk2_div1", 1490 .ops = &clk_regmap_gate_ops, 1491 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1492 .num_parents = 1, 1493 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1494 }, 1495 }; 1496 1497 static struct clk_regmap axg_vclk2_div2_en = { 1498 .data = &(struct clk_regmap_gate_data){ 1499 .offset = HHI_VIID_CLK_CNTL, 1500 .bit_idx = 1, 1501 }, 1502 .hw.init = &(struct clk_init_data) { 1503 .name = "vclk2_div2_en", 1504 .ops = &clk_regmap_gate_ops, 1505 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1506 .num_parents = 1, 1507 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1508 }, 1509 }; 1510 1511 static struct clk_regmap axg_vclk2_div4_en = { 1512 .data = &(struct clk_regmap_gate_data){ 1513 .offset = HHI_VIID_CLK_CNTL, 1514 .bit_idx = 2, 1515 }, 1516 .hw.init = &(struct clk_init_data) { 1517 .name = "vclk2_div4_en", 1518 .ops = &clk_regmap_gate_ops, 1519 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1520 .num_parents = 1, 1521 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1522 }, 1523 }; 1524 1525 static struct clk_regmap axg_vclk2_div6_en = { 1526 .data = &(struct clk_regmap_gate_data){ 1527 .offset = HHI_VIID_CLK_CNTL, 1528 .bit_idx = 3, 1529 }, 1530 .hw.init = &(struct clk_init_data) { 1531 .name = "vclk2_div6_en", 1532 .ops = &clk_regmap_gate_ops, 1533 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1534 .num_parents = 1, 1535 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1536 }, 1537 }; 1538 1539 static struct clk_regmap axg_vclk2_div12_en = { 1540 .data = &(struct clk_regmap_gate_data){ 1541 .offset = HHI_VIID_CLK_CNTL, 1542 .bit_idx = 4, 1543 }, 1544 .hw.init = &(struct clk_init_data) { 1545 .name = "vclk2_div12_en", 1546 .ops = &clk_regmap_gate_ops, 1547 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1548 .num_parents = 1, 1549 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1550 }, 1551 }; 1552 1553 static struct clk_fixed_factor axg_vclk_div2 = { 1554 .mult = 1, 1555 .div = 2, 1556 .hw.init = &(struct clk_init_data){ 1557 .name = "vclk_div2", 1558 .ops = &clk_fixed_factor_ops, 1559 .parent_hws = (const struct clk_hw *[]) { 1560 &axg_vclk_div2_en.hw 1561 }, 1562 .num_parents = 1, 1563 }, 1564 }; 1565 1566 static struct clk_fixed_factor axg_vclk_div4 = { 1567 .mult = 1, 1568 .div = 4, 1569 .hw.init = &(struct clk_init_data){ 1570 .name = "vclk_div4", 1571 .ops = &clk_fixed_factor_ops, 1572 .parent_hws = (const struct clk_hw *[]) { 1573 &axg_vclk_div4_en.hw 1574 }, 1575 .num_parents = 1, 1576 }, 1577 }; 1578 1579 static struct clk_fixed_factor axg_vclk_div6 = { 1580 .mult = 1, 1581 .div = 6, 1582 .hw.init = &(struct clk_init_data){ 1583 .name = "vclk_div6", 1584 .ops = &clk_fixed_factor_ops, 1585 .parent_hws = (const struct clk_hw *[]) { 1586 &axg_vclk_div6_en.hw 1587 }, 1588 .num_parents = 1, 1589 }, 1590 }; 1591 1592 static struct clk_fixed_factor axg_vclk_div12 = { 1593 .mult = 1, 1594 .div = 12, 1595 .hw.init = &(struct clk_init_data){ 1596 .name = "vclk_div12", 1597 .ops = &clk_fixed_factor_ops, 1598 .parent_hws = (const struct clk_hw *[]) { 1599 &axg_vclk_div12_en.hw 1600 }, 1601 .num_parents = 1, 1602 }, 1603 }; 1604 1605 static struct clk_fixed_factor axg_vclk2_div2 = { 1606 .mult = 1, 1607 .div = 2, 1608 .hw.init = &(struct clk_init_data){ 1609 .name = "vclk2_div2", 1610 .ops = &clk_fixed_factor_ops, 1611 .parent_hws = (const struct clk_hw *[]) { 1612 &axg_vclk2_div2_en.hw 1613 }, 1614 .num_parents = 1, 1615 }, 1616 }; 1617 1618 static struct clk_fixed_factor axg_vclk2_div4 = { 1619 .mult = 1, 1620 .div = 4, 1621 .hw.init = &(struct clk_init_data){ 1622 .name = "vclk2_div4", 1623 .ops = &clk_fixed_factor_ops, 1624 .parent_hws = (const struct clk_hw *[]) { 1625 &axg_vclk2_div4_en.hw 1626 }, 1627 .num_parents = 1, 1628 }, 1629 }; 1630 1631 static struct clk_fixed_factor axg_vclk2_div6 = { 1632 .mult = 1, 1633 .div = 6, 1634 .hw.init = &(struct clk_init_data){ 1635 .name = "vclk2_div6", 1636 .ops = &clk_fixed_factor_ops, 1637 .parent_hws = (const struct clk_hw *[]) { 1638 &axg_vclk2_div6_en.hw 1639 }, 1640 .num_parents = 1, 1641 }, 1642 }; 1643 1644 static struct clk_fixed_factor axg_vclk2_div12 = { 1645 .mult = 1, 1646 .div = 12, 1647 .hw.init = &(struct clk_init_data){ 1648 .name = "vclk2_div12", 1649 .ops = &clk_fixed_factor_ops, 1650 .parent_hws = (const struct clk_hw *[]) { 1651 &axg_vclk2_div12_en.hw 1652 }, 1653 .num_parents = 1, 1654 }, 1655 }; 1656 1657 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 1658 static const struct clk_hw *axg_cts_parent_hws[] = { 1659 &axg_vclk_div1.hw, 1660 &axg_vclk_div2.hw, 1661 &axg_vclk_div4.hw, 1662 &axg_vclk_div6.hw, 1663 &axg_vclk_div12.hw, 1664 &axg_vclk2_div1.hw, 1665 &axg_vclk2_div2.hw, 1666 &axg_vclk2_div4.hw, 1667 &axg_vclk2_div6.hw, 1668 &axg_vclk2_div12.hw, 1669 }; 1670 1671 static struct clk_regmap axg_cts_encl_sel = { 1672 .data = &(struct clk_regmap_mux_data){ 1673 .offset = HHI_VIID_CLK_DIV, 1674 .mask = 0xf, 1675 .shift = 12, 1676 .table = mux_table_cts_sel, 1677 }, 1678 .hw.init = &(struct clk_init_data){ 1679 .name = "cts_encl_sel", 1680 .ops = &clk_regmap_mux_ops, 1681 .parent_hws = axg_cts_parent_hws, 1682 .num_parents = ARRAY_SIZE(axg_cts_parent_hws), 1683 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1684 }, 1685 }; 1686 1687 static struct clk_regmap axg_cts_encl = { 1688 .data = &(struct clk_regmap_gate_data){ 1689 .offset = HHI_VID_CLK_CNTL2, 1690 .bit_idx = 3, 1691 }, 1692 .hw.init = &(struct clk_init_data) { 1693 .name = "cts_encl", 1694 .ops = &clk_regmap_gate_ops, 1695 .parent_hws = (const struct clk_hw *[]) { 1696 &axg_cts_encl_sel.hw 1697 }, 1698 .num_parents = 1, 1699 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1700 }, 1701 }; 1702 1703 /* MIPI DSI Host Clock */ 1704 1705 static u32 mux_table_axg_vdin_meas[] = { 0, 1, 2, 3, 6, 7 }; 1706 static const struct clk_parent_data axg_vdin_meas_parent_data[] = { 1707 { .fw_name = "xtal", }, 1708 { .hw = &axg_fclk_div4.hw }, 1709 { .hw = &axg_fclk_div3.hw }, 1710 { .hw = &axg_fclk_div5.hw }, 1711 { .hw = &axg_fclk_div2.hw }, 1712 { .hw = &axg_fclk_div7.hw }, 1713 }; 1714 1715 static struct clk_regmap axg_vdin_meas_sel = { 1716 .data = &(struct clk_regmap_mux_data){ 1717 .offset = HHI_VDIN_MEAS_CLK_CNTL, 1718 .mask = 0x7, 1719 .shift = 21, 1720 .flags = CLK_MUX_ROUND_CLOSEST, 1721 .table = mux_table_axg_vdin_meas, 1722 }, 1723 .hw.init = &(struct clk_init_data){ 1724 .name = "vdin_meas_sel", 1725 .ops = &clk_regmap_mux_ops, 1726 .parent_data = axg_vdin_meas_parent_data, 1727 .num_parents = ARRAY_SIZE(axg_vdin_meas_parent_data), 1728 .flags = CLK_SET_RATE_PARENT, 1729 }, 1730 }; 1731 1732 static struct clk_regmap axg_vdin_meas_div = { 1733 .data = &(struct clk_regmap_div_data){ 1734 .offset = HHI_VDIN_MEAS_CLK_CNTL, 1735 .shift = 12, 1736 .width = 7, 1737 }, 1738 .hw.init = &(struct clk_init_data){ 1739 .name = "vdin_meas_div", 1740 .ops = &clk_regmap_divider_ops, 1741 .parent_hws = (const struct clk_hw *[]) { 1742 &axg_vdin_meas_sel.hw }, 1743 .num_parents = 1, 1744 .flags = CLK_SET_RATE_PARENT, 1745 }, 1746 }; 1747 1748 static struct clk_regmap axg_vdin_meas = { 1749 .data = &(struct clk_regmap_gate_data){ 1750 .offset = HHI_VDIN_MEAS_CLK_CNTL, 1751 .bit_idx = 20, 1752 }, 1753 .hw.init = &(struct clk_init_data) { 1754 .name = "vdin_meas", 1755 .ops = &clk_regmap_gate_ops, 1756 .parent_hws = (const struct clk_hw *[]) { 1757 &axg_vdin_meas_div.hw }, 1758 .num_parents = 1, 1759 .flags = CLK_SET_RATE_PARENT, 1760 }, 1761 }; 1762 1763 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8, 1764 9, 10, 11, 13, 14, }; 1765 static const struct clk_parent_data gen_clk_parent_data[] = { 1766 { .fw_name = "xtal", }, 1767 { .hw = &axg_hifi_pll.hw }, 1768 { .hw = &axg_mpll0.hw }, 1769 { .hw = &axg_mpll1.hw }, 1770 { .hw = &axg_mpll2.hw }, 1771 { .hw = &axg_mpll3.hw }, 1772 { .hw = &axg_fclk_div4.hw }, 1773 { .hw = &axg_fclk_div3.hw }, 1774 { .hw = &axg_fclk_div5.hw }, 1775 { .hw = &axg_fclk_div7.hw }, 1776 { .hw = &axg_gp0_pll.hw }, 1777 }; 1778 1779 static struct clk_regmap axg_gen_clk_sel = { 1780 .data = &(struct clk_regmap_mux_data){ 1781 .offset = HHI_GEN_CLK_CNTL, 1782 .mask = 0xf, 1783 .shift = 12, 1784 .table = mux_table_gen_clk, 1785 }, 1786 .hw.init = &(struct clk_init_data){ 1787 .name = "gen_clk_sel", 1788 .ops = &clk_regmap_mux_ops, 1789 /* 1790 * bits 15:12 selects from 14 possible parents: 1791 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt], 1792 * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4, 1793 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll 1794 */ 1795 .parent_data = gen_clk_parent_data, 1796 .num_parents = ARRAY_SIZE(gen_clk_parent_data), 1797 }, 1798 }; 1799 1800 static struct clk_regmap axg_gen_clk_div = { 1801 .data = &(struct clk_regmap_div_data){ 1802 .offset = HHI_GEN_CLK_CNTL, 1803 .shift = 0, 1804 .width = 11, 1805 }, 1806 .hw.init = &(struct clk_init_data){ 1807 .name = "gen_clk_div", 1808 .ops = &clk_regmap_divider_ops, 1809 .parent_hws = (const struct clk_hw *[]) { 1810 &axg_gen_clk_sel.hw 1811 }, 1812 .num_parents = 1, 1813 .flags = CLK_SET_RATE_PARENT, 1814 }, 1815 }; 1816 1817 static struct clk_regmap axg_gen_clk = { 1818 .data = &(struct clk_regmap_gate_data){ 1819 .offset = HHI_GEN_CLK_CNTL, 1820 .bit_idx = 7, 1821 }, 1822 .hw.init = &(struct clk_init_data){ 1823 .name = "gen_clk", 1824 .ops = &clk_regmap_gate_ops, 1825 .parent_hws = (const struct clk_hw *[]) { 1826 &axg_gen_clk_div.hw 1827 }, 1828 .num_parents = 1, 1829 .flags = CLK_SET_RATE_PARENT, 1830 }, 1831 }; 1832 1833 #define MESON_GATE(_name, _reg, _bit) \ 1834 MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw) 1835 1836 /* Everything Else (EE) domain gates */ 1837 static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0); 1838 static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2); 1839 static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3); 1840 static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5); 1841 static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6); 1842 static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7); 1843 static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8); 1844 static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9); 1845 static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12); 1846 static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13); 1847 static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14); 1848 static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15); 1849 static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16); 1850 static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17); 1851 static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19); 1852 static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23); 1853 static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25); 1854 static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26); 1855 static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27); 1856 static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30); 1857 1858 static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0); 1859 static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3); 1860 static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16); 1861 static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20); 1862 static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21); 1863 static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22); 1864 static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23); 1865 static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26); 1866 static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29); 1867 static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30); 1868 static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31); 1869 1870 static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1); 1871 static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 1872 static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8); 1873 static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9); 1874 static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11); 1875 static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25); 1876 static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 1877 static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30); 1878 1879 /* Always On (AO) domain gates */ 1880 1881 static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0); 1882 static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1); 1883 static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2); 1884 static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3); 1885 static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4); 1886 1887 /* Array of all clocks provided by this provider */ 1888 1889 static struct clk_hw *axg_hw_clks[] = { 1890 [CLKID_SYS_PLL] = &axg_sys_pll.hw, 1891 [CLKID_FIXED_PLL] = &axg_fixed_pll.hw, 1892 [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw, 1893 [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw, 1894 [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw, 1895 [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw, 1896 [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw, 1897 [CLKID_GP0_PLL] = &axg_gp0_pll.hw, 1898 [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw, 1899 [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw, 1900 [CLKID_CLK81] = &axg_clk81.hw, 1901 [CLKID_MPLL0] = &axg_mpll0.hw, 1902 [CLKID_MPLL1] = &axg_mpll1.hw, 1903 [CLKID_MPLL2] = &axg_mpll2.hw, 1904 [CLKID_MPLL3] = &axg_mpll3.hw, 1905 [CLKID_DDR] = &axg_ddr.hw, 1906 [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw, 1907 [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw, 1908 [CLKID_ISA] = &axg_isa.hw, 1909 [CLKID_PL301] = &axg_pl301.hw, 1910 [CLKID_PERIPHS] = &axg_periphs.hw, 1911 [CLKID_SPICC0] = &axg_spicc_0.hw, 1912 [CLKID_I2C] = &axg_i2c.hw, 1913 [CLKID_RNG0] = &axg_rng0.hw, 1914 [CLKID_UART0] = &axg_uart0.hw, 1915 [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw, 1916 [CLKID_SPICC1] = &axg_spicc_1.hw, 1917 [CLKID_PCIE_A] = &axg_pcie_a.hw, 1918 [CLKID_PCIE_B] = &axg_pcie_b.hw, 1919 [CLKID_HIU_IFACE] = &axg_hiu_reg.hw, 1920 [CLKID_ASSIST_MISC] = &axg_assist_misc.hw, 1921 [CLKID_SD_EMMC_B] = &axg_emmc_b.hw, 1922 [CLKID_SD_EMMC_C] = &axg_emmc_c.hw, 1923 [CLKID_DMA] = &axg_dma.hw, 1924 [CLKID_SPI] = &axg_spi.hw, 1925 [CLKID_AUDIO] = &axg_audio.hw, 1926 [CLKID_ETH] = &axg_eth_core.hw, 1927 [CLKID_UART1] = &axg_uart1.hw, 1928 [CLKID_G2D] = &axg_g2d.hw, 1929 [CLKID_USB0] = &axg_usb0.hw, 1930 [CLKID_USB1] = &axg_usb1.hw, 1931 [CLKID_RESET] = &axg_reset.hw, 1932 [CLKID_USB] = &axg_usb_general.hw, 1933 [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw, 1934 [CLKID_EFUSE] = &axg_efuse.hw, 1935 [CLKID_BOOT_ROM] = &axg_boot_rom.hw, 1936 [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw, 1937 [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw, 1938 [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw, 1939 [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw, 1940 [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw, 1941 [CLKID_VPU_INTR] = &axg_vpu_intr.hw, 1942 [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw, 1943 [CLKID_GIC] = &axg_gic.hw, 1944 [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw, 1945 [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw, 1946 [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw, 1947 [CLKID_AO_IFACE] = &axg_ao_iface.hw, 1948 [CLKID_AO_I2C] = &axg_ao_i2c.hw, 1949 [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw, 1950 [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw, 1951 [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw, 1952 [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw, 1953 [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw, 1954 [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw, 1955 [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw, 1956 [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw, 1957 [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw, 1958 [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw, 1959 [CLKID_HIFI_PLL] = &axg_hifi_pll.hw, 1960 [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw, 1961 [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw, 1962 [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw, 1963 [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw, 1964 [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw, 1965 [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw, 1966 [CLKID_PCIE_PLL] = &axg_pcie_pll.hw, 1967 [CLKID_PCIE_MUX] = &axg_pcie_mux.hw, 1968 [CLKID_PCIE_REF] = &axg_pcie_ref.hw, 1969 [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw, 1970 [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw, 1971 [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw, 1972 [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw, 1973 [CLKID_GEN_CLK] = &axg_gen_clk.hw, 1974 [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw, 1975 [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw, 1976 [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw, 1977 [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw, 1978 [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw, 1979 [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw, 1980 [CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw, 1981 [CLKID_VPU_0_SEL] = &axg_vpu_0_sel.hw, 1982 [CLKID_VPU_0] = &axg_vpu_0.hw, 1983 [CLKID_VPU_1_DIV] = &axg_vpu_1_div.hw, 1984 [CLKID_VPU_1_SEL] = &axg_vpu_1_sel.hw, 1985 [CLKID_VPU_1] = &axg_vpu_1.hw, 1986 [CLKID_VPU] = &axg_vpu.hw, 1987 [CLKID_VAPB_0_DIV] = &axg_vapb_0_div.hw, 1988 [CLKID_VAPB_0_SEL] = &axg_vapb_0_sel.hw, 1989 [CLKID_VAPB_0] = &axg_vapb_0.hw, 1990 [CLKID_VAPB_1_DIV] = &axg_vapb_1_div.hw, 1991 [CLKID_VAPB_1_SEL] = &axg_vapb_1_sel.hw, 1992 [CLKID_VAPB_1] = &axg_vapb_1.hw, 1993 [CLKID_VAPB_SEL] = &axg_vapb_sel.hw, 1994 [CLKID_VAPB] = &axg_vapb.hw, 1995 [CLKID_VCLK] = &axg_vclk.hw, 1996 [CLKID_VCLK2] = &axg_vclk2.hw, 1997 [CLKID_VCLK_SEL] = &axg_vclk_sel.hw, 1998 [CLKID_VCLK2_SEL] = &axg_vclk2_sel.hw, 1999 [CLKID_VCLK_INPUT] = &axg_vclk_input.hw, 2000 [CLKID_VCLK2_INPUT] = &axg_vclk2_input.hw, 2001 [CLKID_VCLK_DIV] = &axg_vclk_div.hw, 2002 [CLKID_VCLK2_DIV] = &axg_vclk2_div.hw, 2003 [CLKID_VCLK_DIV2_EN] = &axg_vclk_div2_en.hw, 2004 [CLKID_VCLK_DIV4_EN] = &axg_vclk_div4_en.hw, 2005 [CLKID_VCLK_DIV6_EN] = &axg_vclk_div6_en.hw, 2006 [CLKID_VCLK_DIV12_EN] = &axg_vclk_div12_en.hw, 2007 [CLKID_VCLK2_DIV2_EN] = &axg_vclk2_div2_en.hw, 2008 [CLKID_VCLK2_DIV4_EN] = &axg_vclk2_div4_en.hw, 2009 [CLKID_VCLK2_DIV6_EN] = &axg_vclk2_div6_en.hw, 2010 [CLKID_VCLK2_DIV12_EN] = &axg_vclk2_div12_en.hw, 2011 [CLKID_VCLK_DIV1] = &axg_vclk_div1.hw, 2012 [CLKID_VCLK_DIV2] = &axg_vclk_div2.hw, 2013 [CLKID_VCLK_DIV4] = &axg_vclk_div4.hw, 2014 [CLKID_VCLK_DIV6] = &axg_vclk_div6.hw, 2015 [CLKID_VCLK_DIV12] = &axg_vclk_div12.hw, 2016 [CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw, 2017 [CLKID_VCLK2_DIV2] = &axg_vclk2_div2.hw, 2018 [CLKID_VCLK2_DIV4] = &axg_vclk2_div4.hw, 2019 [CLKID_VCLK2_DIV6] = &axg_vclk2_div6.hw, 2020 [CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw, 2021 [CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw, 2022 [CLKID_CTS_ENCL] = &axg_cts_encl.hw, 2023 [CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw, 2024 [CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw, 2025 [CLKID_VDIN_MEAS] = &axg_vdin_meas.hw, 2026 }; 2027 2028 /* Convenience table to populate regmap in .probe */ 2029 static struct clk_regmap *const axg_clk_regmaps[] = { 2030 &axg_clk81, 2031 &axg_ddr, 2032 &axg_audio_locker, 2033 &axg_mipi_dsi_host, 2034 &axg_isa, 2035 &axg_pl301, 2036 &axg_periphs, 2037 &axg_spicc_0, 2038 &axg_i2c, 2039 &axg_rng0, 2040 &axg_uart0, 2041 &axg_mipi_dsi_phy, 2042 &axg_spicc_1, 2043 &axg_pcie_a, 2044 &axg_pcie_b, 2045 &axg_hiu_reg, 2046 &axg_assist_misc, 2047 &axg_emmc_b, 2048 &axg_emmc_c, 2049 &axg_dma, 2050 &axg_spi, 2051 &axg_audio, 2052 &axg_eth_core, 2053 &axg_uart1, 2054 &axg_g2d, 2055 &axg_usb0, 2056 &axg_usb1, 2057 &axg_reset, 2058 &axg_usb_general, 2059 &axg_ahb_arb0, 2060 &axg_efuse, 2061 &axg_boot_rom, 2062 &axg_ahb_data_bus, 2063 &axg_ahb_ctrl_bus, 2064 &axg_usb1_to_ddr, 2065 &axg_usb0_to_ddr, 2066 &axg_mmc_pclk, 2067 &axg_vpu_intr, 2068 &axg_sec_ahb_ahb3_bridge, 2069 &axg_gic, 2070 &axg_ao_media_cpu, 2071 &axg_ao_ahb_sram, 2072 &axg_ao_ahb_bus, 2073 &axg_ao_iface, 2074 &axg_ao_i2c, 2075 &axg_sd_emmc_b_clk0, 2076 &axg_sd_emmc_c_clk0, 2077 &axg_mpeg_clk_div, 2078 &axg_sd_emmc_b_clk0_div, 2079 &axg_sd_emmc_c_clk0_div, 2080 &axg_mpeg_clk_sel, 2081 &axg_sd_emmc_b_clk0_sel, 2082 &axg_sd_emmc_c_clk0_sel, 2083 &axg_mpll0, 2084 &axg_mpll1, 2085 &axg_mpll2, 2086 &axg_mpll3, 2087 &axg_mpll0_div, 2088 &axg_mpll1_div, 2089 &axg_mpll2_div, 2090 &axg_mpll3_div, 2091 &axg_fixed_pll, 2092 &axg_sys_pll, 2093 &axg_gp0_pll, 2094 &axg_hifi_pll, 2095 &axg_mpll_prediv, 2096 &axg_fclk_div2, 2097 &axg_fclk_div3, 2098 &axg_fclk_div4, 2099 &axg_fclk_div5, 2100 &axg_fclk_div7, 2101 &axg_pcie_pll_dco, 2102 &axg_pcie_pll_od, 2103 &axg_pcie_pll, 2104 &axg_pcie_mux, 2105 &axg_pcie_ref, 2106 &axg_pcie_cml_en0, 2107 &axg_pcie_cml_en1, 2108 &axg_gen_clk_sel, 2109 &axg_gen_clk_div, 2110 &axg_gen_clk, 2111 &axg_fixed_pll_dco, 2112 &axg_sys_pll_dco, 2113 &axg_gp0_pll_dco, 2114 &axg_hifi_pll_dco, 2115 &axg_pcie_pll_dco, 2116 &axg_pcie_pll_od, 2117 &axg_vpu_0_div, 2118 &axg_vpu_0_sel, 2119 &axg_vpu_0, 2120 &axg_vpu_1_div, 2121 &axg_vpu_1_sel, 2122 &axg_vpu_1, 2123 &axg_vpu, 2124 &axg_vapb_0_div, 2125 &axg_vapb_0_sel, 2126 &axg_vapb_0, 2127 &axg_vapb_1_div, 2128 &axg_vapb_1_sel, 2129 &axg_vapb_1, 2130 &axg_vapb_sel, 2131 &axg_vapb, 2132 &axg_vclk, 2133 &axg_vclk2, 2134 &axg_vclk_sel, 2135 &axg_vclk2_sel, 2136 &axg_vclk_input, 2137 &axg_vclk2_input, 2138 &axg_vclk_div, 2139 &axg_vclk_div1, 2140 &axg_vclk2_div, 2141 &axg_vclk2_div1, 2142 &axg_vclk_div2_en, 2143 &axg_vclk_div4_en, 2144 &axg_vclk_div6_en, 2145 &axg_vclk_div12_en, 2146 &axg_vclk2_div2_en, 2147 &axg_vclk2_div4_en, 2148 &axg_vclk2_div6_en, 2149 &axg_vclk2_div12_en, 2150 &axg_cts_encl_sel, 2151 &axg_cts_encl, 2152 &axg_vdin_meas_sel, 2153 &axg_vdin_meas_div, 2154 &axg_vdin_meas, 2155 }; 2156 2157 static const struct meson_eeclkc_data axg_clkc_data = { 2158 .regmap_clks = axg_clk_regmaps, 2159 .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps), 2160 .hw_clks = { 2161 .hws = axg_hw_clks, 2162 .num = ARRAY_SIZE(axg_hw_clks), 2163 }, 2164 }; 2165 2166 2167 static const struct of_device_id clkc_match_table[] = { 2168 { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data }, 2169 {} 2170 }; 2171 MODULE_DEVICE_TABLE(of, clkc_match_table); 2172 2173 static struct platform_driver axg_driver = { 2174 .probe = meson_eeclkc_probe, 2175 .driver = { 2176 .name = "axg-clkc", 2177 .of_match_table = clkc_match_table, 2178 }, 2179 }; 2180 module_platform_driver(axg_driver); 2181 2182 MODULE_DESCRIPTION("Amlogic AXG Main Clock Controller driver"); 2183 MODULE_LICENSE("GPL"); 2184 MODULE_IMPORT_NS("CLK_MESON"); 2185