1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Cryptographic API.
4 *
5 * Support for ATMEL SHA1/SHA256 HW acceleration.
6 *
7 * Copyright (c) 2012 Eukréa Electromatique - ATMEL
8 * Author: Nicolas Royer <nicolas@eukrea.com>
9 *
10 * Some ideas are from omap-sham.c drivers.
11 */
12
13
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/slab.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
19 #include <linux/io.h>
20 #include <linux/hw_random.h>
21 #include <linux/platform_device.h>
22
23 #include <linux/device.h>
24 #include <linux/dmaengine.h>
25 #include <linux/init.h>
26 #include <linux/errno.h>
27 #include <linux/interrupt.h>
28 #include <linux/irq.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/crypto.h>
33 #include <crypto/scatterwalk.h>
34 #include <crypto/algapi.h>
35 #include <crypto/sha1.h>
36 #include <crypto/sha2.h>
37 #include <crypto/hash.h>
38 #include <crypto/internal/hash.h>
39 #include "atmel-sha-regs.h"
40 #include "atmel-authenc.h"
41
42 #define ATMEL_SHA_PRIORITY 300
43
44 /* SHA flags */
45 #define SHA_FLAGS_BUSY BIT(0)
46 #define SHA_FLAGS_FINAL BIT(1)
47 #define SHA_FLAGS_DMA_ACTIVE BIT(2)
48 #define SHA_FLAGS_OUTPUT_READY BIT(3)
49 #define SHA_FLAGS_INIT BIT(4)
50 #define SHA_FLAGS_CPU BIT(5)
51 #define SHA_FLAGS_DMA_READY BIT(6)
52 #define SHA_FLAGS_DUMP_REG BIT(7)
53
54 /* bits[11:8] are reserved. */
55
56 #define SHA_FLAGS_FINUP BIT(16)
57 #define SHA_FLAGS_SG BIT(17)
58 #define SHA_FLAGS_ERROR BIT(23)
59 #define SHA_FLAGS_PAD BIT(24)
60 #define SHA_FLAGS_RESTORE BIT(25)
61 #define SHA_FLAGS_IDATAR0 BIT(26)
62 #define SHA_FLAGS_WAIT_DATARDY BIT(27)
63
64 #define SHA_OP_INIT 0
65 #define SHA_OP_UPDATE 1
66 #define SHA_OP_FINAL 2
67 #define SHA_OP_DIGEST 3
68
69 #define SHA_BUFFER_LEN (PAGE_SIZE / 16)
70
71 #define ATMEL_SHA_DMA_THRESHOLD 56
72
73 struct atmel_sha_caps {
74 bool has_dma;
75 bool has_dualbuff;
76 bool has_sha224;
77 bool has_sha_384_512;
78 bool has_uihv;
79 bool has_hmac;
80 };
81
82 struct atmel_sha_dev;
83
84 /*
85 * .statesize = sizeof(struct atmel_sha_reqctx) must be <= PAGE_SIZE / 8 as
86 * tested by the ahash_prepare_alg() function.
87 */
88 struct atmel_sha_reqctx {
89 struct atmel_sha_dev *dd;
90 unsigned long flags;
91 unsigned long op;
92
93 u8 digest[SHA512_DIGEST_SIZE] __aligned(sizeof(u32));
94 u64 digcnt[2];
95 size_t bufcnt;
96 size_t buflen;
97 dma_addr_t dma_addr;
98
99 /* walk state */
100 struct scatterlist *sg;
101 unsigned int offset; /* offset in current sg */
102 unsigned int total; /* total request */
103
104 size_t block_size;
105 size_t hash_size;
106
107 u8 buffer[SHA_BUFFER_LEN + SHA512_BLOCK_SIZE] __aligned(sizeof(u32));
108 };
109
110 typedef int (*atmel_sha_fn_t)(struct atmel_sha_dev *);
111
112 struct atmel_sha_ctx {
113 struct atmel_sha_dev *dd;
114 atmel_sha_fn_t start;
115
116 unsigned long flags;
117 };
118
119 #define ATMEL_SHA_QUEUE_LENGTH 50
120
121 struct atmel_sha_dma {
122 struct dma_chan *chan;
123 struct dma_slave_config dma_conf;
124 struct scatterlist *sg;
125 int nents;
126 unsigned int last_sg_length;
127 };
128
129 struct atmel_sha_dev {
130 struct list_head list;
131 unsigned long phys_base;
132 struct device *dev;
133 struct clk *iclk;
134 int irq;
135 void __iomem *io_base;
136
137 spinlock_t lock;
138 struct tasklet_struct done_task;
139 struct tasklet_struct queue_task;
140
141 unsigned long flags;
142 struct crypto_queue queue;
143 struct ahash_request *req;
144 bool is_async;
145 bool force_complete;
146 atmel_sha_fn_t resume;
147 atmel_sha_fn_t cpu_transfer_complete;
148
149 struct atmel_sha_dma dma_lch_in;
150
151 struct atmel_sha_caps caps;
152
153 struct scatterlist tmp;
154
155 u32 hw_version;
156 };
157
158 struct atmel_sha_drv {
159 struct list_head dev_list;
160 spinlock_t lock;
161 };
162
163 static struct atmel_sha_drv atmel_sha = {
164 .dev_list = LIST_HEAD_INIT(atmel_sha.dev_list),
165 .lock = __SPIN_LOCK_UNLOCKED(atmel_sha.lock),
166 };
167
168 #ifdef VERBOSE_DEBUG
atmel_sha_reg_name(u32 offset,char * tmp,size_t sz,bool wr)169 static const char *atmel_sha_reg_name(u32 offset, char *tmp, size_t sz, bool wr)
170 {
171 switch (offset) {
172 case SHA_CR:
173 return "CR";
174
175 case SHA_MR:
176 return "MR";
177
178 case SHA_IER:
179 return "IER";
180
181 case SHA_IDR:
182 return "IDR";
183
184 case SHA_IMR:
185 return "IMR";
186
187 case SHA_ISR:
188 return "ISR";
189
190 case SHA_MSR:
191 return "MSR";
192
193 case SHA_BCR:
194 return "BCR";
195
196 case SHA_REG_DIN(0):
197 case SHA_REG_DIN(1):
198 case SHA_REG_DIN(2):
199 case SHA_REG_DIN(3):
200 case SHA_REG_DIN(4):
201 case SHA_REG_DIN(5):
202 case SHA_REG_DIN(6):
203 case SHA_REG_DIN(7):
204 case SHA_REG_DIN(8):
205 case SHA_REG_DIN(9):
206 case SHA_REG_DIN(10):
207 case SHA_REG_DIN(11):
208 case SHA_REG_DIN(12):
209 case SHA_REG_DIN(13):
210 case SHA_REG_DIN(14):
211 case SHA_REG_DIN(15):
212 snprintf(tmp, sz, "IDATAR[%u]", (offset - SHA_REG_DIN(0)) >> 2);
213 break;
214
215 case SHA_REG_DIGEST(0):
216 case SHA_REG_DIGEST(1):
217 case SHA_REG_DIGEST(2):
218 case SHA_REG_DIGEST(3):
219 case SHA_REG_DIGEST(4):
220 case SHA_REG_DIGEST(5):
221 case SHA_REG_DIGEST(6):
222 case SHA_REG_DIGEST(7):
223 case SHA_REG_DIGEST(8):
224 case SHA_REG_DIGEST(9):
225 case SHA_REG_DIGEST(10):
226 case SHA_REG_DIGEST(11):
227 case SHA_REG_DIGEST(12):
228 case SHA_REG_DIGEST(13):
229 case SHA_REG_DIGEST(14):
230 case SHA_REG_DIGEST(15):
231 if (wr)
232 snprintf(tmp, sz, "IDATAR[%u]",
233 16u + ((offset - SHA_REG_DIGEST(0)) >> 2));
234 else
235 snprintf(tmp, sz, "ODATAR[%u]",
236 (offset - SHA_REG_DIGEST(0)) >> 2);
237 break;
238
239 case SHA_HW_VERSION:
240 return "HWVER";
241
242 default:
243 snprintf(tmp, sz, "0x%02x", offset);
244 break;
245 }
246
247 return tmp;
248 }
249
250 #endif /* VERBOSE_DEBUG */
251
atmel_sha_read(struct atmel_sha_dev * dd,u32 offset)252 static inline u32 atmel_sha_read(struct atmel_sha_dev *dd, u32 offset)
253 {
254 u32 value = readl_relaxed(dd->io_base + offset);
255
256 #ifdef VERBOSE_DEBUG
257 if (dd->flags & SHA_FLAGS_DUMP_REG) {
258 char tmp[16];
259
260 dev_vdbg(dd->dev, "read 0x%08x from %s\n", value,
261 atmel_sha_reg_name(offset, tmp, sizeof(tmp), false));
262 }
263 #endif /* VERBOSE_DEBUG */
264
265 return value;
266 }
267
atmel_sha_write(struct atmel_sha_dev * dd,u32 offset,u32 value)268 static inline void atmel_sha_write(struct atmel_sha_dev *dd,
269 u32 offset, u32 value)
270 {
271 #ifdef VERBOSE_DEBUG
272 if (dd->flags & SHA_FLAGS_DUMP_REG) {
273 char tmp[16];
274
275 dev_vdbg(dd->dev, "write 0x%08x into %s\n", value,
276 atmel_sha_reg_name(offset, tmp, sizeof(tmp), true));
277 }
278 #endif /* VERBOSE_DEBUG */
279
280 writel_relaxed(value, dd->io_base + offset);
281 }
282
atmel_sha_complete(struct atmel_sha_dev * dd,int err)283 static inline int atmel_sha_complete(struct atmel_sha_dev *dd, int err)
284 {
285 struct ahash_request *req = dd->req;
286
287 dd->flags &= ~(SHA_FLAGS_BUSY | SHA_FLAGS_FINAL | SHA_FLAGS_CPU |
288 SHA_FLAGS_DMA_READY | SHA_FLAGS_OUTPUT_READY |
289 SHA_FLAGS_DUMP_REG);
290
291 clk_disable(dd->iclk);
292
293 if ((dd->is_async || dd->force_complete) && req->base.complete)
294 ahash_request_complete(req, err);
295
296 /* handle new request */
297 tasklet_schedule(&dd->queue_task);
298
299 return err;
300 }
301
atmel_sha_append_sg(struct atmel_sha_reqctx * ctx)302 static size_t atmel_sha_append_sg(struct atmel_sha_reqctx *ctx)
303 {
304 size_t count;
305
306 while ((ctx->bufcnt < ctx->buflen) && ctx->total) {
307 count = min3(ctx->sg->length - ctx->offset, ctx->total,
308 ctx->buflen - ctx->bufcnt);
309
310 if (count == 0) {
311 /*
312 * Check if count == 0 because the buffer is full or
313 * because the sg length is 0. In the latest case,
314 * check if there is another sg in the list, a 0 length
315 * sg doesn't necessarily mean the end of the sg list.
316 */
317 if ((ctx->sg->length == 0) && !sg_is_last(ctx->sg)) {
318 ctx->sg = sg_next(ctx->sg);
319 continue;
320 } else {
321 break;
322 }
323 }
324
325 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, ctx->sg,
326 ctx->offset, count, 0);
327
328 ctx->bufcnt += count;
329 ctx->offset += count;
330 ctx->total -= count;
331
332 if (ctx->offset == ctx->sg->length) {
333 ctx->sg = sg_next(ctx->sg);
334 if (ctx->sg)
335 ctx->offset = 0;
336 else
337 ctx->total = 0;
338 }
339 }
340
341 return 0;
342 }
343
344 /*
345 * The purpose of this padding is to ensure that the padded message is a
346 * multiple of 512 bits (SHA1/SHA224/SHA256) or 1024 bits (SHA384/SHA512).
347 * The bit "1" is appended at the end of the message followed by
348 * "padlen-1" zero bits. Then a 64 bits block (SHA1/SHA224/SHA256) or
349 * 128 bits block (SHA384/SHA512) equals to the message length in bits
350 * is appended.
351 *
352 * For SHA1/SHA224/SHA256, padlen is calculated as followed:
353 * - if message length < 56 bytes then padlen = 56 - message length
354 * - else padlen = 64 + 56 - message length
355 *
356 * For SHA384/SHA512, padlen is calculated as followed:
357 * - if message length < 112 bytes then padlen = 112 - message length
358 * - else padlen = 128 + 112 - message length
359 */
atmel_sha_fill_padding(struct atmel_sha_reqctx * ctx,int length)360 static void atmel_sha_fill_padding(struct atmel_sha_reqctx *ctx, int length)
361 {
362 unsigned int index, padlen;
363 __be64 bits[2];
364 u64 size[2];
365
366 size[0] = ctx->digcnt[0];
367 size[1] = ctx->digcnt[1];
368
369 size[0] += ctx->bufcnt;
370 if (size[0] < ctx->bufcnt)
371 size[1]++;
372
373 size[0] += length;
374 if (size[0] < length)
375 size[1]++;
376
377 bits[1] = cpu_to_be64(size[0] << 3);
378 bits[0] = cpu_to_be64(size[1] << 3 | size[0] >> 61);
379
380 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
381 case SHA_FLAGS_SHA384:
382 case SHA_FLAGS_SHA512:
383 index = ctx->bufcnt & 0x7f;
384 padlen = (index < 112) ? (112 - index) : ((128+112) - index);
385 *(ctx->buffer + ctx->bufcnt) = 0x80;
386 memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1);
387 memcpy(ctx->buffer + ctx->bufcnt + padlen, bits, 16);
388 ctx->bufcnt += padlen + 16;
389 ctx->flags |= SHA_FLAGS_PAD;
390 break;
391
392 default:
393 index = ctx->bufcnt & 0x3f;
394 padlen = (index < 56) ? (56 - index) : ((64+56) - index);
395 *(ctx->buffer + ctx->bufcnt) = 0x80;
396 memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1);
397 memcpy(ctx->buffer + ctx->bufcnt + padlen, &bits[1], 8);
398 ctx->bufcnt += padlen + 8;
399 ctx->flags |= SHA_FLAGS_PAD;
400 break;
401 }
402 }
403
atmel_sha_find_dev(struct atmel_sha_ctx * tctx)404 static struct atmel_sha_dev *atmel_sha_find_dev(struct atmel_sha_ctx *tctx)
405 {
406 struct atmel_sha_dev *dd;
407
408 spin_lock_bh(&atmel_sha.lock);
409 if (!tctx->dd)
410 tctx->dd = list_first_entry_or_null(&atmel_sha.dev_list,
411 struct atmel_sha_dev, list);
412 dd = tctx->dd;
413 spin_unlock_bh(&atmel_sha.lock);
414
415 return dd;
416 }
417
atmel_sha_init(struct ahash_request * req)418 static int atmel_sha_init(struct ahash_request *req)
419 {
420 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
421 struct atmel_sha_ctx *tctx = crypto_ahash_ctx(tfm);
422 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
423 struct atmel_sha_dev *dd = atmel_sha_find_dev(tctx);
424
425 ctx->dd = dd;
426
427 ctx->flags = 0;
428
429 dev_dbg(dd->dev, "init: digest size: %u\n",
430 crypto_ahash_digestsize(tfm));
431
432 switch (crypto_ahash_digestsize(tfm)) {
433 case SHA1_DIGEST_SIZE:
434 ctx->flags |= SHA_FLAGS_SHA1;
435 ctx->block_size = SHA1_BLOCK_SIZE;
436 break;
437 case SHA224_DIGEST_SIZE:
438 ctx->flags |= SHA_FLAGS_SHA224;
439 ctx->block_size = SHA224_BLOCK_SIZE;
440 break;
441 case SHA256_DIGEST_SIZE:
442 ctx->flags |= SHA_FLAGS_SHA256;
443 ctx->block_size = SHA256_BLOCK_SIZE;
444 break;
445 case SHA384_DIGEST_SIZE:
446 ctx->flags |= SHA_FLAGS_SHA384;
447 ctx->block_size = SHA384_BLOCK_SIZE;
448 break;
449 case SHA512_DIGEST_SIZE:
450 ctx->flags |= SHA_FLAGS_SHA512;
451 ctx->block_size = SHA512_BLOCK_SIZE;
452 break;
453 default:
454 return -EINVAL;
455 }
456
457 ctx->bufcnt = 0;
458 ctx->digcnt[0] = 0;
459 ctx->digcnt[1] = 0;
460 ctx->buflen = SHA_BUFFER_LEN;
461
462 return 0;
463 }
464
atmel_sha_write_ctrl(struct atmel_sha_dev * dd,int dma)465 static void atmel_sha_write_ctrl(struct atmel_sha_dev *dd, int dma)
466 {
467 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
468 u32 valmr = SHA_MR_MODE_AUTO;
469 unsigned int i, hashsize = 0;
470
471 if (likely(dma)) {
472 if (!dd->caps.has_dma)
473 atmel_sha_write(dd, SHA_IER, SHA_INT_TXBUFE);
474 valmr = SHA_MR_MODE_PDC;
475 if (dd->caps.has_dualbuff)
476 valmr |= SHA_MR_DUALBUFF;
477 } else {
478 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
479 }
480
481 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
482 case SHA_FLAGS_SHA1:
483 valmr |= SHA_MR_ALGO_SHA1;
484 hashsize = SHA1_DIGEST_SIZE;
485 break;
486
487 case SHA_FLAGS_SHA224:
488 valmr |= SHA_MR_ALGO_SHA224;
489 hashsize = SHA256_DIGEST_SIZE;
490 break;
491
492 case SHA_FLAGS_SHA256:
493 valmr |= SHA_MR_ALGO_SHA256;
494 hashsize = SHA256_DIGEST_SIZE;
495 break;
496
497 case SHA_FLAGS_SHA384:
498 valmr |= SHA_MR_ALGO_SHA384;
499 hashsize = SHA512_DIGEST_SIZE;
500 break;
501
502 case SHA_FLAGS_SHA512:
503 valmr |= SHA_MR_ALGO_SHA512;
504 hashsize = SHA512_DIGEST_SIZE;
505 break;
506
507 default:
508 break;
509 }
510
511 /* Setting CR_FIRST only for the first iteration */
512 if (!(ctx->digcnt[0] || ctx->digcnt[1])) {
513 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST);
514 } else if (dd->caps.has_uihv && (ctx->flags & SHA_FLAGS_RESTORE)) {
515 const u32 *hash = (const u32 *)ctx->digest;
516
517 /*
518 * Restore the hardware context: update the User Initialize
519 * Hash Value (UIHV) with the value saved when the latest
520 * 'update' operation completed on this very same crypto
521 * request.
522 */
523 ctx->flags &= ~SHA_FLAGS_RESTORE;
524 atmel_sha_write(dd, SHA_CR, SHA_CR_WUIHV);
525 for (i = 0; i < hashsize / sizeof(u32); ++i)
526 atmel_sha_write(dd, SHA_REG_DIN(i), hash[i]);
527 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST);
528 valmr |= SHA_MR_UIHV;
529 }
530 /*
531 * WARNING: If the UIHV feature is not available, the hardware CANNOT
532 * process concurrent requests: the internal registers used to store
533 * the hash/digest are still set to the partial digest output values
534 * computed during the latest round.
535 */
536
537 atmel_sha_write(dd, SHA_MR, valmr);
538 }
539
atmel_sha_wait_for_data_ready(struct atmel_sha_dev * dd,atmel_sha_fn_t resume)540 static inline int atmel_sha_wait_for_data_ready(struct atmel_sha_dev *dd,
541 atmel_sha_fn_t resume)
542 {
543 u32 isr = atmel_sha_read(dd, SHA_ISR);
544
545 if (unlikely(isr & SHA_INT_DATARDY))
546 return resume(dd);
547
548 dd->resume = resume;
549 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
550 return -EINPROGRESS;
551 }
552
atmel_sha_xmit_cpu(struct atmel_sha_dev * dd,const u8 * buf,size_t length,int final)553 static int atmel_sha_xmit_cpu(struct atmel_sha_dev *dd, const u8 *buf,
554 size_t length, int final)
555 {
556 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
557 int count, len32;
558 const u32 *buffer = (const u32 *)buf;
559
560 dev_dbg(dd->dev, "xmit_cpu: digcnt: 0x%llx 0x%llx, length: %zd, final: %d\n",
561 ctx->digcnt[1], ctx->digcnt[0], length, final);
562
563 atmel_sha_write_ctrl(dd, 0);
564
565 /* should be non-zero before next lines to disable clocks later */
566 ctx->digcnt[0] += length;
567 if (ctx->digcnt[0] < length)
568 ctx->digcnt[1]++;
569
570 if (final)
571 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */
572
573 len32 = DIV_ROUND_UP(length, sizeof(u32));
574
575 dd->flags |= SHA_FLAGS_CPU;
576
577 for (count = 0; count < len32; count++)
578 atmel_sha_write(dd, SHA_REG_DIN(count), buffer[count]);
579
580 return -EINPROGRESS;
581 }
582
atmel_sha_xmit_pdc(struct atmel_sha_dev * dd,dma_addr_t dma_addr1,size_t length1,dma_addr_t dma_addr2,size_t length2,int final)583 static int atmel_sha_xmit_pdc(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
584 size_t length1, dma_addr_t dma_addr2, size_t length2, int final)
585 {
586 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
587 int len32;
588
589 dev_dbg(dd->dev, "xmit_pdc: digcnt: 0x%llx 0x%llx, length: %zd, final: %d\n",
590 ctx->digcnt[1], ctx->digcnt[0], length1, final);
591
592 len32 = DIV_ROUND_UP(length1, sizeof(u32));
593 atmel_sha_write(dd, SHA_PTCR, SHA_PTCR_TXTDIS);
594 atmel_sha_write(dd, SHA_TPR, dma_addr1);
595 atmel_sha_write(dd, SHA_TCR, len32);
596
597 len32 = DIV_ROUND_UP(length2, sizeof(u32));
598 atmel_sha_write(dd, SHA_TNPR, dma_addr2);
599 atmel_sha_write(dd, SHA_TNCR, len32);
600
601 atmel_sha_write_ctrl(dd, 1);
602
603 /* should be non-zero before next lines to disable clocks later */
604 ctx->digcnt[0] += length1;
605 if (ctx->digcnt[0] < length1)
606 ctx->digcnt[1]++;
607
608 if (final)
609 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */
610
611 dd->flags |= SHA_FLAGS_DMA_ACTIVE;
612
613 /* Start DMA transfer */
614 atmel_sha_write(dd, SHA_PTCR, SHA_PTCR_TXTEN);
615
616 return -EINPROGRESS;
617 }
618
atmel_sha_dma_callback(void * data)619 static void atmel_sha_dma_callback(void *data)
620 {
621 struct atmel_sha_dev *dd = data;
622
623 dd->is_async = true;
624
625 /* dma_lch_in - completed - wait DATRDY */
626 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
627 }
628
atmel_sha_xmit_dma(struct atmel_sha_dev * dd,dma_addr_t dma_addr1,size_t length1,dma_addr_t dma_addr2,size_t length2,int final)629 static int atmel_sha_xmit_dma(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
630 size_t length1, dma_addr_t dma_addr2, size_t length2, int final)
631 {
632 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
633 struct dma_async_tx_descriptor *in_desc;
634 struct scatterlist sg[2];
635
636 dev_dbg(dd->dev, "xmit_dma: digcnt: 0x%llx 0x%llx, length: %zd, final: %d\n",
637 ctx->digcnt[1], ctx->digcnt[0], length1, final);
638
639 dd->dma_lch_in.dma_conf.src_maxburst = 16;
640 dd->dma_lch_in.dma_conf.dst_maxburst = 16;
641
642 dmaengine_slave_config(dd->dma_lch_in.chan, &dd->dma_lch_in.dma_conf);
643
644 if (length2) {
645 sg_init_table(sg, 2);
646 sg_dma_address(&sg[0]) = dma_addr1;
647 sg_dma_len(&sg[0]) = length1;
648 sg_dma_address(&sg[1]) = dma_addr2;
649 sg_dma_len(&sg[1]) = length2;
650 in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 2,
651 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
652 } else {
653 sg_init_table(sg, 1);
654 sg_dma_address(&sg[0]) = dma_addr1;
655 sg_dma_len(&sg[0]) = length1;
656 in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 1,
657 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
658 }
659 if (!in_desc)
660 return atmel_sha_complete(dd, -EINVAL);
661
662 in_desc->callback = atmel_sha_dma_callback;
663 in_desc->callback_param = dd;
664
665 atmel_sha_write_ctrl(dd, 1);
666
667 /* should be non-zero before next lines to disable clocks later */
668 ctx->digcnt[0] += length1;
669 if (ctx->digcnt[0] < length1)
670 ctx->digcnt[1]++;
671
672 if (final)
673 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */
674
675 dd->flags |= SHA_FLAGS_DMA_ACTIVE;
676
677 /* Start DMA transfer */
678 dmaengine_submit(in_desc);
679 dma_async_issue_pending(dd->dma_lch_in.chan);
680
681 return -EINPROGRESS;
682 }
683
atmel_sha_xmit_start(struct atmel_sha_dev * dd,dma_addr_t dma_addr1,size_t length1,dma_addr_t dma_addr2,size_t length2,int final)684 static int atmel_sha_xmit_start(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
685 size_t length1, dma_addr_t dma_addr2, size_t length2, int final)
686 {
687 if (dd->caps.has_dma)
688 return atmel_sha_xmit_dma(dd, dma_addr1, length1,
689 dma_addr2, length2, final);
690 else
691 return atmel_sha_xmit_pdc(dd, dma_addr1, length1,
692 dma_addr2, length2, final);
693 }
694
atmel_sha_update_cpu(struct atmel_sha_dev * dd)695 static int atmel_sha_update_cpu(struct atmel_sha_dev *dd)
696 {
697 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
698 int bufcnt;
699
700 atmel_sha_append_sg(ctx);
701 atmel_sha_fill_padding(ctx, 0);
702 bufcnt = ctx->bufcnt;
703 ctx->bufcnt = 0;
704
705 return atmel_sha_xmit_cpu(dd, ctx->buffer, bufcnt, 1);
706 }
707
atmel_sha_xmit_dma_map(struct atmel_sha_dev * dd,struct atmel_sha_reqctx * ctx,size_t length,int final)708 static int atmel_sha_xmit_dma_map(struct atmel_sha_dev *dd,
709 struct atmel_sha_reqctx *ctx,
710 size_t length, int final)
711 {
712 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer,
713 ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
714 if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
715 dev_err(dd->dev, "dma %zu bytes error\n", ctx->buflen +
716 ctx->block_size);
717 return atmel_sha_complete(dd, -EINVAL);
718 }
719
720 ctx->flags &= ~SHA_FLAGS_SG;
721
722 /* next call does not fail... so no unmap in the case of error */
723 return atmel_sha_xmit_start(dd, ctx->dma_addr, length, 0, 0, final);
724 }
725
atmel_sha_update_dma_slow(struct atmel_sha_dev * dd)726 static int atmel_sha_update_dma_slow(struct atmel_sha_dev *dd)
727 {
728 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
729 unsigned int final;
730 size_t count;
731
732 atmel_sha_append_sg(ctx);
733
734 final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total;
735
736 dev_dbg(dd->dev, "slow: bufcnt: %zu, digcnt: 0x%llx 0x%llx, final: %d\n",
737 ctx->bufcnt, ctx->digcnt[1], ctx->digcnt[0], final);
738
739 if (final)
740 atmel_sha_fill_padding(ctx, 0);
741
742 if (final || (ctx->bufcnt == ctx->buflen)) {
743 count = ctx->bufcnt;
744 ctx->bufcnt = 0;
745 return atmel_sha_xmit_dma_map(dd, ctx, count, final);
746 }
747
748 return 0;
749 }
750
atmel_sha_update_dma_start(struct atmel_sha_dev * dd)751 static int atmel_sha_update_dma_start(struct atmel_sha_dev *dd)
752 {
753 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
754 unsigned int length, final, tail;
755 struct scatterlist *sg;
756 unsigned int count;
757
758 if (!ctx->total)
759 return 0;
760
761 if (ctx->bufcnt || ctx->offset)
762 return atmel_sha_update_dma_slow(dd);
763
764 dev_dbg(dd->dev, "fast: digcnt: 0x%llx 0x%llx, bufcnt: %zd, total: %u\n",
765 ctx->digcnt[1], ctx->digcnt[0], ctx->bufcnt, ctx->total);
766
767 sg = ctx->sg;
768
769 if (!IS_ALIGNED(sg->offset, sizeof(u32)))
770 return atmel_sha_update_dma_slow(dd);
771
772 if (!sg_is_last(sg) && !IS_ALIGNED(sg->length, ctx->block_size))
773 /* size is not ctx->block_size aligned */
774 return atmel_sha_update_dma_slow(dd);
775
776 length = min(ctx->total, sg->length);
777
778 if (sg_is_last(sg)) {
779 if (!(ctx->flags & SHA_FLAGS_FINUP)) {
780 /* not last sg must be ctx->block_size aligned */
781 tail = length & (ctx->block_size - 1);
782 length -= tail;
783 }
784 }
785
786 ctx->total -= length;
787 ctx->offset = length; /* offset where to start slow */
788
789 final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total;
790
791 /* Add padding */
792 if (final) {
793 tail = length & (ctx->block_size - 1);
794 length -= tail;
795 ctx->total += tail;
796 ctx->offset = length; /* offset where to start slow */
797
798 sg = ctx->sg;
799 atmel_sha_append_sg(ctx);
800
801 atmel_sha_fill_padding(ctx, length);
802
803 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer,
804 ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
805 if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
806 dev_err(dd->dev, "dma %zu bytes error\n",
807 ctx->buflen + ctx->block_size);
808 return atmel_sha_complete(dd, -EINVAL);
809 }
810
811 if (length == 0) {
812 ctx->flags &= ~SHA_FLAGS_SG;
813 count = ctx->bufcnt;
814 ctx->bufcnt = 0;
815 return atmel_sha_xmit_start(dd, ctx->dma_addr, count, 0,
816 0, final);
817 } else {
818 ctx->sg = sg;
819 if (!dma_map_sg(dd->dev, ctx->sg, 1,
820 DMA_TO_DEVICE)) {
821 dev_err(dd->dev, "dma_map_sg error\n");
822 return atmel_sha_complete(dd, -EINVAL);
823 }
824
825 ctx->flags |= SHA_FLAGS_SG;
826
827 count = ctx->bufcnt;
828 ctx->bufcnt = 0;
829 return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg),
830 length, ctx->dma_addr, count, final);
831 }
832 }
833
834 if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
835 dev_err(dd->dev, "dma_map_sg error\n");
836 return atmel_sha_complete(dd, -EINVAL);
837 }
838
839 ctx->flags |= SHA_FLAGS_SG;
840
841 /* next call does not fail... so no unmap in the case of error */
842 return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg), length, 0,
843 0, final);
844 }
845
atmel_sha_update_dma_stop(struct atmel_sha_dev * dd)846 static void atmel_sha_update_dma_stop(struct atmel_sha_dev *dd)
847 {
848 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
849
850 if (ctx->flags & SHA_FLAGS_SG) {
851 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
852 if (ctx->sg->length == ctx->offset) {
853 ctx->sg = sg_next(ctx->sg);
854 if (ctx->sg)
855 ctx->offset = 0;
856 }
857 if (ctx->flags & SHA_FLAGS_PAD) {
858 dma_unmap_single(dd->dev, ctx->dma_addr,
859 ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
860 }
861 } else {
862 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen +
863 ctx->block_size, DMA_TO_DEVICE);
864 }
865 }
866
atmel_sha_update_req(struct atmel_sha_dev * dd)867 static int atmel_sha_update_req(struct atmel_sha_dev *dd)
868 {
869 struct ahash_request *req = dd->req;
870 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
871 int err;
872
873 dev_dbg(dd->dev, "update_req: total: %u, digcnt: 0x%llx 0x%llx\n",
874 ctx->total, ctx->digcnt[1], ctx->digcnt[0]);
875
876 if (ctx->flags & SHA_FLAGS_CPU)
877 err = atmel_sha_update_cpu(dd);
878 else
879 err = atmel_sha_update_dma_start(dd);
880
881 /* wait for dma completion before can take more data */
882 dev_dbg(dd->dev, "update: err: %d, digcnt: 0x%llx 0%llx\n",
883 err, ctx->digcnt[1], ctx->digcnt[0]);
884
885 return err;
886 }
887
atmel_sha_final_req(struct atmel_sha_dev * dd)888 static int atmel_sha_final_req(struct atmel_sha_dev *dd)
889 {
890 struct ahash_request *req = dd->req;
891 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
892 int err = 0;
893 int count;
894
895 if (ctx->bufcnt >= ATMEL_SHA_DMA_THRESHOLD) {
896 atmel_sha_fill_padding(ctx, 0);
897 count = ctx->bufcnt;
898 ctx->bufcnt = 0;
899 err = atmel_sha_xmit_dma_map(dd, ctx, count, 1);
900 }
901 /* faster to handle last block with cpu */
902 else {
903 atmel_sha_fill_padding(ctx, 0);
904 count = ctx->bufcnt;
905 ctx->bufcnt = 0;
906 err = atmel_sha_xmit_cpu(dd, ctx->buffer, count, 1);
907 }
908
909 dev_dbg(dd->dev, "final_req: err: %d\n", err);
910
911 return err;
912 }
913
atmel_sha_copy_hash(struct ahash_request * req)914 static void atmel_sha_copy_hash(struct ahash_request *req)
915 {
916 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
917 u32 *hash = (u32 *)ctx->digest;
918 unsigned int i, hashsize;
919
920 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
921 case SHA_FLAGS_SHA1:
922 hashsize = SHA1_DIGEST_SIZE;
923 break;
924
925 case SHA_FLAGS_SHA224:
926 case SHA_FLAGS_SHA256:
927 hashsize = SHA256_DIGEST_SIZE;
928 break;
929
930 case SHA_FLAGS_SHA384:
931 case SHA_FLAGS_SHA512:
932 hashsize = SHA512_DIGEST_SIZE;
933 break;
934
935 default:
936 /* Should not happen... */
937 return;
938 }
939
940 for (i = 0; i < hashsize / sizeof(u32); ++i)
941 hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
942 ctx->flags |= SHA_FLAGS_RESTORE;
943 }
944
atmel_sha_copy_ready_hash(struct ahash_request * req)945 static void atmel_sha_copy_ready_hash(struct ahash_request *req)
946 {
947 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
948
949 if (!req->result)
950 return;
951
952 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
953 default:
954 case SHA_FLAGS_SHA1:
955 memcpy(req->result, ctx->digest, SHA1_DIGEST_SIZE);
956 break;
957
958 case SHA_FLAGS_SHA224:
959 memcpy(req->result, ctx->digest, SHA224_DIGEST_SIZE);
960 break;
961
962 case SHA_FLAGS_SHA256:
963 memcpy(req->result, ctx->digest, SHA256_DIGEST_SIZE);
964 break;
965
966 case SHA_FLAGS_SHA384:
967 memcpy(req->result, ctx->digest, SHA384_DIGEST_SIZE);
968 break;
969
970 case SHA_FLAGS_SHA512:
971 memcpy(req->result, ctx->digest, SHA512_DIGEST_SIZE);
972 break;
973 }
974 }
975
atmel_sha_finish(struct ahash_request * req)976 static int atmel_sha_finish(struct ahash_request *req)
977 {
978 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
979 struct atmel_sha_dev *dd = ctx->dd;
980
981 if (ctx->digcnt[0] || ctx->digcnt[1])
982 atmel_sha_copy_ready_hash(req);
983
984 dev_dbg(dd->dev, "digcnt: 0x%llx 0x%llx, bufcnt: %zd\n", ctx->digcnt[1],
985 ctx->digcnt[0], ctx->bufcnt);
986
987 return 0;
988 }
989
atmel_sha_finish_req(struct ahash_request * req,int err)990 static void atmel_sha_finish_req(struct ahash_request *req, int err)
991 {
992 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
993 struct atmel_sha_dev *dd = ctx->dd;
994
995 if (!err) {
996 atmel_sha_copy_hash(req);
997 if (SHA_FLAGS_FINAL & dd->flags)
998 err = atmel_sha_finish(req);
999 } else {
1000 ctx->flags |= SHA_FLAGS_ERROR;
1001 }
1002
1003 /* atomic operation is not needed here */
1004 (void)atmel_sha_complete(dd, err);
1005 }
1006
atmel_sha_hw_init(struct atmel_sha_dev * dd)1007 static int atmel_sha_hw_init(struct atmel_sha_dev *dd)
1008 {
1009 int err;
1010
1011 err = clk_enable(dd->iclk);
1012 if (err)
1013 return err;
1014
1015 if (!(SHA_FLAGS_INIT & dd->flags)) {
1016 atmel_sha_write(dd, SHA_CR, SHA_CR_SWRST);
1017 dd->flags |= SHA_FLAGS_INIT;
1018 }
1019
1020 return 0;
1021 }
1022
atmel_sha_get_version(struct atmel_sha_dev * dd)1023 static inline unsigned int atmel_sha_get_version(struct atmel_sha_dev *dd)
1024 {
1025 return atmel_sha_read(dd, SHA_HW_VERSION) & 0x00000fff;
1026 }
1027
atmel_sha_hw_version_init(struct atmel_sha_dev * dd)1028 static int atmel_sha_hw_version_init(struct atmel_sha_dev *dd)
1029 {
1030 int err;
1031
1032 err = atmel_sha_hw_init(dd);
1033 if (err)
1034 return err;
1035
1036 dd->hw_version = atmel_sha_get_version(dd);
1037
1038 dev_info(dd->dev,
1039 "version: 0x%x\n", dd->hw_version);
1040
1041 clk_disable(dd->iclk);
1042
1043 return 0;
1044 }
1045
atmel_sha_handle_queue(struct atmel_sha_dev * dd,struct ahash_request * req)1046 static int atmel_sha_handle_queue(struct atmel_sha_dev *dd,
1047 struct ahash_request *req)
1048 {
1049 struct crypto_async_request *async_req, *backlog;
1050 struct atmel_sha_ctx *ctx;
1051 unsigned long flags;
1052 bool start_async;
1053 int err = 0, ret = 0;
1054
1055 spin_lock_irqsave(&dd->lock, flags);
1056 if (req)
1057 ret = ahash_enqueue_request(&dd->queue, req);
1058
1059 if (SHA_FLAGS_BUSY & dd->flags) {
1060 spin_unlock_irqrestore(&dd->lock, flags);
1061 return ret;
1062 }
1063
1064 backlog = crypto_get_backlog(&dd->queue);
1065 async_req = crypto_dequeue_request(&dd->queue);
1066 if (async_req)
1067 dd->flags |= SHA_FLAGS_BUSY;
1068
1069 spin_unlock_irqrestore(&dd->lock, flags);
1070
1071 if (!async_req)
1072 return ret;
1073
1074 if (backlog)
1075 crypto_request_complete(backlog, -EINPROGRESS);
1076
1077 ctx = crypto_tfm_ctx(async_req->tfm);
1078
1079 dd->req = ahash_request_cast(async_req);
1080 start_async = (dd->req != req);
1081 dd->is_async = start_async;
1082 dd->force_complete = false;
1083
1084 /* WARNING: ctx->start() MAY change dd->is_async. */
1085 err = ctx->start(dd);
1086 return (start_async) ? ret : err;
1087 }
1088
1089 static int atmel_sha_done(struct atmel_sha_dev *dd);
1090
atmel_sha_start(struct atmel_sha_dev * dd)1091 static int atmel_sha_start(struct atmel_sha_dev *dd)
1092 {
1093 struct ahash_request *req = dd->req;
1094 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1095 int err;
1096
1097 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %u\n",
1098 ctx->op, req->nbytes);
1099
1100 err = atmel_sha_hw_init(dd);
1101 if (err)
1102 return atmel_sha_complete(dd, err);
1103
1104 /*
1105 * atmel_sha_update_req() and atmel_sha_final_req() can return either:
1106 * -EINPROGRESS: the hardware is busy and the SHA driver will resume
1107 * its job later in the done_task.
1108 * This is the main path.
1109 *
1110 * 0: the SHA driver can continue its job then release the hardware
1111 * later, if needed, with atmel_sha_finish_req().
1112 * This is the alternate path.
1113 *
1114 * < 0: an error has occurred so atmel_sha_complete(dd, err) has already
1115 * been called, hence the hardware has been released.
1116 * The SHA driver must stop its job without calling
1117 * atmel_sha_finish_req(), otherwise atmel_sha_complete() would be
1118 * called a second time.
1119 *
1120 * Please note that currently, atmel_sha_final_req() never returns 0.
1121 */
1122
1123 dd->resume = atmel_sha_done;
1124 if (ctx->op == SHA_OP_UPDATE) {
1125 err = atmel_sha_update_req(dd);
1126 if (!err && (ctx->flags & SHA_FLAGS_FINUP))
1127 /* no final() after finup() */
1128 err = atmel_sha_final_req(dd);
1129 } else if (ctx->op == SHA_OP_FINAL) {
1130 err = atmel_sha_final_req(dd);
1131 }
1132
1133 if (!err)
1134 /* done_task will not finish it, so do it here */
1135 atmel_sha_finish_req(req, err);
1136
1137 dev_dbg(dd->dev, "exit, err: %d\n", err);
1138
1139 return err;
1140 }
1141
atmel_sha_enqueue(struct ahash_request * req,unsigned int op)1142 static int atmel_sha_enqueue(struct ahash_request *req, unsigned int op)
1143 {
1144 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1145 struct atmel_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1146 struct atmel_sha_dev *dd = tctx->dd;
1147
1148 ctx->op = op;
1149
1150 return atmel_sha_handle_queue(dd, req);
1151 }
1152
atmel_sha_update(struct ahash_request * req)1153 static int atmel_sha_update(struct ahash_request *req)
1154 {
1155 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1156
1157 if (!req->nbytes)
1158 return 0;
1159
1160 ctx->total = req->nbytes;
1161 ctx->sg = req->src;
1162 ctx->offset = 0;
1163
1164 if (ctx->flags & SHA_FLAGS_FINUP) {
1165 if (ctx->bufcnt + ctx->total < ATMEL_SHA_DMA_THRESHOLD)
1166 /* faster to use CPU for short transfers */
1167 ctx->flags |= SHA_FLAGS_CPU;
1168 } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
1169 atmel_sha_append_sg(ctx);
1170 return 0;
1171 }
1172 return atmel_sha_enqueue(req, SHA_OP_UPDATE);
1173 }
1174
atmel_sha_final(struct ahash_request * req)1175 static int atmel_sha_final(struct ahash_request *req)
1176 {
1177 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1178
1179 ctx->flags |= SHA_FLAGS_FINUP;
1180
1181 if (ctx->flags & SHA_FLAGS_ERROR)
1182 return 0; /* uncompleted hash is not needed */
1183
1184 if (ctx->flags & SHA_FLAGS_PAD)
1185 /* copy ready hash (+ finalize hmac) */
1186 return atmel_sha_finish(req);
1187
1188 return atmel_sha_enqueue(req, SHA_OP_FINAL);
1189 }
1190
atmel_sha_finup(struct ahash_request * req)1191 static int atmel_sha_finup(struct ahash_request *req)
1192 {
1193 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1194 int err1, err2;
1195
1196 ctx->flags |= SHA_FLAGS_FINUP;
1197
1198 err1 = atmel_sha_update(req);
1199 if (err1 == -EINPROGRESS ||
1200 (err1 == -EBUSY && (ahash_request_flags(req) &
1201 CRYPTO_TFM_REQ_MAY_BACKLOG)))
1202 return err1;
1203
1204 /*
1205 * final() has to be always called to cleanup resources
1206 * even if udpate() failed, except EINPROGRESS
1207 */
1208 err2 = atmel_sha_final(req);
1209
1210 return err1 ?: err2;
1211 }
1212
atmel_sha_digest(struct ahash_request * req)1213 static int atmel_sha_digest(struct ahash_request *req)
1214 {
1215 return atmel_sha_init(req) ?: atmel_sha_finup(req);
1216 }
1217
1218
atmel_sha_export(struct ahash_request * req,void * out)1219 static int atmel_sha_export(struct ahash_request *req, void *out)
1220 {
1221 const struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1222
1223 memcpy(out, ctx, sizeof(*ctx));
1224 return 0;
1225 }
1226
atmel_sha_import(struct ahash_request * req,const void * in)1227 static int atmel_sha_import(struct ahash_request *req, const void *in)
1228 {
1229 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1230
1231 memcpy(ctx, in, sizeof(*ctx));
1232 return 0;
1233 }
1234
atmel_sha_cra_init(struct crypto_tfm * tfm)1235 static int atmel_sha_cra_init(struct crypto_tfm *tfm)
1236 {
1237 struct atmel_sha_ctx *ctx = crypto_tfm_ctx(tfm);
1238
1239 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1240 sizeof(struct atmel_sha_reqctx));
1241 ctx->start = atmel_sha_start;
1242
1243 return 0;
1244 }
1245
atmel_sha_alg_init(struct ahash_alg * alg)1246 static void atmel_sha_alg_init(struct ahash_alg *alg)
1247 {
1248 alg->halg.base.cra_priority = ATMEL_SHA_PRIORITY;
1249 alg->halg.base.cra_flags = CRYPTO_ALG_ASYNC |
1250 CRYPTO_ALG_KERN_DRIVER_ONLY;
1251 alg->halg.base.cra_ctxsize = sizeof(struct atmel_sha_ctx);
1252 alg->halg.base.cra_module = THIS_MODULE;
1253 alg->halg.base.cra_init = atmel_sha_cra_init;
1254
1255 alg->halg.statesize = sizeof(struct atmel_sha_reqctx);
1256
1257 alg->init = atmel_sha_init;
1258 alg->update = atmel_sha_update;
1259 alg->final = atmel_sha_final;
1260 alg->finup = atmel_sha_finup;
1261 alg->digest = atmel_sha_digest;
1262 alg->export = atmel_sha_export;
1263 alg->import = atmel_sha_import;
1264 }
1265
1266 static struct ahash_alg sha_1_256_algs[] = {
1267 {
1268 .halg.base.cra_name = "sha1",
1269 .halg.base.cra_driver_name = "atmel-sha1",
1270 .halg.base.cra_blocksize = SHA1_BLOCK_SIZE,
1271
1272 .halg.digestsize = SHA1_DIGEST_SIZE,
1273 },
1274 {
1275 .halg.base.cra_name = "sha256",
1276 .halg.base.cra_driver_name = "atmel-sha256",
1277 .halg.base.cra_blocksize = SHA256_BLOCK_SIZE,
1278
1279 .halg.digestsize = SHA256_DIGEST_SIZE,
1280 },
1281 };
1282
1283 static struct ahash_alg sha_224_alg = {
1284 .halg.base.cra_name = "sha224",
1285 .halg.base.cra_driver_name = "atmel-sha224",
1286 .halg.base.cra_blocksize = SHA224_BLOCK_SIZE,
1287
1288 .halg.digestsize = SHA224_DIGEST_SIZE,
1289 };
1290
1291 static struct ahash_alg sha_384_512_algs[] = {
1292 {
1293 .halg.base.cra_name = "sha384",
1294 .halg.base.cra_driver_name = "atmel-sha384",
1295 .halg.base.cra_blocksize = SHA384_BLOCK_SIZE,
1296
1297 .halg.digestsize = SHA384_DIGEST_SIZE,
1298 },
1299 {
1300 .halg.base.cra_name = "sha512",
1301 .halg.base.cra_driver_name = "atmel-sha512",
1302 .halg.base.cra_blocksize = SHA512_BLOCK_SIZE,
1303
1304 .halg.digestsize = SHA512_DIGEST_SIZE,
1305 },
1306 };
1307
atmel_sha_queue_task(unsigned long data)1308 static void atmel_sha_queue_task(unsigned long data)
1309 {
1310 struct atmel_sha_dev *dd = (struct atmel_sha_dev *)data;
1311
1312 atmel_sha_handle_queue(dd, NULL);
1313 }
1314
atmel_sha_done(struct atmel_sha_dev * dd)1315 static int atmel_sha_done(struct atmel_sha_dev *dd)
1316 {
1317 int err = 0;
1318
1319 if (SHA_FLAGS_CPU & dd->flags) {
1320 if (SHA_FLAGS_OUTPUT_READY & dd->flags) {
1321 dd->flags &= ~SHA_FLAGS_OUTPUT_READY;
1322 goto finish;
1323 }
1324 } else if (SHA_FLAGS_DMA_READY & dd->flags) {
1325 if (SHA_FLAGS_DMA_ACTIVE & dd->flags) {
1326 dd->flags &= ~SHA_FLAGS_DMA_ACTIVE;
1327 atmel_sha_update_dma_stop(dd);
1328 }
1329 if (SHA_FLAGS_OUTPUT_READY & dd->flags) {
1330 /* hash or semi-hash ready */
1331 dd->flags &= ~(SHA_FLAGS_DMA_READY |
1332 SHA_FLAGS_OUTPUT_READY);
1333 err = atmel_sha_update_dma_start(dd);
1334 if (err != -EINPROGRESS)
1335 goto finish;
1336 }
1337 }
1338 return err;
1339
1340 finish:
1341 /* finish curent request */
1342 atmel_sha_finish_req(dd->req, err);
1343
1344 return err;
1345 }
1346
atmel_sha_done_task(unsigned long data)1347 static void atmel_sha_done_task(unsigned long data)
1348 {
1349 struct atmel_sha_dev *dd = (struct atmel_sha_dev *)data;
1350
1351 dd->is_async = true;
1352 (void)dd->resume(dd);
1353 }
1354
atmel_sha_irq(int irq,void * dev_id)1355 static irqreturn_t atmel_sha_irq(int irq, void *dev_id)
1356 {
1357 struct atmel_sha_dev *sha_dd = dev_id;
1358 u32 reg;
1359
1360 reg = atmel_sha_read(sha_dd, SHA_ISR);
1361 if (reg & atmel_sha_read(sha_dd, SHA_IMR)) {
1362 atmel_sha_write(sha_dd, SHA_IDR, reg);
1363 if (SHA_FLAGS_BUSY & sha_dd->flags) {
1364 sha_dd->flags |= SHA_FLAGS_OUTPUT_READY;
1365 if (!(SHA_FLAGS_CPU & sha_dd->flags))
1366 sha_dd->flags |= SHA_FLAGS_DMA_READY;
1367 tasklet_schedule(&sha_dd->done_task);
1368 } else {
1369 dev_warn(sha_dd->dev, "SHA interrupt when no active requests.\n");
1370 }
1371 return IRQ_HANDLED;
1372 }
1373
1374 return IRQ_NONE;
1375 }
1376
1377
1378 /* DMA transfer functions */
1379
atmel_sha_dma_check_aligned(struct atmel_sha_dev * dd,struct scatterlist * sg,size_t len)1380 static bool atmel_sha_dma_check_aligned(struct atmel_sha_dev *dd,
1381 struct scatterlist *sg,
1382 size_t len)
1383 {
1384 struct atmel_sha_dma *dma = &dd->dma_lch_in;
1385 struct ahash_request *req = dd->req;
1386 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1387 size_t bs = ctx->block_size;
1388 int nents;
1389
1390 for (nents = 0; sg; sg = sg_next(sg), ++nents) {
1391 if (!IS_ALIGNED(sg->offset, sizeof(u32)))
1392 return false;
1393
1394 /*
1395 * This is the last sg, the only one that is allowed to
1396 * have an unaligned length.
1397 */
1398 if (len <= sg->length) {
1399 dma->nents = nents + 1;
1400 dma->last_sg_length = sg->length;
1401 sg->length = ALIGN(len, sizeof(u32));
1402 return true;
1403 }
1404
1405 /* All other sg lengths MUST be aligned to the block size. */
1406 if (!IS_ALIGNED(sg->length, bs))
1407 return false;
1408
1409 len -= sg->length;
1410 }
1411
1412 return false;
1413 }
1414
atmel_sha_dma_callback2(void * data)1415 static void atmel_sha_dma_callback2(void *data)
1416 {
1417 struct atmel_sha_dev *dd = data;
1418 struct atmel_sha_dma *dma = &dd->dma_lch_in;
1419 struct scatterlist *sg;
1420 int nents;
1421
1422 dma_unmap_sg(dd->dev, dma->sg, dma->nents, DMA_TO_DEVICE);
1423
1424 sg = dma->sg;
1425 for (nents = 0; nents < dma->nents - 1; ++nents)
1426 sg = sg_next(sg);
1427 sg->length = dma->last_sg_length;
1428
1429 dd->is_async = true;
1430 (void)atmel_sha_wait_for_data_ready(dd, dd->resume);
1431 }
1432
atmel_sha_dma_start(struct atmel_sha_dev * dd,struct scatterlist * src,size_t len,atmel_sha_fn_t resume)1433 static int atmel_sha_dma_start(struct atmel_sha_dev *dd,
1434 struct scatterlist *src,
1435 size_t len,
1436 atmel_sha_fn_t resume)
1437 {
1438 struct atmel_sha_dma *dma = &dd->dma_lch_in;
1439 struct dma_slave_config *config = &dma->dma_conf;
1440 struct dma_chan *chan = dma->chan;
1441 struct dma_async_tx_descriptor *desc;
1442 dma_cookie_t cookie;
1443 unsigned int sg_len;
1444 int err;
1445
1446 dd->resume = resume;
1447
1448 /*
1449 * dma->nents has already been initialized by
1450 * atmel_sha_dma_check_aligned().
1451 */
1452 dma->sg = src;
1453 sg_len = dma_map_sg(dd->dev, dma->sg, dma->nents, DMA_TO_DEVICE);
1454 if (!sg_len) {
1455 err = -ENOMEM;
1456 goto exit;
1457 }
1458
1459 config->src_maxburst = 16;
1460 config->dst_maxburst = 16;
1461 err = dmaengine_slave_config(chan, config);
1462 if (err)
1463 goto unmap_sg;
1464
1465 desc = dmaengine_prep_slave_sg(chan, dma->sg, sg_len, DMA_MEM_TO_DEV,
1466 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1467 if (!desc) {
1468 err = -ENOMEM;
1469 goto unmap_sg;
1470 }
1471
1472 desc->callback = atmel_sha_dma_callback2;
1473 desc->callback_param = dd;
1474 cookie = dmaengine_submit(desc);
1475 err = dma_submit_error(cookie);
1476 if (err)
1477 goto unmap_sg;
1478
1479 dma_async_issue_pending(chan);
1480
1481 return -EINPROGRESS;
1482
1483 unmap_sg:
1484 dma_unmap_sg(dd->dev, dma->sg, dma->nents, DMA_TO_DEVICE);
1485 exit:
1486 return atmel_sha_complete(dd, err);
1487 }
1488
1489
1490 /* CPU transfer functions */
1491
atmel_sha_cpu_transfer(struct atmel_sha_dev * dd)1492 static int atmel_sha_cpu_transfer(struct atmel_sha_dev *dd)
1493 {
1494 struct ahash_request *req = dd->req;
1495 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1496 const u32 *words = (const u32 *)ctx->buffer;
1497 size_t i, num_words;
1498 u32 isr, din, din_inc;
1499
1500 din_inc = (ctx->flags & SHA_FLAGS_IDATAR0) ? 0 : 1;
1501 for (;;) {
1502 /* Write data into the Input Data Registers. */
1503 num_words = DIV_ROUND_UP(ctx->bufcnt, sizeof(u32));
1504 for (i = 0, din = 0; i < num_words; ++i, din += din_inc)
1505 atmel_sha_write(dd, SHA_REG_DIN(din), words[i]);
1506
1507 ctx->offset += ctx->bufcnt;
1508 ctx->total -= ctx->bufcnt;
1509
1510 if (!ctx->total)
1511 break;
1512
1513 /*
1514 * Prepare next block:
1515 * Fill ctx->buffer now with the next data to be written into
1516 * IDATARx: it gives time for the SHA hardware to process
1517 * the current data so the SHA_INT_DATARDY flag might be set
1518 * in SHA_ISR when polling this register at the beginning of
1519 * the next loop.
1520 */
1521 ctx->bufcnt = min_t(size_t, ctx->block_size, ctx->total);
1522 scatterwalk_map_and_copy(ctx->buffer, ctx->sg,
1523 ctx->offset, ctx->bufcnt, 0);
1524
1525 /* Wait for hardware to be ready again. */
1526 isr = atmel_sha_read(dd, SHA_ISR);
1527 if (!(isr & SHA_INT_DATARDY)) {
1528 /* Not ready yet. */
1529 dd->resume = atmel_sha_cpu_transfer;
1530 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
1531 return -EINPROGRESS;
1532 }
1533 }
1534
1535 if (unlikely(!(ctx->flags & SHA_FLAGS_WAIT_DATARDY)))
1536 return dd->cpu_transfer_complete(dd);
1537
1538 return atmel_sha_wait_for_data_ready(dd, dd->cpu_transfer_complete);
1539 }
1540
atmel_sha_cpu_start(struct atmel_sha_dev * dd,struct scatterlist * sg,unsigned int len,bool idatar0_only,bool wait_data_ready,atmel_sha_fn_t resume)1541 static int atmel_sha_cpu_start(struct atmel_sha_dev *dd,
1542 struct scatterlist *sg,
1543 unsigned int len,
1544 bool idatar0_only,
1545 bool wait_data_ready,
1546 atmel_sha_fn_t resume)
1547 {
1548 struct ahash_request *req = dd->req;
1549 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1550
1551 if (!len)
1552 return resume(dd);
1553
1554 ctx->flags &= ~(SHA_FLAGS_IDATAR0 | SHA_FLAGS_WAIT_DATARDY);
1555
1556 if (idatar0_only)
1557 ctx->flags |= SHA_FLAGS_IDATAR0;
1558
1559 if (wait_data_ready)
1560 ctx->flags |= SHA_FLAGS_WAIT_DATARDY;
1561
1562 ctx->sg = sg;
1563 ctx->total = len;
1564 ctx->offset = 0;
1565
1566 /* Prepare the first block to be written. */
1567 ctx->bufcnt = min_t(size_t, ctx->block_size, ctx->total);
1568 scatterwalk_map_and_copy(ctx->buffer, ctx->sg,
1569 ctx->offset, ctx->bufcnt, 0);
1570
1571 dd->cpu_transfer_complete = resume;
1572 return atmel_sha_cpu_transfer(dd);
1573 }
1574
atmel_sha_cpu_hash(struct atmel_sha_dev * dd,const void * data,unsigned int datalen,bool auto_padding,atmel_sha_fn_t resume)1575 static int atmel_sha_cpu_hash(struct atmel_sha_dev *dd,
1576 const void *data, unsigned int datalen,
1577 bool auto_padding,
1578 atmel_sha_fn_t resume)
1579 {
1580 struct ahash_request *req = dd->req;
1581 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1582 u32 msglen = (auto_padding) ? datalen : 0;
1583 u32 mr = SHA_MR_MODE_AUTO;
1584
1585 if (!(IS_ALIGNED(datalen, ctx->block_size) || auto_padding))
1586 return atmel_sha_complete(dd, -EINVAL);
1587
1588 mr |= (ctx->flags & SHA_FLAGS_ALGO_MASK);
1589 atmel_sha_write(dd, SHA_MR, mr);
1590 atmel_sha_write(dd, SHA_MSR, msglen);
1591 atmel_sha_write(dd, SHA_BCR, msglen);
1592 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST);
1593
1594 sg_init_one(&dd->tmp, data, datalen);
1595 return atmel_sha_cpu_start(dd, &dd->tmp, datalen, false, true, resume);
1596 }
1597
1598
1599 /* hmac functions */
1600
1601 struct atmel_sha_hmac_key {
1602 bool valid;
1603 unsigned int keylen;
1604 u8 buffer[SHA512_BLOCK_SIZE];
1605 u8 *keydup;
1606 };
1607
atmel_sha_hmac_key_init(struct atmel_sha_hmac_key * hkey)1608 static inline void atmel_sha_hmac_key_init(struct atmel_sha_hmac_key *hkey)
1609 {
1610 memset(hkey, 0, sizeof(*hkey));
1611 }
1612
atmel_sha_hmac_key_release(struct atmel_sha_hmac_key * hkey)1613 static inline void atmel_sha_hmac_key_release(struct atmel_sha_hmac_key *hkey)
1614 {
1615 kfree(hkey->keydup);
1616 memset(hkey, 0, sizeof(*hkey));
1617 }
1618
atmel_sha_hmac_key_set(struct atmel_sha_hmac_key * hkey,const u8 * key,unsigned int keylen)1619 static inline int atmel_sha_hmac_key_set(struct atmel_sha_hmac_key *hkey,
1620 const u8 *key,
1621 unsigned int keylen)
1622 {
1623 atmel_sha_hmac_key_release(hkey);
1624
1625 if (keylen > sizeof(hkey->buffer)) {
1626 hkey->keydup = kmemdup(key, keylen, GFP_KERNEL);
1627 if (!hkey->keydup)
1628 return -ENOMEM;
1629
1630 } else {
1631 memcpy(hkey->buffer, key, keylen);
1632 }
1633
1634 hkey->valid = true;
1635 hkey->keylen = keylen;
1636 return 0;
1637 }
1638
atmel_sha_hmac_key_get(const struct atmel_sha_hmac_key * hkey,const u8 ** key,unsigned int * keylen)1639 static inline bool atmel_sha_hmac_key_get(const struct atmel_sha_hmac_key *hkey,
1640 const u8 **key,
1641 unsigned int *keylen)
1642 {
1643 if (!hkey->valid)
1644 return false;
1645
1646 *keylen = hkey->keylen;
1647 *key = (hkey->keydup) ? hkey->keydup : hkey->buffer;
1648 return true;
1649 }
1650
1651
1652 struct atmel_sha_hmac_ctx {
1653 struct atmel_sha_ctx base;
1654
1655 struct atmel_sha_hmac_key hkey;
1656 u32 ipad[SHA512_BLOCK_SIZE / sizeof(u32)];
1657 u32 opad[SHA512_BLOCK_SIZE / sizeof(u32)];
1658 atmel_sha_fn_t resume;
1659 };
1660
1661 static int atmel_sha_hmac_setup(struct atmel_sha_dev *dd,
1662 atmel_sha_fn_t resume);
1663 static int atmel_sha_hmac_prehash_key(struct atmel_sha_dev *dd,
1664 const u8 *key, unsigned int keylen);
1665 static int atmel_sha_hmac_prehash_key_done(struct atmel_sha_dev *dd);
1666 static int atmel_sha_hmac_compute_ipad_hash(struct atmel_sha_dev *dd);
1667 static int atmel_sha_hmac_compute_opad_hash(struct atmel_sha_dev *dd);
1668 static int atmel_sha_hmac_setup_done(struct atmel_sha_dev *dd);
1669
1670 static int atmel_sha_hmac_init_done(struct atmel_sha_dev *dd);
1671 static int atmel_sha_hmac_final(struct atmel_sha_dev *dd);
1672 static int atmel_sha_hmac_final_done(struct atmel_sha_dev *dd);
1673 static int atmel_sha_hmac_digest2(struct atmel_sha_dev *dd);
1674
atmel_sha_hmac_setup(struct atmel_sha_dev * dd,atmel_sha_fn_t resume)1675 static int atmel_sha_hmac_setup(struct atmel_sha_dev *dd,
1676 atmel_sha_fn_t resume)
1677 {
1678 struct ahash_request *req = dd->req;
1679 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1680 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1681 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
1682 unsigned int keylen;
1683 const u8 *key;
1684 size_t bs;
1685
1686 hmac->resume = resume;
1687 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
1688 case SHA_FLAGS_SHA1:
1689 ctx->block_size = SHA1_BLOCK_SIZE;
1690 ctx->hash_size = SHA1_DIGEST_SIZE;
1691 break;
1692
1693 case SHA_FLAGS_SHA224:
1694 ctx->block_size = SHA224_BLOCK_SIZE;
1695 ctx->hash_size = SHA256_DIGEST_SIZE;
1696 break;
1697
1698 case SHA_FLAGS_SHA256:
1699 ctx->block_size = SHA256_BLOCK_SIZE;
1700 ctx->hash_size = SHA256_DIGEST_SIZE;
1701 break;
1702
1703 case SHA_FLAGS_SHA384:
1704 ctx->block_size = SHA384_BLOCK_SIZE;
1705 ctx->hash_size = SHA512_DIGEST_SIZE;
1706 break;
1707
1708 case SHA_FLAGS_SHA512:
1709 ctx->block_size = SHA512_BLOCK_SIZE;
1710 ctx->hash_size = SHA512_DIGEST_SIZE;
1711 break;
1712
1713 default:
1714 return atmel_sha_complete(dd, -EINVAL);
1715 }
1716 bs = ctx->block_size;
1717
1718 if (likely(!atmel_sha_hmac_key_get(&hmac->hkey, &key, &keylen)))
1719 return resume(dd);
1720
1721 /* Compute K' from K. */
1722 if (unlikely(keylen > bs))
1723 return atmel_sha_hmac_prehash_key(dd, key, keylen);
1724
1725 /* Prepare ipad. */
1726 memcpy_and_pad(hmac->ipad, bs, key, keylen, 0);
1727 return atmel_sha_hmac_compute_ipad_hash(dd);
1728 }
1729
atmel_sha_hmac_prehash_key(struct atmel_sha_dev * dd,const u8 * key,unsigned int keylen)1730 static int atmel_sha_hmac_prehash_key(struct atmel_sha_dev *dd,
1731 const u8 *key, unsigned int keylen)
1732 {
1733 return atmel_sha_cpu_hash(dd, key, keylen, true,
1734 atmel_sha_hmac_prehash_key_done);
1735 }
1736
atmel_sha_hmac_prehash_key_done(struct atmel_sha_dev * dd)1737 static int atmel_sha_hmac_prehash_key_done(struct atmel_sha_dev *dd)
1738 {
1739 struct ahash_request *req = dd->req;
1740 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1741 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
1742 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1743 size_t ds = crypto_ahash_digestsize(tfm);
1744 size_t bs = ctx->block_size;
1745 size_t i, num_words = ds / sizeof(u32);
1746
1747 /* Prepare ipad. */
1748 for (i = 0; i < num_words; ++i)
1749 hmac->ipad[i] = atmel_sha_read(dd, SHA_REG_DIGEST(i));
1750 memset((u8 *)hmac->ipad + ds, 0, bs - ds);
1751 return atmel_sha_hmac_compute_ipad_hash(dd);
1752 }
1753
atmel_sha_hmac_compute_ipad_hash(struct atmel_sha_dev * dd)1754 static int atmel_sha_hmac_compute_ipad_hash(struct atmel_sha_dev *dd)
1755 {
1756 struct ahash_request *req = dd->req;
1757 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1758 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
1759 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1760 size_t bs = ctx->block_size;
1761 size_t i, num_words = bs / sizeof(u32);
1762
1763 unsafe_memcpy(hmac->opad, hmac->ipad, bs,
1764 "fortified memcpy causes -Wrestrict warning");
1765 for (i = 0; i < num_words; ++i) {
1766 hmac->ipad[i] ^= 0x36363636;
1767 hmac->opad[i] ^= 0x5c5c5c5c;
1768 }
1769
1770 return atmel_sha_cpu_hash(dd, hmac->ipad, bs, false,
1771 atmel_sha_hmac_compute_opad_hash);
1772 }
1773
atmel_sha_hmac_compute_opad_hash(struct atmel_sha_dev * dd)1774 static int atmel_sha_hmac_compute_opad_hash(struct atmel_sha_dev *dd)
1775 {
1776 struct ahash_request *req = dd->req;
1777 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1778 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
1779 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1780 size_t bs = ctx->block_size;
1781 size_t hs = ctx->hash_size;
1782 size_t i, num_words = hs / sizeof(u32);
1783
1784 for (i = 0; i < num_words; ++i)
1785 hmac->ipad[i] = atmel_sha_read(dd, SHA_REG_DIGEST(i));
1786 return atmel_sha_cpu_hash(dd, hmac->opad, bs, false,
1787 atmel_sha_hmac_setup_done);
1788 }
1789
atmel_sha_hmac_setup_done(struct atmel_sha_dev * dd)1790 static int atmel_sha_hmac_setup_done(struct atmel_sha_dev *dd)
1791 {
1792 struct ahash_request *req = dd->req;
1793 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1794 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
1795 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1796 size_t hs = ctx->hash_size;
1797 size_t i, num_words = hs / sizeof(u32);
1798
1799 for (i = 0; i < num_words; ++i)
1800 hmac->opad[i] = atmel_sha_read(dd, SHA_REG_DIGEST(i));
1801 atmel_sha_hmac_key_release(&hmac->hkey);
1802 return hmac->resume(dd);
1803 }
1804
atmel_sha_hmac_start(struct atmel_sha_dev * dd)1805 static int atmel_sha_hmac_start(struct atmel_sha_dev *dd)
1806 {
1807 struct ahash_request *req = dd->req;
1808 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1809 int err;
1810
1811 err = atmel_sha_hw_init(dd);
1812 if (err)
1813 return atmel_sha_complete(dd, err);
1814
1815 switch (ctx->op) {
1816 case SHA_OP_INIT:
1817 err = atmel_sha_hmac_setup(dd, atmel_sha_hmac_init_done);
1818 break;
1819
1820 case SHA_OP_UPDATE:
1821 dd->resume = atmel_sha_done;
1822 err = atmel_sha_update_req(dd);
1823 break;
1824
1825 case SHA_OP_FINAL:
1826 dd->resume = atmel_sha_hmac_final;
1827 err = atmel_sha_final_req(dd);
1828 break;
1829
1830 case SHA_OP_DIGEST:
1831 err = atmel_sha_hmac_setup(dd, atmel_sha_hmac_digest2);
1832 break;
1833
1834 default:
1835 return atmel_sha_complete(dd, -EINVAL);
1836 }
1837
1838 return err;
1839 }
1840
atmel_sha_hmac_setkey(struct crypto_ahash * tfm,const u8 * key,unsigned int keylen)1841 static int atmel_sha_hmac_setkey(struct crypto_ahash *tfm, const u8 *key,
1842 unsigned int keylen)
1843 {
1844 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
1845
1846 return atmel_sha_hmac_key_set(&hmac->hkey, key, keylen);
1847 }
1848
atmel_sha_hmac_init(struct ahash_request * req)1849 static int atmel_sha_hmac_init(struct ahash_request *req)
1850 {
1851 int err;
1852
1853 err = atmel_sha_init(req);
1854 if (err)
1855 return err;
1856
1857 return atmel_sha_enqueue(req, SHA_OP_INIT);
1858 }
1859
atmel_sha_hmac_init_done(struct atmel_sha_dev * dd)1860 static int atmel_sha_hmac_init_done(struct atmel_sha_dev *dd)
1861 {
1862 struct ahash_request *req = dd->req;
1863 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1864 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1865 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
1866 size_t bs = ctx->block_size;
1867 size_t hs = ctx->hash_size;
1868
1869 ctx->bufcnt = 0;
1870 ctx->digcnt[0] = bs;
1871 ctx->digcnt[1] = 0;
1872 ctx->flags |= SHA_FLAGS_RESTORE;
1873 memcpy(ctx->digest, hmac->ipad, hs);
1874 return atmel_sha_complete(dd, 0);
1875 }
1876
atmel_sha_hmac_final(struct atmel_sha_dev * dd)1877 static int atmel_sha_hmac_final(struct atmel_sha_dev *dd)
1878 {
1879 struct ahash_request *req = dd->req;
1880 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1881 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1882 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
1883 u32 *digest = (u32 *)ctx->digest;
1884 size_t ds = crypto_ahash_digestsize(tfm);
1885 size_t bs = ctx->block_size;
1886 size_t hs = ctx->hash_size;
1887 size_t i, num_words;
1888 u32 mr;
1889
1890 /* Save d = SHA((K' + ipad) | msg). */
1891 num_words = ds / sizeof(u32);
1892 for (i = 0; i < num_words; ++i)
1893 digest[i] = atmel_sha_read(dd, SHA_REG_DIGEST(i));
1894
1895 /* Restore context to finish computing SHA((K' + opad) | d). */
1896 atmel_sha_write(dd, SHA_CR, SHA_CR_WUIHV);
1897 num_words = hs / sizeof(u32);
1898 for (i = 0; i < num_words; ++i)
1899 atmel_sha_write(dd, SHA_REG_DIN(i), hmac->opad[i]);
1900
1901 mr = SHA_MR_MODE_AUTO | SHA_MR_UIHV;
1902 mr |= (ctx->flags & SHA_FLAGS_ALGO_MASK);
1903 atmel_sha_write(dd, SHA_MR, mr);
1904 atmel_sha_write(dd, SHA_MSR, bs + ds);
1905 atmel_sha_write(dd, SHA_BCR, ds);
1906 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST);
1907
1908 sg_init_one(&dd->tmp, digest, ds);
1909 return atmel_sha_cpu_start(dd, &dd->tmp, ds, false, true,
1910 atmel_sha_hmac_final_done);
1911 }
1912
atmel_sha_hmac_final_done(struct atmel_sha_dev * dd)1913 static int atmel_sha_hmac_final_done(struct atmel_sha_dev *dd)
1914 {
1915 /*
1916 * req->result might not be sizeof(u32) aligned, so copy the
1917 * digest into ctx->digest[] before memcpy() the data into
1918 * req->result.
1919 */
1920 atmel_sha_copy_hash(dd->req);
1921 atmel_sha_copy_ready_hash(dd->req);
1922 return atmel_sha_complete(dd, 0);
1923 }
1924
atmel_sha_hmac_digest(struct ahash_request * req)1925 static int atmel_sha_hmac_digest(struct ahash_request *req)
1926 {
1927 int err;
1928
1929 err = atmel_sha_init(req);
1930 if (err)
1931 return err;
1932
1933 return atmel_sha_enqueue(req, SHA_OP_DIGEST);
1934 }
1935
atmel_sha_hmac_digest2(struct atmel_sha_dev * dd)1936 static int atmel_sha_hmac_digest2(struct atmel_sha_dev *dd)
1937 {
1938 struct ahash_request *req = dd->req;
1939 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1940 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1941 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
1942 struct scatterlist *sgbuf;
1943 size_t hs = ctx->hash_size;
1944 size_t i, num_words = hs / sizeof(u32);
1945 bool use_dma = false;
1946 u32 mr;
1947
1948 /* Special case for empty message. */
1949 if (!req->nbytes) {
1950 req->nbytes = 0;
1951 ctx->bufcnt = 0;
1952 ctx->digcnt[0] = 0;
1953 ctx->digcnt[1] = 0;
1954 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
1955 case SHA_FLAGS_SHA1:
1956 case SHA_FLAGS_SHA224:
1957 case SHA_FLAGS_SHA256:
1958 atmel_sha_fill_padding(ctx, 64);
1959 break;
1960
1961 case SHA_FLAGS_SHA384:
1962 case SHA_FLAGS_SHA512:
1963 atmel_sha_fill_padding(ctx, 128);
1964 break;
1965 }
1966 sg_init_one(&dd->tmp, ctx->buffer, ctx->bufcnt);
1967 }
1968
1969 /* Check DMA threshold and alignment. */
1970 if (req->nbytes > ATMEL_SHA_DMA_THRESHOLD &&
1971 atmel_sha_dma_check_aligned(dd, req->src, req->nbytes))
1972 use_dma = true;
1973
1974 /* Write both initial hash values to compute a HMAC. */
1975 atmel_sha_write(dd, SHA_CR, SHA_CR_WUIHV);
1976 for (i = 0; i < num_words; ++i)
1977 atmel_sha_write(dd, SHA_REG_DIN(i), hmac->ipad[i]);
1978
1979 atmel_sha_write(dd, SHA_CR, SHA_CR_WUIEHV);
1980 for (i = 0; i < num_words; ++i)
1981 atmel_sha_write(dd, SHA_REG_DIN(i), hmac->opad[i]);
1982
1983 /* Write the Mode, Message Size, Bytes Count then Control Registers. */
1984 mr = (SHA_MR_HMAC | SHA_MR_DUALBUFF);
1985 mr |= ctx->flags & SHA_FLAGS_ALGO_MASK;
1986 if (use_dma)
1987 mr |= SHA_MR_MODE_IDATAR0;
1988 else
1989 mr |= SHA_MR_MODE_AUTO;
1990 atmel_sha_write(dd, SHA_MR, mr);
1991
1992 atmel_sha_write(dd, SHA_MSR, req->nbytes);
1993 atmel_sha_write(dd, SHA_BCR, req->nbytes);
1994
1995 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST);
1996
1997 /* Special case for empty message. */
1998 if (!req->nbytes) {
1999 sgbuf = &dd->tmp;
2000 req->nbytes = ctx->bufcnt;
2001 } else {
2002 sgbuf = req->src;
2003 }
2004
2005 /* Process data. */
2006 if (use_dma)
2007 return atmel_sha_dma_start(dd, sgbuf, req->nbytes,
2008 atmel_sha_hmac_final_done);
2009
2010 return atmel_sha_cpu_start(dd, sgbuf, req->nbytes, false, true,
2011 atmel_sha_hmac_final_done);
2012 }
2013
atmel_sha_hmac_cra_init(struct crypto_tfm * tfm)2014 static int atmel_sha_hmac_cra_init(struct crypto_tfm *tfm)
2015 {
2016 struct atmel_sha_hmac_ctx *hmac = crypto_tfm_ctx(tfm);
2017
2018 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
2019 sizeof(struct atmel_sha_reqctx));
2020 hmac->base.start = atmel_sha_hmac_start;
2021 atmel_sha_hmac_key_init(&hmac->hkey);
2022
2023 return 0;
2024 }
2025
atmel_sha_hmac_cra_exit(struct crypto_tfm * tfm)2026 static void atmel_sha_hmac_cra_exit(struct crypto_tfm *tfm)
2027 {
2028 struct atmel_sha_hmac_ctx *hmac = crypto_tfm_ctx(tfm);
2029
2030 atmel_sha_hmac_key_release(&hmac->hkey);
2031 }
2032
atmel_sha_hmac_alg_init(struct ahash_alg * alg)2033 static void atmel_sha_hmac_alg_init(struct ahash_alg *alg)
2034 {
2035 alg->halg.base.cra_priority = ATMEL_SHA_PRIORITY;
2036 alg->halg.base.cra_flags = CRYPTO_ALG_ASYNC |
2037 CRYPTO_ALG_KERN_DRIVER_ONLY;
2038 alg->halg.base.cra_ctxsize = sizeof(struct atmel_sha_hmac_ctx);
2039 alg->halg.base.cra_module = THIS_MODULE;
2040 alg->halg.base.cra_init = atmel_sha_hmac_cra_init;
2041 alg->halg.base.cra_exit = atmel_sha_hmac_cra_exit;
2042
2043 alg->halg.statesize = sizeof(struct atmel_sha_reqctx);
2044
2045 alg->init = atmel_sha_hmac_init;
2046 alg->update = atmel_sha_update;
2047 alg->final = atmel_sha_final;
2048 alg->digest = atmel_sha_hmac_digest;
2049 alg->setkey = atmel_sha_hmac_setkey;
2050 alg->export = atmel_sha_export;
2051 alg->import = atmel_sha_import;
2052 }
2053
2054 static struct ahash_alg sha_hmac_algs[] = {
2055 {
2056 .halg.base.cra_name = "hmac(sha1)",
2057 .halg.base.cra_driver_name = "atmel-hmac-sha1",
2058 .halg.base.cra_blocksize = SHA1_BLOCK_SIZE,
2059
2060 .halg.digestsize = SHA1_DIGEST_SIZE,
2061 },
2062 {
2063 .halg.base.cra_name = "hmac(sha224)",
2064 .halg.base.cra_driver_name = "atmel-hmac-sha224",
2065 .halg.base.cra_blocksize = SHA224_BLOCK_SIZE,
2066
2067 .halg.digestsize = SHA224_DIGEST_SIZE,
2068 },
2069 {
2070 .halg.base.cra_name = "hmac(sha256)",
2071 .halg.base.cra_driver_name = "atmel-hmac-sha256",
2072 .halg.base.cra_blocksize = SHA256_BLOCK_SIZE,
2073
2074 .halg.digestsize = SHA256_DIGEST_SIZE,
2075 },
2076 {
2077 .halg.base.cra_name = "hmac(sha384)",
2078 .halg.base.cra_driver_name = "atmel-hmac-sha384",
2079 .halg.base.cra_blocksize = SHA384_BLOCK_SIZE,
2080
2081 .halg.digestsize = SHA384_DIGEST_SIZE,
2082 },
2083 {
2084 .halg.base.cra_name = "hmac(sha512)",
2085 .halg.base.cra_driver_name = "atmel-hmac-sha512",
2086 .halg.base.cra_blocksize = SHA512_BLOCK_SIZE,
2087
2088 .halg.digestsize = SHA512_DIGEST_SIZE,
2089 },
2090 };
2091
2092 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
2093 /* authenc functions */
2094
2095 static int atmel_sha_authenc_init2(struct atmel_sha_dev *dd);
2096 static int atmel_sha_authenc_init_done(struct atmel_sha_dev *dd);
2097 static int atmel_sha_authenc_final_done(struct atmel_sha_dev *dd);
2098
2099
2100 struct atmel_sha_authenc_ctx {
2101 struct crypto_ahash *tfm;
2102 };
2103
2104 struct atmel_sha_authenc_reqctx {
2105 struct atmel_sha_reqctx base;
2106
2107 atmel_aes_authenc_fn_t cb;
2108 struct atmel_aes_dev *aes_dev;
2109
2110 /* _init() parameters. */
2111 struct scatterlist *assoc;
2112 u32 assoclen;
2113 u32 textlen;
2114
2115 /* _final() parameters. */
2116 u32 *digest;
2117 unsigned int digestlen;
2118 };
2119
atmel_sha_authenc_complete(void * data,int err)2120 static void atmel_sha_authenc_complete(void *data, int err)
2121 {
2122 struct ahash_request *req = data;
2123 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req);
2124
2125 authctx->cb(authctx->aes_dev, err, authctx->base.dd->is_async);
2126 }
2127
atmel_sha_authenc_start(struct atmel_sha_dev * dd)2128 static int atmel_sha_authenc_start(struct atmel_sha_dev *dd)
2129 {
2130 struct ahash_request *req = dd->req;
2131 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req);
2132 int err;
2133
2134 /*
2135 * Force atmel_sha_complete() to call req->base.complete(), ie
2136 * atmel_sha_authenc_complete(), which in turn calls authctx->cb().
2137 */
2138 dd->force_complete = true;
2139
2140 err = atmel_sha_hw_init(dd);
2141 return authctx->cb(authctx->aes_dev, err, dd->is_async);
2142 }
2143
atmel_sha_authenc_is_ready(void)2144 bool atmel_sha_authenc_is_ready(void)
2145 {
2146 struct atmel_sha_ctx dummy;
2147
2148 dummy.dd = NULL;
2149 return (atmel_sha_find_dev(&dummy) != NULL);
2150 }
2151 EXPORT_SYMBOL_GPL(atmel_sha_authenc_is_ready);
2152
atmel_sha_authenc_get_reqsize(void)2153 unsigned int atmel_sha_authenc_get_reqsize(void)
2154 {
2155 return sizeof(struct atmel_sha_authenc_reqctx);
2156 }
2157 EXPORT_SYMBOL_GPL(atmel_sha_authenc_get_reqsize);
2158
atmel_sha_authenc_spawn(unsigned long mode)2159 struct atmel_sha_authenc_ctx *atmel_sha_authenc_spawn(unsigned long mode)
2160 {
2161 struct atmel_sha_authenc_ctx *auth;
2162 struct crypto_ahash *tfm;
2163 struct atmel_sha_ctx *tctx;
2164 const char *name;
2165 int err = -EINVAL;
2166
2167 switch (mode & SHA_FLAGS_MODE_MASK) {
2168 case SHA_FLAGS_HMAC_SHA1:
2169 name = "atmel-hmac-sha1";
2170 break;
2171
2172 case SHA_FLAGS_HMAC_SHA224:
2173 name = "atmel-hmac-sha224";
2174 break;
2175
2176 case SHA_FLAGS_HMAC_SHA256:
2177 name = "atmel-hmac-sha256";
2178 break;
2179
2180 case SHA_FLAGS_HMAC_SHA384:
2181 name = "atmel-hmac-sha384";
2182 break;
2183
2184 case SHA_FLAGS_HMAC_SHA512:
2185 name = "atmel-hmac-sha512";
2186 break;
2187
2188 default:
2189 goto error;
2190 }
2191
2192 tfm = crypto_alloc_ahash(name, 0, 0);
2193 if (IS_ERR(tfm)) {
2194 err = PTR_ERR(tfm);
2195 goto error;
2196 }
2197 tctx = crypto_ahash_ctx(tfm);
2198 tctx->start = atmel_sha_authenc_start;
2199 tctx->flags = mode;
2200
2201 auth = kzalloc_obj(*auth);
2202 if (!auth) {
2203 err = -ENOMEM;
2204 goto err_free_ahash;
2205 }
2206 auth->tfm = tfm;
2207
2208 return auth;
2209
2210 err_free_ahash:
2211 crypto_free_ahash(tfm);
2212 error:
2213 return ERR_PTR(err);
2214 }
2215 EXPORT_SYMBOL_GPL(atmel_sha_authenc_spawn);
2216
atmel_sha_authenc_free(struct atmel_sha_authenc_ctx * auth)2217 void atmel_sha_authenc_free(struct atmel_sha_authenc_ctx *auth)
2218 {
2219 if (auth)
2220 crypto_free_ahash(auth->tfm);
2221 kfree(auth);
2222 }
2223 EXPORT_SYMBOL_GPL(atmel_sha_authenc_free);
2224
atmel_sha_authenc_setkey(struct atmel_sha_authenc_ctx * auth,const u8 * key,unsigned int keylen,u32 flags)2225 int atmel_sha_authenc_setkey(struct atmel_sha_authenc_ctx *auth,
2226 const u8 *key, unsigned int keylen, u32 flags)
2227 {
2228 struct crypto_ahash *tfm = auth->tfm;
2229
2230 crypto_ahash_clear_flags(tfm, CRYPTO_TFM_REQ_MASK);
2231 crypto_ahash_set_flags(tfm, flags & CRYPTO_TFM_REQ_MASK);
2232 return crypto_ahash_setkey(tfm, key, keylen);
2233 }
2234 EXPORT_SYMBOL_GPL(atmel_sha_authenc_setkey);
2235
atmel_sha_authenc_schedule(struct ahash_request * req,struct atmel_sha_authenc_ctx * auth,atmel_aes_authenc_fn_t cb,struct atmel_aes_dev * aes_dev)2236 int atmel_sha_authenc_schedule(struct ahash_request *req,
2237 struct atmel_sha_authenc_ctx *auth,
2238 atmel_aes_authenc_fn_t cb,
2239 struct atmel_aes_dev *aes_dev)
2240 {
2241 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req);
2242 struct atmel_sha_reqctx *ctx = &authctx->base;
2243 struct crypto_ahash *tfm = auth->tfm;
2244 struct atmel_sha_ctx *tctx = crypto_ahash_ctx(tfm);
2245 struct atmel_sha_dev *dd;
2246
2247 /* Reset request context (MUST be done first). */
2248 memset(authctx, 0, sizeof(*authctx));
2249
2250 /* Get SHA device. */
2251 dd = atmel_sha_find_dev(tctx);
2252 if (!dd)
2253 return cb(aes_dev, -ENODEV, false);
2254
2255 /* Init request context. */
2256 ctx->dd = dd;
2257 ctx->buflen = SHA_BUFFER_LEN;
2258 authctx->cb = cb;
2259 authctx->aes_dev = aes_dev;
2260 ahash_request_set_tfm(req, tfm);
2261 ahash_request_set_callback(req, 0, atmel_sha_authenc_complete, req);
2262
2263 return atmel_sha_handle_queue(dd, req);
2264 }
2265 EXPORT_SYMBOL_GPL(atmel_sha_authenc_schedule);
2266
atmel_sha_authenc_init(struct ahash_request * req,struct scatterlist * assoc,unsigned int assoclen,unsigned int textlen,atmel_aes_authenc_fn_t cb,struct atmel_aes_dev * aes_dev)2267 int atmel_sha_authenc_init(struct ahash_request *req,
2268 struct scatterlist *assoc, unsigned int assoclen,
2269 unsigned int textlen,
2270 atmel_aes_authenc_fn_t cb,
2271 struct atmel_aes_dev *aes_dev)
2272 {
2273 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req);
2274 struct atmel_sha_reqctx *ctx = &authctx->base;
2275 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
2276 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
2277 struct atmel_sha_dev *dd = ctx->dd;
2278
2279 if (unlikely(!IS_ALIGNED(assoclen, sizeof(u32))))
2280 return atmel_sha_complete(dd, -EINVAL);
2281
2282 authctx->cb = cb;
2283 authctx->aes_dev = aes_dev;
2284 authctx->assoc = assoc;
2285 authctx->assoclen = assoclen;
2286 authctx->textlen = textlen;
2287
2288 ctx->flags = hmac->base.flags;
2289 return atmel_sha_hmac_setup(dd, atmel_sha_authenc_init2);
2290 }
2291 EXPORT_SYMBOL_GPL(atmel_sha_authenc_init);
2292
atmel_sha_authenc_init2(struct atmel_sha_dev * dd)2293 static int atmel_sha_authenc_init2(struct atmel_sha_dev *dd)
2294 {
2295 struct ahash_request *req = dd->req;
2296 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req);
2297 struct atmel_sha_reqctx *ctx = &authctx->base;
2298 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
2299 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
2300 size_t hs = ctx->hash_size;
2301 size_t i, num_words = hs / sizeof(u32);
2302 u32 mr, msg_size;
2303
2304 atmel_sha_write(dd, SHA_CR, SHA_CR_WUIHV);
2305 for (i = 0; i < num_words; ++i)
2306 atmel_sha_write(dd, SHA_REG_DIN(i), hmac->ipad[i]);
2307
2308 atmel_sha_write(dd, SHA_CR, SHA_CR_WUIEHV);
2309 for (i = 0; i < num_words; ++i)
2310 atmel_sha_write(dd, SHA_REG_DIN(i), hmac->opad[i]);
2311
2312 mr = (SHA_MR_MODE_IDATAR0 |
2313 SHA_MR_HMAC |
2314 SHA_MR_DUALBUFF);
2315 mr |= ctx->flags & SHA_FLAGS_ALGO_MASK;
2316 atmel_sha_write(dd, SHA_MR, mr);
2317
2318 msg_size = authctx->assoclen + authctx->textlen;
2319 atmel_sha_write(dd, SHA_MSR, msg_size);
2320 atmel_sha_write(dd, SHA_BCR, msg_size);
2321
2322 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST);
2323
2324 /* Process assoc data. */
2325 return atmel_sha_cpu_start(dd, authctx->assoc, authctx->assoclen,
2326 true, false,
2327 atmel_sha_authenc_init_done);
2328 }
2329
atmel_sha_authenc_init_done(struct atmel_sha_dev * dd)2330 static int atmel_sha_authenc_init_done(struct atmel_sha_dev *dd)
2331 {
2332 struct ahash_request *req = dd->req;
2333 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req);
2334
2335 return authctx->cb(authctx->aes_dev, 0, dd->is_async);
2336 }
2337
atmel_sha_authenc_final(struct ahash_request * req,u32 * digest,unsigned int digestlen,atmel_aes_authenc_fn_t cb,struct atmel_aes_dev * aes_dev)2338 int atmel_sha_authenc_final(struct ahash_request *req,
2339 u32 *digest, unsigned int digestlen,
2340 atmel_aes_authenc_fn_t cb,
2341 struct atmel_aes_dev *aes_dev)
2342 {
2343 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req);
2344 struct atmel_sha_reqctx *ctx = &authctx->base;
2345 struct atmel_sha_dev *dd = ctx->dd;
2346
2347 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
2348 case SHA_FLAGS_SHA1:
2349 authctx->digestlen = SHA1_DIGEST_SIZE;
2350 break;
2351
2352 case SHA_FLAGS_SHA224:
2353 authctx->digestlen = SHA224_DIGEST_SIZE;
2354 break;
2355
2356 case SHA_FLAGS_SHA256:
2357 authctx->digestlen = SHA256_DIGEST_SIZE;
2358 break;
2359
2360 case SHA_FLAGS_SHA384:
2361 authctx->digestlen = SHA384_DIGEST_SIZE;
2362 break;
2363
2364 case SHA_FLAGS_SHA512:
2365 authctx->digestlen = SHA512_DIGEST_SIZE;
2366 break;
2367
2368 default:
2369 return atmel_sha_complete(dd, -EINVAL);
2370 }
2371 if (authctx->digestlen > digestlen)
2372 authctx->digestlen = digestlen;
2373
2374 authctx->cb = cb;
2375 authctx->aes_dev = aes_dev;
2376 authctx->digest = digest;
2377 return atmel_sha_wait_for_data_ready(dd,
2378 atmel_sha_authenc_final_done);
2379 }
2380 EXPORT_SYMBOL_GPL(atmel_sha_authenc_final);
2381
atmel_sha_authenc_final_done(struct atmel_sha_dev * dd)2382 static int atmel_sha_authenc_final_done(struct atmel_sha_dev *dd)
2383 {
2384 struct ahash_request *req = dd->req;
2385 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req);
2386 size_t i, num_words = authctx->digestlen / sizeof(u32);
2387
2388 for (i = 0; i < num_words; ++i)
2389 authctx->digest[i] = atmel_sha_read(dd, SHA_REG_DIGEST(i));
2390
2391 return atmel_sha_complete(dd, 0);
2392 }
2393
atmel_sha_authenc_abort(struct ahash_request * req)2394 void atmel_sha_authenc_abort(struct ahash_request *req)
2395 {
2396 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req);
2397 struct atmel_sha_reqctx *ctx = &authctx->base;
2398 struct atmel_sha_dev *dd = ctx->dd;
2399
2400 /* Prevent atmel_sha_complete() from calling req->base.complete(). */
2401 dd->is_async = false;
2402 dd->force_complete = false;
2403 (void)atmel_sha_complete(dd, 0);
2404 }
2405 EXPORT_SYMBOL_GPL(atmel_sha_authenc_abort);
2406
2407 #endif /* CONFIG_CRYPTO_DEV_ATMEL_AUTHENC */
2408
2409
atmel_sha_unregister_algs(struct atmel_sha_dev * dd)2410 static void atmel_sha_unregister_algs(struct atmel_sha_dev *dd)
2411 {
2412 if (dd->caps.has_hmac)
2413 crypto_unregister_ahashes(sha_hmac_algs,
2414 ARRAY_SIZE(sha_hmac_algs));
2415
2416 crypto_unregister_ahashes(sha_1_256_algs, ARRAY_SIZE(sha_1_256_algs));
2417
2418 if (dd->caps.has_sha224)
2419 crypto_unregister_ahash(&sha_224_alg);
2420
2421 if (dd->caps.has_sha_384_512)
2422 crypto_unregister_ahashes(sha_384_512_algs,
2423 ARRAY_SIZE(sha_384_512_algs));
2424 }
2425
atmel_sha_register_algs(struct atmel_sha_dev * dd)2426 static int atmel_sha_register_algs(struct atmel_sha_dev *dd)
2427 {
2428 int err, i;
2429
2430 for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++) {
2431 atmel_sha_alg_init(&sha_1_256_algs[i]);
2432
2433 err = crypto_register_ahash(&sha_1_256_algs[i]);
2434 if (err)
2435 goto err_sha_1_256_algs;
2436 }
2437
2438 if (dd->caps.has_sha224) {
2439 atmel_sha_alg_init(&sha_224_alg);
2440
2441 err = crypto_register_ahash(&sha_224_alg);
2442 if (err)
2443 goto err_sha_224_algs;
2444 }
2445
2446 if (dd->caps.has_sha_384_512) {
2447 for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++) {
2448 atmel_sha_alg_init(&sha_384_512_algs[i]);
2449
2450 err = crypto_register_ahash(&sha_384_512_algs[i]);
2451 if (err)
2452 goto err_sha_384_512_algs;
2453 }
2454 }
2455
2456 if (dd->caps.has_hmac) {
2457 for (i = 0; i < ARRAY_SIZE(sha_hmac_algs); i++) {
2458 atmel_sha_hmac_alg_init(&sha_hmac_algs[i]);
2459
2460 err = crypto_register_ahash(&sha_hmac_algs[i]);
2461 if (err)
2462 goto err_sha_hmac_algs;
2463 }
2464 }
2465
2466 return 0;
2467
2468 /*i = ARRAY_SIZE(sha_hmac_algs);*/
2469 err_sha_hmac_algs:
2470 crypto_unregister_ahashes(sha_hmac_algs, i);
2471 i = ARRAY_SIZE(sha_384_512_algs);
2472 err_sha_384_512_algs:
2473 crypto_unregister_ahashes(sha_384_512_algs, i);
2474 crypto_unregister_ahash(&sha_224_alg);
2475 err_sha_224_algs:
2476 i = ARRAY_SIZE(sha_1_256_algs);
2477 err_sha_1_256_algs:
2478 crypto_unregister_ahashes(sha_1_256_algs, i);
2479
2480 return err;
2481 }
2482
atmel_sha_dma_init(struct atmel_sha_dev * dd)2483 static int atmel_sha_dma_init(struct atmel_sha_dev *dd)
2484 {
2485 dd->dma_lch_in.chan = dma_request_chan(dd->dev, "tx");
2486 if (IS_ERR(dd->dma_lch_in.chan)) {
2487 return dev_err_probe(dd->dev, PTR_ERR(dd->dma_lch_in.chan),
2488 "DMA channel is not available\n");
2489 }
2490
2491 dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base +
2492 SHA_REG_DIN(0);
2493 dd->dma_lch_in.dma_conf.src_maxburst = 1;
2494 dd->dma_lch_in.dma_conf.src_addr_width =
2495 DMA_SLAVE_BUSWIDTH_4_BYTES;
2496 dd->dma_lch_in.dma_conf.dst_maxburst = 1;
2497 dd->dma_lch_in.dma_conf.dst_addr_width =
2498 DMA_SLAVE_BUSWIDTH_4_BYTES;
2499 dd->dma_lch_in.dma_conf.device_fc = false;
2500
2501 return 0;
2502 }
2503
atmel_sha_dma_cleanup(struct atmel_sha_dev * dd)2504 static void atmel_sha_dma_cleanup(struct atmel_sha_dev *dd)
2505 {
2506 dma_release_channel(dd->dma_lch_in.chan);
2507 }
2508
atmel_sha_get_cap(struct atmel_sha_dev * dd)2509 static void atmel_sha_get_cap(struct atmel_sha_dev *dd)
2510 {
2511
2512 dd->caps.has_dma = 0;
2513 dd->caps.has_dualbuff = 0;
2514 dd->caps.has_sha224 = 0;
2515 dd->caps.has_sha_384_512 = 0;
2516 dd->caps.has_uihv = 0;
2517 dd->caps.has_hmac = 0;
2518
2519 /* keep only major version number */
2520 switch (dd->hw_version & 0xff0) {
2521 case 0x800:
2522 case 0x700:
2523 case 0x600:
2524 case 0x510:
2525 dd->caps.has_dma = 1;
2526 dd->caps.has_dualbuff = 1;
2527 dd->caps.has_sha224 = 1;
2528 dd->caps.has_sha_384_512 = 1;
2529 dd->caps.has_uihv = 1;
2530 dd->caps.has_hmac = 1;
2531 break;
2532 case 0x420:
2533 dd->caps.has_dma = 1;
2534 dd->caps.has_dualbuff = 1;
2535 dd->caps.has_sha224 = 1;
2536 dd->caps.has_sha_384_512 = 1;
2537 dd->caps.has_uihv = 1;
2538 break;
2539 case 0x410:
2540 dd->caps.has_dma = 1;
2541 dd->caps.has_dualbuff = 1;
2542 dd->caps.has_sha224 = 1;
2543 dd->caps.has_sha_384_512 = 1;
2544 break;
2545 case 0x400:
2546 dd->caps.has_dma = 1;
2547 dd->caps.has_dualbuff = 1;
2548 dd->caps.has_sha224 = 1;
2549 break;
2550 case 0x320:
2551 break;
2552 default:
2553 dev_warn(dd->dev,
2554 "Unmanaged sha version, set minimum capabilities\n");
2555 break;
2556 }
2557 }
2558
2559 static const struct of_device_id atmel_sha_dt_ids[] = {
2560 { .compatible = "atmel,at91sam9g46-sha" },
2561 { /* sentinel */ }
2562 };
2563
2564 MODULE_DEVICE_TABLE(of, atmel_sha_dt_ids);
2565
atmel_sha_probe(struct platform_device * pdev)2566 static int atmel_sha_probe(struct platform_device *pdev)
2567 {
2568 struct atmel_sha_dev *sha_dd;
2569 struct device *dev = &pdev->dev;
2570 struct resource *sha_res;
2571 int err;
2572
2573 sha_dd = devm_kzalloc(&pdev->dev, sizeof(*sha_dd), GFP_KERNEL);
2574 if (!sha_dd)
2575 return -ENOMEM;
2576
2577 sha_dd->dev = dev;
2578
2579 platform_set_drvdata(pdev, sha_dd);
2580
2581 INIT_LIST_HEAD(&sha_dd->list);
2582 spin_lock_init(&sha_dd->lock);
2583
2584 tasklet_init(&sha_dd->done_task, atmel_sha_done_task,
2585 (unsigned long)sha_dd);
2586 tasklet_init(&sha_dd->queue_task, atmel_sha_queue_task,
2587 (unsigned long)sha_dd);
2588
2589 crypto_init_queue(&sha_dd->queue, ATMEL_SHA_QUEUE_LENGTH);
2590
2591 sha_dd->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &sha_res);
2592 if (IS_ERR(sha_dd->io_base)) {
2593 err = PTR_ERR(sha_dd->io_base);
2594 goto err_tasklet_kill;
2595 }
2596 sha_dd->phys_base = sha_res->start;
2597
2598 /* Get the IRQ */
2599 sha_dd->irq = platform_get_irq(pdev, 0);
2600 if (sha_dd->irq < 0) {
2601 err = sha_dd->irq;
2602 goto err_tasklet_kill;
2603 }
2604
2605 err = devm_request_irq(&pdev->dev, sha_dd->irq, atmel_sha_irq,
2606 IRQF_SHARED, "atmel-sha", sha_dd);
2607 if (err)
2608 goto err_tasklet_kill;
2609
2610 /* Initializing the clock */
2611 sha_dd->iclk = devm_clk_get_prepared(&pdev->dev, "sha_clk");
2612 if (IS_ERR(sha_dd->iclk)) {
2613 dev_err(dev, "clock initialization failed.\n");
2614 err = PTR_ERR(sha_dd->iclk);
2615 goto err_tasklet_kill;
2616 }
2617
2618 err = atmel_sha_hw_version_init(sha_dd);
2619 if (err)
2620 goto err_tasklet_kill;
2621
2622 atmel_sha_get_cap(sha_dd);
2623
2624 if (sha_dd->caps.has_dma) {
2625 err = atmel_sha_dma_init(sha_dd);
2626 if (err)
2627 goto err_tasklet_kill;
2628
2629 dev_info(dev, "using %s for DMA transfers\n",
2630 dma_chan_name(sha_dd->dma_lch_in.chan));
2631 }
2632
2633 spin_lock(&atmel_sha.lock);
2634 list_add_tail(&sha_dd->list, &atmel_sha.dev_list);
2635 spin_unlock(&atmel_sha.lock);
2636
2637 err = atmel_sha_register_algs(sha_dd);
2638 if (err)
2639 goto err_algs;
2640
2641 dev_info(dev, "Atmel SHA1/SHA256%s%s\n",
2642 sha_dd->caps.has_sha224 ? "/SHA224" : "",
2643 sha_dd->caps.has_sha_384_512 ? "/SHA384/SHA512" : "");
2644
2645 return 0;
2646
2647 err_algs:
2648 spin_lock(&atmel_sha.lock);
2649 list_del(&sha_dd->list);
2650 spin_unlock(&atmel_sha.lock);
2651 if (sha_dd->caps.has_dma)
2652 atmel_sha_dma_cleanup(sha_dd);
2653 err_tasklet_kill:
2654 tasklet_kill(&sha_dd->queue_task);
2655 tasklet_kill(&sha_dd->done_task);
2656
2657 return err;
2658 }
2659
atmel_sha_remove(struct platform_device * pdev)2660 static void atmel_sha_remove(struct platform_device *pdev)
2661 {
2662 struct atmel_sha_dev *sha_dd = platform_get_drvdata(pdev);
2663
2664 spin_lock(&atmel_sha.lock);
2665 list_del(&sha_dd->list);
2666 spin_unlock(&atmel_sha.lock);
2667
2668 atmel_sha_unregister_algs(sha_dd);
2669
2670 tasklet_kill(&sha_dd->queue_task);
2671 tasklet_kill(&sha_dd->done_task);
2672
2673 if (sha_dd->caps.has_dma)
2674 atmel_sha_dma_cleanup(sha_dd);
2675 }
2676
2677 static struct platform_driver atmel_sha_driver = {
2678 .probe = atmel_sha_probe,
2679 .remove = atmel_sha_remove,
2680 .driver = {
2681 .name = "atmel_sha",
2682 .of_match_table = atmel_sha_dt_ids,
2683 },
2684 };
2685
2686 module_platform_driver(atmel_sha_driver);
2687
2688 MODULE_DESCRIPTION("Atmel SHA (1/256/224/384/512) hw acceleration support.");
2689 MODULE_LICENSE("GPL v2");
2690 MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");
2691