1 /* SPDX-License-Identifier: GPL-2.0-only 2 * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION. All rights reserved. 3 * 4 * tegra210_amx.h - Definitions for Tegra210 AMX driver 5 * 6 */ 7 8 #ifndef __TEGRA210_AMX_H__ 9 #define __TEGRA210_AMX_H__ 10 11 #include <linux/types.h> 12 13 /* Register offsets from TEGRA210_AMX*_BASE */ 14 #define TEGRA210_AMX_RX_STATUS 0x0c 15 #define TEGRA210_AMX_RX_INT_STATUS 0x10 16 #define TEGRA210_AMX_RX_INT_MASK 0x14 17 #define TEGRA210_AMX_RX_INT_SET 0x18 18 #define TEGRA210_AMX_RX_INT_CLEAR 0x1c 19 #define TEGRA210_AMX_RX1_CIF_CTRL 0x20 20 #define TEGRA210_AMX_RX2_CIF_CTRL 0x24 21 #define TEGRA210_AMX_RX3_CIF_CTRL 0x28 22 #define TEGRA210_AMX_RX4_CIF_CTRL 0x2c 23 #define TEGRA210_AMX_TX_STATUS 0x4c 24 #define TEGRA210_AMX_TX_INT_STATUS 0x50 25 #define TEGRA210_AMX_TX_INT_MASK 0x54 26 #define TEGRA210_AMX_TX_INT_SET 0x58 27 #define TEGRA210_AMX_TX_INT_CLEAR 0x5c 28 #define TEGRA210_AMX_TX_CIF_CTRL 0x60 29 #define TEGRA210_AMX_ENABLE 0x80 30 #define TEGRA210_AMX_SOFT_RESET 0x84 31 #define TEGRA210_AMX_CG 0x88 32 #define TEGRA210_AMX_STATUS 0x8c 33 #define TEGRA210_AMX_INT_STATUS 0x90 34 #define TEGRA210_AMX_CTRL 0xa4 35 #define TEGRA210_AMX_OUT_BYTE_EN0 0xa8 36 #define TEGRA210_AMX_CYA 0xb0 37 #define TEGRA210_AMX_CFG_RAM_CTRL 0xb8 38 #define TEGRA210_AMX_CFG_RAM_DATA 0xbc 39 40 #define TEGRA194_AMX_RX1_FRAME_PERIOD 0xc0 41 #define TEGRA194_AMX_RX4_FRAME_PERIOD 0xcc 42 #define TEGRA194_AMX_RX4_LAST_FRAME_PERIOD 0xdc 43 44 #define TEGRA264_AMX_STREAMS_AUTO_DISABLE 0xb8 45 #define TEGRA264_AMX_CFG_RAM_CTRL 0xc0 46 #define TEGRA264_AMX_CFG_RAM_DATA 0xc4 47 #define TEGRA264_AMX_RX1_FRAME_PERIOD 0xc8 48 #define TEGRA264_AMX_RX4_FRAME_PERIOD 0xd4 49 #define TEGRA264_AMX_RX4_LAST_FRAME_PERIOD 0xe4 50 51 /* Fields in TEGRA210_AMX_ENABLE */ 52 #define TEGRA210_AMX_ENABLE_SHIFT 0 53 54 /* Fields in TEGRA210_AMX_CTRL */ 55 #define TEGRA210_AMX_CTRL_MSTR_RX_NUM_SHIFT 14 56 #define TEGRA210_AMX_CTRL_MSTR_RX_NUM_MASK (3 << TEGRA210_AMX_CTRL_MSTR_RX_NUM_SHIFT) 57 58 #define TEGRA210_AMX_CTRL_RX_DEP_SHIFT 12 59 #define TEGRA210_AMX_CTRL_RX_DEP_MASK (3 << TEGRA210_AMX_CTRL_RX_DEP_SHIFT) 60 61 /* Fields in TEGRA210_AMX_CFG_RAM_CTRL */ 62 #define TEGRA210_AMX_CFG_RAM_CTRL_RW_SHIFT 14 63 #define TEGRA210_AMX_CFG_RAM_CTRL_RW_WRITE (1 << TEGRA210_AMX_CFG_RAM_CTRL_RW_SHIFT) 64 65 #define TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT 13 66 #define TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN (1 << TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT) 67 68 #define TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT 12 69 #define TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT) 70 71 #define TEGRA210_AMX_CFG_CTRL_RAM_ADDR_SHIFT 0 72 73 /* Fields in TEGRA210_AMX_SOFT_RESET */ 74 #define TEGRA210_AMX_SOFT_RESET_SOFT_EN 1 75 #define TEGRA210_AMX_SOFT_RESET_SOFT_RESET_MASK TEGRA210_AMX_SOFT_RESET_SOFT_EN 76 77 #define TEGRA210_AMX_AUDIOCIF_CH_STRIDE 4 78 #define TEGRA_AMX_SLOTS_PER_WORD 4 79 #define TEGRA210_AMX_RAM_DEPTH 16 80 #define TEGRA210_AMX_MAP_STREAM_NUM_SHIFT 6 81 #define TEGRA210_AMX_MAP_WORD_NUM_SHIFT 2 82 #define TEGRA210_AMX_MAP_BYTE_NUM_SHIFT 0 83 #define TEGRA210_AMX_BYTE_MASK_COUNT 2 84 #define TEGRA210_AMX_MAX_CHANNEL 16 85 #define TEGRA210_AMX_AUTO_DISABLE_OFFSET 0 86 87 #define TEGRA264_AMX_RAM_DEPTH 32 88 #define TEGRA264_AMX_BYTE_MASK_COUNT 4 89 #define TEGRA264_AMX_MAX_CHANNEL 32 90 #define TEGRA264_AMX_AUTO_DISABLE_OFFSET 8 91 #define TEGRA_AMX_OUT_DAI_ID 4 92 93 enum { 94 TEGRA210_AMX_WAIT_ON_ALL, 95 TEGRA210_AMX_WAIT_ON_ANY, 96 }; 97 98 struct tegra210_amx_soc_data { 99 const struct regmap_config *regmap_conf; 100 bool auto_disable; 101 const struct snd_kcontrol_new *controls; 102 unsigned int num_controls; 103 unsigned int max_ch; 104 unsigned int ram_depth; 105 unsigned int byte_mask_size; 106 unsigned int reg_offset; 107 }; 108 109 struct tegra210_amx { 110 const struct tegra210_amx_soc_data *soc_data; 111 unsigned int *byte_mask; 112 u16 *map; 113 struct regmap *regmap; 114 }; 115 116 #endif 117