1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * ZynqMP DPSUB Subsystem Driver
4 *
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
6 *
7 * Authors:
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 */
11
12 #ifndef _ZYNQMP_DPSUB_H_
13 #define _ZYNQMP_DPSUB_H_
14
15 #include <linux/types.h>
16
17 struct clk;
18 struct device;
19 struct drm_bridge;
20 struct zynqmp_disp;
21 struct zynqmp_disp_layer;
22 struct zynqmp_dp;
23 struct zynqmp_dpsub_drm;
24
25 #define ZYNQMP_DPSUB_NUM_LAYERS 2
26
27 enum zynqmp_dpsub_port {
28 ZYNQMP_DPSUB_PORT_LIVE_VIDEO,
29 ZYNQMP_DPSUB_PORT_LIVE_GFX,
30 ZYNQMP_DPSUB_PORT_LIVE_AUDIO,
31 ZYNQMP_DPSUB_PORT_OUT_VIDEO,
32 ZYNQMP_DPSUB_PORT_OUT_AUDIO,
33 ZYNQMP_DPSUB_PORT_OUT_DP,
34 ZYNQMP_DPSUB_NUM_PORTS,
35 };
36
37 enum zynqmp_dpsub_format {
38 ZYNQMP_DPSUB_FORMAT_RGB,
39 ZYNQMP_DPSUB_FORMAT_YCRCB444,
40 ZYNQMP_DPSUB_FORMAT_YCRCB422,
41 ZYNQMP_DPSUB_FORMAT_YONLY,
42 };
43
44 struct zynqmp_dpsub_audio;
45
46 /**
47 * struct zynqmp_dpsub - ZynqMP DisplayPort Subsystem
48 * @dev: The physical device
49 * @apb_clk: The APB clock
50 * @vid_clk: Video clock
51 * @vid_clk_from_ps: True of the video clock comes from PS, false from PL
52 * @aud_clk: Audio clock
53 * @aud_clk_from_ps: True of the audio clock comes from PS, false from PL
54 * @connected_ports: Bitmask of connected ports in the device tree
55 * @dma_enabled: True if the DMA interface is enabled, false if the DPSUB is
56 * driven by the live input
57 * @drm: The DRM/KMS device data
58 * @bridge: The DP encoder bridge
59 * @disp: The display controller
60 * @layers: Video and graphics layers
61 * @dp: The DisplayPort controller
62 * @dma_align: DMA alignment constraint (must be a power of 2)
63 * @audio: DP audio data
64 */
65 struct zynqmp_dpsub {
66 struct device *dev;
67
68 struct clk *apb_clk;
69 struct clk *vid_clk;
70 bool vid_clk_from_ps;
71 struct clk *aud_clk;
72 bool aud_clk_from_ps;
73
74 unsigned int connected_ports;
75 bool dma_enabled;
76
77 struct zynqmp_dpsub_drm *drm;
78 struct drm_bridge *bridge;
79
80 struct zynqmp_disp *disp;
81 struct zynqmp_disp_layer *layers[ZYNQMP_DPSUB_NUM_LAYERS];
82 struct zynqmp_dp *dp;
83
84 unsigned int dma_align;
85
86 struct zynqmp_dpsub_audio *audio;
87 };
88
89 #ifdef CONFIG_DRM_ZYNQMP_DPSUB_AUDIO
90 int zynqmp_audio_init(struct zynqmp_dpsub *dpsub);
91 void zynqmp_audio_uninit(struct zynqmp_dpsub *dpsub);
92 #else
zynqmp_audio_init(struct zynqmp_dpsub * dpsub)93 static inline int zynqmp_audio_init(struct zynqmp_dpsub *dpsub) { return 0; }
zynqmp_audio_uninit(struct zynqmp_dpsub * dpsub)94 static inline void zynqmp_audio_uninit(struct zynqmp_dpsub *dpsub) { }
95 #endif
96
97 void zynqmp_dpsub_release(struct zynqmp_dpsub *dpsub);
98
99 #endif /* _ZYNQMP_DPSUB_H_ */
100